US9105539B2

Solid-state imaging device and manufacturing method of the same, and electronic apparatus

Summary by NHIP

Solid-state imaging device

The device comprises a semiconductor substrate with photoelectric conversion units separated by a recessed portion containing an embedded insulating film. A convex light shielding portion laminated on the insulating film protrudes toward the substrate to prevent charge mixing between adjacent units.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench. The present technology can be applied to a back surface irradiation type CMOS solid-state imaging device.

US9105539B2, drawing sheet 1 — Sheet 1 of 15

Term

6.3 yearsleft in the term

Expires 11 January 2033.

8 claims: 3 independent, 5 dependent

1
Broadest claimClaim Score 75, broad(NHIP)A solid-state imaging device comprising:a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed;a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate;an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semiconductor substrate;and a light shielding portion that is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.
7
A manufacturing method of a solid-state imaging device comprising the steps of:forming a recessed portion between photoelectric conversion units so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the photoelectric conversion units, each of which receives light to generate charges, are formed;embedding an insulating film in the recessed portion and laminating the insulating film on a back surface side of the semiconductor substrate;and laminating a light shielding portion on the insulating film and forming the light shielding portion into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.
8
An electronic apparatus comprising:a solid-state imaging device including a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed;a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate;an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semiconductor substrate;and a light shielding portion that is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

Independent claims3

127 paragraphs in 8 sections, as filed

0001This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2013/050406 having an international filing date of Jan. 11, 2013, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2012-011125 filed Jan. 23, 2012, the disclosure of each of which is incorporated herein by reference.

TECHNICAL FIELD

0002The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, and in particular, to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing.

BACKGROUND ART

0003In general, in a Complementary Metal Oxide Semiconductor (CMOS) type solid-state imaging device, a unit pixel is formed with a photo diode which is a light receiving unit and a plurality of transistors, and a plurality of the pixels are arranged two-dimensionally. In the CMOS type solid-state imaging device, respective electrodes of the transistors are connected to a multilayer wiring, and signal charges generated in the photo diode are read as a signal current by desired voltage pulses being applied to the electrodes of the transistors through respective wirings.

0004In addition, in a Charge Coupled Device (CCD) type solid-state imaging device, the signal charges generated in the photo diode pass through a charge transfer unit (a vertical CCD and a horizontal CCD) configured with CCDs and are supplied to a charge detection unit.

0005Further, in recent years, a back surface irradiation type imaging device has been put into practical use in which light is applied to a back surface side which is the side opposite to a front surface on which wiring layers are laminated on a device substrate in which the photo diode and the transistors are formed. In the back surface irradiation type imaging device, charges by photoelectric conversion occur most frequently in the back surface side of the device substrate. Therefore, if color mixing occurs due to leakage of electrons generated by photoelectric conversion in a vicinity of the back surface of the device substrate to adjacent pixels, a signal characteristic deteriorates, and thus suppressing the occurrence of such color mixing is important.

0006However, when the formation of impurities for performing element isolation between the photodiodes is performed by ion implantation from the front surface side of the device substrate and annealing, a method by high-energy implantation disclosed in PTL 1 is employed.

0007However, in a deep position of the back surface side far from the front surface of the device substrate to which the ion implantation is performed, ions diffuse to extend in a transverse direction. Accordingly, in a fine pixel, since an electric field in the transverse direction in the vicinity of the back surface of the device substrate is weak, it is difficult to suppress the color mixing due to the leakage of electrons generated by the photoelectric conversion to adjacent pixels.

0008Therefore, as disclosed in PTL 2, the present applicant has proposed a method which physically separates pixels by forming a trench on the back surface of the device substrate and suppresses the leakage of charges to adjacent pixels by embedding metal in the trench portion.

CITATION LIST

Patent Literature

0000<ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0009">PTL 1: Japanese Unexamined Patent Application Publication No. 2003-318122</li><li id="ul0001-0002" num="0010">PTL 2: Japanese Unexamined Patent Application Publication No. 2011-3860</li></ul>

SUMMARY OF INVENTION

Technical Problem

0011Meanwhile, in a structure disclosed in PTL 2, it is effective to form a deep trench as a method for suppressing incidence of light in an oblique direction or suppressing occurrence of shading. However, when a light shielding metal film is embedded in the deep trench which is formed, an interference characteristic deteriorates due to formation of the metal film such that noise and white spots due to a dark current occur, which results in a concern that an image quality deteriorates. Therefore, avoiding the deterioration in the image quality and suppressing the occurrence of the color mixing are required.

0012The present disclosure has been made in view of such circumstances, and is intended to be able to more reliably suppress occurrence of color mixing.

Solution to Problem

0013A solid-state imaging device according to an aspect of the present disclosure includes a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed; a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate; an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semiconductor substrate; and a light shielding portion that is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

0014A manufacturing method according to another aspect of the present disclosure includes the steps of forming a recessed portion between photoelectric conversion units so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the photoelectric conversion units, each of which receives light to generate charges, are formed; embedding an insulating film in the recessed portion and laminating the insulating film on a back surface side of the semiconductor substrate; and laminating a light shielding portion on the insulating film and forming the light shielding portion into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

0015An electronic apparatus according to still another aspect of the present disclosure includes a solid-state imaging device including a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed; a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate; an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semiconductor substrate; and a light shielding portion that is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

0016According to still another aspect of the present disclosure, a recessed portion is formed between photoelectric conversion units so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the photoelectric conversion units, each of which receives light to generate charges, are formed, an insulating film is embedded in the recessed portion and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

Advantageous Effects of Invention

0017According to the aspects of the present disclosure, it is possible to more reliably suppress occurrence of color mixing.

BRIEF DESCRIPTION OF DRAWINGS

0018<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a configuration example of an imaging device to which an embodiment of the present technology is applied.

0019<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating a cross-sectional configuration example of the imaging device.

0020<figref idref="DRAWINGS">FIG. 3</figref> is a diagram illustrating a first process of manufacturing the imaging device.

0021<figref idref="DRAWINGS">FIG. 4</figref> is a diagram illustrating a second process of manufacturing the imaging device.

0022<figref idref="DRAWINGS">FIG. 5</figref> is a diagram illustrating a third process of manufacturing the imaging device.

0023<figref idref="DRAWINGS">FIG. 6</figref> is a diagram illustrating a fourth process of manufacturing the imaging device.

0024<figref idref="DRAWINGS">FIG. 7</figref> is a diagram illustrating a fifth process of manufacturing the imaging device.

0025<figref idref="DRAWINGS">FIG. 8</figref> is a diagram illustrating a sixth process of manufacturing the imaging device.

0026<figref idref="DRAWINGS">FIG. 9</figref> is a diagram illustrating a seventh process of manufacturing the imaging device.

0027<figref idref="DRAWINGS">FIG. 10</figref> is a diagram illustrating an eighth process of manufacturing the imaging device.

0028<figref idref="DRAWINGS">FIG. 11</figref> is a diagram illustrating a ninth process of manufacturing the imaging device.

0029<figref idref="DRAWINGS">FIG. 12</figref> is a diagram illustrating a first modified example of the imaging device.

0030<figref idref="DRAWINGS">FIG. 13</figref> is a diagram illustrating a second modified example of the imaging device.

0031<figref idref="DRAWINGS">FIG. 14</figref> is a block diagram illustrating a configuration example of an imaging apparatus mounted on an electronic apparatus.

DESCRIPTION OF EMBODIMENTS

0032Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to drawings.

0033<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating a configuration example of an imaging device to which an embodiment of the present technology is applied.

0034As illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, an imaging device 11 is a CMOS-type solid-state imaging device, and is configured to include a pixel array unit 12, a vertical driving unit 13, a column processing unit 14, a horizontal driving unit 15, an output unit 16, and a driving control unit 17.

0035The pixel array unit 12 includes a plurality of pixels 21 which are arranged in an array shape, is connected to the vertical driving unit 13 through a plurality of horizontal signal lines 22 corresponding to the number of rows of the pixels 21, and is connected to the column processing unit 14 through a plurality of vertical signal lines 23 corresponding to the number of columns of the pixels 21. In other words, the plurality of pixels 21 included in the pixel array unit 12 are respectively disposed at points in which the horizontal signal lines 22 and the vertical signal lines 23 intersect.

0036The vertical driving unit 13 sequentially supplies drive signals (transfer signals, selection signals, reset signals, or the like) for driving respective pixels 21 to respective rows of the plurality of pixels 21 included in the pixel array unit 12 through the horizontal signal line 22.

0037The column processing unit 14 extracts the signal levels of the pixel signals by performing a Correlated Double Sampling (CDS) process on the pixel signals which are output from respective pixels 21 through the vertical signal line 23 and acquires pixel data corresponding to the amount of received light of the pixels 21.

0038The horizontal driving unit 15 sequentially supplies the column processing unit 14 with drive signals for outputting pixel data which is acquired from respective pixels 21 from the column processing unit 14 in number order, for each column of the plurality of pixels 21 included in the pixel array unit 12.

0039The pixel data is supplied from the column processing unit 14 to the output unit 16 at a timing corresponding to the drive signal of the horizontal driving unit 15, and the output unit 16 amplifies, for example, the pixel data and outputs the amplified pixel data to an image processing circuit in the subsequent stage.

0040The driving control unit 17 controls the driving of each block in the imaging device 11. For example, the driving control unit 17 generates a clock signal according to the driving period of each block and supplies the clock signal to each block.

0041Further, as illustrated on a right upper part of <figref idref="DRAWINGS">FIG. 1</figref>, the pixel 21 is configured to include a PD 24, a transfer transistor 25, an FD 26, an amplification transistor 27, a selection transistor 28, and a reset transistor 29.

0042The PD 24 is a photoelectric conversion unit, which receives light applied to the pixel 21 and generates charges corresponding to the amount of the light to accumulate the generated charges.

0043The transfer transistor 25 is driven according to a transfer signal supplied from the vertical driving unit 13 through the horizontal signal line 22, and when the transfer transistor 25 is turned ON, the charges accumulated in the PD 24 are transferred to the FD 26.

0044The FD 26 is a floating diffusion region having a predetermined capacity, which is formed at a connection portion between the transfer transistor 25 and a gate electrode of the amplification transistor 27, and accumulates charges transferred from the PD 24 through the transfer transistor 25.

0045The amplification transistor 27 is connected to a power potential VDD, and outputs a pixel signal of a level corresponding to charges accumulated in the FD 26 to the vertical signal line 23 through the selection transistor 28.

0046The selection transistor 28 is driven according to a selection signal supplied from the vertical driving unit 13 through the horizontal signal line 22, and when the selection transistor 28 is turned ON, the pixel signal output from the amplification transistor 27 is in a state capable of being output to the vertical signal line 23.

0047The reset transistor 29 is driven according to a reset signal supplied from the vertical driving unit 13 through the horizontal signal line 22, and when the reset transistor 29 is turned ON, the charges accumulated in the FD 26 are discharged to the power potential VDD and the FD 26 is reset.

0048In addition, in the imaging device 11 illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, although a circuit configuration is adopted in which the selection of the pixel 21 which outputs the pixel signal is performed by the selection transistor 28, a circuit structure (so-called, three-transistor structure) in which the selection transistor 28 is omitted can be employed. Further, the imaging device 11 can adopt a pixel sharing structure in which the PDs 24 and the transfer transistors 25 of a predetermined number share the FD 26, the amplification transistor 27, the selection transistor 28, and the reset transistor 29.

0049<figref idref="DRAWINGS">FIG. 2</figref> is a diagram illustrating a cross-sectional configuration example of the imaging device 11. Further, <figref idref="DRAWINGS">FIG. 2</figref> illustrates a cross-sectional view of a vicinity of three pixels 21-1 to 21-3 included in the imaging device 11.

0050The imaging device 11 performs imaging by light applied from the upper part of the <figref idref="DRAWINGS">FIG. 2</figref>, and is configured with an on-chip lens 31, a color filter 32, a light receiving layer 33, a multilayer wiring layer 34, and a supporting substrate 35, which are laminated in order from the upper part. In other words, the imaging device 11 is a so-called back surface irradiation type CMOS solid-state imaging device in which light is applied from a back surface side which is opposite to a front surface, assuming the front surface is a surface on which the multilayer wiring layer 34 is formed on the light receiving layer 33.

0051The on-chip lens 31 is formed of a small lens disposed for each of the pixels 21-1 to 21-3, and condenses light applied to the imaging device 11 to each of the PDs 24-1 to 24-3 of the pixels 21-1 to 21-3.

0052The color filter 32 is formed by disposing a filter which transmits light of a predetermined color in each of the pixels 21-1 to 21-3, and causes the light of corresponding color, among light beams applied to the imaging device 11, to be applied to the PDs 24-1 to 24-3 of pixels 21-1 to 21-3.

0053In the light receiving layer 33, for example, the PDs 24-1 to 24-3, the transfer transistors 25-1 to 25-3, and the FDs 26-1 to 26-3 are formed for each of the pixels 21-1 to 21-3, on a semiconductor substrate 41 made from a silicon wafer. Then, in the light receiving layer 33, trenches 42-1 to 42-3 are formed so as to separate the pixels 21-1 to 21-3, and a fixed charge film 43, an insulating film 44, and a planarizing film 45 are laminated. Further, in the light receiving layer 33, light shielding portions 46-1 to 46-3 are formed between the insulating film 44 and the planarizing film 45.

0054The PDs 24-1 to 24-3 are configured to be formed in such a manner that a P-type region and an N-type region are joined in the inside of the semiconductor substrate 41, and receive light which is condensed by the on-chip lens 31 and passed through the color filter 32 so as to generate charges corresponding to the amount of the light.

0055The transfer transistors 25-1 to 25-3 are respectively configured to have gate electrodes 48-1 to 48-3 which are laminated on the front surface (a surface facing the lower part of <figref idref="DRAWINGS">FIG. 2</figref>) of the semiconductor substrate 41 through the insulating films 47-1 to 47-3. The transfer transistors 25-1 to 25-3 are respectively disposed between the PDs 24-1 to 24-3 and the FDs 26-1 to 26-3. Then, if the transfer signals supplied to the gate electrodes 48-1 to 48-3 are at a high level, the charges accumulated in the PDs 24-1 to 24-3 are transferred to the FDs 26-1 to 26-3 through the corresponding transfer transistors 25-1 to 25-3.

0056The FDs 26-1 to 26-3 are dense N-type regions which are formed so as to be in contact with the front surface of the semiconductor substrate 41, and accumulates the charges transferred from the corresponding PDs 24-1 to 24-3.

0057The trenches 42-1 to 42-3 are recessed portions which are formed between the PDs 24-1 to 24-3 so as to be opened in the back surface (a surface facing the upper part of <figref idref="DRAWINGS">FIG. 2</figref>) which is a light receiving surface of the semiconductor substrate 41.

0058The fixed charge film 43 is a film having negative fixed charges which is provided in order not to deplete a silicon layer near the boundary surface in the back surface of the semiconductor substrate 41, and is formed along the shape of the back surface of the semiconductor substrate 41.

0059The insulating film 44 has an insulating property, and fills the inside of the trenches 42-1 to 42-3 while being laminated on the back surface of the semiconductor substrate 41.

0060The planarizing film 45 is a film for planarizing a surface in which the light shielding portions 46-1 to 46-3 are formed in order to laminate the color filter 32 on the light receiving layer 33.

0061The light shielding portions 46-1 to 46-3 shield the light incident on the pixels 21-1 to 21-3 in an oblique direction, thereby preventing color mixing between adjacent pixels 21-1 to 21-3 due to the light incident in the oblique direction. For example, the light shielding portion 46-1 shields the light directing the adjacent pixel 21-1 from the pixel 21-2 in the oblique direction, and prevents the light from transmitting through the color filter 32 of the pixel 21-2 and entering the PD 24-1 of the pixel 21-1.

0062Further, the light shielding portions 46-1 to 46-3 are formed into a convex shape protruding to the semiconductor substrate 41 side in order to improve the light shielding property. Further, the light shielding portions 46-1 to 46-3 are formed into lengths sufficient for preventing the leading ends from entering the trenches 42-1 to 42-3. In other words, the leading ends of the light shielding portions 46-1 to 46-3 protruding to the semiconductor substrate 41 side are formed so as to not enter the trenches 42-1 to 42-3 formed on the semiconductor substrate 41.

0063The multilayer wiring layer 34 is configured in such a manner that a plurality of layers of wirings constituting, for example, the horizontal signal line 22 and the vertical signal line 23 of <figref idref="DRAWINGS">FIG. 1</figref> are laminated between the inter-layer insulating films 51, and in the configuration example of <figref idref="DRAWINGS">FIG. 2</figref>, three layers of wirings 52-1 to 52-3 are laminated. Further, through electrodes 53-1 and 53-2 which connect wirings 52-1 to 52-3 to each other and through electrodes 54-1 to 54-3 which connect the FDs 26-1 to 26-3 and the wiring 42-1 are formed on the multilayer wiring layer 34.

0064The supporting substrate 35 is a base for ensuring the strength of the light receiving layer 33 formed as a thin film and supporting the light receiving layer 33.

0065The imaging device 11 is configured in this manner and the light shielding portion 46 shields light incident in an oblique direction, thereby preventing the light from leaking to other adjacent pixels 21 and suppressing the occurrence of color mixing. For example, in a configuration in which the light shielding portion is formed in a plane manner, in an insulating film portion of an upper layer, it is assumed that obtaining a sufficient light shielding property is difficult and suppression of the color mixing is insufficient. In contrast, in the imaging device 11, the light shielding portion 46 is formed into a convex shape protruding to the semiconductor substrate 41 side, such that even in the configuration in which the light shielding portion is formed in a plane manner, it is possible to improve light shielding property with respect to the light incident in the oblique direction. Thus, the imaging device 11 can more reliably suppress the occurrence of color mixing.

0066Further, for example, in the configuration in which the light shielding portion 46 extends to the inside of the trench 42, there is a concern that a dark current and white spots are exacerbated due to deterioration in interface characteristics. In contrast, in the imaging device 11, since the light shielding portions 46-1 to 46-3 are formed so as to not enter the trenches 42-1 to 42-3, it is possible to make improvements for the dark current and white spots, and to avoid degradation in image quality.

0067Further, since the imaging device 11 performs the element isolation between pixels 21 by filling the trench 42 with the insulating film 44, for example, even in a configuration in which the element isolation is performed by ion implantation and annealing, it is possible to more reliably perform the element isolation. Thus, it is possible to reliably prevent color mixing even if a pixel isolation region with a narrow width is formed in response to miniaturization of the imaging device 11. Further, it is possible to increase a capacity of the PD 24 in particular, and to increase the capacity of the PD 24 in a blue region in the vicinity of a light receiving surface in the imaging device 11, thereby increasing a saturation signal amount and improving a dynamic range.

0068Next, a manufacturing method of the imaging device 11 will be described with reference to <figref idref="DRAWINGS">FIGS. 3 to 11</figref>.

0069In a first process, as illustrated in <figref idref="DRAWINGS">FIG. 3</figref>, PDs 24-1 to 24-3 and FDs 26-1 to 26-3 are formed by ion implantation performed on the front surface side (upper part of <figref idref="DRAWINGS">FIG. 3</figref>) of the semiconductor substrate 41. Thereafter, transfer transistors 25-1 to 25-3 are formed by laminating the insulating films 47-1 to 47-3 and the gate electrodes 48-1 to 48-3 on the front surface of the semiconductor substrate 41. In addition, without being illustrated, the other transistors, that is, the amplification transistor 27, the selection transistor 28, and the reset transistor 29 in <figref idref="DRAWINGS">FIG. 1</figref> are also formed in the same manner as in the transfer transistor 25.

0070Then, after an inter-layer insulating film 51 is laminated, contact holes are formed on the inter-layer insulating film 51, and through electrodes 54-1 to 54-3 are formed at the contact holes so as to be connected to respective FDs 26-1 to 26-3. In addition, in the same manner, a through electrode (not illustrated) for supplying a transfer signal is formed so as to be connected to the gate electrodes 48-1 to 48-3.

0071In a second process, as illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the multilayer wiring layer 34 is formed by the wirings 52-1 to 52-3 and the through electrodes 53-1 and 53-2 are formed so as to be respectively insulated by the inter-layer insulating film 51.

0072In other words, the multilayer wiring layer 34 is formed through the following manner: after the wiring 52-1 is formed on the inter-layer insulating film 51 laminated in the first process, the inter-layer insulating film 51 is laminated and the through electrode 53-1 is formed so as to form the wiring 52-2 on the inter-layer insulating film 51, and further, the inter-layer insulating film 51 is laminated and the through electrode 53-2 is formed so as to form the wiring 52-3 on the inter-layer insulating film 51, and then the inter-layer insulating film 51 is further laminated.

0073In a third process, as illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, the supporting substrate 35 is bonded to the multilayer wiring layer 34 from the top of the multilayer wiring layer 34.

0074In a fourth process, as illustrated in <figref idref="DRAWINGS">FIG. 6</figref>, the back surface side of the semiconductor substrate 41 is inverted to face upward, and the back surface side of the semiconductor substrate 41 is scraped off with high accuracy until the semiconductor substrate 41 has a desired film thickness; for example, the bottom of a vertical type transistor which is not shown is exposed. For example, a Chemical Mechanical Polishing (CMP) method, a dry etching, a wet etching, or the like can be used for the process, and a combination of these methods can also be used.

0075In a fifth process, as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the trenches 42-1 to 42-3 are formed in an element isolation region between respective PDs 24-1 to 24-3 at a predetermined depth, for example, at a depth of about 2 μm from the back surface of the semiconductor substrate 41. For example, the dry etching can be used in forming the trenches 42-1 to 42-3.

0076In a sixth process, as illustrated in <figref idref="DRAWINGS">FIG. 8</figref>, a fixed charge film 43 is formed along the shape of the back surface of the semiconductor substrate 41. In other words, the fixed charge film 43 is formed not only on the back surface of the semiconductor substrate 41 but also on the side surfaces and the bottom surfaces of the trenches 42-1 to 42-3 formed in the semiconductor substrate 41. Further, for example, a HfO2 (hafnium oxide) film formed by an Atomic Layer Deposition (ALD) method can be used as the fixed charge film 43.

0077In seventh and eighth processes, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref> and <figref idref="DRAWINGS">FIG. 10</figref>, an insulating film 44 is formed so as to be embedded in the trenches 42-1 to 42-3. Further, a film forming method of forming the concave portions 49-1 to 49-3 in which the back surface of the insulating film 44 is concave as a V-shape, depending on the locations of trenches 42-1 to 42-3, is adopted in forming the insulating film 44. For example, the concave portions 49-1 to 49-3 are formed by forming the insulating film 44 as a two-layer structure (laminated structure) in which after an SiO2 film is formed by the ALD method, an oxide film is formed by a High Density Plasma (HDP)

0078In other words, in the seventh process, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, an insulating film 44-1 is formed by the ALD method, and in the eighth process, as illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, an insulating film 44-2 is formed by the HDP. Since the film formation and the sputtering are simultaneously performed in the film formation by the HDP, as illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the concave portions 49-1 to 49-3 of substantially V-shape linearly cutting into shoulder portions of the trenches 42-1 to 42-3 are formed.

0079In a ninth process, as illustrated in <figref idref="DRAWINGS">FIG. 11</figref>, light shielding portions 46-1 to 46-3 are formed for the insulating film 44, depending on locations at which the trenches 42-1 to 42-3 are formed. In other words, as illustrated in <figref idref="DRAWINGS">FIG. 10</figref>, the concave portions 49-1 to 49-3 are formed on the insulating film 44, depending on locations at which the trenches 42-1 to 42-3 are formed, and the light shielding portions 46-1 to 46-3 are formed along the shape of the front surface of the concave portions 49-1 to 49-3. Accordingly, the light shielding portions 46-1 to 46-3 is formed so as to have a convex shape protruding to the semiconductor substrate 41 in such a manner that the cross sectional shape is a substantially V-shape.

0080For example, the light shielding portions 46-1 to 46-3 are formed by performing a process of removing parts other than the locations which are required for a light shielding structure after metal films forming the light shielding portions 46-1 to 46-3 are formed by a sputtering method or a CVD method. Further, a laminated film of titanium (Ti) and tungsten (W), or a laminated film of titanium nitride (TiN) and tungsten (W) can be used as the light shielding portions 46-1 to 46-3. Further, the insulating film 44 is formed so as to fill the inside of the trench 42, which prevents the leading end of the light shielding portion 46 from entering the trench 42.

0081Thereafter, as illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, the light receiving layer 33 is formed by laminating the planarizing film 45, and the imaging device 11 is manufactured by laminating the color filter 32 and the on-chip lens 31 on the light receiving layer 33.

0082As described above, in the imaging device 11, the trench 42 is formed so as to perform element isolation between the PDs 24, thereby allowing the insulating film 44 to be formed in such a manner that the concave portion 49 is formed between the PDs 24. Accordingly, it is possible to easily form the light shielding portion 46 having a convex shape protruding to the semiconductor substrate 41 side, using the concave portion 49 of the insulating film 44. Thus, it is possible to manufacture the imaging device 11 capable of reliably suppressing the occurrence of color mixing.

0083In addition, the cross sectional shapes of the light shielding portions 46-1 to 46-3 may have shapes other than the substantially V-shape as illustrated in <figref idref="DRAWINGS">FIG. 2</figref>. For example, it is possible to vary the shapes of the concave portions 49-1 to 49-3 of the insulating film 44 by a film forming method, and to make the cross-sectional shapes of the light shielding portions 46-1 to 46-3 have shapes other than the substantially V-shape, depending on the shapes of the concave portions 49-1 to 49-3.

0084A first modified example of the imaging device 11 will be described with reference to <figref idref="DRAWINGS">FIG. 12</figref>. In addition, in an imaging device 11′ illustrated in <figref idref="DRAWINGS">FIG. 12</figref>, the illustration of the on-chip lens 31, the color filter 32, the multilayer wiring layer 34, and the supporting substrate 35 is omitted.

0085For example, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, in the seventh process, after the insulating film 44-1 is formed by the ALD method, as illustrated in the upper part of <figref idref="DRAWINGS">FIG. 12</figref>, in the eighth process, an insulating film 44′ is formed by forming an insulating film 44-2′ by a Plasma Tetra Ethyl Oxysilane (P-TEOS). In the film formation by the P-TEOS, the concave portions 49-1 to 49-3 are formed into a shape in which the front surface is concave in a curved shape so as to have a steep slope to the center.

0086Accordingly, thereafter, in the ninth process, when light shielding portions 46a-1 to 46a-3 are formed along the front surface shapes of the concave portions 49-1 to 49-3, as illustrated in the lower part of <figref idref="DRAWINGS">FIG. 12</figref>, the cross-sectional shape is formed in such a manner that the upper and lower surfaces have a convex shape protruding to the semiconductor substrate 41 in a curved shape.

0087In this manner, it is possible to form the light shielding portions 46-1 to 46-3 in a desired shape by the film formation method of the insulating film 44.

0088In addition, the structure of the insulating film 44 is not limited to a configuration example (refer to <figref idref="DRAWINGS">FIG. 9</figref> and <figref idref="DRAWINGS">FIG. 10</figref>) in which the insulating film 44-2 formed by the HDP is laminated on the insulating film 44-1 formed by the ALD method and a configuration example (refer to <figref idref="DRAWINGS">FIG. 12</figref>) in which the insulating film 44-2′ formed by the P-TEOS is laminated on the insulating film 44-1 formed by the ALD method. In other words, if light shielding portion 46 can be formed into a convex shape protruding to the semiconductor substrate 41, it is possible to adopt structures other than the configuration examples as the structure of the insulating film 44. For example, as the structure of the insulating film 44, a configuration in which an insulating film formed by the ALD method is laminated on the insulating film formed by the P-TEOS, a configuration of a single film formed by the P-TEOS, or a configuration of a single film formed by the ALD method may be adopted.

0089Further, the light shielding portions 46-1 to 46-3 may be formed, for example, in such a manner that after the insulating film 44 is formed to be planarized, recessed portions are formed depending on locations at which the trenches 42-1 to 42-3 are formed, and the insulating film is embedded in the recessed portion.

0090In other words, <figref idref="DRAWINGS">FIG. 13</figref> illustrates a second modified example of the imaging device 11. In addition, in an imaging device 11″ illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, the illustration of the on-chip lens 31, the color filter 32, the multilayer wiring layer 34, and the supporting substrate 35 is omitted.

0091As illustrated in <figref idref="DRAWINGS">FIG. 13</figref>, light shielding portions 46b-1 to 46b-3 are formed into cross-sectional shapes of a T-shape, depending on the recessed portions formed in the insulating film 44.

0092In this manner, the light shielding portions 46-1 to 46-3 can be formed into any cross-sectional shape of a convex shape protruding to the semiconductor substrate 41, so as to obtain a better light shielding property.

0093Further, the imaging device 11 described above can be applied to various electronic apparatuses including imaging systems such as digital still cameras and digital video cameras, mobile phones with an imaging function, or other apparatuses with an imaging function.

0094<figref idref="DRAWINGS">FIG. 14</figref> is a block diagram illustrating a configuration example of an imaging apparatus mounted on an electronic apparatus.

0095As illustrated in <figref idref="DRAWINGS">FIG. 14</figref>, an imaging apparatus 101 is configured to include an optical system 102, an imaging device 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

0096The optical system 102 is configured to include one or a plurality of lenses, and guides image light (incident light) from an object to the imaging device 103 so as to form an image on a light receiving surface (sensor unit) of the imaging device 103.

0097As the imaging device 103, the imaging devices 11 of the configuration examples and the modified examples described above are applied. Electrons are accumulated in the imaging device 103 for a fixed period, according to an image formed on the light receiving surface through the optical system 102. Thus, signals according to the electrons accumulated in the imaging device 103 are supplied to the signal processing circuit 104.

0098The signal processing circuit 104 performs various signal processes on the signal charges which are output from the imaging device 103. The image (image data) obtained by the signal processing circuit 104 performing the signal processes is supplied to and displayed on the monitor 105, or is supplied to and stored (recorded) in the memory 106.

0099In the imaging apparatus 101 configured in this manner, it is possible to obtain a good quality image in which the occurrence of color mixing is suppressed, by applying the imaging device 11 of the configuration examples or the modified examples as described above as the imaging device 103.

0100In addition, the imaging device 11 can also be applied to a front surface irradiation type CMOS solid-state imaging device in which incidence light is applied from a front surface side on which the multilayer wiring layer 34 is formed on the light receiving layer 33, and the light shielding portion 46 is formed between the light receiving layer 33 and the multilayer wiring layer 34.

0101In addition, the present technology may have the following configurations.

0102(1)

0103A solid-state imaging device including:

0104a semiconductor substrate on which a plurality of photoelectric conversion units, each of which receives light to generate charges, are formed;

0105a recessed portion that is formed between the photoelectric conversion units so as to be opened to a light receiving surface side of the semiconductor substrate;

0106an insulating film which is embedded in the recessed portion and laminated on the back surface side of the semiconductor substrate; and

0107a light shielding portion that is laminated on the insulating film and is formed into a convex shape protruding to the semiconductor substrate at a location corresponding to the recessed portion.

0108(2)

0109The solid-state imaging device according to (1),

0110in which the light shielding portion is formed into a length sufficient to prevent a leading end on the semiconductor substrate side from entering the recessed portion.

0111(3)

0112The solid-state imaging device according to (1) or (2),

0113in which when the insulating film is formed, a concave portion in which a surface of the insulating film is concave is formed, depending on a location of the recessed portion.

0114(4)

0115The solid-state imaging device according to any one of (1) to (3),

0116in which the insulating film is configured as a laminated structure in which a plurality of layers are laminated.

0117(5)

0118The solid-state imaging device according to any one of (1) to (4),

0119in which with respect to the light receiving surface of the semiconductor substrate in which the recessed portion is formed, after a fixed charge film having negative fixed charges is formed, the insulating film is formed.

0120(6)

0121The solid-state imaging device according to any one of (1) to (5),

0122in which light is applied to a back surface which is a side opposite to a front surface on which a wiring layer is laminated on the semiconductor substrate.

0123In addition, the present embodiments are not limited to the embodiments described above, and various modifications are possible without departing from the scope of the present disclosure.

REFERENCE SIGNS LIST

0000<ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0000"><ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0124">11 IMAGING DEVICE</li><li id="ul0003-0002" num="0125">12 PIXEL ARRAY UNIT</li><li id="ul0003-0003" num="0126">13 VERTICAL DRIVING UNIT</li><li id="ul0003-0004" num="0127">14 COLUMN PROCESSING UNIT</li><li id="ul0003-0005" num="0128">15 HORIZONTAL DRIVING UNIT</li><li id="ul0003-0006" num="0129">16 OUTPUT UNIT</li><li id="ul0003-0007" num="0130">17 DRIVING CONTROL UNIT</li><li id="ul0003-0008" num="0131">21 PIXEL</li><li id="ul0003-0009" num="0132">22 HORIZONTAL SIGNAL LINE</li><li id="ul0003-0010" num="0133">23 VERTICAL SIGNAL LINE</li><li id="ul0003-0011" num="0134">24 PD</li><li id="ul0003-0012" num="0135">25 TRANSFER TRANSISTOR</li><li id="ul0003-0013" num="0136">26 FD</li><li id="ul0003-0014" num="0137">27 AMPLIFICATION TRANSISTOR</li><li id="ul0003-0015" num="0138">28 SELECTION TRANSISTOR</li><li id="ul0003-0016" num="0139">29 RESET TRANSISTOR</li><li id="ul0003-0017" num="0140">31 ON-CHIP LENS</li><li id="ul0003-0018" num="0141">32 COLOR FILTER</li><li id="ul0003-0019" num="0142">33 LIGHT RECEIVING LAYER</li><li id="ul0003-0020" num="0143">34 MULTILAYER WIRING LAYER</li><li id="ul0003-0021" num="0144">35 SUPPORTING SUBSTRATE</li><li id="ul0003-0022" num="0145">41 SEMICONDUCTOR SUBSTRATE</li><li id="ul0003-0023" num="0146">42 TRENCH</li><li id="ul0003-0024" num="0147">43 CHARGE FILM</li><li id="ul0003-0025" num="0148">44 INSULATING FILM</li><li id="ul0003-0026" num="0149">45 PLANARIZING FILM</li><li id="ul0003-0027" num="0150">46 LIGHT SHIELDING PORTION</li><li id="ul0003-0028" num="0151">47 INSULATING FILM</li><li id="ul0003-0029" num="0152">48 GATE ELECTRODE</li><li id="ul0003-0030" num="0153">49 CONCAVE PORTION</li></ul></li></ul>

Contents8

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Document	Relation	Office	Cited during
US2016126276A1	Cited by	United States of America	Pre-grant
US10276624B2	Cited by	United States of America	Search report
US9247173B2	Cited by	United States of America	Search report
US2017148840A1	Cited by	United States of America	Pre-grant
US10593721B2	Cited by	United States of America	Search report
US10002902B2	Cited by	United States of America	Search report
US9590003B2	Cited by	United States of America	Search report
US2019252452A1	Cited by	United States of America	Search report
US2015189211A1	Cited by	United States of America	Pre-grant
JP2006019653A	Cites	Japan	Applicant
JP2011151126A	Cites	Japan	Applicant
JP2011216826A	Cites	Japan	Applicant
JP2011243996A	Cites	Japan	Applicant
US8928784B2	Cites	United States of America	Search report
JP2006019653A	Cites	Japan	Applicant
JP2011151126A	Cites	Japan	Applicant
JP2011216826A	Cites	Japan	Applicant
JP2011243996A	Cites	Japan	Applicant
International Search Report prepared by the Japanese Patent Office on Feb. 5, 2013, for International Application No. PCT/JP2013/050406.	Non-patent	–	Applicant
International Search Report prepared by the Japanese Patent Office on Feb. 5, 2013, for International Application No. PCT/JP2013/050406.	Non-patent	–	Applicant

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2012011125	Japan	–	2012-01-23
2012011125	Japan	A	2012-01-23
2013050406	Japan	W	2013-01-11

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WO2013111628A1	World Intellectual Property Organization (WIPO)	A1	2013-08-01
CN104067393A	China	A	2014-09-24
KR20140127215A	Republic of Korea	A	2014-11-03
US2015028442A1	United States of America	A1	2015-01-29
JPWO2013111628A1	Japan	A1	2015-05-11
US9105539B2This record	United States of America	B2	2015-08-11
US2015255496A1	United States of America	A1	2015-09-10
US9184201B2	United States of America	B2	2015-11-10
US2016013225A1	United States of America	A1	2016-01-14
US9368532B2	United States of America	B2	2016-06-14
US2016211289A1	United States of America	A1	2016-07-21
JP5971261B2	Japan	B2	2016-08-17
CN105938841A	China	A	2016-09-14
US9461085B2	United States of America	B2	2016-10-04
US2016372508A1	United States of America	A1	2016-12-22
KR20170104009A	Republic of Korea	A	2017-09-13
US9812481B2	United States of America	B2	2017-11-07
US2018019276A1	United States of America	A1	2018-01-18
CN104067393B	China	B	2018-06-12
CN105938841B	China	B	2019-01-29
US10332922B2	United States of America	B2	2019-06-25
KR102031470B1	Republic of Korea	B1	2019-10-11
KR20190116567A	Republic of Korea	A	2019-10-14
KR102221993B1	Republic of Korea	B1	2021-03-02

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Solid-state imaging device and manufacturing method of the same, and electronic apparatus

Summary by NHIP

Claim Score by NHIP

Abstract