Devices and methodologies related to structures having HBT and FET

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is a continuation-in-part of U.S. patent application Ser. No. 12/939,474, filed on Nov. 4, 2010, entitled “BIPOLAR AND FED DEVICE STRUCTURE,” the benefits of the filing date of which is hereby claimed and the specification of which is incorporated herein by this reference.

BACKGROUND

0002In some semiconductor material systems it is possible to combine different device technologies on a single semiconductor die to form hybrid structures. For example, in certain material systems, it is possible to integrate a heterojunction bipolar transistor (HBT) with a field effect transistors (FET) on a single substrate, to fabricate what is referred to as a BiFET. Devices, such as RF power amplifiers, can be fabricated using BiFET technology to have increased design flexibility. As a result, a BiFET power amplifier including an HBT and a FET can be advantageously designed to operate at a lower reference voltage than a bipolar transistor power amplifier. Of particular interest to device manufacturers are high power BiFET amplifiers, which can be formed by integrating a FET into a gallium arsenide (GaAs) HBT process. However, previous attempts to integrate a FET into a GaAs HBT process have resulted only in an n-type FET device.

0003Therefore, it would be desirable to have a BiFET device structure that includes a p-type FET device, and that may include complementary n-type and p-type FET devices.

SUMMARY

0004Embodiments of a semiconductor structure include a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer comprising a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET comprising a channel formed in the semiconductor material that forms the collector layer of the HBT.

0005In some embodiments, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some embodiments, the semiconductor structure can further include an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. In some embodiments, such an etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such an etch stop layer can include any material with etch selectivity to, for example, the channel layer of the FET. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

0006In accordance with some embodiments, the present disclosure relates to a semiconductor structure having a heterojunction bipolar transistor (HBT) that includes a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The semiconductor structure further includes a first field effect transistor (FET) located over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The semiconductor structure further includes a second field effect transistor (FET) located over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

0007In some embodiments, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some embodiments, semiconductor structure can further include a first etch stop layer segment located over the collector layer of the HBT and the channel of the first FET, and a second etch stop layer segment located over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, such etch stop layers can include any material with etch selectivity to, for example, the channel layers of the first and second FETs. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaAs or InGaP.

0008In a number of implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate and an emitter layer located over the substrate. The collector layer includes a first semiconductor material of a first conductivity type (P), and the emitter layer includes a second semiconductor material of a second conductivity type (N). The method further includes forming a first field effect transistor (FET) over the substrate. The first FET includes a channel formed in the first semiconductor material that forms the collector layer of the HBT. The method further includes forming a second field effect transistor (FET) over the substrate. The second FET includes a channel formed in the second semiconductor material that forms the emitter layer of the HBT.

0009In some implementations, the first semiconductor material that forms the collector layer of the HBT and the channel of the first FET can include p-type gallium arsenide, and the second semiconductor material that forms the emitter layer of the HBT and the channel of the second FET can include n-type gallium arsenide. In some implementations, the method can further include forming a first etch stop layer segment over the collector layer of the HBT and the channel of the first FET, and forming a second etch stop layer segment over the emitter layer of the HBT and the channel of the second FET. The first etch stop layer segment and the second etch stop layer segment can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

0010According to some implementations, the present disclosure relates to a method that includes forming a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate. The collector layer includes a semiconductor material. The method further includes forming a field effect transistor (FET) located over the substrate. The FET includes a channel formed in the semiconductor material that forms the collector layer of the HBT.

0011In some implementations, the semiconductor material that forms the collector layer of the HBT and the channel of the FET can include p-type gallium arsenide. In some implementations, the method can further include forming an etch stop layer segment located over the collector layer of the HBT and the channel of the FET. The etch stop layer can include indium gallium arsenide (InGaAs) or indium gallium phosphide (InGaP), and can have a thickness range between 10 nanometers (nm) and 15 nm.

0012According to some embodiments, the present disclosure relates to a die having an integrated circuit (IC). The die includes a circuit configured to process radiofrequency (RF) signal. The die further includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the circuit. The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

0013In some embodiments, the circuit configured to process RF signal can include a power amplifier circuit, a controller circuit for the power amplifier circuit, or a controller for a switching circuit. In some embodiments, the assembly can further include a second FET having a channel located over the substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET, and the second FET can include an nFET. In some embodiments, the substrate can include gallium arsenide (GaAs).

0014In a number of embodiments, the present disclosure relates to a packaged module for a radiofrequency (RF) device. The module includes a packaging substrate and an integrated circuit (IC) formed on a die and mounted on the packaging substrate. The IC includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) configured to facilitate operation of the IC. The HBT includes a collector layer including a semiconductor material located over a die substrate. The FET includes a channel located over the die substrate and formed in the semiconductor material that forms the collector layer of the HBT. The module further includes one or more connections configured to facilitate transfer of power to the IC and RF signals to and from the IC.

0015In some embodiments, the assembly can further include a second FET having a channel located over the die substrate and formed in same semiconductor material as an emitter of the HBT. The first FET can include a pFET and the second FET can include an nFET.

0016In accordance with some embodiments, the present disclosure relates to a wireless device having an antenna and a radiofrequency integrated circuit (RFIC) configured to process RF signals received from the antenna and for transmission through the antenna. The wireless device further includes a power amplifier (PA) circuit configured to amplify the RF signals. The PA circuit includes an assembly of a heterojunction bipolar transistor (HBT) and a field effect transistor (FET). The HBT includes a collector layer including a semiconductor material located over a substrate. The FET includes a channel located over the substrate and formed in the semiconductor material that forms the collector layer of the HBT.

0017In some embodiments, the PA can be configured to operate as a high power BiFET amplifier capable of operating at a lower reference voltage than that of a bipolar transistor PA. In some embodiments, the substrate can include gallium arsenide (GaAs).

0018Other embodiments are also provided. Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

BRIEF DESCRIPTION OF THE FIGURES

0019The invention can be better understood with reference to the following figures. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.

0020<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram illustrating a cross-sectional view of an exemplary structure including an exemplary BiFET.

0021<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram illustrating a cross-sectional view of an alternative embodiment of the structure of <figref idref="DRAWINGS">FIG. 1</figref>.

0022<figref idref="DRAWINGS">FIG. 3</figref> shows a process that can be implemented to fabricate the example structure of <figref idref="DRAWINGS">FIG. 1</figref>.

0023<figref idref="DRAWINGS">FIG. 4</figref> shows a process that can be implemented to fabricate the example structure of <figref idref="DRAWINGS">FIG. 2</figref>.

0024<figref idref="DRAWINGS">FIG. 5</figref> shows a process that can be implemented to fabricate the example HBTs of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

0025<figref idref="DRAWINGS">FIG. 6</figref> shows a process that can be implemented to fabricate the example FET of <figref idref="DRAWINGS">FIG. 1</figref> and the first FET of <figref idref="DRAWINGS">FIG. 2</figref>.

0026<figref idref="DRAWINGS">FIG. 7</figref> shows a process that can be implemented to fabricate the example second FET of <figref idref="DRAWINGS">FIG. 2</figref>.

0027<figref idref="DRAWINGS">FIG. 8</figref> shows that in some embodiments, a semiconductor die having a circuit, such as a power amplifier (PA) circuit, can include a BiFET device having one or more features as described herein.

0028<figref idref="DRAWINGS">FIG. 9</figref> shows that in some embodiments, a semiconductor die having a PA controller and/or a switch controller circuit can include a BiFET device having one or more features as described herein.

0029<figref idref="DRAWINGS">FIG. 10</figref> shows that in some embodiments, a packaged module can include a die having one or more features as described herein.

0030<figref idref="DRAWINGS">FIG. 11</figref> shows that in some embodiments, a wireless device can include a module, such as the packaged module <figref idref="DRAWINGS">FIG. 10</figref>, having one or more features as described herein.

DETAILED DESCRIPTION

0031Although described with particular reference to a device fabricated in the gallium arsenide (GaAs) material system, the structures described herein can be fabricated using other III-V semiconductor materials, such as indium phosphide (InP) and gallium nitride (GaN). Further, any of a variety of semiconductor growth, formation and processing technologies can be used to form the layers and fabricate the structure or structures described herein. For example, the semiconductor layers can be formed using molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), which is also sometimes referred to as organic metallic vapor phase epitaxy (OMVPE), or any other technique. Moreover, the thicknesses of the various semiconductor layers described below are approximate, and may range to thinner or thicker than that described. Similarly, the doping levels of the doped semiconductor layers described below are relative.

0032The present invention is directed to a semiconductor structure that includes a bipolar device, such as a heterojunction bipolar transistor (HBT), and a p-type field effect transistor (pFET) integrated on a common substrate, referred to generally as a BiFET, and formed in a GaAs material system. Embodiments also include a complementary BiFET (BiCFET) including a p-type FET (pFET) and an n-type FET (nFET) integrated with an HBT in a GaAs material system. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention.

0033The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. Certain details and features have been left out of the drawings, which will be apparent to a person of ordinary skill in the art. Although structure <b>100</b> illustrates an exemplary BiFET comprising an NPN HBT and a pFET, which are situated over a substrate in a semiconductor die, the present invention may also apply to a BiFET comprising a PNP HBT and an NFET; an NPN HBT and both an nFET and a pFET; and a PNP HBT and both an nFET and a pFET.

0034<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram illustrating a cross-sectional view of an exemplary structure including an exemplary BiFET in accordance with one embodiment of the present invention. Certain details and features have been left out of <figref idref="DRAWINGS">FIG. 1</figref>, which are apparent to a person of ordinary skill in the art. The structure <b>100</b> includes BiFET <b>102</b>, isolation regions <b>110</b>, <b>112</b>, and <b>114</b>, and substrate <b>108</b>, which can be a semi-insulating GaAs substrate. The BiFET <b>102</b> includes an HBT <b>104</b>, which is located over substrate <b>108</b> between isolation regions <b>110</b> and <b>112</b>, and pFET <b>106</b>, which is located over substrate <b>108</b> between isolation regions <b>112</b> and <b>114</b>. Isolation regions <b>110</b>, <b>112</b>, and <b>114</b> provide electrical isolation from other devices on substrate <b>108</b> and can be formed in a manner known in the art.

0035The HBT <b>104</b> includes sub-collector layer <b>116</b>, a first collector layer segment <b>118</b>, a second collector layer segment <b>119</b>, an optional etch-stop layer segment <b>121</b>, a base layer segment <b>122</b>, an emitter layer segment <b>124</b>, an emitter cap layer segment <b>126</b>, a bottom contact layer segment <b>132</b>, a top contact layer segment <b>134</b>, collector contact <b>136</b>, base contacts <b>138</b>, and emitter contact <b>142</b>.

0036For the purpose of description herein, an emitter can include one or more parts associated with an emitter stack. In the example HBT configuration <b>104</b> of <figref idref="DRAWINGS">FIG. 1</figref>, such an emitter stack can include the emitter layer <b>124</b>, the emitter cap layer <b>126</b>, the bottom contact layer <b>132</b>, and the top contact layer <b>134</b>. Accordingly, an emitter as described herein can include the emitter layer <b>124</b> and/or the emitter cap layer <b>126</b>.

0037Also for the purpose of description herein, the example HBT topology is described in the context of GaAs/InGaP. It will be understood, however, that one or more features of the present disclosure can also be applied to other material systems used for HBTs, including, for example, indium phosphide (InP), antimonides, or nitride based materials.

0038The pFET <b>106</b> includes a back gate contact <b>113</b>, a lightly doped N type GaAs segment <b>152</b>, a lightly doped P type GaAs segment <b>154</b>, an optional etch stop layer segment <b>156</b>, typically comprising lightly doped N type or P type InGaP, source contact layer <b>158</b> and drain contact layer <b>162</b>, typically comprising heavily doped P type GaAs, gate contact <b>164</b>, source contact <b>166</b>, and drain contact <b>168</b>. Alternatively, the optional etch stop layer segment <b>156</b> can be undoped. In the present embodiment, the HBT <b>104</b> can be an NPN HBT integrated in a complementary arrangement with the pFET <b>106</b>. In another embodiment, the HBT <b>104</b> can be a PNP HBT integrated with an nFET, or can be a PNP HBT or an NPN HBT integrated with the pFET <b>106</b> and with an nFET. In the present embodiment, the pFET <b>106</b> can be a depletion mode FET or an enhancement mode FET.

0039The sub-collector layer <b>116</b> is situated on substrate <b>108</b> and can comprise heavily doped N type GaAs. The sub-collector layer <b>116</b> can be formed by using a metal organic chemical vapor deposition (MOCVD) process or other processes. The first collector layer segment <b>118</b> and the collector contact <b>136</b> are located on the sub-collector layer <b>116</b>. The first collector layer segment <b>118</b> can comprise lightly doped N type GaAs. The second collector layer segment <b>119</b> can comprise lightly doped P type GaAs. The first collector layer segment <b>118</b> and the second collector layer segment <b>119</b> can be formed by using a MOCVD process or other processes. The collector contact <b>136</b> can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the sub-collector layer <b>116</b>.

0040The optional etch stop layer segment <b>121</b> can be located on the second collector layer segment <b>119</b> and can comprise lightly doped N type or P type InGaP. Alternatively, the optional etch stop layer segment <b>121</b> can be undoped. The etch stop layer segment <b>121</b> can be formed by using a MOCVD process or other processes.

0041The base layer segment <b>122</b> is located on the etch stop layer segment <b>121</b> and can comprise heavily doped P type GaAs. The base layer segment <b>122</b> can be formed by using a MOCVD process or other processes.

0042The emitter layer segment <b>124</b> and base contacts <b>138</b> are located on base layer segment <b>122</b>. The emitter layer segment <b>124</b> can comprise lightly doped N type indium gallium phosphide (InGaP) and can be formed on the base layer segment <b>122</b> by using a MOCVD process or other processes. The base contacts <b>138</b> can comprise an appropriate metal or combination of metals, which can be deposited and patterned over base layer segment <b>122</b>. The emitter cap layer segment <b>126</b> is located on the emitter layer segment <b>124</b> and can comprise lightly doped N type GaAs. The emitter cap layer segment <b>126</b> can be formed by using a MOCVD process or other processes.

0043The bottom contact layer segment <b>132</b> is located on the emitter cap layer segment <b>126</b> and can comprise heavily doped N type GaAs. The bottom contact layer segment <b>132</b> can be formed by using an MOCVD process or other processes.

0044The top contact layer segment <b>134</b> is situated on the bottom contact layer segment <b>132</b> and can comprise heavily doped N type indium gallium arsenide (InGaAs). The top contact layer segment <b>134</b> can be formed by using a MOCVD process or other processes. The emitter contact <b>142</b> is located on the top contact layer segment <b>134</b> and can comprise an appropriate metal or combination of metals, which can be deposited and patterned over top contact layer segment <b>134</b>.

0045During operation of the HBT <b>104</b>, current flows from the emitter contact <b>142</b>, through the top contact layer segment <b>134</b>, bottom contact layer segment <b>132</b>, emitter cap layer segment <b>126</b>, emitter layer segment <b>124</b>, and into the base layer segment <b>122</b> and is indicated by arrow <b>137</b>.

0046To form the pFET <b>106</b> in the collector of the HBT <b>104</b>, a lightly doped P type GaAs layer segment <b>154</b> is located over a lightly doped N type GaAs layer segment <b>152</b>, which is located over a heavily doped N type GaAs layer segment <b>151</b>. A back gate contact <b>113</b> is formed on the heavily doped N type GaAs layer segment <b>151</b> to create a back gate for the pFET <b>106</b>. The back gate contact <b>113</b> can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped N type GaAs layer segment <b>151</b>.

0047The lightly doped N type GaAs layer segment <b>152</b> is substantially similar in composition and formation to the first collector layer segment <b>118</b> discussed above. The lightly doped P type GaAs layer segment <b>154</b> is substantially similar in composition and formation to the second collector layer segment <b>119</b> discussed above.

0048The lightly doped P type GaAs layer segment <b>154</b> forms the channel of the pFET <b>106</b>. The etch stop layer segment <b>156</b> is situated on the lightly doped P type GaAs layer segment <b>154</b> and can comprise lightly doped N type or P type InGaP. Alternatively, the etch stop layer segment <b>156</b> can be undoped. The etch stop layer segment <b>156</b> can be formed on the lightly doped P type GaAs layer segment <b>154</b> by using a MOCVD process or other appropriate processes. If implemented, the etch stop layer segment <b>156</b> can have a thickness between approximately 10 nanometers (nm) and approximately 15 nm. In one embodiment, the pFET <b>106</b> can be an enhancement mode FET and the etch stop layer segment <b>156</b> can have a thickness less than 10 nm.

0049The source contact layer <b>158</b> and the drain contact layer <b>162</b> are located on the etch stop layer segment <b>156</b> and can comprise heavily doped P type GaAs to form source and drain regions, respectively. The source and drain contact layers <b>158</b> and <b>162</b> can be formed by using a MOCVD process or other processes. A source contact <b>166</b> and drain contact <b>168</b> are located on the etch stop layer segment <b>156</b>. Source contact <b>166</b> and drain contact <b>168</b> can comprise platinum gold (“PtAu”) or other appropriate metals and can be formed in a manner known in the art. A gate contact <b>164</b> is located on the etch stop layer segment <b>156</b> in gap <b>165</b>, which is formed between source and drain contact layers <b>158</b> and <b>162</b>, and can comprise an appropriate metal or combination of metals. The gap <b>165</b> can be formed by utilizing an appropriate etch chemistry to selectively etch through a layer of InGaAs and a layer of GaAs and stop on etch stop layer segment <b>156</b>. After the gap <b>165</b> has been formed, gate contact <b>164</b> can be formed on etch stop layer segment <b>156</b> in a manner known in the art. In one embodiment, the FET <b>106</b> can be an enhancement mode FET and gate contact <b>164</b> can be formed directly on the lightly doped P type GaAs layer segment <b>154</b>. In that embodiment, an appropriate etch chemistry can be utilized to selectively etch through etch stop layer segment <b>156</b> and stop on lightly doped P type GaAs layer segment <b>154</b>.

0050Thus, by forming the pFET <b>106</b> in the layers that comprise the collector of the HBT <b>104</b>, a pFET can be integrated with an NPN HBT, yielding a complementary BiFET.

0051<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram illustrating a cross-sectional view of an alternative embodiment of the structure of <figref idref="DRAWINGS">FIG. 1</figref>. The structure <b>200</b> shown in <figref idref="DRAWINGS">FIG. 2</figref> includes a BiCFET structure that includes an HBT <b>204</b>, a pFET <b>206</b> and an nFET <b>207</b>.

0052Elements and structures in <figref idref="DRAWINGS">FIG. 2</figref> that are similar to corresponding elements and structures in <figref idref="DRAWINGS">FIG. 1</figref> will not be described again in detail, but instead, will be referred to using the nomeclature <b>2</b>XX, where “XX” refers to a similar element in <figref idref="DRAWINGS">FIG. 1</figref>.

0053The BiCFET <b>202</b> includes an HBT <b>204</b> located between isolation region <b>210</b> and isolation region <b>212</b>, a pFET <b>206</b> located between isolation region <b>212</b> and <b>214</b>, and includes an nFET <b>207</b> located between isolation region <b>214</b> and isolation region <b>215</b>.

0054The HBT <b>204</b> includes sub-collector layer <b>216</b>, a first collector layer segment <b>218</b>, a second collector layer segment <b>219</b>, an optional etch-stop layer segment <b>221</b>, a base layer segment <b>222</b>, an emitter layer segment <b>224</b>, an emitter cap layer segment <b>226</b>, a second optional etch stop layer <b>228</b>, a bottom contact layer segment <b>232</b>, a top contact layer segment <b>234</b>, collector contact <b>236</b>, base contacts <b>238</b>, and emitter contact <b>242</b>.

0055As description herein, an emitter can include one or more parts associated with an emitter stack. In the example HBT configuration <b>204</b> of <figref idref="DRAWINGS">FIG. 2</figref>, such an emitter stack can include the emitter layer <b>224</b>, the emitter cap layer <b>226</b>, second etch stop layer <b>228</b>, the bottom contact layer <b>232</b>, and the top contact layer <b>234</b>. Accordingly, an emitter as described herein can include the emitter layer <b>224</b> and/or the emitter cap layer <b>226</b>.

0056As also described herein, the example HBT topology is described in the context of GaAs/InGaP. It will be understood, however, that one or more features of the present disclosure can also be applied to other material systems used for HBTs, including, for example, indium phosphide (InP), antimonides, or nitride based materials.

0057The pFET <b>206</b> comprises a lightly doped P type GaAs layer segment <b>254</b> located over a lightly doped N type GaAs layer segment <b>252</b>, which is located over a heavily doped N type GaAs layer segment <b>251</b>. A back gate contact <b>213</b> is formed on the heavily doped N type GaAs layer segment <b>251</b> to create a back gate for the pFET <b>206</b>. The back gate contact <b>213</b> can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped N type GaAs layer segment <b>251</b>.

0058The lightly doped P type GaAs layer segment <b>254</b> forms the channel of the pFET <b>206</b>. The etch stop layer segment <b>256</b> is situated on the lightly doped P type GaAs layer segment <b>254</b> and can comprise lightly doped N type or P type InGaP. Alternatively, the optional etch stop layer segment <b>256</b> can be undoped. The etch stop layer segment <b>256</b> can be formed on the lightly doped P type GaAs layer segment <b>254</b> by using a MOCVD process or other appropriate processes. If implemented, the etch stop layer segment <b>256</b> can have a thickness between approximately 10 nanometers (nm) and approximately 15 nm. The source contact layer <b>258</b> and the drain contact layer <b>262</b> are located on the etch stop layer segment <b>256</b> and can comprise heavily doped P type GaAs to form source and drain regions, respectively. A source contact <b>266</b> and drain contact <b>268</b> are located on the etch stop layer segment <b>256</b>. A gate contact <b>264</b> is located on the etch stop layer segment <b>256</b> in gap <b>285</b>, which is formed between source and drain regions <b>258</b> and <b>262</b>, and can comprise an appropriate metal or combination of metals.

0059To form the nFET <b>207</b> in the layers that comprise the emitter of the HBT <b>104</b>, a lightly doped P type GaAs layer segment <b>255</b> is located over a lightly doped N type GaAs layer segment <b>253</b>, which is located over the heavily doped N type GaAs layer segment <b>251</b>. The lightly doped N type GaAs layer segment <b>253</b> is substantially similar in composition and formation to the first collector layer segment <b>118</b> discussed above. The lightly doped P type GaAs layer segment <b>255</b> is substantially similar in composition and formation to the second collector layer segment <b>119</b> discussed above.

0060An etch stop layer segment <b>257</b> is located on the lightly doped P type GaAs layer segment <b>255</b> and is similar to the etch stop layer segment <b>256</b>.

0061A heavily doped P type GaAs layer segment <b>259</b> is located on the etch stop layer segment <b>257</b> and is substantially similar in composition and formation to base layer segment <b>122</b> discussed above. A back gate contact <b>260</b> is formed on the heavily doped P type GaAs layer segment <b>259</b> to create a back gate for the nFET <b>207</b>. The back gate contact <b>260</b> can comprise an appropriate metal or combination of metals, which can be deposited and patterned over the heavily doped P type GaAs layer segment <b>259</b>. A lightly doped N type InGaP segment <b>261</b> is located on the heavily doped P type GaAs segment <b>259</b> and is substantially similar in composition and formation to the emitter layer segment <b>124</b> discussed above.

0062A lightly doped N type GaAs layer segment <b>263</b> is located on the lightly doped N type InGaP layer segment <b>261</b> and is substantially similar in composition and formation to the emitter cap layer segment <b>126</b> discussed above. The lightly doped N type GaAs layer segment <b>263</b> forms a channel for the nFET <b>207</b>. The second optional etch stop layer segment <b>267</b> is located on the lightly doped N type GaAs layer segment <b>263</b> and can comprise lightly doped N type or P type InGaP. Alternatively, the second optional etch stop layer segment <b>267</b> can be undoped. The second optional etch stop layer segment <b>267</b> can be formed on the lightly doped N type GaAs layer segment <b>263</b> by using a MOCVD process or other appropriate processes. In an embodiment, the second optional etch stop layer segment <b>267</b> can have a thickness between approximately 10 nm and approximately 15 nm. In an embodiment, the nFET <b>207</b> can be an enhancement mode FET and the etch stop layer segment <b>267</b> can have a thickness less than 10 nm.

0063A source region <b>269</b> and drain region <b>271</b> are located on the second optional etch stop layer segment <b>267</b> and can comprise heavily doped N type GaAs. The source region <b>269</b> and the drain region <b>271</b> can be formed by using a MOCVD process or other processes. Contact layer segments <b>273</b> and <b>275</b> are located on source and drain regions <b>269</b> and <b>271</b>, respectively, and can comprise heavily doped N type InGaAs. Contact layer segments <b>273</b> and <b>275</b> can be formed by using a MOCVD process or other processes.

0064A source contact <b>277</b> and a drain contact <b>279</b> are located on top contact layer segments <b>271</b> and <b>273</b>, respectively. A gate contact <b>281</b> is located on the second optional etch stop layer segment <b>267</b> in gap <b>285</b>. Gap <b>285</b> can be formed by utilizing an appropriate etch chemistry to selectively etch through a layer of InGaAs and a layer of GaAs and stop on second optional etch stop layer segment <b>267</b>. After gap <b>285</b> has been formed, gate contact <b>281</b> can be formed on the second optional etch stop layer segment <b>267</b> in a manner known in the art. In an embodiment, the nFET <b>207</b> can be an enhancement mode FET and gate contact <b>281</b> can be formed directly on lightly doped N type GaAs layer segment <b>263</b>. In that embodiment, an appropriate etch chemistry can be utilized to selectively etch through the second optional etch stop layer segment <b>267</b> and stop on lightly doped N type GaAs layer segment <b>263</b>.

0065Accordingly, a BiCFET can be fabricated that includes complementary pFET <b>206</b> and nFET <b>207</b>, formed on a GaAs substrate along with either an NPN or a PNP HBT.

0066In some embodiments as described herein, some or all of the etch stop layers (e.g., <b>121</b>, <b>156</b>, <b>221</b>, <b>228</b>, <b>256</b>, <b>257</b> and <b>267</b>) can include indium gallium phosphide (InGaP) or indium gallium arsenide (InGaAs). Such an etch stop layer can have a thickness range between 10 nanometers (nm) and 15 nm. Other thickness ranges can also be implemented. In some embodiments, some or all of the foregoing etch stop layers can include any material with etch selectivity to, for example, a channel of an FET. Such a material can be implemented in an appropriate thickness or within an appropriate range of thicknesses so as to achieve similar results as the foregoing example materials InGaP or InGaAs.

0067<figref idref="DRAWINGS">FIG. 3</figref> shows a process <b>300</b> that can be implemented to fabricate the example BiFET <b>102</b> of <figref idref="DRAWINGS">FIG. 1</figref> or a portion of the example BiCFET <b>202</b> of <figref idref="DRAWINGS">FIG. 2</figref>. In block <b>302</b>, a semiconductor substrate can be provided. In some embodiments, such a semiconductor layer can include one or more layers disclosed herein, including a semi-insulating GaAs layer such as the example layers <b>108</b> and <b>208</b> of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. In block <b>304</b>, a heterojunction bipolar transistor (HBT) can be formed so as to include a collector layer disposed over the substrate. In some embodiments, such a collector layer can include one or more layers disclosed herein, including a p− GaAs layer (<b>119</b> in <figref idref="DRAWINGS">FIG. 1 and 219</figref> in <figref idref="DRAWINGS">FIG. 2</figref>). In block <b>306</b>, a field effect transistor (FET) can be formed so as to include a channel region disposed over the substrate and formed from the same material as the collector layer of the HBT. In some embodiments, such a channel region can include one or more layers disclosed herein, including the p− GaAs layer (<b>154</b> in <figref idref="DRAWINGS">FIG. 1 and 254</figref> in <figref idref="DRAWINGS">FIG. 2</figref>). In some implementations, other structures associated with the HBT (e.g., base, emitter and contacts) and the FET (e.g., source, drain and contacts) can be formed.

0068<figref idref="DRAWINGS">FIG. 4</figref> shows a process <b>310</b> that can be implemented to fabricate the example BiCFET <b>202</b> of <figref idref="DRAWINGS">FIG. 2</figref>. In block <b>312</b>, a semiconductor substrate can be provided. In some embodiments, such a semiconductor layer can include one or more layers disclosed herein, including a semi-insulating GaAs layer such as the example layer <b>208</b> of <figref idref="DRAWINGS">FIG. 2</figref>. In block <b>314</b>, a sub-collector layer can be formed over the substrate layer. In some embodiments, such a sub-collector layer can include one or more layers disclosed herein, including the n+ GaAs layer (<b>216</b> and/or <b>251</b> in <figref idref="DRAWINGS">FIG. 2</figref>). In block <b>316</b>, an HBT can be formed over the sub-collector layer. In some embodiments, such an HBT can be formed so as to include the example layers described herein in reference to <figref idref="DRAWINGS">FIG. 2</figref>, including a collector <b>219</b> (e.g., p− GaAs), a base <b>222</b> (e.g., p+ GaAs), an emitter <b>224</b> (e.g., n− InGaP), and an emitter cap <b>226</b> (e.g., n− GaAs). In block <b>318</b>, a first FET can be formed over the sub-collector layer, so that its channel region is formed from same material as the HBT's collector region. In some embodiments, such a first FET can be formed so as to include the example layers described herein in reference to <figref idref="DRAWINGS">FIG. 2</figref>, including a channel layer <b>254</b> (e.g., p− GaAs), a source contact layer <b>258</b> (e.g., p+ GaAs), and a drain contact layer <b>262</b> (e.g., p+ GaAs). In block <b>320</b>, a second FET can be formed over the sub-collector layer, so that its channel region is formed from same material as the HBT's emitter cap region. In some embodiments, such a second FET can be formed so as to include the example layers described herein in reference to <figref idref="DRAWINGS">FIG. 2</figref>, including a channel layer <b>263</b> (e.g., n− GaAs), a source contact layer <b>269</b> (e.g., n+ GaAs), and a drain contact layer <b>271</b> (e.g., n+ GaAs).

0069<figref idref="DRAWINGS">FIGS. 5-7</figref> show processes that can be more specific examples of the processes described in reference to <figref idref="DRAWINGS">FIGS. 3 and 4</figref>, in the context of the example configurations of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. <figref idref="DRAWINGS">FIG. 5</figref> shows a process <b>330</b> that can be implemented to fabricate an HBT such as those of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. <figref idref="DRAWINGS">FIG. 6</figref> shows a process <b>350</b> that can be implemented to fabricate an FET such as those of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>. <figref idref="DRAWINGS">FIG. 7</figref> shows a process <b>360</b> that can be implemented to fabricate a second FET such as that of <figref idref="DRAWINGS">FIG. 2</figref>. For the purpose of description of <figref idref="DRAWINGS">FIGS. 5-7</figref>, it will be assumed that a semiconductor substrate (such as semi-insulating GaAs) and a sub-collector layer (such as n+ GaAs) are provided.

0070The example processes <b>330</b>, <b>350</b> and <b>360</b> can be performed in sequence, in parallel where applicable, or in any combination thereof. Examples of such schemes of integrating an HBT with one or more FETs are described herein in greater detail.

0071In the example process <b>330</b> of <figref idref="DRAWINGS">FIG. 5</figref> where an HBT is being fabricated, a first collector layer (e.g., n− GaAs) can be formed on the sub-collector layer in block <b>332</b>. In block <b>334</b>, a second collector layer (e.g., p− GaAs) can be formed on the first collector layer. In block <b>336</b>, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the second collector layer. In block <b>338</b>, a base layer (e.g., p+ GaAs) can be formed on the first etch stop layer. In block <b>340</b>, an emitter layer (e.g., n− InGaP) can be formed on the base layer. In block <b>342</b>, an emitter cap layer (e.g., n− GaAs) can be formed on the emitter layer. In block <b>344</b>, a second etch stop layer (e.g., n− or p− InGaP) can be formed on the emitter cap layer. In block <b>346</b>, a bottom contact layer (e.g., n+ GaAs) for the emitter can be formed on the second etch stop layer. In block <b>348</b>, a top contact layer (e.g., InGaAs) for the emitter can be formed on the bottom contact layer. In block <b>349</b>, contacts for the emitter, base and collector can be formed so as to yield HBT configurations such as those (<b>104</b>, <b>204</b>) of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

0072In the example process <b>350</b> of <figref idref="DRAWINGS">FIG. 6</figref> where a first FET (e.g., a pFET) is being fabricated, a doped layer (e.g., n− GaAs) can be formed on the sub-collector layer in block <b>352</b>. In block <b>354</b>, a channel layer (e.g., p− GaAs) can be formed on the doped layer. In block <b>356</b>, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the channel layer. In block <b>358</b>, source and drain contact layers (e.g., p+ GaAs) can be formed on the first etch stop layer. In block <b>359</b>, contacts for the source, drain, gate and back gate can be formed so as to yield FET configurations such as the example pFETs <b>106</b> and <b>206</b> of <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

0073In the example process <b>360</b> of <figref idref="DRAWINGS">FIG. 7</figref> where s second FET (e.g., an nFET) is being fabricated, a first doped layer (e.g., n− GaAs) can be formed on the sub-collector layer in block <b>362</b>. In block <b>364</b>, a second doped layer (e.g., p− GaAs) can be formed on the first doped layer. In block <b>366</b>, a first etch stop layer (e.g., n− or p− InGaP) can be formed on the second doped layer. In block <b>368</b>, a third doped layer (e.g., p+ GaAs) can be formed on the first etch stop layer. In block <b>370</b>, a fourth doped layer (e.g., n− InGaP) can be formed on the third doped layer. In block <b>372</b>, a channel layer (e.g., n− GaAs) can be formed on the fourth doped layer. In block <b>374</b>, a second etch stop layer (e.g., n− or p− InGaP) can be formed on the channel layer. In block <b>376</b>, source and drain regions (e.g., n+ GaAs) can be formed on the second etch stop layer. In block <b>378</b>, source and drain contact layer (e.g., InGaAs) can be formed on the source and drain regions. In block <b>379</b>, contacts for the source, drain, gate and back gate can be formed so as to yield an FET configuration such as the example nFET (<b>207</b>) of <figref idref="DRAWINGS">FIG. 2</figref>.

0074In some implementations, the foregoing integration of an HBT with one or more FETs can be achieved in a number of ways, including a re-growth methodology, a two-step methodology, and/or a co-integration methodology. In the re-growth methodology, re-growth can involve a selective area, multilayer, and/or pre-patterned multilayer techniques. The selected area technique can include growing one device, etching in one or more selected areas, and then growing the other device in those selected area(s). The multilayer technique can include a single growth run, with the device layers stacked, not merged or shared. The pre-patterned multi-layer technique can include selective etching of a substrate prior to depositing layers for two or more devices.

0075In the two-step growth methodology, one device can be formed first, followed by formation of the other device adjacent to the first device. In the context of integration of three devices (such as the example of <figref idref="DRAWINGS">FIG. 2</figref>), such a two-step growth can be extended to include a third step growth of the third device.

0076In the co-integration methodology, a single growth can yield layers that are shared by two or more devices. In some implementations, the co-integration methodology can include single growth generated layers that constitute a majority of the layers of the two or more devices.

0077<figref idref="DRAWINGS">FIG. 8</figref> shows that in some embodiments, one or more features associated with the BiFET and/or BiCFET configurations described herein can be implemented as part of a semiconductor die <b>400</b>. For example, such a die can include a power amplifier (PA) circuit <b>402</b> having one or more BiFET and/or BiCFET devices <b>404</b>. Such a PA circuit <b>402</b> can be configured so as to amplify an input RF signal (RF_IN) to generate as an amplified output RF signal (RF_OUT).

0078<figref idref="DRAWINGS">FIG. 9</figref> shows another example die <b>410</b> that includes a PA circuit <b>412</b> controlled by a PA/Switch controller <b>414</b>. The controller <b>414</b> can be configured to include one or more BiFET and/or BiCFET devices <b>404</b>.

0079<figref idref="DRAWINGS">FIG. 10</figref> shows that in some embodiments, a die (such as the example die <b>410</b> of <figref idref="DRAWINGS">FIG. 9</figref>) can be implemented in a packaged module <b>420</b>. The die <b>410</b> can include a PA <b>412</b> and a controller <b>414</b> having a BiFET (and/or BiCFET) <b>404</b> having one or more features as described herein. Such a module can further include one or more connections <b>422</b> configured to facilitate passage of signals and/or power to and from the die <b>410</b>. Such a module can further include one or more packaging structures <b>424</b> that provide functionalities such as protection (e.g., physical, electromagnetic shielding, etc.) for the die <b>410</b>.

0080<figref idref="DRAWINGS">FIG. 11</figref> shows that in some embodiments, a component such as the die <b>410</b> of <figref idref="DRAWINGS">FIG. 9</figref> or the module <b>420</b> of <figref idref="DRAWINGS">FIG. 10</figref> can be included in a wireless device <b>430</b> such as a cellular phone, a smart phone, etc. In <figref idref="DRAWINGS">FIG. 11</figref>, a packaged RF module <b>420</b> is depicted as being part of the wireless device <b>430</b>; and such a module is shown to include a BiFET and/or BiCFET <b>404</b> having one or more features as described herein. In some embodiments, an unpackaged die having similar functionality can also be utilized to achieve similar functionalities. The wireless device <b>430</b> is depicted as including other common components such an RFIC <b>434</b> and an antenna <b>436</b>. The wireless device <b>436</b> can also be configured to receive a power source such as a battery <b>432</b>.

0081While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the invention. For example, the invention is not limited to the gallium arsenide material system.