US9083333B2

Switching circuit

Summary by NHIP

Switching circuit with surge suppression

The switching circuit connects parallel insulated gate transistors between high and low voltage lines using individual gate resistors and a single voltage application unit. A single fixed-value capacitor links the gate voltage apply line to the high voltage line to suppress surge voltage generated during synchronous transistor turn-off.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A switching circuit (80) includes: a plurality of insulated gate transistors (30-33) connected in parallel between a high voltage line (L1) and a low voltage line (L2); gate resistors (50-53) each provided for one of the plurality of insulated gate transistors (30-33) and each including a first terminal connected to a gate electrode of each of the insulated gate transistors (30-33); and a single gate voltage application unit (60) configured to apply pulsing gate voltage to the gate electrode of each of the insulated gate transistors (30-33) via the gate resistors (50-53). A second terminal of each of the gate resistors (50-53) provided for each of the plurality of insulated gate transistors (30-33) is connected to the gate voltage application unit (60) via a gate voltage apply line (L3), and a single capacitor is connected between the gate voltage apply line (L3) and the high voltage line (L1).

US9083333B2, drawing sheet 1 — Sheet 1 of 5

Term

Projected expiry 18 August 2032.

8 claims: 1 independent, 7 dependent

1
Broadest claimClaim Score 44, average(NHIP)A switching circuit comprising:a plurality of insulated gate transistors connected in parallel between a high voltage line and a low voltage line;gate resistors, each being connected to one of the plurality of insulated gate transistors, wherein each of the gate resistors includes a first terminal and a second terminal, the first terminal of each of the gate resistors being connected to the respective gate electrode of each of the plurality of insulated gate transistors;a gate voltage application unit configured to apply pulsing gate voltage to the gate electrode of each of the plurality of insulated gate transistors, the gate voltage application unit being connected to the second terminal of each of the gate resistor via a gate voltage apply line;and a single fixed-value capacitor connected to a single location between the gate voltage apply line before or at the second terminal of one of the gate resistors and the high voltage line, wherein the single fixed-value capacitor substantially suppresses a surge voltage that is generated when the plurality of insulated gate transistors is synchronously turned off.

49 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

The present invention relates to a switching circuit.

A switching circuit used in a DC-DC converter, an inverter, or the like has various requirements, such as small size and a small number of components, low ON resistance, low switching loss, and a low surge voltage.

A switching circuit such as that described above uses MOSFETs, IGBTs, or the like. The switching circuit switches these transistors between an ON state and an OFF state by switching a gate voltage applied to the gate terminal, or in other words, a gate electrode, of each transistor. The speed of the switch, or in other words, the switching speed, is dependent on the parasitic capacity of the transistors, or in other words, the input capacity Ciss, the feedback capacity Crss, the output capacity Coss, as well as the resistance value of the gate resistor connected to the gate terminal. The input capacity Ciss is the sum of the gate-source capacity Cgs and the gate-drain capacity Cgd. The feedback capacity Crss corresponds to the gate-drain capacity Cgd, and the output capacity Coss is the sum of the drain-source capacity Cds and the gate-drain capacity Cgd. The switching speed is typically set such that the surge voltage, which is generated by the inductance of an external circuit connected to the transistors, does not exceed the withstand voltage of the transistors. A surge voltage Vsu is determined from the following relational expression using inductance L and switching speed di/dt. Vsu=Ldi/dt

This equation shows that in order to keep the surge voltage Vsu low, it is necessary to perform at least one of lowering the inductance L and reducing the switching speed di/dt. The inductance L is a value determined in accordance with the structure of the switching circuit, and it is therefore difficult to adjust the inductance L. The switching speed di/dt, on the other hand, can be controlled by adjusting the parasitic capacity and the resistance value of the gate resistor, as described above.

However, when the switching speed di/dt is reduced excessively with the aim of protecting the transistors from the surge voltage, another problem arises in that the switching loss at the switching circuit increases. Further, the parasitic capacity Ciss, Crss, Coss of the transistors varies according to the applied voltage, and therefore the switching speed di/dt must be adjusted taking this variation into account.

Another method of suppressing the surge voltage is to connect a snubber circuit between the drain and the source of the transistor, for example. However, a switching circuit for controlling a large amount of power (large current) requires a snubber circuit having large capacity, and therefore the overall cost of the switching circuit increases.

Japanese Laid-Open Patent Publication No. 2009-296216 discloses a switching circuit for reducing high-frequency noise and reducing an increase of switching loss. The switching circuit connects a drain electrode as a high voltage electrode of a transistor with a gate electrode, i.e., a gate terminal via a variable capacitor. Thus, for example, as the voltage between the drain electrode and the gate electrode increases, the prior art reduces the capacity of the capacitor.

An objective of the present invention is to provide a switching circuit that is capable of reducing switching loss and suppressing a surge voltage while controlling a large current with a compact configuration having a small number of components.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present disclosure, a switching circuit includes a plurality of insulated gate transistors, gate resistors, a gate voltage application unit, and a capacitor. The insulated gate transistors are connected in parallel between a high voltage line and a low voltage line. Each gate resistor is connected to one of the plurality of insulated gate transistors. Each of the gate resistors includes a first terminal and a second terminal. The first terminal of each of the gate resistors is connected to the respective gate electrode of each of the plurality of insulated gate transistors. The gate voltage application unit is configured to apply pulsing gate voltage to the gate electrode of each of the plurality of insulated gate transistors. The gate voltage application unit is connected to the second terminal of each of the gate resistor via a gate voltage apply line. The capacitor is connected to a single location between the gate voltage apply line and the high voltage line.

According to this configuration, the plurality of insulated gate transistors are connected in parallel between the high voltage line and the low voltage line, and the first terminal of each gate resistor is connected to the gate electrode of each insulated gate transistor. Further, the second terminal of the gate resistor provided for each of the plurality of insulated gate transistors is connected to the gate voltage application unit via the gate voltage apply line, and the gate voltage application unit applies the pulsing gate voltage to the gate electrode of each insulated gate transistor via the corresponding gate resistor. As a result, the switching circuit can control a large current.

Further, the capacitor is connected to a single location between the gate voltage apply line and the high voltage line. By providing the capacitor, capacity variation between the gate electrodes of the insulated gate transistors and the high voltage line during gate voltage switching is suppressed. Hence, according to this configuration, switching loss can be reduced and a surge voltage can be suppressed with a compact configuration having a small amount of components.

In accordance with one aspect, the insulated gate transistors are MOSFETs in the switching circuit.

Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention that are believed to be novel are set forth with particularity in the appended claims. The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:

<figref idref="DRAWINGS">FIG. 1</figref> is a circuit configuration diagram showing a switching circuit according to one embodiment;

<figref idref="DRAWINGS">FIG. 2</figref> is a waveform diagram illustrating operation of the switching circuit shown in <figref idref="DRAWINGS">FIG. 1</figref>; and

<figref idref="DRAWINGS">FIG. 3</figref> is a circuit configuration diagram showing a typical switching circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the present disclosure will be described below with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>.

<figref idref="DRAWINGS">FIG. 1</figref> is a circuit diagram of a switching circuit 80. The switching circuit 80 includes four MOSFETs 30, 31, 32, 33, gate resistors 50, 51, 52, 53 connected to gate electrodes of the respective MOSFETs 30, 31, 32, 33, a single pulse generator 60, and a single capacitor 70. The switching circuit 80 is connected to a load 20 which is connected to a direct current power supply 10.

As shown in <figref idref="DRAWINGS">FIG. 1</figref>, a negative electrode terminal of the direct current power supply 10 is grounded. The positive electrode terminal of the direct current power supply 10 is connected to one end of the load 20. The other end of the load 20 is connected to the drain terminals of the MOSFETs 30, 31, 32, 33, which serve as a plurality of insulated gate transistors connected in parallel, by a high voltage line L1. The source terminals of the MOSFETs 30, 31, 32, 33 connected in parallel are grounded by a low voltage line L2. In other words, the four MOSFETs 30, 31, 32, 33 are connected in parallel between the high voltage line L1 and the low voltage line L2. In this embodiment, the load 20 is a motor driven by a large current.

In this embodiment, main electrodes of the transistors are the drain electrodes and the source electrodes of the respective MOSFETs 30, 31, 32, 33.

Each of the MOSFETs 30, 31, 32, 33 is a single chip element, and the respective chips, i.e., the MOSFETs 30, 31, 32, 33, are mounted on a substrate. The substrate on which the MOSFETs 30, 31, 32, 33 are mounted is also installed with other components, namely the gate resistors 50, 51, 52, 53, the capacitor 70, and the pulse generator 60.

The gate resistors 50, 51, 52, 53 are provided respectively on the MOSFETs 30, 31, 32, 33 such that respective first terminals of the gate resistors 50, 51, 52, 53 are connected to the respective gate electrodes of the MOSFETs 30, 31, 32, 33. More specifically, in <figref idref="DRAWINGS">FIG. 1</figref>, the first terminal of the gate resistor 50 is connected to the gate electrode of the MOSFET 30, the first terminal of the gate resistor 51 is connected to the gate electrode of the MOSFET 31, the first terminal of the gate resistor 52 is connected to the gate electrode of the MOSFET 32, and the first terminal of the gate resistor 53 is connected to the gate electrode of the MOSFET 33.

The pulse generator 60, which serves as a gate voltage application unit, is configured to apply a pulsing gate voltage to the respective gate electrodes of the MOSFETs 30, 31, 32, 33 via the gate resistors 50, 51, 52, 53. The pulse generator 60 includes a gate voltage apply line L3 for applying the gate voltage. The gate voltage apply line L3 splits at a branch point P1 and connects the pulse generator 60 to each of second terminals of the gate resistors 50, 51, 52 and 53 of the respective MOSFETs 30, 31, 32 and 33 via a branch point P1. That is, each of the gate resistors 50, 51, 52 and 53 provided respectively to the MOSFETs 30, 31, 32 and 33 has a second terminal. Each second terminal of the gate resistors 50, 51, 52 and 53 is connected to the pulse generator 60 via the gate voltage apply line L3. In other words, the gate voltage apply line L3 includes a pre-branch part between the pulse generator 60 and the branch point P1 and a post-branch part between the branch point P1 and the gate resistors 50, 51, 52, 53.

When the pulse generator 60 applies the pulsing gate voltage to the gate electrodes of the respective MOSFETs 30, 31, 32, 33 via the gate voltage apply line L3, the four MOSFETs 30, 31, 32, 33 are switched ON and OFF synchronously. Specifically, each of the MOSFETs 30, 31, 32 and 33 is switched to the ON state or OFF state, and supplies current to the load 20 during the ON state. That is, the pulse generator 60 switches the gate voltage applied to each gate electrode of the MOSFETs 30, 31, 32 and 33 connected in parallel between the high voltage line L1 and the low voltage line L2. By doing so, the pulse generator 60 switches the electrical connection between the source and the drain electrode of each of the MOSFETs synchronously from a conducting state to a non-conducting state or from a non-conducting state to a conducting state periodically.

Further, the single capacitor 70 is connected between the gate voltage apply line L3 and the high voltage line L1. More specifically, in <figref idref="DRAWINGS">FIG. 1</figref>, a connection point α serving as a first connection point is positioned between the pulse generator 60 and the branch point P1 on the gate voltage apply line L3, or in other words in the pre-branch part of the gate voltage apply line L3. A connection point β serving as a second connection point is positioned immediately before the drain electrode of the MOSFET 30 on the high voltage line L1. In other words, the connection point β is connected to the respective drain electrodes of the MOSFETs 30, 31, 32, 33. The single capacitor 70 is connected between the connection point α and the connection point β. More specifically, a first terminal of the capacitor 70 is connected to the connection point α and a second terminal of the capacitor 70 is connected to the connection point β. The capacity of the capacitor 70 is approximately 3 nF, for example. As described above, the capacitor 70 is likewise installed on the substrate mounted with the MOSFETs 30, 31, 32, 33, and the like.

Operation of the switching circuit 80 will be described below.

The pulse generator 60 applies high level gate voltage greater than or equal to On-voltage to each MOSFET in the OFF state of the MOSFETs 30, 31, 23 and 33. Then MOSFETs 30-33 in the OFF state will be switched to the ON state, or turned on, to supply current to the load 20.

When the MOSFETs 30, 31, 32, 33 are in the ON state, on the other hand, the pulse generator 60 applies an L level gate voltage to the gate electrode of each MOSFET. Then, the MOSFETs 30-33 in the ON state will be switched to the OFF state, or turned off, to interrupt current to the load 20. By performing this operation repeatedly, the pulse generator 60 outputs a pulse current.

Operations of the MOSFETs 30, 31, 32, 33 will be described in detail below.

<figref idref="DRAWINGS">FIG. 2</figref> shows a current waveform and a voltage waveform of the MOSFETs 30, 31, 32, 33 provided in the switching circuit 80 of <figref idref="DRAWINGS">FIG. 1</figref> in a turned-off state. The abscissa in <figref idref="DRAWINGS">FIG. 2</figref> shows time. Time dependences of the drain-source voltage Vds and the drain current ID in a turned-off state are shown as a voltage waveform and a current waveform, respectively.

In <figref idref="DRAWINGS">FIG. 1</figref>, the single capacitor 70 is connected between the gate voltage apply line L3 and the high voltage line L1. <figref idref="DRAWINGS">FIG. 2</figref> also shows the result of the configuration without the capacitor 70 of <figref idref="DRAWINGS">FIG. 1</figref> for comparison.

In <figref idref="DRAWINGS">FIG. 2</figref>, the broken line shows a Vds waveform of the MOSFET of the switching circuit without the capacitor 70 between the gate voltage apply line L3 and the high voltage line L1, while the solid line shows a Vds waveform of the MOSFET of the switching circuit 80 with the capacitor 70 of the present embodiment.

During operation of the MOSFETs, the parasitic capacities Ciss, Crss are charged or discharged. For example, when the MOSFET attempts to turn OFF, the voltage applied between the drain and the gate gradually increases. More specifically, for example, when the transistor ON state switches to the turned-off state, the drain voltage Vd varies from 0 volts to 48 volts, the gate voltage Vg varies from 15 volts to 0 volts, and the source voltage Vs remains at 0 volts. In other words, when the transistor ON state switches to the turned-off state, an absolute value of a voltage difference between the drain and the gate varies from 15 volts to 48 volts.

When the capacitor 70 is not provided between the gate voltage apply line L3 and the high voltage line L1, the parasitic capacity between the drain and the gate, or in other words the feedback capacity Crss, decreases greatly as the drain-source voltage Vds increases. This phenomenon is a characteristic of the MOSFET. Hence, at the moment when the transistor is turned OFF, or in other words, in a part where the drain-source voltage Vds rises, the parasitic capacity between the drain and the gate is small, and therefore the drain current Id varies momentarily. As a result, di/dt, which is a time derivative of the drain current Id, increases such that the surge voltage becomes extremely large. See Vsu=L di/dt. That is to say, <figref idref="DRAWINGS">FIG. 2</figref> shows a surge voltage ΔV1 evaluated from the broken line (without the capacitor 70), where the surge voltage is the difference between the maximum value of the Vds during the turned-off state and the Vds during a stabilization state after the turned-off state.

When the capacitor 70 is provided between the gate voltage apply line L3 and the high voltage line L1, as in this embodiment, the capacity of the capacitor 70 is added to the parasitic capacity between the drain and the gate, i.e., the feedback capacity Crss. In this case, a change, i.e., reduction of the capacity between the drain and the gate caused by an increase of the drain-source voltage Vds is prevented. Hence, according to this embodiment, in contrast to the case shown in <figref idref="DRAWINGS">FIG. 3</figref>, the surge voltage does not have to be taken into consideration when selecting a gate resistance value corresponding to a final value of the feedback capacity Crss resulting from an increase in the drain-source voltage Vds. Since the capacity between the drain and the gate does not change so much (does not reduce) even with increasing the drain-source voltage Vds, a rise time of the drain-source voltage Vds is shortened. Further, the surge voltage generated when the drain-source voltage Vds rises can be suppressed. As shown in <figref idref="DRAWINGS">FIG. 2</figref>, the surge voltage ΔV2 evaluated from the waveform of the drain-source voltage Vds indicated by the solid line is smaller than the surge voltage ΔV1 evaluated from the waveform of the drain-source voltage Vds indicated by the broken line.

In <figref idref="DRAWINGS">FIG. 2</figref>, the drain-source voltage Vds with the capacitor, i.e. according to this embodiment, is shaped to fall below the voltage Vds without the capacitor over time. In other words, Vds indicated by the solid line decreases below Vds indicated by the broken line over time, and a maximum value of Vds on the solid line is smaller than a maximum value of Vds on the broken line. A loss at the switching circuit 80, or in other words a switching loss, corresponds to an integrated value of the drain-source voltage Vds and the drain current Id. In the turned-off state, the Vds waveform according to this embodiment, indicated by the solid line in <figref idref="DRAWINGS">FIG. 2</figref>, varies sharply in contrast to the gentle variation of the Vds waveform according to the comparative example, indicated by the broken line. In other words, an incline of Vds indicated by the broken line varies gently, whereas an incline of the Vds waveform indicated by the solid line varies in steps. Hence, the switching loss according to this embodiment can be reduced below that of the comparative example.

In this embodiment, the capacitor 70 provided between the gate voltage apply line L3 and the high voltage line L1 reduces variation in the drain-gate capacity accompanying variation in the drain-source voltage Vds. In other words, the switching circuit 80 according to this embodiment is less likely to be affected by variation in the parasitic capacity between the drain and the gate. As a result, since the switching speed can be determined without considering the effect of the change of capacity so that the switching speed is not too slow, switching loss may be reduced.

In contrast to the switching circuit shown in <figref idref="DRAWINGS">FIG. 3</figref>, the switching circuit 80 according to this embodiment, shown in <figref idref="DRAWINGS">FIG. 1</figref>, is provided with the single capacitor 70. In other words, the capacitor 70 is connected to a single location between the gate voltage apply line L3 and a drain line, i.e. the high voltage line L1. More specifically, the capacitor 70 electrically connects the high voltage line L1 to the gate voltage apply line L3. It is possible with this configuration to prevent an imbalance between the transistors (between the chips). With the configuration shown in <figref idref="DRAWINGS">FIG. 1</figref>, the number of installed capacitors can be reduced in comparison with the configuration shown in <figref idref="DRAWINGS">FIG. 3</figref>. By reducing the number of capacitors, a mounting surface area of the capacitors can also be reduced. As a result, reductions in size and cost are achieved.

According to this embodiment, as described above, the following effects are obtained.

In the switching circuit 80, the respective first terminals of the gate resistors 50, 51, 52, 53 are connected to the gate electrodes of the respective MOSFETs 30, 31, 32, 33. The second terminal of each of the gate resistors 50, 51, 52 and 53 connected to corresponding one of MOSFETs 30, 31, 32 and 33 is connected to the pulse generator 60 via the gate voltage apply line L3. The pulse generator 60 applies pulsing gate voltages to the gate electrode of the respective MOSFETs 30, 31, 32, 33 via the gate resistors 50, 51, 52, 53, and therefore the plurality of MOSFETs 30, 31, 32, 33 are operated to turn ON and OFF in synchronization with each other. As a result, the switching circuit can control a large current. Further, the capacitor 70 is connected to a single location between the gate voltage apply line L3 and the high voltage line L1. By providing the capacitor 70, capacity variation between the gate electrodes of the MOSFETs 30, 31, 32, 33 and the high voltage line L1 during gate voltage switching is suppressed. Hence, the switching circuit according to the present disclosure can reduce switching loss and suppress a surge voltage with a compact configuration having a small number of components.

As shown in <figref idref="DRAWINGS">FIG. 3</figref> of the present application, for example, a switching circuit for controlling a large amount of power (large current) is constituted by a direct current power supply 100, a load 110, and a plurality of transistors 120, 121, 122, 123 connected in parallel.

The gate electrodes of the transistors 120, 121, 122, and 123 are connected to a pulse generation circuit 140, which serves as a gate voltage application circuit, via respective gate resistors 130, 131, 132, and 133. When an ON voltage is applied to the gate electrodes of the respective transistors 120, 121, 122, 123 from the pulse generation circuit 140, the respective transistors 120, 121, 122, 123 are switched ON, whereby a current flows to the load 110, or in other words the load is driven. When the transistors 120, 121, 122, 123 connected in parallel are used in this manner, a current flowing to each transistor can be reduced in comparison with a case where a single transistor is used, for example. Thus, even though current capacity of each transistor is small, it enables the load to receive large current via a plurality of transistors connected in parallel.

In this type of switching circuit using a plurality of transistors connected in parallel, variable capacitors 150, 151, 152, 153 are connected to the respective transistors 120, 121, 122, 123 between the gate electrode and a drain electrode thereof in order to reduce switching loss and suppress the surge voltage in the configurations of Japanese Laid-Open Patent Publication No. 2009-296216, as shown in <figref idref="DRAWINGS">FIG. 3</figref> of the present application. In this case, an increase occurs in the number of components, leading to an increase in the overall size of the switching circuit. For example, if only one transistor among four transistors 120, 121, 122 and 123 has a variable capacitor between the gate and drain electrode to reduce a number of components as shown in Japanese Laid-Open Patent Publication No. 2009-296216, there would be a problem in that current imbalance between transistors is caused upon driving the switching circuit to cause overheat and huge surge voltage in the switching circuit.

The present invention is not limited to the embodiment described above and may be modified as follows, for example.

In the above embodiment, the four MOSFETs 30, 31, 32, 33 are connected in parallel between the high voltage line L1 and the low voltage line L2. However, there are no limitations on the number of MOSFETs, and a number other than four, for example two, three, five, or more, i.e. any plurality of MOSFETs, may be connected in parallel.

IGBTs may be used as the insulated gate transistors in place of the MOSFETs 30, 31, 32, 33 serving as the insulated gate transistors. A collector electrode and an emitter electrode constitute main electrodes of an IGBT.

The aforesaid connection point α may be the branch point P1, or may exist in the post-branch part of the gate voltage apply line L3.

The aforesaid connection point β does not have to be provided immediately before the MOSFET 30 as long as it exists on the high voltage line L1.

Contents4

Every citation, both waysCites: the store holds 38 of 39

Citations
Document	Relation	Office	Cited during
US9998111B2	Cited by	United States of America	Search report
US2017179944A1	Cited by	United States of America	Pre-grant
US2003107905A1	Cites	United States of America	Search report
JP2004072811A	Cites	Japan	Applicant
WO2005022747A1	Cites	World Intellectual Property Organization (WIPO)	Applicant
JP2005261012A	Cites	Japan	Search report
US2008012610A1	Cites	United States of America	Search report
JP2008035621A	Cites	Japan	Applicant
US2008054325A1	Cites	United States of America	Search report
JP2009225648A	Cites	Japan	Search report
JP2009296216A	Cites	Japan	Applicant
US2013021700A1	Cites	United States of America	Search report
US4647848A	Cites	United States of America	Search report
US4939485A	Cites	United States of America	Search report
US5023494A	Cites	United States of America	Search report
US5124595A	Cites	United States of America	Search report
US5416387A	Cites	United States of America	Search report
US5563545A	Cites	United States of America	Search report
US5739717A	Cites	United States of America	Search report
US5744823A	Cites	United States of America	Search report
US5946178A	Cites	United States of America	Search report
US6054899A	Cites	United States of America	Search report
US6373731B1	Cites	United States of America	Search report
US6490182B2	Cites	United States of America	Search report
US6614633B1	Cites	United States of America	Search report
US6829152B2	Cites	United States of America	Search report
US7026858B2	Cites	United States of America	Search report
JPH01243721A	Cites	Japan	Applicant
JPH02207617A	Cites	Japan	Applicant
US20030107905A1	Cites	United States of America	Search report
US20080012610A1	Cites	United States of America	Search report
US20080054325A1	Cites	United States of America	Search report
US20130021700A1	Cites	United States of America	Search report
JP1243721A	Cites	Japan	Applicant
JP2207617	Cites	Japan	Applicant
JP2207617A	Cites	Japan	Applicant
JP2004072811A	Cites	Japan	Applicant
JP200835621A	Cites	Japan	Applicant
JP2009296216A	Cites	Japan	Applicant
WO2005022747A1	Cites	World Intellectual Property Organization (WIPO)	Applicant
Japanese Office Action with English Summary for Japanese Patent Application 2011-127614 mailed on Jul. 16, 2013.	Non-patent	–	Applicant
Japanese Notice of Allowance with English Summary for Japanese Patent Application 2011-127614 mailed on Jul. 16, 2013.	Non-patent	–	Applicant
Japanese Office Action with English Summary for Japanese Patent Application 2011-127614 mailed on Apr. 23, 2013.	Non-patent	–	Applicant
European Search Report (in English) corresponding to European Patent Application No. 12170644.4-1809 mailed on Aug. 21, 2014.	Non-patent	–	Applicant
Japanese Office Action with English Summary for Japanese Patent Application 2011-127614 mailed on Jul. 16, 2013.	Non-patent	–	Applicant
Japanese Notice of Allowance with English Summary for Japanese Patent Application 2011-127614 mailed on Jul. 16, 2013.	Non-patent	–	Applicant
Japanese Office Action with English Summary for Japanese Patent Application 2011-127614 mailed on Apr. 23, 2013.	Non-patent	–	Applicant
European Search Report (in English) corresponding to European Patent Application No. 12170644.4-1809 mailed on Aug. 21, 2014.	Non-patent	–	Applicant

7 members in 3 offices

This recordMember, by publication datePriority claim

Priority claims5

Priority claims
Document	Office	Kind	Date
2011127614	Japan	–	2011-06-07
2011127614	Japan	A	2011-06-07
2011127614	Japan	A	2011-06-07
2011127614	–	–	–
JP20110127614	–	–	–

Members7

Family members, oldest first
Document	Office	Kind
EP2533407A2	European Patent Office (EPO)	A2	2012-12-12
US2012313184A1	United States of America	A1	2012-12-13
JP2012256987A	Japan	A	2012-12-27
JP5344005B2	Japan	B2	2013-11-20
EP2533407A3	European Patent Office (EPO)	A3	2014-09-24
US9083333B2This record	United States of America	B2	2015-07-14
EP2533407B1	European Patent Office (EPO)	B1	2015-08-12

91 transactions on the USPTO file

Allowed after 2 non-final rejections, 2 final rejections and 2 RCEs.

Non-final rejections: 2
Final rejections: 2
RCEs: 2
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2023-08-21	Expire PatentEXP.	EXP.
2023-03-06	Maintenance Fee Reminder MailedREM.	REM.
2019-01-03	Payment of Maintenance Fee, 4th Year, Large EntityM1551	M1551
2015-07-14	Recordation of Patent Grant MailedPGM/	PGM/
2015-07-14	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2015-06-25	Email NotificationEML_NTR	EML_NTR
2015-06-24	Issue Notification MailedAllowedWPIR	WPIR
2015-06-09	Dispatch to FDCD1935	D1935
2015-06-05	Application Is Considered Ready for IssuePILS	PILS
2015-06-04	Issue Fee Payment VerifiedN084	N084
2015-06-04	Issue Fee Payment ReceivedIFEE	IFEE
2015-05-26	Electronic ReviewELC_RVW	ELC_RVW
2015-05-26	Email NotificationEML_NTF	EML_NTF
2015-05-26	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2015-05-20	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2015-05-19	Reasons for AllowanceEX.R	EX.R
2015-04-29	Date Forwarded to ExaminerFWDX	FWDX
2015-04-29	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2015-04-28	Request for Continued Examination (RCE)RCEX	RCEX
2015-04-28	Workflow - Request for RCE - BeginBRCE	BRCE
2015-04-24	Mail Interview Summary - Applicant Initiated - TelephonicMEXAT	MEXAT
2015-04-21	Interview Summary- Applicant InitiatedEXIA	EXIA
2015-04-21	Interview Summary - Applicant Initiated - TelephonicEXAT	EXAT
2015-01-30	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2015-01-15	Final RejectionFinal rejectionCTFR	CTFR
2015-01-15	Date Forwarded to ExaminerFWDX	FWDX
2015-01-06	Incoming Letter Pertaining to the DrawingsLTDR	LTDR
2015-01-06	Response after Non-Final ActionA...	A...
2014-10-08	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2014-10-03	Non-Final RejectionNon-final rejectionCTNF	CTNF
2014-10-03	Information Disclosure Statement consideredIDSC	IDSC
2014-10-03	Information Disclosure Statement consideredIDSC	IDSC
2014-10-03	Date Forwarded to ExaminerFWDX	FWDX
2014-10-03	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2014-09-26	New or Additional Drawing FiledC614	C614
2014-09-26	Request for Continued Examination (RCE)RCEX	RCEX
2014-09-26	Workflow - Request for RCE - BeginBRCE	BRCE
2014-09-02	Request for Extension of Time - GrantedXT/G	XT/G
2014-09-02	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-09-02	Information Disclosure Statement (IDS) FiledM844	M844
2014-09-02	Oath or Declaration Filed (Including Supplemental)C602	C602
2014-09-02	Request for Extension of Time - GrantedXT/G	XT/G
2014-08-29	Electronic Information Disclosure StatementEIDS.	EIDS.
2014-08-29	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-05-29	Mail Interview Summary - Applicant Initiated - TelephonicMEXAT	MEXAT
2014-05-27	Mail Advisory Action (PTOL - 303)MCTAV	MCTAV
2014-05-22	Interview Summary- Applicant InitiatedEXIA	EXIA
2014-05-22	Interview Summary - Applicant Initiated - TelephonicEXAT	EXAT
2014-05-22	Advisory Action (PTOL-303)CTAV	CTAV
2014-05-22	Date Forwarded to ExaminerFWDX	FWDX
2014-05-15	New or Additional Drawing FiledC614	C614
2014-05-15	Response after Final ActionA.NE	A.NE
2014-04-01	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2014-03-25	Final RejectionFinal rejectionCTFR	CTFR
2014-03-24	Date Forwarded to ExaminerFWDX	FWDX
2014-03-21	Response after Non-Final ActionA...	A...
2014-01-13	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2014-01-08	Non-Final RejectionNon-final rejectionCTNF	CTNF
2014-01-07	Case Docketed to Examiner in GAUDOCK	DOCK
2013-09-30	Mail-Record Petition Decision of Granted to Make SpecialMP003	MP003
2013-09-30	Record Petition Decision of Granted to Make SpecialP003	P003
2013-09-10	Information Disclosure Statement consideredIDSC	IDSC
2013-09-10	Electronic Information Disclosure StatementEIDS.	EIDS.
2013-09-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-09-05	Mail Interview Summary - Applicant Initiated - TelephonicMEXAT	MEXAT
2013-08-27	Information Disclosure Statement consideredIDSC	IDSC
2013-08-27	Petition EnteredPET.	PET.
2013-08-27	Electronic Information Disclosure StatementEIDS.	EIDS.
2013-08-27	Preliminary AmendmentA.PE	A.PE
2013-08-27	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-08-27	Interview Summary- Applicant InitiatedEXIA	EXIA
2013-08-27	Interview Summary - Applicant Initiated - TelephonicEXAT	EXAT
2013-08-22	Case Docketed to Examiner in GAUDOCK	DOCK
2013-05-24	Information Disclosure Statement consideredIDSC	IDSC
2013-05-24	Electronic Information Disclosure StatementEIDS.	EIDS.
2013-05-24	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-03-22	Case Docketed to Examiner in GAUDOCK	DOCK
2013-03-16	Case Docketed to Examiner in GAUDOCK	DOCK
2013-03-14	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2013-03-11	Correspondence Address ChangeC.AD	C.AD
2012-12-13	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2012-06-27	Application Dispatched from OIPEOIPE	OIPE
2012-06-12	Application Is Now CompleteCOMP	COMP
2012-06-12	Sent to Classification ContractorPGPC	PGPC
2012-06-12	Filing ReceiptFLRCPT.O	FLRCPT.O
2012-05-31	Cleared by OIPE CSRL194	L194
2012-05-30	Information Disclosure Statement consideredIDSC	IDSC
2012-05-30	Request from applicant for the USPTO to retrieve the Priority DocumentPDREQUST	PDREQUST
2012-05-30	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-05-30	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2012-05-30	Initial Exam Team nnIEXX	IEXX

7 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2023-09-12	Lapsed due to failure to pay maintenance feeLapsedFP	FP
2023-08-21	Lapse for failure to pay maintenance feesLapsedPATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYLAPS	LAPS
2023-08-21	Information on status: patent discontinuationPATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362STCH	STCH
2023-03-06	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2019-01-03	Maintenance fee paymentMAFP	MAFP
2015-06-24	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2012-06-15	AssignmentAS	AS