Circuit and method for sensing a physical quantity, an oscillator circuit, a smartcard, and a temperature-sensing circuit

FIELD

Embodiments according to the present invention relate to a circuit and a method for sensing a physical quantity, an oscillator circuit, a smartcard, and a temperature-sensing circuit.

BACKGROUND

In many applications, sensing a physical quantity, such as a temperature, is useful, sometimes even necessary because of a wide range of possible reasons. For instance, sensing a temperature outside of a predefined range of temperatures may represent an undesired state of a system. Such a temperature may for instance be caused by a malfunction of the system or a distortion or deviation of the environmental conditions from their specified tolerances. For instance, in case of an integrated circuit, sensing an exceeded temperature beyond a predefined temperature range may indicate that the system is producing too much heat or that the heat produced cannot be removed adequately.

In some applications, such a deviation from a specified temperature range may also be indicative of an attempt to break the system security or to tamper with the system.

The same may also apply to other physical quantities.

Conventionally, a sensor typically employs a sensor element, which transfers the physical quantity to be measured into an electrical signal, which is then compared to a fixed, predefined signal having a constant property.

However, providing such a fixed, predetermined signal often represents a significant challenge, since a signal source for such a signal typically relies on a specific physical effect, which in turn may depend on intrinsic material properties or extrinsic parameters such as shape, dimensions or the like.

To utilize the physical effect, the signal source is typically driven in a closed-feedback loop configuration to maintain the fixed, predefined signal. However, it may be advisable or sometimes even necessary to implement further circuitries and components to cope with drifts and other distortions of operating parameters.

In some applications, the physical effect requires an implementation of a specific structure, which may be difficult to implement in a given environment. Both may give rise to additional circuitries or complex structures to incorporate.

Therefore, a demand exists to provide an infrastructure for sensing a physical quantity with a reduced complexity.

SUMMARY

A circuit for sensing a physical quantity according to an embodiment of the present invention comprises a first oscillator circuit operable to provide a first clock signal comprising a first frequency depending on the physical quantity. The circuit further comprises a second oscillator circuit operable to provide a second clock signal comprising a second frequency depending on the physical quantity and a frequency comparator circuit operable to provide a frequency signal indicative of the physical quantity. The frequency signal is based on the first and second frequencies. The first and second oscillator circuits are further operable to provide the first and second clock signals such that due to a change in the physical quantity one frequency of the first and second frequencies increases, while the other frequency of the first and second frequencies decreases.

By employing a circuit for sensing a physical quantity according to an embodiment of the present invention, it may be possible to reduce the complexity by employing two oscillator circuits each with a pronounced frequency dependency of the physical quantity. Since the frequency dependencies differ as outlined above, in a circuit according to an embodiment of the present invention the second clock signal may be used to convey information on the physical quantity instead of just providing a stabilized time basis by outputting a fixed, predefined reference signal.

An oscillator circuit according to an embodiment of the present invention comprises an oscillation generator operable to provide a clock signal. The oscillation generator comprises a comparator with a first input and a second input. The oscillator circuit further comprises a current source coupled to the first input of the comparator and operable to provide a current. The current comprises a magnitude depending on the physical quantity. The oscillator circuit further comprises a reference signal circuit coupled to the second input of the comparator and operable to provide a reference signal, which also comprises a magnitude depending on the physical quantity. The current source and the reference signal circuit are operable to provide the current and the reference signal, respectively, such that due to a change in the physical quantity the magnitude of the current or of the reference signal increases, while the other magnitude of the current and the reference signal decreases.

By employing an oscillator circuit according to an embodiment of the present invention, it may also be possible to reduce the complexity of such a circuit by using the current source and the reference signal circuit having the described dependencies on the physical quantity. In other words, instead of comparing the magnitude of the current source to a fixed current or a fixed voltage, an oscillator circuit according to an embodiment of the present employs the reference signal circuit, which itself shows a pronounced dependency on the physical quantity and hence carries information on the physical quantity. Therefore, an infrastructure necessary to provide a fixed and constant reference signal may be omitted.

BRIEF DESCRIPTION OF THE DRAWINGS

Several embodiments of the present invention will be described in the enclosed Figures.

<figref idref="DRAWINGS">FIG. 1</figref> shows a block diagram of a circuit for sensing a physical quantity according to an embodiment of the present invention comprising two oscillator circuits;

<figref idref="DRAWINGS">FIG. 2</figref> shows a flow chart of a method according to an embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 3</figref> illustrates an uncertainty of a determination of a temperature based on sensing the temperature as a function of a voltage level;

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a sensing principle of determining an absolute temperature based on determining a frequency;

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a sensing principle for an absolute temperature based on determining a frequency, taking an offset into account;

<figref idref="DRAWINGS">FIG. 6</figref><i>a </i>shows two frequency/temperature characteristics of two clock signals provided by two oscillator circuits according to an embodiment of the present invention, illustrating a calibration and measurement process;

<figref idref="DRAWINGS">FIG. 6</figref><i>b </i>shows a temperature dependency of a ratio of the frequency/temperature characteristics of the oscillator circuits shown in <figref idref="DRAWINGS">FIG. 6</figref><i>a; </i>

<figref idref="DRAWINGS">FIG. 7</figref> shows a simplified circuit diagram of an oscillator circuit according to an embodiment of the present invention;

<figref idref="DRAWINGS">FIG. 8</figref> shows a time dependence of a voltage across a capacitor of the oscillator shown in <figref idref="DRAWINGS">FIG. 7</figref>;

<figref idref="DRAWINGS">FIG. 9</figref> shows a circuit diagram of a current source, a PTAT bias generator, a CTAT bias generator, and a further current source as employed in the oscillator circuit of <figref idref="DRAWINGS">FIG. 7</figref>;

<figref idref="DRAWINGS">FIG. 10</figref><i>a </i>shows two frequency/temperature characteristics of two clock signals provided by two oscillator circuits according to an embodiment of the present invention, illustrating a calibration and measurement process; and

<figref idref="DRAWINGS">FIG. 10</figref><i>b </i>shows a temperature dependency of a ratio of the frequency/temperature characteristics of the oscillator circuits shown in <figref idref="DRAWINGS">FIG. 10</figref><i>a; </i>

DETAILED DESCRIPTION

In the following, embodiments according to the present invention will be described in more detail. In this context, summarizing reference signs will be used to describe several objects simultaneously or to describe common features, dimensions, characteristics, or the like of these objects. The summarizing reference signs are based on their individual reference signs. Moreover, objects appearing in several embodiments or several figures, but which are identical or at least similar in terms of at least some of their functions or structural features, will be denoted with the same or similar reference signs. To avoid unnecessary repetitions, parts of the description referring to such objects also relate to the corresponding objects of the different embodiments or the different figures, unless explicitly or—taking the context of the description and the figures into account—implicitly stated otherwise. Therefore, similar or related objects may be implemented with at least some identical or similar features, dimensions, and characteristics, but may be also implemented with differing properties.

Smartcards are used in wide range of applications to protect certain goods, such as privileges or access to certain facilities and information. For instance, smartcards may be used to protect buildings, laboratories and other areas from unauthorized access. They may be also used to protect access to an account. Smartcards typically comprise an integrated circuit (IC), which is operable to perform the task of the respective smartcard. However, depending on the value of the goods protected by the smartcard, the smartcard itself may be the target of attacks or attempts to tamper with its content. As a consequence, it may comprise security measures to protect it and, as a consequence, the goods it is intended to protect.

A smartcard may comprise a processor or another form of an integrated circuit. Hence, it may also suffer from thermal or other conditions, such a circuit may encounter during its operation. In view of an applications or an implementation, it may be therefore advisable to implement a circuit for sensing a physical quantity, like a temperature.

Since a smartcard is a device to be carried around by a user, certain restrictions may apply to the implementable infrastructures. Due to these restrictions, for instance in the field of smartcards, a demand exists to employ circuits and infrastructures with a reduced complexity. However, embodiments according to the present invention that will be described below, may be also implemented as or in the context of other classes of devices than smartcards and other systems.

<figref idref="DRAWINGS">FIG. 1</figref> shows a block diagram of a circuit <b>100</b> for sensing a physical quantity according to an embodiment of the present invention. The circuit <b>100</b> comprises a first oscillator circuit (OSC<b>1</b>) <b>110</b>-<b>1</b> and a second oscillator circuit (OSC<b>2</b>) <b>110</b>-<b>2</b>, which are coupled to a frequency comparator circuit <b>120</b>. The frequency comparator circuit <b>120</b> is operable to provide a frequency signal FS at an output <b>130</b>. The frequency signal FS is indicative of the physical quantity to be sensed by the circuit <b>100</b>.

The frequency signal FS is based on a first frequency and a second frequency of a first clock signal CS<b>1</b> and a second clock signal CS<b>2</b> provided by the first and second oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>, respectively. The oscillator circuits <b>110</b> are operable to provide the respective clock signals CS<b>1</b>, CS<b>2</b> such that the frequency of the respective oscillator circuit <b>110</b> depends on the physical quantity. However, to enable the frequency comparator circuit <b>120</b> to provide the frequency signal FS indicative of the physical quantity, the first and second oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> are operable to provide their respective clock signals CS<b>1</b>, CS<b>2</b> in such a way that a change in the physical quantity causes one of the frequencies of the two clock signals CS<b>1</b>, CS<b>2</b> to increase, while the other frequency decreases.

By employing two oscillator circuits <b>110</b> with at least locally opposing frequency characteristics as a function of the physical quantity, a circuit <b>100</b> according to an embodiment of the present invention may enable a simpler implementation and a more accurate sensing of the physical quantity since a measurement of the physical quantity is based on two oscillator circuits <b>110</b>, which both depend on the physical quantity instead of using just one oscillator circuit <b>110</b> along with a reference oscillator providing a clock signal with a predefined and fixed frequency as a time basis. In other words, the circuit <b>100</b> according to an embodiment of the present invention uses a principle that a physical quantity may equally well be sensed by employing a non-constant “time basis” that varies with the physical quantity itself, instead of providing a fixed, predetermined and constant time basis. Therefore, in some embodiments according to the present invention, an implementation of an oscillating crystal or an oscillator with a fixed and predetermined frequency signal may be omitted.

Conventionally, such a reference clock signal with a predetermined and fixed frequency is generated, for instance, by implementing an oscillating crystal. However, implementing an oscillating crystal may be difficult in some applications. If, for instance, the circuit <b>100</b> according to an embodiment of the present invention is implemented on a single, monolithic integrated circuit, integrating the oscillating crystal may not be compatible with the underlying technology, or process parameters or other technological restraints. Moreover, due to application-related or cost restraints an implementation of an oscillating crystal may not be a viable option, either.

Under some circumstances, providing the reference clock signal with a fixed and predetermined frequency externally may not be an alternative either. This may be the case because such a reference clock signal is simply not available or cannot be trusted. The latter may for instance be the case in a security-related application, when the circuit <b>100</b> is, for instance, comprised in a smartcard <b>140</b>, which is used to protect privileges, facilities or information. In such a case, the smartcard <b>140</b> may be subjected to attacks to gain access to the protected goods mentioned above. In other words, the smartcard <b>140</b> may be subjected to attempts of tampering.

Conventionally, as an alternative to implementing an oscillating crystal, a reference clock signal may also be provided by an appropriately compensated oscillator circuit. However, such an oscillator circuit is typically required to provide the reference clock signal under a wide range of specified and eventually unspecified operating conditions if it is to be implemented in a security-related application. Circuits like these, however, may eventually require a significant size or area on a die of an integrated circuit.

A circuit <b>100</b> according to an embodiment of the present invention may make use of a fact that such a reference oscillator circuit may be omitted in terms of sensing a physical quantity. A circuit <b>100</b> according to an embodiment of the present invention may therefore offer the opportunity to reduce the complexity of such a circuit and a demand for size considerably compared to implementing a reference oscillator circuit as described above. Moreover, it may even be possible to increase the accuracy of sensing the physical quantity, since the second oscillator circuit (OSC<b>2</b>) <b>110</b>-<b>2</b> also carries information concerning the physical quantity instead of just providing a constant time-base.

The circuit <b>100</b> further comprises an evaluation circuit <b>150</b>, which is coupled to the output <b>130</b> of the frequency comparator circuit <b>120</b> to receive the frequency signal FS. The evaluation circuit <b>150</b> is operable to compare the frequency signal FS with a predetermined condition and provide a status signal SS at an output <b>160</b>, when the frequency signal FS fulfills the predetermined condition.

The smartcard <b>140</b> may further comprise a counter measure circuit <b>170</b> which is operable to receive the status signal SS and to initiate a countermeasure upon receipt of the status signal SS. Among the possible countermeasures to be initiated by the countermeasure circuit <b>170</b>, for example, is initiating a security reset of the smartcard <b>140</b>, reducing a voltage level, and reducing a frequency of an operating clock signal.

Initiating a security reset of the smartcard <b>140</b> may be an advisable countermeasure, when the frequency signal FS indicates the presence of an attack on the smartcard <b>140</b> or another attempt to tamper with its content. Reducing a voltage level and reducing a frequency of an operating clock signal may be suitable countermeasures in case the smartcard <b>140</b> tends to overheat such that an energy amount dissipated by the smartcard <b>140</b> should be reduced to ensure its functionality and health.

In an embodiment according to the present invention, the frequency comparator circuit <b>120</b> may be operable, for instance, to provide the frequency signal FS such that it is indicative of a ratio of the frequency values of the first and second frequencies of the respective clock signals CS<b>1</b>, CS<b>2</b>. To facilitate this, the frequency comparator circuit <b>120</b> may be operable to provide the frequency signal FS based on counting a number of edges of one clock signal of the first and second clock signals CS<b>1</b>, CS<b>2</b> during a period of time, which depends on a predefined number of edges, for instance falling or raising edges, of the other clock signal.

In other words, in one embodiment the frequency comparator circuit may for instance comprise a first and a second counter coupled to the first and second oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>, respectively. The period of time may depend, for instance, on the predefined number of edges of the second clock signal CS<b>2</b> as provided by the second oscillating circuit <b>110</b>-<b>2</b>. In this case, the first counter coupled to the first oscillator circuit <b>110</b>-<b>1</b> may be controllable by the second counter in such a way that the first counter ceases counting the edges of the first clock signal CS<b>1</b> when the second counter reaches the predefined number or, starting from the predefined number and counting downwards towards zero. When the second counter reaches zero or the predefined number, the number of edges as counted by the first counter is proportional to a product of the ratio of the two frequencies of the two clock signals CS<b>1</b>, CS<b>2</b> and the predefined number.

In some embodiments according to the present invention, the frequency comparator circuit <b>120</b> may be operable such that the predefined number is a fixed or a programmable integer. The number of edges counted during the period of time of the first clock signal CS<b>1</b> is proportional to a product of the predefined number and the aforementioned ratio of the two frequencies of the two clock signals CS<b>1</b>, CS<b>2</b>.

Naturally, in other embodiments according to the present invention, the first clock signal CS<b>1</b> may be used to control the number of edges to be counted by the frequency comparator circuit <b>120</b>. Depending on the implementation of the frequency comparator circuit <b>120</b> and its optionally implemented counters, rising edges (leading edges) or falling edges (trailing edges) may be counted. In other embodiments of a circuit <b>100</b>, the frequency comparator circuit <b>120</b> may be implemented differently to provide the frequency signal FS optionally being indicative of a ratio of the frequency values of the first and second frequencies.

As outlined before, the optional evaluation circuit <b>150</b> may be operable to receive the frequency signal FS and to provide the status signal SS, when the frequency signal FS fulfills the predetermined condition. The predetermined condition may be fixed or programmable. For instance, in the case of a security-related implementation of the circuit <b>100</b> according to an embodiment of the present invention, it may be advisable to implement the predetermined condition in a fixed way. As a consequence, the predetermined condition may be more difficult to be altered by an attacker. Implementing a programmable predetermined condition might be more attractive under other circumstances because it may provide the user of the circuit <b>100</b> with a greater flexibility of determining actions depending on the physical quantity sensed by the circuit <b>100</b>.

For instance, when the physical quantity is a temperature, the predetermined condition may be fulfilled when the temperature—or in more general terms—the physical quantity drops below or exceeds a predetermined threshold value. For instance, when the temperature drops below a predetermined threshold value, this may be interpreted as an attack on the smartcard <b>140</b> leading the countermeasure circuit <b>170</b> to initiate the security reset of the smartcard <b>140</b>. The countermeasure circuit <b>170</b> is in this case triggered by the status signal SS provided by the evaluation circuit <b>150</b>. Alternatively or additionally, when the temperature sensed by the circuit <b>100</b> exceeds a predetermined threshold value, it may be advisable to reduce the power consumption of the smartcard <b>140</b>. In this case, the countermeasure circuit <b>170</b> may be adapted such that a voltage level, for instance a supply voltage level, or a frequency of an operating clock of the smartcard <b>140</b> is reduced to limit the power dissipated by the smartcard <b>140</b>.

Hence, the evaluation circuit <b>150</b> may be operable such that the predetermined condition is fulfilled, when the ratio of the frequencies of the first and second clock signals CS<b>1</b>, CS<b>2</b> exceeds or is less than a predetermined threshold.

In some embodiments of the circuit <b>100</b> according to the present invention, at least one oscillator circuit <b>110</b> of a first and second oscillator circuit <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> is operable to provide the respective clock signal CS<b>1</b>, CS<b>2</b> such that the respective frequency changes essentially non-linearly and, optionally, essentially non-inverse linearly with the physical quantity. As will be outlined below in more detail, this may facilitate an easier calibration of the circuit <b>100</b>. For instance, the changes may be essentially polynomial (e.g. quadratic) or essentially inverse polynomial (e.g. inverse quadratic).

Before a possible implementation of an oscillator circuit <b>110</b> is outlined in more detail below, it should be mentioned that although the circuit <b>100</b> has been described so far only in the context of the smartcard <b>140</b>, embodiments according to the present invention are by far not limited to being implemented in the framework of a smartcard. Moreover, it should also be noted that the evaluation circuit <b>150</b> may be adapted to provide more than one status signal SS or to provide a status signal SS with different states. In such a case, the countermeasure circuit <b>170</b> may be adapted such that different countermeasures may be initiated depending on the status of the status signal received from the evaluation circuit <b>150</b>.

In the circuit <b>100</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>, each oscillator <b>110</b> comprises an oscillation generator <b>180</b>, <b>180</b>′, a current source <b>190</b>, <b>190</b>′ as well as a reference signal circuit <b>200</b>, <b>200</b>′. Each of the oscillation generators <b>180</b>, <b>180</b>′ comprise a comparator <b>210</b>, <b>210</b>′ with a first input <b>220</b>, <b>220</b>′, respectively, and a second input <b>230</b>, <b>230</b>′, respectively. The components denoted by an apostrophe (') are components of the second oscillator circuit (OSC<b>2</b>) <b>110</b>-<b>2</b>, while the components without the apostrophes refer to the components of the first oscillator circuit (OSC<b>1</b>) <b>110</b>-<b>1</b>.

For the sake of simplicity only, the structure of the first oscillator circuit <b>110</b>-<b>1</b> will be described in more detail in the following. As can be seen from <figref idref="DRAWINGS">FIG. 1</figref>, the same structure may also apply to the second oscillator <b>110</b>-<b>2</b>. Naturally, in other embodiments according to the present invention the oscillators <b>110</b> may be implemented differently.

The oscillation generator <b>180</b> is adapted to provide the clock signal CS<b>1</b> of the first oscillator <b>110</b>-<b>1</b>. The current source <b>190</b> is coupled to the first input <b>220</b> of a comparator <b>210</b> and operable to provide a current with a magnitude depending on the physical quantity to be sensed by the circuit <b>100</b>. The reference signal circuit <b>200</b> is coupled to the second input <b>230</b> of the comparator <b>210</b> and operable to provide a reference signal with a magnitude depending on the physical quantity. Once again, the current source <b>190</b> and the reference signal circuit <b>200</b> are operable to provide the current and the reference signal, respectively, such that due to an identical change in the physical quantity, the magnitude of the current or of the reference signal increases while the other magnitude of the current and the reference signal decreases. In other words, also the current source <b>190</b> and the reference signal circuit <b>200</b> comprise at least locally opposite dependencies with respect to the physical quantity.

The oscillator circuits <b>110</b> according to an embodiment of the present invention make also use of the fact that it is not necessary to implement a fixed reference signal circuit providing a fixed reference signal with a fixed, predetermined and constant magnitude. For the same reasons as mentioned above, the complexity of the oscillator circuit <b>110</b> may be reduced or simplified by implementing the reference signal circuit <b>200</b> such that the magnitude of the reference signal output by the reference signal circuit <b>200</b> depends on the physical quantity to be sensed by the circuit <b>100</b>.

The reference signal circuit <b>200</b> may be a voltage source or a current source depending on the concrete implementation. However, a more detailed description of an embodiment of an oscillator circuit <b>110</b> according to the present invention will be given in context with <figref idref="DRAWINGS">FIGS. 7 and 8</figref>.

In the case outlined above, in which the physical quantity to be sensed or measured is the temperature, the current source <b>190</b> may be based on a Proportional-To-Absolute-Temperature current source (PTAT current source) and the reference signal circuit <b>200</b> may be based on a Complementary-To-Absolute-Temperature current source (CTAT current source) or vice-versa. Sometimes, the CTAT current source is also referred to as an Inverse-Proportional-To-Absolute-Temperature current source (IPTAT current source). However, since it may not be necessary to implement full sets of PTAT current sources and CTAT current sources for both oscillators <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>, the circuit <b>100</b> may further comprise a first bias generator <b>240</b> and a second bias generator <b>250</b>. In the case of the physical quantity being the temperature, the current sources <b>190</b>, <b>190</b>′ being based on a PTAT or a CTAT current source, while the respective reference signal circuits <b>200</b>, <b>200</b>′ are based on the other alternative of PTAT and CTAT current sources, the first bias generator <b>240</b> may be a PTAT bias generator, while the second bias generator may be a CTAT bias generator. In the implementation shown in <figref idref="DRAWINGS">FIG. 1</figref>, the second bias generator <b>250</b> depends on an input signal provided by the first bias generator <b>240</b>. As a consequence, the two bias generators <b>240</b>, <b>250</b> are coupled. The first bias generator <b>240</b> is coupled to the current sources <b>190</b>, <b>190</b>′ and the second bias generator <b>250</b> is coupled to the reference signal circuits <b>200</b>, <b>200</b>′.

<figref idref="DRAWINGS">FIG. 2</figref> shows a flow chart of an embodiment of a method for sensing the physical quantity. After a start of the embodiment of the method in a step S<b>100</b>, the first clock signal CS<b>1</b> is provided in a step S<b>110</b>. For instance, step S<b>110</b> may be performed by the first oscillator circuit (OSC<b>1</b>) <b>110</b>-<b>1</b>. In a parallel step S<b>120</b>, the second clock signal CS<b>2</b> is provided, for instance, by the second oscillator circuit (OSC<b>2</b>) <b>110</b>-<b>2</b>. In a step S<b>130</b> the ratio of the frequency values of the first and second frequencies of the first and second clock signals CS<b>1</b>, CS<b>2</b> are determined. Based on the ratio determined in step S<b>130</b>, the frequency signal FS is provided in a step S<b>140</b>, before the method according to an embodiment ends in a step <b>150</b>.

While steps S<b>110</b> and S<b>120</b> of providing the first and second clock signals CS<b>1</b>, CS<b>2</b>, respectively, are typically performed by the first and second oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>, steps S<b>130</b> and S<b>140</b> may be performed by the frequency comparator circuit <b>120</b>. Steps S<b>110</b> and S<b>120</b> may be performed simultaneously by the two oscillator circuits <b>110</b>, as outlined above. In principle, the steps S<b>110</b> and S<b>120</b> may also be performed sequentially or—in terms of time—fully or partially overlapping. In other words, the flow chart as shown in <figref idref="DRAWINGS">FIG. 2</figref> does not necessarily represent an order in which the steps have to be performed. As outlined before, the method for sensing a physical quantity according to an embodiment of a present invention may comprise further steps as also outlined below.

However, before the oscillator circuits <b>110</b> according to an embodiment of the present invention will be described in more detail, possibilities, which some embodiments may offer, will be described along with further embodiments according to the present invention.

In the following embodiment description, the physical quantity will always be assumed to be the temperature without loss of generality.

A conventional temperature sensor is typically adjusted by measuring the response of the sensor at one or more reference temperatures. To illustrate this for a conventional voltage-based temperature sensor, <figref idref="DRAWINGS">FIG. 3</figref> shows a diagram of an output voltage/temperature characteristic of an output voltage V in arbitrary units (a.u.) as a function of the temperature T in Centigrade (° C.).

In the conventional temperature sensor, on which the illustration in <figref idref="DRAWINGS">FIG. 3</figref> is based, a current is applied to the sensor and a resulting voltage is measured. The voltage depends linearly on the temperature. A comparator circuit evaluates the linear temperature-dependent voltage with a temperature-independent voltage. These measurements are performed during a calibration process at the reference temperatures <b>260</b>-<b>1</b> and <b>260</b>-<b>2</b> of 25° C. and at 85° C., respectively. Based on these measurements, a calculation of a low temperature sensor trigger point will be performed afterwards.

The conventional temperature sensor generates a PTAT-voltage, a CTAT-voltage and/or a temperature-independent voltage. It uses a voltage-comparison circuit to compare two of the aforementioned voltages. However implementing such a circuitry with a high resolution may consume a large area on an integrated circuit due to the necessary implementation of transmission gates and further infrastructures.

<figref idref="DRAWINGS">FIG. 3</figref> shows several voltage/temperature characteristics <b>270</b>-<b>1</b>, <b>270</b>-<b>2</b>, <b>270</b>-<b>3</b> and <b>270</b>-<b>4</b>, which are based on slight variations of the voltages present at the two reference temperatures <b>260</b>, but which are considered by the voltage-comparison circuit to correspond to the same voltages. To be more precise, the characteristics <b>270</b>-<b>1</b> and <b>270</b>-<b>2</b> are based on the assumption that at the first reference temperature <b>260</b>-<b>1</b> of 25° C. the measured voltage differs from that of the other two characteristics <b>270</b>-<b>3</b>, <b>270</b>-<b>4</b> by a little less than one resolution step of the comparison circuitry. Similarly, voltage dependencies <b>270</b>-<b>2</b> and <b>270</b>-<b>4</b> on the one hand and characteristics <b>270</b>-<b>1</b> and <b>270</b>-<b>3</b> on the other hand are assumed to be based on voltages corresponding to marginally less than a one-step difference concerning the resolution at the second reference temperature <b>260</b>-<b>2</b> of 85° C. Nevertheless, all voltages will result in the same voltage values being attributed to them by the voltage-comparison circuit.

This granularity with respect to the voltages translates into a granularity of the temperatures, as well. In the situation shown in <figref idref="DRAWINGS">FIG. 3</figref>, this will result in a granularity with respect to temperature of approximately 2 K. Since the temperature sensors are typically not only operated in the temperature regime between the two reference temperatures <b>260</b>, but are also used to measure temperatures below and above, an error or a resulting granularity due to the finite voltage resolution may result in a significant uncertainty in terms of the sensed temperature. Under the circumstances and the situation shown in <figref idref="DRAWINGS">FIG. 3</figref>, due to extrapolating to lower temperatures the granularity may increase by a factor of 3.

<figref idref="DRAWINGS">FIG. 4</figref> shows a frequency/temperature characteristic <b>290</b> based on a frequency measurement instead of a voltage measurement. To be more precise, <figref idref="DRAWINGS">FIG. 4</figref> shows a dependency of the frequency f in arbitrary units (a.u.) as a function of the temperature in Centigrade (° C.).

The temperature sensor, on which the illustration of <figref idref="DRAWINGS">FIG. 4</figref> is based, is calibrated at a single reference temperature <b>260</b> of 25° C. and implemented using a PTAT current source or a PTAT voltage source. Due to the linear characteristics of the PTAT current source or the PTAT voltage source, which will be described in more detail in context of <figref idref="DRAWINGS">FIGS. 7 and 9</figref>, after a conversion of the current into the frequency domain the frequency dependency <b>290</b> starts at a frequency of zero at the absolute zero point (0 K=−273.15° C.).

In other words, under ideal conditions, a single point measurement during the calibration process at the reference temperature <b>260</b> should be enough to provide enough data to calibrate the temperature sensor reliably on which the diagram of <figref idref="DRAWINGS">FIG. 4</figref> is based. However, under field conditions, a highly precise time base might be necessary, which may be, for instance, implemented as a crystal oscillator or an external clock. As outlined before, such a highly precise time base may not always be available.

To increase the accuracy of a temperature sensor, a two-point measurement during the calibration process may be used. To illustrate this, <figref idref="DRAWINGS">FIG. 5</figref> illustrates another frequency dependency <b>290</b>, which is based on acquiring the frequency values at a first reference temperature <b>260</b>-<b>1</b> of 25° C. and at a second reference temperature <b>260</b>-<b>2</b> of 85° C. As a consequence, a deviation from the absolute zero point may be taken into consideration to increase the accuracy of the determination of a temperature.

However, although such a sensor calibrated at two reference temperatures <b>260</b> may work more precisely, under field conditions in contrast to test conditions once again a highly precise time base should be present, which is not necessarily available. However, to realize the additional accuracy of this conventional approach, it might be necessary under field conditions to implement an appropriate source.

<figref idref="DRAWINGS">FIG. 6</figref><i>a </i>shows two frequency dependencies <b>290</b>-<b>1</b>, <b>290</b>-<b>2</b> of oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> of a circuit <b>100</b> according to an embodiment of the present invention as shown in <figref idref="DRAWINGS">FIG. 1</figref>. The first oscillator circuit (OSC<b>1</b>) <b>110</b>-<b>1</b> comprises a monotonically increasing frequency/temperature-characteristic <b>290</b>-<b>1</b>, which changes essentially quadratically with temperature. The second oscillator circuit (OSC<b>2</b>) <b>110</b>-<b>2</b> comprises a monotonically decreasing frequency/temperature-characteristic <b>290</b>-<b>2</b>, which changes essentially inverse quadratically with temperature. In the temperature range shown in <figref idref="DRAWINGS">FIG. 6</figref><i>a </i>of approximately −15° C. to approximately 125° C., the frequencies of both oscillator circuits <b>110</b> vary in the range between approximately 4 MHz and approximately 10 MHz.

In the embodiment of the circuit <b>100</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the frequency comparator circuit <b>120</b> may be adapted to provide the frequency signal such that it is indicative of a ratio of the frequencies of the two oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>. To achieve this, <figref idref="DRAWINGS">FIG. 6</figref><i>b </i>shows a ratio/temperature characteristic <b>300</b>, which is based on a ratio of the frequency f₂of the second oscillator circuit <b>110</b>-<b>2</b> with respect to the frequency f₁of the first oscillator circuit <b>110</b>-<b>1</b>. In other words, <figref idref="DRAWINGS">FIG. 6</figref><i>b </i>shows the ratio f₂/f₁as a function of the temperature for the frequency/temperature characteristics <b>290</b> of <figref idref="DRAWINGS">FIG. 6</figref><i>a</i>. The ratio varies in the temperature range of −15° C. to approximately 125° C. from approximately 2.4 to approximately 0.5. The ratio is monotonically decreasing in this temperature range. It is therefore indicative of the temperature. Hence, a frequency signal FS comprising information on the aforementioned ratio is also indicative of the temperature.

<figref idref="DRAWINGS">FIG. 7</figref> shows a circuitry diagram of an oscillator circuit <b>110</b> according to an embodiment of the present invention. The oscillator circuit <b>110</b> comprises the oscillation generator <b>180</b>, the current source <b>190</b>, and the reference signal circuit <b>200</b> as already shown in <figref idref="DRAWINGS">FIG. 1</figref>.

The oscillation generator <b>180</b> comprises the comparator <b>210</b> with its first input <b>220</b> and its second input <b>230</b>. The first input <b>220</b> is a non-inverting input of the comparator <b>210</b>, while the second input <b>230</b> is an inverting input. An output <b>310</b> of a comparator is coupled to a driver circuit <b>320</b> which comprises a first CMOS-inverter <b>330</b> and a second CMOS-inverter <b>340</b> (CMOS=Complementary Metal Oxide Semiconductor) which are coupled in series. To be more precise, the output <b>310</b> of the comparator <b>210</b> is coupled to an input of the first CMOS-inverter <b>330</b>, an output of which is coupled to an input of the second CMOS-inverter <b>340</b>.

An output of the driver circuit <b>320</b> and, hence, of the second CMOS-inverter <b>340</b> is coupled to a control terminal of a transistor <b>350</b>. The transistor <b>350</b> is implemented in the oscillator circuit <b>110</b> according to an embodiment of the present invention as a PMOS-transistor (PMOS=p-channel Metal Oxide Semiconductor). As a consequence, the control terminal is a gate terminal of the transistor.

The transistor <b>350</b> further comprises a first terminal and a second terminal. The first terminal is coupled to the first input <b>220</b> of the comparator <b>210</b>. The second terminal of the transistor <b>350</b> is coupled to a supply voltage terminal <b>360</b> at which the positive supply voltage VDD is obtainable.

The oscillation generator <b>180</b> further comprises a capacitor <b>370</b> with a capacitance C, which is coupled in parallel to the current source <b>190</b> between the first terminal of the transistor <b>350</b> and terminals <b>380</b>, <b>390</b> for a reference potential VSS. The reference potential may be a ground (GND) potential. The terminal for the reference potential <b>380</b> is coupled to the capacitor <b>370</b>, while the terminal <b>390</b> is coupled to the current source <b>190</b>.

The oscillation generator <b>180</b> further comprises a flip-flop <b>400</b> which is coupled in between the two CMOS-inverters <b>330</b>, <b>340</b>. The flip-flop <b>400</b> is implemented in one embodiment as a T-flip-flop, which is operable to toggle between a first state and a second state when a signal with a predetermined edge is provided to the flip-flop <b>400</b>. The predetermined edge may be either a falling or a rising edge. An output <b>410</b> of the flip-flop <b>400</b> represents an output of the oscillation generator <b>180</b> at which the clock signal CS or dco_clk is obtainable. Therefore, the output <b>410</b> of the flip-flop <b>400</b> also represents the output of the oscillation generator <b>180</b>.

The oscillator circuit <b>110</b> further comprises the reference signal circuit <b>200</b>. The reference signal circuit <b>200</b> comprises a further current source <b>420</b>, which is coupled in between a terminal <b>430</b> of a reference potential <b>430</b> and the second input <b>230</b> of a comparator <b>210</b>. The reference signal circuit <b>200</b> further comprises one or more resistors <b>440</b>, which are coupled in between the further current source <b>420</b> and the second input <b>230</b> of the comparator <b>210</b> and a supply voltage terminal <b>450</b> for the supply voltage VDD.

Furthermore, as already illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the current source <b>190</b> is coupled to the optional first bias generator <b>240</b>, while the reference signal circuit <b>200</b> or, to be more precise, the further current source <b>420</b> is coupled to the second bias generator <b>250</b>. Both, the first and the second bias generator <b>240</b>, <b>250</b> may be interconnected.

It is once again to be noted, that the first and second bias generators <b>240</b>, <b>250</b> do not have to be part of the oscillator circuit <b>110</b>. However, in some embodiments according to the present invention they may be part of the oscillator circuit <b>110</b>.

Furthermore, it is to be noted that many of the structures shown may be implemented differently. For instance, instead of a PMOS-transistor as the transistor <b>350</b>, also a bipolar transistor may be used. Moreover, it is not necessary to implement more than one resistor <b>440</b>. In the present case, the oscillator circuit <b>110</b> according to an embodiment of the present invention comprises a series of resistors <b>440</b>, which may be used for fine trimming the reference signal circuit <b>200</b>.

To illustrate the operation of the oscillator circuit <b>110</b> as shown in <figref idref="DRAWINGS">FIG. 7</figref>, <figref idref="DRAWINGS">FIG. 8</figref> shows a diagram of a voltage V_cacross the capacitor <b>370</b> in arbitrary units (a.u.) as a function of time t. Starting at a point in time t₁, at which the transistor <b>350</b> has just been turned off by the driver circuit <b>320</b> and, hence, the supply voltage terminal <b>360</b> has just been decoupled from the capacitor <b>370</b>, the current source <b>190</b> discharges the capacitor <b>370</b> linearly over time. As a consequence, the voltage V_cacross the capacitor <b>370</b> decreases from a starting value approximately equal to the supply voltage VDD until a voltage level V_Refis reached, which is caused by the further current source <b>420</b>. When the voltage across the capacitor <b>370</b> reaches the voltage level V_Ref, the comparator <b>210</b> provides at its output <b>310</b> a signal, which is inverted by the first CMOS-inverter <b>330</b> and provided to the flip-flop <b>400</b>. Moreover, the inverted signal of the first CMOS-inverter <b>330</b> is provided to the second CMOS-inverter <b>340</b> providing to the control terminal of the transistor <b>350</b> a signal, which causes the transistor <b>350</b> to turn on, in other words, to become conducting. The supply voltage terminal <b>360</b> will be connected to the capacitor <b>370</b>. When the transistor <b>350</b> is implemented as a large transistor with a low resistance, the capacitor <b>370</b> may be charged quickly back to its original voltage, which is approximately equal to the supply voltage VDD.

Due to the rising voltage across the capacitor <b>370</b>, the comparator <b>210</b> is provided with a voltage larger than the potential V_Refprovided by the reference signal circuit <b>200</b>. As a consequence, the driver circuit <b>320</b> provides the transistor <b>350</b> with a signal, which causes the transistor <b>350</b> to turn off again. However, the flip-flop <b>400</b> is also provided with a signal of the opposite edge.

As a consequence, the flip-flop <b>400</b> is provided with one falling and one rising edge for each charging cycle of the capacitor <b>370</b>. Therefore, every two charging cycles, the same, predetermined edge is present at an input of the flip-flop <b>400</b>. This will result in the clock signal CS being output at the output <b>410</b> of the flip-flop <b>400</b> with a frequency half that of the charging cycle. However, the duty cycle of the clock signal CS is 1:1.

Since the frequency of the charging of the capacitor <b>370</b> is determined by comparison of the voltages across a capacitor <b>370</b> (voltage V_c) and the voltage across the resistors <b>440</b> (voltage V_R; V_R=V_c), wherein R is the overall resistance of the resistors <b>440</b>, a frequency f of the clock signal CS is given by <br /><i>f=</i>1/(2<i>RC I</i>_R<i>/I</i>_C<i>+T</i>_d),<br /> wherein I_Ris the current of the further current source <b>420</b> and I_cis the magnitude of the current of the current source <b>190</b>. T_drepresents a charging time of the capacitor <b>370</b>, which may be significantly shorter than a discharging time. While the discharging time is at least partially determined by the current source <b>190</b>, the charging time is at least determined by the transistor <b>350</b>, which is—at least in this embodiment—implemented as a large transistor. Moreover, T_dmay depend on the temperature and the underlying process technology. However, in many cases these may be neglected in a good approximation, if the frequency of the oscillator circuit <b>110</b> is chosen to be low enough. A frequency sufficiently low for the variations to be neglected, may be in the range of several MHz or several 10 MHz. By adjusting the lowest frequency to be less than 5 MHz, for all practical purposes, the variations contributing to T_dmay be, therefore, small or low enough.

As a consequence, the frequency is proportional to a ratio of the magnitudes of the currents I_cto I_R, wherein k is a constant: <br /><i>f=k I</i>_C<i>/I</i>_R

Changes in the magnitude of the current I_cof the current source are precisely transferred into the frequency, since they relate directly to the time necessary for discharging the capacitor <b>370</b>. On the other hand, the magnitude I_Rof the further current source <b>420</b> merely causes the voltage V_Rto vary so that the frequency is indirectly proportional to this current. However, its range may be limited.

<figref idref="DRAWINGS">FIG. 9</figref> shows a circuit diagram of the two bias generators <b>240</b>, <b>250</b> and their interconnection to the current source <b>190</b> and the further current source <b>420</b> according to one embodiment. The current source <b>190</b> is formed by a PMOS-transistor <b>460</b>. A gate terminal of the PMOS-transistor <b>460</b> (PMOS=p-channel Metal Oxide Semiconductor) is coupled to a node <b>470</b> of the first bias generator <b>240</b>, which is implemented as a PTAT-bias generator based on a Widlar-current source.

The first bias generator <b>240</b> comprises a first NMOS-transistor <b>520</b> (NMOS=n-channel Metal Oxide Semiconductor) and a second NMOS-transistor <b>530</b>, wherein the drain terminal of the first NMOS-transistor <b>520</b> is coupled to a source terminal of a third NMOS-transistor <b>500</b>, while a drain terminal of the second NMOS-transistor <b>530</b> is coupled to a source terminal of a fourth NMOS-transistor <b>510</b>. The drain terminal of the second NMOS-transistor <b>530</b> is furthermore coupled to a further node <b>540</b>, which is also coupled to both gate terminals of the first and second NMOS-transistors <b>520</b>, <b>530</b>.

The bias generator <b>240</b> further comprises a first PMOS-transistor <b>480</b> and a second PMOS-transistor <b>490</b>, which are coupled to form a current mirror, wherein the two gate terminals of the two PMOS-transistors <b>480</b>, <b>490</b> are coupled to the node <b>470</b>.

The third NMOS-transistor <b>500</b> and the fourth NMOS-transistor <b>510</b> are part of a cascode wherein a drain terminal of the third NMOS-transistor <b>500</b> is coupled to the node <b>470</b>. A drain terminal of the fourth NMOS-transistor <b>510</b> is coupled to both gate terminals of the two NMOS-transistors <b>500</b>, <b>510</b>.

A resistor <b>560</b> is coupled in between the source terminal of the first NMOS-transistor <b>520</b> and a terminal <b>550</b> for the reference potential VSS. As a consequence, the first PMOS-transistor <b>480</b>, the first NMOS-transistor <b>520</b>, the third NMOS-transistor <b>500</b> and the resistor <b>560</b> form a series connection in between the terminal <b>550</b> for the reference potential and a terminal for the supply voltage VDD. On the other side of the current mirrors, the second PMOS-transistor <b>490</b>, the second NMOS-transistor <b>530</b> and the fourth NMOS-transistor <b>510</b> form a series connection between a terminal <b>570</b> for the reference potential and a terminal for the supply voltage VDD. In the embodiment shown at least partly in <figref idref="DRAWINGS">FIG. 9</figref>, the resistor <b>560</b> comprises a resistance value high enough such that the first and second NMOS-transistors <b>520</b>, <b>530</b> are operated in their weak inversion regimes.

As outlined before, the first bias generator <b>240</b> is a PTAT-bias generator. Accordingly, the first NMOS-transistor <b>520</b> and the second NMOS-transistor <b>530</b> differ in terms of their dimensions. To be more precise, in the embodiment shown in <figref idref="DRAWINGS">FIG. 9</figref>, the first NMOS-transistor <b>520</b> may be capable of carrying approximately 8 times the current of the second NMOS-transistor <b>530</b>. As a consequence, the first and second NMOS-transistors <b>520</b>, <b>530</b> along with the resistor <b>560</b> create a voltage V_R, which is proportional to the absolute temperature.

The second bias generator <b>250</b> comprises an operational amplifier <b>580</b>, which is coupled to the further node <b>540</b> of the first bias generator. An output of the operational amplifier <b>580</b> is coupled to a gate terminal of a NMOS-transistor <b>590</b>, while a source terminal of the NMOS-transistor is coupled to an inverting input of the operational amplifier <b>580</b>. As a result, the further node <b>540</b> is coupled to a non-inverting input of the operational amplifier <b>580</b>. The source terminal of the NMOS-transistor <b>590</b> is furthermore coupled via a resistor <b>600</b> to a terminal <b>610</b> for the reference potential. The second bias generator <b>250</b> further comprises a PMOS-transistor <b>620</b>, which is coupled in between a terminal for the supply voltage VDD and the drain terminal of the NMOS-transistor <b>590</b>. Furthermore, a gate terminal of the PMOS transistor <b>620</b> is also coupled to the drain terminal of the NMOS-transistor <b>590</b>. The further current source <b>420</b> also comprises a PMOS-transistor <b>630</b>, a gate terminal of which is also coupled to the gate terminal of the PMOS transistor <b>620</b> of the second bias generator <b>250</b>. Accordingly the two PMOS-transistors <b>620</b>, <b>630</b> form a current mirror.

By providing the voltage across the second NMOS-transistor <b>530</b> to the non-inverting input of the operational amplifier <b>580</b>, and by taking the output of the operational amplifier <b>580</b> to control the gate terminal of the NMOS-transistor <b>590</b>, the (approximately) inverse proportional temperature dependence of the voltage across the second NMOS-transistor <b>530</b> as a function of temperature is used to control the PMOS-transistor <b>630</b> of the further current source <b>420</b>. Therefore, the second bias generator <b>250</b> is also referred to as a CTAT-bias generator or an IPTAT-bias generator.

As a consequence, the current source <b>190</b> is, in the embodiment shown in <figref idref="DRAWINGS">FIG. 9</figref>, based on a PTAT current source, while the further current source <b>420</b> is based on a CTAT current source.

<figref idref="DRAWINGS">FIGS. 10</figref><i>a </i>and <b>10</b><i>b </i>show similar diagrams as the <figref idref="DRAWINGS">FIGS. 6</figref><i>a </i>and <b>6</b><i>b</i>. However, it is to be noted that the common temperature axis of the two diagrams is reversed with respect to the illustration in <figref idref="DRAWINGS">FIGS. 6</figref><i>a </i>and <b>6</b><i>b</i>. While <figref idref="DRAWINGS">FIG. 10</figref><i>a </i>shows two frequency/temperature characteristics <b>290</b>, the <figref idref="DRAWINGS">FIG. 10</figref><i>b </i>shows the resulting ratio/temperature characteristic <b>300</b> of the two frequency/temperature characteristics <b>290</b> shown in <figref idref="DRAWINGS">FIG. 10</figref><i>a. </i>

<figref idref="DRAWINGS">FIGS. 10</figref><i>a </i>and <b>10</b><i>b </i>illustrate the use of two oscillators <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> as illustrated in the context of <figref idref="DRAWINGS">FIG. 1</figref> for a frequency measurement at two different reference temperatures <b>260</b>-<b>1</b>, <b>260</b>-<b>2</b>. The two reference temperatures are chosen to be 25° C. and 85° C. Due to the different behavior with respect to temperature of the oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b>, the frequency/temperature characteristics <b>290</b>-<b>1</b>, <b>290</b>-<b>2</b> of the two oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> respectively, are formed. However, it is to be noted that oscillators <b>110</b> having identical temperature dependence in terms of their frequencies may not work since these typically do not provide a temperature dependent ratio. Naturally, other reference temperatures <b>260</b> than the temperatures mentioned, may be used.

In the embodiment shown here, the frequency dependencies of the first and second oscillator circuits <b>110</b>-<b>1</b>, <b>110</b>-<b>2</b> are given by <br /><i>f=b</i>₁<i>T</i>/(1<i>−a</i>₁<i>T</i>)<br />and<br /><i>f</i>=(1<i>−a</i>₂<i>T</i>)/<i>b</i>₂<i>T. </i>

By measuring the two frequency values at the two reference temperatures <b>260</b>, a system of equations with two unknown variables (a₁, b₁; a₂, b₂) is to be solved. Therefore, for both oscillators <b>110</b> the frequency/temperature characteristics f(T) may be predictable. As a consequence, the ratio of the frequencies and, hence, the timer values may be used to initiate countermeasures or to sense the temperature.

Naturally, a circuit <b>100</b> for sensing a temperature or—in general terms—a physical quantity does not have to implement oscillator circuits <b>110</b> according to an embodiment of the present invention. Different combinations for current sources or reference signal circuits may be used, however, a combination of a current source <b>190</b> and a further current source <b>420</b> of the reference signal circuit <b>200</b> with a positive and a negative gradient might give an improved accuracy. In other words, the first oscillator <b>110</b>-<b>1</b> may be based on a current source <b>190</b> implemented as a CTAT-based current source, while the further current source <b>420</b> may be implemented as a PTAT-based current source. Accordingly, the second oscillator <b>110</b>-<b>2</b> may be implemented such that the current source <b>190</b> is a PTAT-based current source, while the further current source <b>420</b> is a CTAT- or IPTAT-based current source.

The embodiment of the circuit <b>100</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref> may therefore be based on generating a PTAT-based voltage and a CTAT-based voltage. The voltages may be transferred into linear currents, depending on the temperature, and then transferred by the oscillation generator <b>180</b> into two oscillator frequencies with different dependencies with respect to the physical quantity, for instance, the temperature. A circuit <b>100</b> may for instance be implemented as a temperature sensor or a temperature monitor. Such a temperature sensor may eventually be capable of providing a higher accuracy, a lower area and a smaller susceptibility to distortions.

A circuit <b>100</b> according to an embodiment of the present invention may therefore allow reducing the area necessary to implement such a circuit compared to a conventional design based on comparing and evaluating a voltage level without using the frequency. It may be possible to reduce the area of circuits of up to 50% for some circuits <b>100</b> according to an embodiment of the present invention. However, also smaller or even larger area reductions may be achievable. Moreover, due to using the frequency instead of a voltage, a circuit <b>100</b> according to an embodiment of the present invention may not be necessarily restricted by the granularity caused by the comparator circuit. It might therefore be possible to achieve a higher accuracy. Dynamic distortions may eventually be averaged out, which may result in an alarm situation in a conventional approach.

Furthermore, a circuit <b>100</b> according to an embodiment of the present invention may be able to satisfy future accuracy demands more easily, since a higher accuracy may be achievable by increasing the number of edges (predefined number) to be counted. Furthermore, the number of devices to be fabricated to a higher degree of accuracy may be reducible compared to a conventional design. Therefore, the design may become more robust in terms of a spread in the series of a production.

Furthermore, a circuit <b>100</b> according to an embodiment of the present invention as well as the other embodiments according to the present invention may offer an easier access to higher or lower temperatures due to employing PTAT-based and CTAT-based current sources during operation in the field and the possibility of acquiring a higher accuracy. As a consequence, it may be possible to employ less strict test conditions during the calibration process. The costs for the test equipment for calibrating embodiments according to the present invention may be, therefore, reducible. Moreover, estimates indicate that a current consumption may be approximately in the same range as a conventional approach.

By employing two oscillator circuits <b>110</b> or by employing a current source and a reference signal circuit with opposing temperature dependencies, the absolute values of the oscillator frequencies may become of no further importance. Therefore, precise, predetermined and fixed reference oscillators do not need to be implemented. Naturally, depending on the concrete implementation of an embodiment, they may be part of a circuit <b>100</b> or another embodiment according to the present invention. However, in some embodiments the determination of the temperature or the physical quantity may be reducible to determine the ratio of the frequencies. Therefore, monitoring a temperature or another physical quantity at a wider range of temperatures may become feasible with less effort.

The description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

Functional blocks denoted as “means for . . . ” (performing a certain function) shall be understood as functional blocks comprising circuitry that is adapted for performing or to perform a certain function, respectively. Hence, a “means for s.th.” may as well be understood as a “means being adapted or suited for s.th.”. A means being adapted for performing a certain function does, hence, not imply that such means necessarily is performing said function (at a given time instant).

The functions of the various elements shown in the Figures, including any functional blocks labeled as “means”, “means for forming”, “means for determining” etc., may be provided through the use of dedicated hardware, such as “a former”, “a determiner”, etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the Figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, the particular technique being selectable by the implementer as more specifically understood from the context.

It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes, which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

Furthermore, the following claims are hereby incorporated into the Detailed Description, where each claim may stand on its own as a separate embodiment. While each claim may stand on its own as a separate embodiment, it is to be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other embodiments may also include a combination of the dependent claim with the subject matter of each other dependent claim. Such combinations are proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.

It is further to be noted that methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective steps of these methods.

Further, it is to be understood that the disclosure of multiple steps or functions disclosed in the specification or claims may not be construed as to be within the specific order. Therefore, the disclosure of multiple steps or functions will not limit these to a particular order unless such steps or functions are not interchangeable for technical reasons.

Furthermore, in some embodiments a single step may include or may be broken into multiple substeps. Such substeps may be included and part of the disclosure of this single step unless explicitly excluded.