POP structures and methods of forming the same
Summary by NHIP
Stacked POP Package with TAV
The device features a bottom package with a die containing metal posts and a Through Assembly Via penetrating the molding material. A top package bonds over the bottom package, housing a discrete capacitor electrically coupled to a redistribution line via the via.
Claim Score by NHIP
Abstract
A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.

Term
6 yearsleft in the term
Expires 11 October 2032.
- Priority and filed
- Granted
- Today
- Expires
17 claims: 2 independent, 15 dependent
- 1Broadest claimClaim Score 72, broad(NHIP)A device comprising:a bottom package comprising: a molding material;a first device die molded in the molding material, wherein the first device die comprises metal posts, with the molding material disposed into gaps between the metal posts;a Through Assembly Via (TAV) penetrating through the molding material;and a first redistribution line over the molding material;and a top package comprising a discrete passive device packaged therein, wherein the top package is over and bonded to the bottom package, and wherein the discrete passive device is electrically coupled to the first redistribution line.
- 11A device comprising:a bottom package comprising: a molding material;a first device die molded in the molding material;a Through Assembly Via (TAV) penetrating through the molding material;and a first redistribution line over the molding material;a top package over and bonded to the bottom package, wherein the top package comprises: an additional electrical device electrically coupled to the first redistribution line;and an additional molding compound molding the additional electrical device therein, wherein the additional molding compound is in direct contact with a second redistribution line that is over the molding material.
Independent claims2
23 paragraphs in 3 sections, as filed
BACKGROUND
0001In integrated circuit applications, more and more functions are integrated into products. For example, different functional elements such as 3G video elements, WiFi elements, Bluetooth elements, and audio/video elements may need to be integrated together to form an application.
0002In conventional integration schemes, different components are bonded to an interposer, which is further bonded to a package substrate. For example, in mobile applications, a power management integrated circuit die, a transceiver die, and a multi-layer ceramic capacitor may be bonded using this scheme. The resulting package is typically very thick and large in area. In addition, since the various components that are bonded to the interposer are connected to the interposer through many electrical connections, the pitch of the electrical connections of the interposer need to be very small, and sometimes as small as about 40 nm to 50 nm. Such small pitch requires the interposer to use micro-bumps (u-bumps), whose formation still faces technical challenges.
BRIEF DESCRIPTION OF THE DRAWINGS
0003For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
0004<figref idref="DRAWINGS">FIGS. 1 through 10</figref> are cross-sectional views of intermediate stages in the manufacturing of a Package-On-Package (POP) structure in accordance with some exemplary embodiments, wherein device dies are embedded in the POP package.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
0005The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
0006A Package-On-Package (POP) structure and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package structure are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
0007<figref idref="DRAWINGS">FIGS. 1 through 10</figref> are cross-sectional views of intermediate stages in the manufacturing of a POP structure in accordance with some exemplary embodiments. <figref idref="DRAWINGS">FIG. 1</figref> illustrates carrier <b>20</b>, and adhesive layer <b>22</b> on carrier <b>20</b>. Carrier <b>20</b> may be a glass carrier, a ceramic carrier, or the like. Adhesive layer <b>22</b> may be formed of an adhesive such as an Ultra-Violet (UV) glue.
0008<figref idref="DRAWINGS">FIG. 2</figref> illustrates the placement of device dies <b>24</b> and <b>25</b>, and the formation of conductive posts <b>28</b>. Device dies <b>24</b> and <b>25</b> are placed over carrier <b>20</b>, for example, through adhesive layer <b>22</b>, and are level with each other. Device dies <b>24</b> and <b>25</b> may be logic device dies including logic transistors therein. In some exemplary embodiments, device dies <b>24</b> and <b>25</b> are dies that are designed for mobile applications, and may include a Power Management Integrated Circuit (PMIC) die and a Transceiver (TRX) die, for example. Although two dies <b>24</b> and <b>25</b> are illustrated, more dies may be placed over carrier <b>20</b> and level with each other.
0009Throughout the description, conductive posts <b>28</b> are alternatively referred to as Through Assembly Vias (TAVs) <b>28</b>. In some embodiments, TAVs <b>28</b> are pre-formed, and are then placed on adhesive layer <b>22</b>. In alternative embodiments, TAVs <b>28</b> may be formed by plating. The plating of TAVs <b>28</b> may be performed before the placement of dies <b>24</b> and <b>25</b>, and may include forming a seed layer (not shown) over carrier <b>20</b>, forming and patterning a photo resist (not shown), and plating TAVs <b>28</b> on the portions of the seed layer that are exposed through the photo resist. The photo resist and the portions of the seed layer that were covered by the photo resist may then be removed. Device dies <b>24</b> and <b>25</b> may then be placed over carrier <b>20</b>. The material of TAVs <b>28</b> may include copper, aluminum, or the like. In the resulting structure in <figref idref="DRAWINGS">FIG. 2</figref>, the bottom ends of TAVs <b>28</b> are substantially level with the bottom surface of device dies <b>24</b> and <b>25</b>.
0010In some exemplary embodiments, metal posts <b>26</b> (such as copper posts) are formed as the top portions of device dies <b>24</b> and <b>25</b>, and are electrically coupled to the devices in device dies <b>24</b> and <b>25</b>. In some embodiments, dielectric layers <b>27</b> are formed at the top surfaces of device dies <b>24</b> and <b>25</b>, with metal posts <b>26</b> having at least lower portions in dielectric layer <b>27</b>. The top surfaces of dielectric layers <b>27</b> may also be substantially level with the top ends of metal posts <b>26</b>. Alternatively, dielectric layers <b>27</b> are not formed, and metal posts <b>26</b> protrude above remaining portions of device dies <b>24</b> and <b>25</b>.
0011Referring to <figref idref="DRAWINGS">FIG. 3</figref>, molding material <b>40</b> is molded on device dies <b>24</b> and <b>25</b> and TAVs <b>28</b>. Molding material <b>40</b> fills the gaps between device dies <b>24</b> and <b>25</b> and TAVs <b>28</b>, and may be in contact with adhesive layer <b>22</b>. Furthermore, molding material <b>40</b> may be filled into the gaps between metal posts <b>26</b>. Molding material <b>40</b> may include a molding compound, a molding underfill, an epoxy, or a resin. The top surface of molding material <b>40</b> is higher than the top ends of metal posts <b>26</b> and TAVs <b>28</b>. Next, a thinning step, which may be a grinding step, is performed to thin molding material <b>40</b>, until metal posts <b>26</b> and TAVs <b>28</b> are exposed. The resulting structure is shown in <figref idref="DRAWINGS">FIG. 4</figref>. Due to the step of thinning, the top ends <b>28</b>A of TAVs <b>28</b> are substantially level with the top ends <b>26</b>A of metal posts <b>26</b>, and are substantially level with top surface <b>40</b>A of molding material <b>40</b>.
0012Next, referring to <figref idref="DRAWINGS">FIG. 5</figref>, Redistribution Lines (RDLs) <b>42</b> are formed over molding material <b>40</b> to connect to metal posts <b>26</b> and TAVs <b>28</b>. RDLs <b>42</b> may also interconnect metal posts <b>26</b> and TAVs <b>28</b>. RDLs <b>42</b> are formed in dielectric layers <b>44</b>. In some embodiments, RDLs <b>42</b> are formed by depositing metal layers, patterning the metal layers, and fill the gaps between RDLs <b>42</b> with dielectric layers <b>44</b>. In alternative embodiments, RDLs <b>42</b> and dielectric layers <b>44</b> are formed using damascene processes. RDLs <b>42</b> may comprise a metal or a metal alloy including aluminum, copper, tungsten, and/or alloys thereof.
0013<figref idref="DRAWINGS">FIG. 5</figref> also illustrates the formation of electrical connectors <b>46</b> in accordance with some exemplary embodiments. The formation of connectors <b>46</b> may include placing solder balls on the exposed portions of RDLs <b>42</b>, and then reflowing the solder balls. In alternative embodiments, the formation of connectors <b>46</b> includes performing a plating step to form solder regions over RDLs <b>42</b>, and then reflowing the solder regions. Connectors <b>46</b> may also include metal pillars, or metal pillars and solder caps, which may also be formed through plating. Throughout the description, the combined structure including device dies <b>24</b> and <b>25</b>, TAVs <b>28</b>, molding material <b>40</b>, and the overlying RDLs <b>42</b> and dielectric layers <b>44</b> is referred to as package <b>48</b>, which may have a wafer form in this step. In alternative embodiments, instead of forming electrical connectors <b>46</b> at this manufacturing stage, electrical connectors <b>46</b> are formed after the bonding of package components <b>58</b> and <b>60</b>, which bonding step is shown in <figref idref="DRAWINGS">FIG. 9</figref>.
0014Referring to <figref idref="DRAWINGS">FIG. 6</figref>, a carrier switch is performed. In the carrier switch process, carrier <b>49</b> is first attached to package <b>48</b>, wherein carriers <b>20</b> and <b>49</b> are on opposite sides of package <b>48</b>. Carrier <b>49</b> may be attached to package <b>48</b> through adhesive <b>50</b>, which may be a UV glue, a tape, or the like. Carrier <b>20</b> is then detached from package <b>48</b> by causing adhesive layer <b>22</b> to lose adhesion. Adhesive layer <b>22</b> is then removed. For example, when adhesive layer <b>22</b> is formed of the UV glue, adhesive layer <b>22</b> may be exposed to UV light, so that adhesive layer <b>22</b> loses adhesion, and hence carrier <b>20</b> and adhesive layer <b>22</b> can be removed from package <b>48</b>.
0015Referring to <figref idref="DRAWINGS">FIG. 7</figref>, after the carrier switch, the back ends <b>28</b>B of TAVs <b>28</b> are exposed. In the illustrated structure, back ends <b>28</b>B of TAVs <b>28</b> are level with back surface <b>24</b>A of device die <b>24</b> and back surface <b>25</b>A of device die <b>25</b>. Back ends <b>28</b>B of TAVs <b>28</b> may also be substantially level with surface <b>40</b>B of molding material <b>40</b>. In some embodiments, a grinding is performed to lightly grind the back surface of device dies <b>24</b> and <b>25</b> and TAVs <b>28</b>. As a result of the grinding, TAVs <b>28</b> may protrude slightly above the back surface of device dies <b>24</b> and <b>25</b>, or have their ends <b>28</b>B level with surfaces <b>40</b>B, <b>24</b>A, and <b>25</b>A. Alternatively, the grinding step is skipped.
0016As shown in <figref idref="DRAWINGS">FIG. 8</figref>, dielectric layers <b>52</b> and RDLs <b>54</b> are formed. In some embodiments, dielectric layers <b>52</b> are formed of dielectric materials such as oxides, nitrides, carbides, carbon nitrides, combinations thereof, and/or multi-layers thereof. RDLs <b>54</b> are formed in dielectric layer <b>52</b> and connected to TAVs <b>28</b>. Some of RDLs <b>54</b> may extend over and aligned to device dies <b>24</b> and <b>25</b>. Accordingly, RDLs <b>54</b> have a fan-in structure. For example, the portions of RDLs <b>54</b> that are over and aligned to device dies <b>24</b> and <b>25</b> may be connected to the portions of RDLs <b>54</b> that are over and aligned to TAVs <b>28</b>.
0017<figref idref="DRAWINGS">FIG. 9</figref> illustrates the bonding of package components <b>58</b> and <b>60</b> to package <b>48</b>. Package components <b>58</b> and <b>60</b> may be packages, device dies, passive devices, and/or the like. In some exemplary embodiments, package component <b>58</b> is a device die, and package components <b>60</b> are discrete passive devices, which are not integrated on same chips as active devices such as transistors. For example, when the respective package is for a mobile application, package component <b>58</b> may be a base band die, and package components <b>60</b> are Multi-Layer Ceramic Capacitors (MLCC). The bonding may be performed using flip chip bonding through connectors <b>62</b>, which may comprise solder, for example. It is appreciated that device dies <b>24</b>, <b>25</b>, and <b>58</b> may be arranged differently than in the illustrated exemplary embodiments. For example, the PMIC die or the TRX die may be device die <b>58</b>, and the base band die may be one of device dies <b>24</b> and <b>25</b>.
0018After the bonding of package components <b>58</b> and <b>60</b>, package components <b>58</b> and <b>60</b> are molded, for example, in molding material <b>64</b>. Molding material <b>64</b> may be in contact with bottom package <b>48</b>. The resulting package components <b>58</b> and <b>60</b> and molding compound <b>64</b> thus form top package <b>66</b>, which is bonded to the underlying bottom package <b>48</b>. Accordingly, the resulting structure is a POP structure. Next, top package <b>66</b> and bottom package <b>48</b> are demounted from carrier <b>49</b>. The resulting structure is shown in <figref idref="DRAWINGS">FIG. 10</figref>. The wafer-level package <b>48</b> may then be sawed into a plurality of POP structures <b>68</b>, with each of the POP structures <b>68</b> including one top package <b>66</b> bonded to one bottom package <b>48</b>.
0019In the embodiments, the plurality of device dies is embedded into bottom package <b>48</b> along with TAVs <b>28</b>. The embedded bottom package <b>48</b> has a thickness smaller than the thickness of typical package substrates, and smaller than a combined thickness of an interposer and a package substrate. Accordingly, the resulting POP structure <b>68</b> has a reduced thickness compared to conventional structures in which device dies and package components are bonded to an interposer, which is further bonded on a package substrate. Furthermore, device dies <b>24</b> and <b>25</b> and package components <b>58</b> and <b>60</b> (<figref idref="DRAWINGS">FIG. 10</figref>) are stacked rather than being bonded on a same interposer (as in conventional structures). The total area occupied by device dies <b>24</b> and <b>25</b> and package components <b>58</b> and <b>60</b> is hence reduced compared to the conventional structures.
0020In accordance with embodiments, a device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a TAV penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.
0021In accordance with other embodiments, a device includes a top package and a bottom package. The bottom package includes a molding material, a first device die molded in the molding material, and a second device die molded in the molding material. The electrical connectors of the first and the second device dies have ends that are level with a surface of the molding material. The bottom package further includes a plurality of TAVs penetrating through the molding material, wherein the ends of the electrical connectors of the first and the second device dies are level with ends of the plurality of TAVs. The bottom package further includes a first redistribution layer on a first side of the molding material, wherein the first redistribution layer includes a first plurality of redistribution lines, and a second redistribution layer on a second side of the molding material opposite the first side, wherein the second redistribution layer includes a second plurality of redistribution lines. The top package includes a discrete capacitor packaged therein, wherein the discrete capacitor is bonded to the bottom package.
0022In accordance with yet other embodiments, a method includes forming a bottom package including placing a first device die and a second device die over a carrier, forming a plurality of TAVs over the carrier, molding the first device die, the second device die, and the plurality of TAVs in a molding material, and thinning the molding material. After the step of thinning, top ends of the plurality of TAVs and top ends of electrical connectors of the first device die and the second device die are exposed through the molding material. The formation of the top package further includes forming a plurality of RDLs on a side of the molding material, wherein the plurality of RDLs is electrically coupled to the plurality of TAVs. The method further includes forming a top package, which includes bonding a discrete passive device to the bottom package.
0023Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Contents3
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| Email NotificationEML_NTR | EML_NTR | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Preliminary AmendmentA.PE | A.PE | |
| Response to Election / Restriction FiledELC. | ELC. | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Restriction RequirementMCTRS | MCTRS | |
| Restriction/Election RequirementCTRS | CTRS | |
| Incoming Letter Pertaining to the DrawingsLTDR | LTDR | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Application Is Now CompleteCOMP | COMP | |
| Email NotificationEML_NTR | EML_NTR | |
| Email NotificationEML_NTR | EML_NTR | |
| Change in Power of Attorney (May Include Associate POA)PA.. | PA.. | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Sent to Classification ContractorPGPC | PGPC | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Applicants have given acceptable permission for participating foreignAPPERMS | APPERMS | |
| Initial Exam Team nnIEXX | IEXX |
4 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS |
Numbers
- Publication
- 8975726
- Application
- 13649941
Titles
- English
- POP structures and methods of forming the same
Patent term adjustment
- Net adjustment
- 0 days
Classification
- CPC, 17
- H10W70/614
- H10W20/063
- H10P72/7422
- H10P72/7416
- H10P72/7436
- H10P72/74
- H10W74/019
- H10W72/241
- H10W90/724
- H10W70/09
- H10W90/00
- H10W72/874
- H10W72/0198
- H10W70/60
- H10W90/722
- H10W74/00
- H10W72/073
- IPC, 2
- H01L27 04
- H10W74 01