Method and apparatus for despread data in wireless communication system

CROSS-REFERENCE TO RELATED APPLICATION(S)

0001The present application claims priority under 35 U.S.C. §365 to International Patent Application No. PCT/IB2006/050194 filed Jan. 19, 2006, entitled “METHOD AND APPARATUS FOR DESPREAD DATA IN WIRELESS COMMUNICATION SYSTEM”. International Patent Application No. PCT/IB2006/050194 claims priority under 35 U.S.C. §365 and/or 35 U.S.C. §119(a) to Chinese Patent Application No. 200510005057.1 filed Jan. 31, 2005 and which are incorporated herein by reference into the present disclosure as if fully set forth herein.

FIELD OF THE INVENTION

0002The present invention relates to the wireless communication field, and more particularly, to a method and apparatus for despreading a spread signal in TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) and/or WCDMA (Wideband Code Division Multiple Access) system.

BACKGROUND OF THE INVENTION

0003Spread spectrum technology, or spreading technology, is a technology developed very quickly in the recent years, which not only plays an advantageous role in military communication but also is widely used in every field of communication, for example, satellite communication, mobile communication, microwave communication, wireless positioning system, wireless local area network (LAN), global personal communication.

0004Spreading communication can be briefly expressed as follows: a way for transmitting information, with the signal occupying a bandwidth far more wider than the narrowest bandwidth necessary for transmitting information; the bandwidth is spread by encoding and modulation methods and is irrelevant to the transmitted information data; and the transmitted information data are despread and restored by an identical spreading code at a receiver. Spreading technology is used in the following forms: direct sequence spread spectrum (abbreviated as Direct Spread (DS)), Frequency Hopping (FH), Time Hopping (TH) and linear frequency modulation (Chirp), and the combinations thereof such as FH/DS, TH/DS and FH/TH, wherein DS, FH and FH/DS are used most frequently in the communication.

0005Spreading communication technology is characterized as follows:

00061. Potent Anti-Scrambling Capacity

0007Since signal is spread to a wide band, narrowband signal is restored by compressing bandwidth of spread signal at receiver. Because the scrambling signal, which is irrelevant to a spreading pseudo-random code, is spread to a wide band, the scrambling power, which enters into communication bandwidth of a useful signal, is greatly reduced, and then the signal-to-interference ratio of the correlator is increased. Thus the spreading communication technology has a strong anti-scrambling capacity. This capability is in a direct ratio to the spreading times of the band: the wider the spectrum is spread, the stronger anti-scrambling capacity is.

00082. Multiple Access Communication

0009Spreading communication per se is a way of multiple access communication, named SSMA (Spread Spectrum Multiple Access). It per se is a form of CDMA (Code Division Multiple Access), which forms different networks with different spreading codes. Although occupying a wide band, the spectrum utilization ratio of a spreading system is higher than that of a single channel single carrier system, because different networks can share the same frequency simultaneously. CDMA is a main form of multiple access communication for the future global personal communication.

00103. Secure and Confidential

0011Since spreading system spreads the transmitted information to a wide band, the power density reduces with the spreading of the spectrum, and the signal may even be submerged by the noises. Accordingly, the spread signal has strong security, and is quite difficult to be intercepted, eavesdropped and detected. Unless the same spreading code as that used by transmitter is used and correlation detection is performed after synchronization therewith, nothing can be done about the spread signal. Since the spread signal has a low power spectrum density, a specific frequency band, e.g. ISM frequency band, can be used without approval in many countries such as USA, Japan and European countries, as long as the power spectrum density meets some requirements.

00124. Multi-Path Interference Rejection

0013Under some communication circumstances such as mobile communication and indoor communication where there is serious multi-path interference, a system must have a strong anti-interference capacity to ensure unimpeded communication. Spreading technology has a strong multi-path interference rejection capacity by use of the relevant characteristics of the spreading code used by spreading, and can even improve the performance of the system by use of multi-path energy.

0014CDMA system, which employs spreading technology, operates quite differently from the conventional TDMA and FDMA communication systems. In a direct sequence-CDMA (DS-CDMA) transmitter, for example, a digital symbol stream for a given dedicated or common channel at a basic symbol rate is spread to a chip rate. This spreading operation involves applying a channel unique spreading code (sometimes referred to as a signature sequence) to the symbol stream that increases its signal gain while adding bandwidth redundancy.

0015Typically, the digital symbol stream is multiplied by a channel code during spreading to derive a channelized intermediate signal including data information. The intermediate signal is then added to other intermediate signals using different channel codes. The summed intermediate signals are then multiplied by cell scrambling code to obtain a group of spread signals. Since all channel codes are orthogonal with each other, different users may share transmitting bandwidth at a specific time slot via different channel codes. And through the application of proper processing techniques at the receiver, the intermediate signals may be distinguished from others.

0016In the TD-SCDMA systems, the original data are restored by applying (i.e. multiplying, or matching) the appropriate scrambling codes and channel codes to despread spread signal at the receiver. Where the spreading code is applied to other transmitted and received intermediate signals, however, only noise is produced. The despreading operation thus effectively comprises a correlation process that compares the received signal with the appropriate digital code to recover the desired information from the channel.

0017In the TD-SCDMA systems, spreading is applied to the data part of the physical channels and comprises two operations. The first is the channelisation operation, which transforms every data symbol into a number of chips, thus increasing the bandwidth of the signal. The number of chips per data symbol is called the Spreading Factor (SF). The second operation is the scrambling operation, where a scrambling code is applied to the spread signal. The two operations are generally called spread operation together, wherein channel code and scrambling code are called spreading code together. It is required in TD-SCDMA system standard that downlink physical channels shall use SF=16. Multiple parallel physical channels can be used to support higher data rates. These parallel physical channels shall be transmitted using different channelisation codes.

0018The spread and despread of signals can be expressed by the following formula.

0019<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mo>⌈</mo><mrow><mrow><mo>[</mo><mrow><mrow><mo>(</mo><mrow><mi>i</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>/</mo><mi>SF</mi></mrow><mo>]</mo></mrow><mo>+</mo><mn>1</mn></mrow><mo>⌉</mo></mrow><mo>)</mo></mrow></mrow><mo>⁢</mo><mi>p</mi><mo>⁢</mo><mrow><mo>{</mo><mrow><mrow><mo>[</mo><mrow><mrow><mo>(</mo><mrow><mi>i</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>⁢</mo><mstyle><mspace width="0.6em" height="0.6ex" /></mstyle><mo>⁢</mo><mi>mod</mi><mo>⁢</mo><mstyle><mspace width="0.6em" height="0.6ex" /></mstyle><mo>⁢</mo><mi>SF</mi></mrow><mo>]</mo></mrow><mo>+</mo><mn>1</mn></mrow><mo>}</mo></mrow></mrow></mrow><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mfrac><mn>1</mn><mi>SF</mi></mfrac><mo>⁢</mo><mrow><munderover><mo>∑</mo><mrow><mi>i</mi><mo>=</mo><mn>1</mn></mrow><mi>SF</mi></munderover><mo>⁢</mo><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mrow><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow></mrow><mo>⁢</mo><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>.</mo></mrow></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>1</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0001.tif" />

0020Where x(n) is the signal before spreading, p(i) is the spreading code and z(i) is the signal after spreading, ┌A┐ denotes the round operation and the return value is the nearest integers greater than or equal to A.

0021The conventional despreading method and apparatus require a large amount of multipliers. However, such multipliers have complicated structures and occupy a relatively large chip area. So, if they can be replaced by other simple circuit structure, then the chip area can be greatly reduced and the production cost decreased by a big margin. Therefore, there is a need for a despreading method and apparatus capable of reducing the production cost significantly.

OBJECT AND SUMMARY OF THE INVENTION

0022It is an object of the present invention to provide a dispreading method and apparatus, which can remarkably reduce the circuit area in comparison with the conventional apparatus.

0023It is another object of the present invention to provide a dispreading method and apparatus, which can perform the despreading function via a simple circuit without multipliers employing complicated circuits.

0024It is a further object of the present invention to provide a dispreading method and apparatus, which can process data in parallel.

0025It is the furthermost object of the present invention to provide a dispreading method and apparatus, wherein only one set of data input port is needed for each pipeline of despread calculation.

0026To partly or completely fulfill these objects, according to one aspect of the present invention, there is provided a method for despreading a spread signal in a receiver of a wireless communication system, which comprises the steps of: preprocessing the spread signal to derive a group of spreading chips, the group of spreading chips corresponding to a data symbol; processing the spreading chips to extract the cophase components and the orthogonal components of each of the spreading chips; and converting and combining the group of cophase components and orthogonal components based on a preset selecting signal to derive a group of despreading chips.

0027According to another aspect of the present invention, there is provided an apparatus for despreading spread signal in a receiver of a wireless communication system, which comprises: a preprocess means for preprocessing spread signal to derive a group of spreading chips corresponding to a data symbol; an extraction means for processing the spreading chips to extract the cophase components and the orthogonal components of each of the spreading chips; and a selecting and processing means for converting and combining the group of cophase components and orthogonal components to derive a group of despreading chips based on a preset selecting signal.

0028Other objects and effects of the present invention will become more explicit and comprehensible from the following description taken in conjunction with the accompanying drawings, contents in the claims as well as a fuller understanding of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

0029Hereinafter, the preferred embodiments of the present invention will be described with reference to the accompanying drawings in which:

0030<figref idref="DRAWINGS">FIG. 1</figref> is a structure diagram illustrating the principle of a despreading apparatus according to an embodiment of the present invention;

0031<figref idref="DRAWINGS">FIG. 2</figref> is a schematic view of the inner structure of a selecting and processing means as shown in <figref idref="DRAWINGS">FIG. 1</figref>;

0032<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart of a despreading method according to an embodiment of the present invention;

0033<figref idref="DRAWINGS">FIG. 4</figref> is a circuit structure diagram of a despreading apparatus according to the first embodiment of the present invention;

0034<figref idref="DRAWINGS">FIG. 5</figref> is a structure diagram of a despreading apparatus according to the second embodiment of the present invention for illustrating the principle of the present invention from another aspect;

0035<figref idref="DRAWINGS">FIG. 6</figref> shows an example of the inner structure of an ALU (Arithmetic Logical Unit) shown in <figref idref="DRAWINGS">FIG. 5</figref>; and

0036<figref idref="DRAWINGS">FIG. 7</figref> shows a variation of the inner structure of the ALU shown in <figref idref="DRAWINGS">FIG. 6</figref>.

DETAILED DESCRIPTION OF THE INVENTION

0037The principles of a despreading apparatus and method according to the present invention will be further explained with reference to <figref idref="DRAWINGS">FIGS. 1 to 3</figref>. <figref idref="DRAWINGS">FIG. 1</figref> is a structure diagram illustrating the principle of a despreading apparatus according to an embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the despreading apparatus according to the present invention comprises a preset means <b>10</b>, a preprocess means <b>20</b>, an extraction means <b>30</b>, a selecting and processing means <b>40</b> and a summing means <b>50</b>.

0038The preprocess means <b>20</b> preprocesses a received spread signal to derive a group of spreading chips corresponding to a data symbol. The length of the spreading chips equals that of a known spreading sequence p(i); {i=1, 2, . . . , SF}. The extraction means <b>30</b> processes the spreading chips derived from the preprocess means <b>20</b> to extract the cophase components and the orthogonal components of each of the spreading chips, wherein the cophase components correspond to the above-mentioned I components, and the orthogonal components correspond to the above-mentioned Q components. The cophase components I and the orthogonal components Q derived by the extraction means <b>30</b> are provided to the selecting and processing means <b>40</b>, which comprises one or more selectors. The selecting and processing means <b>40</b> converts and combines a group of cophase components I and orthogonal components Q, based on a preset selecting signal, to obtain a group of despreading chips r. The dispreading chips r obtained by the selecting and processing means <b>40</b> are summed by the summing means <b>50</b> to restore the data symbol.

0039<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram of the inner structure of the selecting and processing means <b>40</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>. The selecting and processing means <b>40</b> comprises a combining means <b>401</b> and a negated means <b>402</b>. The negated means <b>402</b> receives the cophase component I and the orthogonal component Q, derives the negated signals −I and −Q, and inputs the cophase component I, the orthogonal component Q, together with the negated signals −I and −Q into the combining means <b>401</b>. The combining means selectively calculates and outputs the preset combining result between the cophase component I, the orthogonal component Q and the negated signals thereof based on the preset selecting signal. The preset combining result is one of an expected group of specific combining results. As depicted with respect to the first and second embodiments hereinafter, when the wireless communication system is TD-SCDMA system, a value of each unit p(i) of the known spreading sequence is selected from the set {1, −1, j, −j}, and the group of expected results is selected from the set {I+jQ, −I−jQ, −Q+jI, Q−jI}, in which I is a cophase component, Q is an orthogonal component, −I is a negated cophase component, and −Q is a negated orthogonal component.

0040The idea of the present invention can also be used in WCDMA wireless communication system. When the wireless communication system is WCDMA system, a value of each unit p(i) of the known spreading sequence is one of the set {1+j, 1−j, 1+j, −1−j}. The preset means <b>10</b> generates a corresponding preset selecting signal based on the value of p*(i) selected from {1+j, 1−j, I+j, −1−j}, which may, for example, be expressed by two-bit binary digit. The selecting and processing means <b>40</b> outputs an expected result selected based on the received preset selecting signal. It can be seen by calculation that the group of expected results is one of the set {(I−Q)+j(I+Q), (I+Q)+j(−I+Q), (−I−Q)+j(I−Q), (−I+Q)+j(−I−Q)}, in which I is a cophase component, Q is an orthogonal component, −I is a negated cophase component, and −Q is a negated orthogonal component.

0041Hence, when spreading sequence p(i) is a value selected from a limited set, it is expectable that the despreading result is also a value selected from a limited set. Thus, a combining calculation of selector, negator and adder can be used to implement multiplication for despreading, so as to simplify a despreading circuit and reduce a circuit area.

0042<figref idref="DRAWINGS">FIG. 3</figref> is a flowchart of a despreading method according to the present invention. Firstly, a spread signal is preprocessed in step S<b>20</b> to derive a group of spreading chips; cophase components I and the orthogonal components Q of each of the spreading chips are extracted in step S<b>30</b>; then, in step S<b>40</b>, the group of cophase components Q and orthogonal components I is converted and combined to derive a group of despreading chips based on a preset selecting signal; and finally, in step S<b>50</b>, the despreading chips are summed to derive despread data symbol.

Embodiment 1

0043<figref idref="DRAWINGS">FIG. 4</figref> is a circuit structure diagram of a despread apparatus according to Embodiment 1 of the present invention. Hereinafter, Embodiment 1 will be further illustrated with reference to <figref idref="DRAWINGS">FIG. 4</figref>.

0044In the TD-SCDMA systems, the spreading of data comprises two operations: channelisation and scrambling. Firstly, each complex valued data symbol is spread with a real valued channelisation code. The resulting sequence is then scrambled by a cell specific complex scrambling sequence. The combination of the user specific channelisation and cell specific scrambling codes can be seen as a user and cell specific spreading code. In the downlink of TD-SCDMA systems, both the SF and the length of scrambling sequence are <b>16</b>. Hence, it is convenient to recover the original data by spreading a received signal with the channelisation code and scrambling code together.

0045the scrambling code in TD-CDMA is complex, of which the elements are alternating real and imaginary. And the channelisation code is always real. Therefore, the spreading code is alternating real and imaginary.

0046According to the 3GPP standard for TD-SCDMA, spreading sequence is p(i); {i=1, 2, . . . , SF}. <br /><i>p</i>(<i>i</i>)=(<i>j</i>)ⁱ<i>·v</i>_i<i>v</i>_iε(1,−1);<i>i=</i>1,2<i>, . . . ,SF </i>

0047where, j denotes an imaginary unit, and SF denotes a spreading factor.

0048The odd bits in spreading code are always imaginary and the even bits in spreading code are always real. That is

0049<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mtable><mtr><mtd><mrow><mo>{</mo><mtable><mtr><mtd><mrow><mrow><mrow><mi>p</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mn>1</mn><mo>,</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow><mo>}</mo></mrow></mrow><mo>,</mo></mrow></mtd><mtd><mrow><mi>i</mi><mo>=</mo><mrow><mn>2</mn><mo>⁢</mo><mi>n</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mrow><mi>p</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mi>j</mi><mo>,</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow><mo>}</mo></mrow></mrow><mo>,</mo></mrow></mtd><mtd><mrow><mi>i</mi><mo>=</mo><mrow><mrow><mn>2</mn><mo>⁢</mo><mi>n</mi></mrow><mo>+</mo><mn>1</mn></mrow></mrow></mtd></mtr></mtable></mrow></mtd><mtd><mrow><mo>(</mo><mn>2</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0002.tif" />

0050where n is an integer;

0051Suppose <br /><i>z</i>[(<i>n−</i>1)×<i>SF+i]=w</i>(<i>i</i>)=<i>I+jQ</i>  (3)

0052is a received signal, in which I is a cophase component, and Q is an orthogonal component. In the despreading, the data multiplies the conjugate of the spreading code and sums the number of results. Suppose y(i) is the result of one multiplication, which is

0053<maths id="MATH-US-00003" num="00003"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><mrow><mi>z</mi><mo>⁢</mo><mi /><mo>[</mo><mrow><mrow><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow><mo>×</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow><mo>=</mo><mrow><mrow><mrow><mi>w</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>×</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mtable><mtr><mtd><mrow><mi>I</mi><mo>+</mo><mi>jQ</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>-</mo><mi>I</mi></mrow><mo>-</mo><mi>jQ</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>-</mo><mi>Q</mi></mrow><mo>+</mo><mi>jI</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mi>j</mi></mrow></mtd></mtr><mtr><mtd><mrow><mi>Q</mi><mo>-</mo><mi>jI</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow></mtd></mtr></mtable></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>4</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0003.tif" />

0054where p*(i) is the conjugate of the spreading code p(i).

0055In the conventional way for despreading, both I component and Q component are required at any time to calculate a multiplication result. In the present invention, however, only I component or Q component is required at a time to derive the multiplication result.

0056According to the present invention, in order to obtain the real component of the despread data, only the Q component is needed to be input for the multiplication with the odd bits of a spreading sequence, and only the I component is needed to be input for the multiplication with the even bits of a spreading sequence. Similarly, to obtain the imaginary component of the despread data, only the I component is needed to be input for the multiplication with the odd bits of a spreading sequence, and only the Q component is needed to be input for the multiplication with the even bits of a spreading sequence.

0057From formula (4) it can be seen that the multiplier is not required in implementation, and the sign of the conjugate of the spreading code p*(i) can be used as an input to the selector to derive the result of multiplication. In the following formula sign[p*(i)]=0 denotes a positive, and sign [p*(i)]=1 denotes a negative.

0058when n=2k, kεinteger,

0059<maths id="MATH-US-00004" num="00004"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>Re</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mrow><mrow><mtable><mtr><mtd><mi>I</mi></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mrow><mo>-</mo><mi>I</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd></mtr></mtable><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>Im</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mtable><mtr><mtd><mi>Q</mi></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mrow><mo>-</mo><mi>Q</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd></mtr></mtable></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>5</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mrow><mi>when</mi><mo>⁢</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mi>n</mi></mrow><mo>=</mo><mrow><mrow><mn>2</mn><mo>⁢</mo><mi>k</mi></mrow><mo>+</mo><mn>1</mn></mrow></mrow><mo>,</mo><mrow><mi>k</mi><mo>∈</mo><mi>integer</mi></mrow><mo>,</mo></mrow></mtd><mtd><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle></mtd></mtr><mtr><mtd><mrow><mrow><mi>Re</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mrow><mrow><mtable><mtr><mtd><mrow><mo>-</mo><mi>Q</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mi>j</mi></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mi>Q</mi></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd></mtr></mtable><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>Im</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mrow><mtable><mtr><mtd><mi>I</mi></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mi>j</mi></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>0</mn></mrow></mtd></mtr><mtr><mtd><mrow><mo>-</mo><mi>I</mi></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow></mtd><mtd><mrow><mrow><mi>sign</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>=</mo><mn>1</mn></mrow></mtd></mtr></mtable><mo>.</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>6</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0004.tif" />

0060In formula (5), when i is even, if the sign of the conjugate of the spreading code p*(i) is 0, then in formula (4), the real of the result of multiplication y(i) is I and the imaginary is Q; if the sign of the conjugate of the spreading code p*(i) is 1, then in formula (4), the real of the result of multiplication y(i) is −I and the imaginary is −Q. In formula (6), when n is odd, if the sign of the conjugate of the spreading code p*(i) is 0, then in formula (4), the real of the result of multiplication y(i) is Q and the imaginary is I; if the sign of the conjugate of the spreading code p*(i) is 1, then in formula (4), the real of the result of multiplication y(i) is Q and the imaginary is −I.

0061From an implementation point of view, only the sign bit of the conjugate of spread code is used as a selecting signal of the selector. In <figref idref="DRAWINGS">FIG. 1</figref>, s(i) means sign of p*(i).

0062The following formula (7) can be derived from formula (1) and formula (4), both the real and imaginary of the despread data are the sum of two parts. The first part is the summed result of the multiplication of the even bits of a spreading sequence, and the second part is the summed result of the multiplication of the odd bits of a despreading sequence.

0063<maths id="MATH-US-00005" num="00005"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mrow><mi>Re</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>⁢</mo><mn>1</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>i</mi><mo>=</mo><mn>1</mn></mrow><mrow><mi>SF</mi><mo>-</mo><mn>1</mn></mrow></munderover><mo>⁢</mo><mrow><mi>Re</mi><mo>⁢</mo><mrow><mo>{</mo><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow><mo>⁢</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow></mrow></mrow><mo>}</mo></mrow><mo>,</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>i</mi><mo>∈</mo><mrow><mrow><mn>2</mn><mo>⁢</mo><mi>k</mi></mrow><mo>+</mo><mn>1</mn></mrow></mrow><mo>,</mo><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mi>j</mi><mo>,</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow><mo>}</mo></mrow></mrow></mrow><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mrow><mrow><mi>Re</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>⁢</mo><mn>2</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>i</mi><mo>=</mo><mn>2</mn></mrow><mi>SF</mi></munderover><mo>⁢</mo><mrow><mi>Re</mi><mo>⁢</mo><mrow><mo>{</mo><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow><mo>⁢</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mrow><mo>}</mo></mrow><mo>,</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>i</mi><mo>∈</mo><mrow><mn>2</mn><mo>⁢</mo><mi>k</mi></mrow></mrow><mo>,</mo><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mn>1</mn><mo>,</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow><mo>}</mo></mrow></mrow></mrow><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mrow><mi>Im</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>⁢</mo><mn>1</mn></mrow></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>i</mi><mo>=</mo><mn>1</mn></mrow><mrow><mi>SF</mi><mo>-</mo><mn>1</mn></mrow></munderover><mo>⁢</mo><mrow><mi>Re</mi><mo>⁢</mo><mrow><mo>{</mo><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow><mo>⁢</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow></mrow></mrow><mo>}</mo></mrow><mo>,</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>i</mi><mo>∈</mo><mrow><mrow><mn>2</mn><mo>⁢</mo><mi>k</mi></mrow><mo>+</mo><mn>1</mn></mrow></mrow><mo>,</mo><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mi>j</mi><mo>,</mo><mrow><mo>-</mo><mi>j</mi></mrow></mrow><mo>}</mo></mrow></mrow></mrow><mo>⁢</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mrow><mrow><mi>Im</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mi>x</mi><mo>⁡</mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>⁢</mo><mn>2</mn></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>i</mi><mo>=</mo><mn>2</mn></mrow><mi>SF</mi></munderover><mo>⁢</mo><mrow><mi>Re</mi><mo>⁢</mo><mrow><mo>{</mo><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow><mo>⁢</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow></mrow></mrow></mrow><mo>}</mo></mrow><mo>,</mo><mstyle><mtext></mtext></mstyle><mo>⁢</mo><mrow><mi>i</mi><mo>∈</mo><mrow><mn>2</mn><mo>⁢</mo><mi>k</mi></mrow></mrow><mo>,</mo><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>∈</mo><mrow><mo>{</mo><mrow><mn>1</mn><mo>,</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow><mo>}</mo></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>7</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0005.tif" />

0064In the above formula, Re[x] denotes the real of x, IM[x] denotes the imaginary of x, i, <b>1</b>, n and k are all integers.

0065The despreading method and apparatus of the present invention are set forth using the above formula. First, sign [i]=sign[p*(i)] of conjugate p*(i) of the spreading code p(i) is calculated. Then, the obtained sign value serves as an input to a selecting end of a selector, and Q and −Q or I and −I serve as inputs to a standby inputting end of the selector. In this way, the multiplication in formula (4) can be performed by the alternative selector.

0066Specifically, the present invention applies the following methods to despread a received signal. The first step is to store signals after Raised Cosine Filter (RCF) separately. Suppose w(i)=I(i)+jQ(i) is the data needed to be despread, we store all I(i), i=2k, kε integer into a consecutive memory space, such as RAM (Random Access Memory); and store all I(i), i=2k+1, kε integer into another consecutive memory space. Similarly, we store all Q(i), i=2k, kε integer and all Q(i), i=2k+1, kε integer into a consecutive memory space, respectively. Thus, totally four blocks of memory are needed.

0067<figref idref="DRAWINGS">FIG. 4</figref> is a circuit structure diagram illustrating a despreading apparatus according to the first Embodiment of the present invention. In <figref idref="DRAWINGS">FIG. 4</figref>, data to be despread are filtered by a filter <b>101</b> (the filter can be Raised Cosine Filter or Root Raised Cosine Filter) and divided into I and Q components. According to sequence, the I and Q components are alternatively divided into odd and even components, namely I_oand I_e, Q_oand Q_e, respectively (“o” as subscript denotes an odd components in the odd sequence, “e” as subscript denotes an even component in the even sequence), which are stored in four blocks of memory <b>103</b>_o, <b>103</b>_e, <b>104</b>_oand <b>104</b>_e, respectively. Q_ocomponent is sequentially input to the first inputting end of a plurality of selectors <b>202</b> (represented by “1” of the selector <b>202</b> as shown in <figref idref="DRAWINGS">FIG. 4</figref>), and result −Q_oof Q_opassing through the negator is input to the second inputting end of the selectors (represented by “0” of selector <b>202</b> as shown in <figref idref="DRAWINGS">FIG. 4</figref>). Please note that, the memories <b>103</b>_o, <b>103</b>_e, <b>104</b>_oand <b>104</b>_ecan be omitted and the I and Q components are directly output to the following cascades of the circuit. Where the memories <b>103</b>_o, <b>103</b>_e, <b>104</b>_oand <b>104</b>_eare used, each clock period can output two groups of components I and Q downwards; for example, during the first clock period, the components I₁and Q₁and I₂and Q₂are output, and in the second clock period, the components I₃and Q₃and I₄and Q₄are output downwards. Where the memories <b>103</b>_o, <b>103</b>_e, <b>104</b>_oand <b>104</b>_eare omitted, each clock period can output two groups of components I and Q downwards; for example, in the first clock period, the components I₁and Q₁are output, and during the second clock period, the components I₂and Q₂are output downwards. Suppose {p(1), p(2), p(3), . . . , p(16)} is a spread sequence used in the downlink of the TD-SCDMA system, firstly, the spreading sequence is separated into two parts: {p(1), p(3), p(5), . . . , p(15)} and {p(2), p(4), p(6), . . . , p(16)}; next, conjugate p*(i)(i=1˜16){p(1),p(3),p(5), . . . , p(15)} of and {p(2),p(4),p(6), . . . , p(16)} is calculated; and then, sign of the p*(i) is calculated to obtain s[i]=sign[p*(i)] (when p*(i) is a positive, s[i] is 0; when p*(i) is a negative, s[i] is 1). The signs [1], s[3], . . . , s[15] in odd positions of p*(i) are input in parallel to the selecting ends of the plurality of alternative selector <b>202</b>, the components Q₁, Q₃, . . . , Q_2n−1in odd number of Q component are sequentially input to inputting end “1” of the selectors <b>202</b>, and the values resulting from negating Q1, Q₃, . . . , Q_2n−1by the negator <b>201</b> are sequentially input to inputting end “0” of the plurality of selectors <b>202</b>, respectively. The selector <b>202</b> correspondingly selects and outputs a signal input at inputting ends “0” input and “1” based on the sign 0 or 1 input at the selecting end. The output of each selector <b>202</b> is summed with the output of the upper cascade of the circuit, and the summed result is output as the present cascade of the circuit after being delayed one clock period by a delayer and is further summed with the output from the selector of the next cascade, as so on. Till the last cascade of the circuit, the result Real 1 of the first circuit branch is obtained. Please note that, if two groups of I and Q components are output in each clock period, only result Real 1 output at the last cascade of the circuit is the correct result after SF integral times of clock periods since the selector <b>202</b> receives the first group of I and Q components; therefore, results output in the other clock periods, except the SF/2 integral times of clock periods, will not be considered. Similarly, if a group of I and Q components is output during each clock period, only result Real 1 output at the last cascade of the circuit is the correct result after SF integral times of clock periods since the selector <b>202</b> receives the first group of I and Q components; therefore, results output in the other clock periods, except SF/2 integral times of clock periods, will not be considered. This will be more clearly represented in Table 1 below, and it is the same case in the second to fourth branches of circuit.

0068Similarly, signs s[2], [4], . . . , s[16] in even position of p*(i) are input in parallel to the selecting end of the plurality of alternative selectors <b>202</b>, the components I₂, I₄, . . . , I_2nof I components in even number are sequentially input to inputting end “0” of the plurality of selectors <b>202</b> and are then sequentially input to inputting end “1” of the plurality of selectors <b>202</b> after being negated by the negator <b>201</b> respectively. The selector <b>202</b> correspondingly selects and outputs a signal input at “0” or “1” based on the sign 0 or 1 input at the selecting end. The output of the selector <b>202</b> at each cascade is summed with the output of the upper cascade of the circuit, and the summed result is output after being delayed a clock period by the delayer and is further summed with the output from the selector of the next cascade, and so on. Till the last cascade of the circuit, the result Real 2 of the second circuit branch is obtained.

0069Please note that, each of the circuits mentioned above comprises a selector <b>202</b>, a adder <b>203</b> and a delayer circuit <b>204</b>; moreover, because no signal from the previous cascade is summed with the present cascade selector <b>202</b> in the first cascade circuit of the first and second circuit branches, a adder <b>203</b> can be omitted in the first cascade circuit as shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0070The results Real 1 and Real 2 of the two circuit branches are summed in a adder <b>112</b> to derive the Real of the despread result.

0071The structure of a circuit branch for calculating an imaginary of an apparatus according to the present invention as shown in <figref idref="DRAWINGS">FIG. 4</figref> is described below.

0072The signs s[1], s[3], . . . , s[15] in odd position of p*(i) are input to the selecting end of a plurality of alternative selector <b>202</b> in parallel, the components I₁, I₃, . . . , I_2n−1of I component in odd number are sequentially input to “0” input of the plurality of selectors <b>202</b> and are sequentially input to “1” input of the plurality of selectors <b>202</b> after being negated by negator <b>201</b> respectively. The selector <b>202</b> correspondingly selects and outputs a signal input at “0” input or “1” input based on the sign 0 or 1 input at the selecting end. The output of each selector <b>202</b> is summed with the output of the upper cascade of the circuit, and the summed result is output after being delayed a clock period by the delayer and is further summed with the output from the selector of the next cascade, and so on. Till the last cascade of the circuit, the result Imag1 of the third circuit branch is obtained.

0073Similarly, the signs [2], [4], . . . , s[16] in even position of p*(i) are input to the selecting end of the plurality of alternative selector <b>202</b> in parallel, components I₂, I₄, . . . , I_2nof I components in even number are sequentially input to “0” input of the plurality of selectors <b>202</b> and are sequentially input to “1” input of the plurality of selectors <b>202</b> after being negated by the negator <b>201</b> respectively. The selector <b>202</b> correspondingly selects and outputs a signal input at “0” input or “1” input based on the sign 0 or 1 input at the selecting end. The output of each selector <b>202</b> is summed with the output of the upper cascade of the circuit, and the summed result is output after being delayed a clock period by the delayer and is further summed with the output from the selector of the next cascade, and so on. Till the last cascade of the circuit, the result Imag2 of the fourth circuit branch is obtained.

0074In <figref idref="DRAWINGS">FIG. 4</figref>, ‘Real1’, ‘Real2’, ‘Imag1’ and ‘Imag2’ meanRe[x(n)]1, Re[x(n)]2, Im[x(n)]1 and Im[x(n)]2 in formula (10), respectively.

0075Please note that, each of the circuits mentioned above comprises a selector <b>202</b>, a adder <b>203</b> and delayer circuit <b>204</b>; moreover, because no signal from the previous cascade is summed with the output of the present cascade selector <b>202</b> at the first cascade of the circuit of the third and fourth circuit branches, a adder <b>203</b> can be omitted in the first cascade of the circuit as shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0076The results Image 1 and Image 2 from the two circuit branches are summed in the adder <b>112</b> to derive the imaginary Imag of the despread result. A combination of the Real and the Imag of the despread result is the final despread result.

Embodiment II

0077<figref idref="DRAWINGS">FIG. 5</figref> is a structure diagram of a despreading apparatus according to the second embodiment of the present invention, for describing the principle of the present invention from another aspect.

0078As shown in <figref idref="DRAWINGS">FIG. 5</figref>, data to be despread are filtered by filter <b>101</b> and divided into I and Q components. According to sequence, the I and Q components are alternatively divided into components in odd and even numbers, namely I_oand I_e, Q_oand Q_erespectively. At the same time, spreading code p is input to a calculator <b>102</b> for conjugate sign of the spreading code to calculate the conjugate signs of the spreading code and divide the signs into s_eand s_oin odd and even positions, respectively.

0079Q_ois input to a plurality of ALUs <b>105</b>₁, <b>105</b>₃, . . . , <b>105</b>₁₅simultaneously. These ALUs simultaneously receive odd positions s[1], s[3], . . . , s[15] from the conjugate signs of the spreading code and are cascaded with one another. That is, the output of the ALU of the previous cascade is connected to the inputting end of the ALU of the subsequent cascade. Since there is no input from other ALU before ALU <b>105</b>₁of the first cascade, input to the inputting end corresponding thereto is 0. Similarly, Q_eis simultaneously input to a plurality of ALUs <b>106</b>₂, <b>106</b>₄, . . . , <b>106</b>₁₆. These ALUs simultaneously receive even positions s[2], s[4], . . . , s[16] from the conjugate signs of the spreading code and are cascaded; I_eis simultaneously input to multiple ALUs <b>105</b>₂, <b>105</b>₄, . . . , <b>105</b>₁₆, which simultaneously receive even positions s[2], s[4], . . . , s[16] from the conjugate signs of the spreading code and are cascaded; I_ois simultaneously input to a plurality of ALUs <b>106</b>₁,<b>106</b>₃, . . . ,<b>106</b>₁₅, which simultaneously receive odd positions s[1], s[3], . . . , s[15] from the conjugate signs of the spreading code and are cascaded.

0080Suppose an input value of Q_o, Q_e, I_oor I_einput is A, an input value of the input connected to the previous cascade is B, and an input value of the sign s input is C and an output value thereof is D, the following operation is performed at each ALU:

0081<maths id="MATH-US-00006" num="00006"><math overflow="scroll"><mtable><mtr><mtd><mrow><mi>D</mi><mo>=</mo><mrow><mo>{</mo><mrow><mtable><mtr><mtd><mrow><mrow><mo>-</mo><mi>A</mi></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>1</mn></mrow></mtd></mtr><mtr><mtd><mrow><mi>A</mi><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>0</mn></mrow></mtd></mtr></mtable><mo>⁢</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mi>or</mi></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>8</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mi>D</mi><mo>=</mo><mrow><mo>{</mo><mtable><mtr><mtd><mrow><mi>A</mi><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>1</mn></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>-</mo><mi>A</mi></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>0</mn></mrow></mtd></mtr></mtable></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>9</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0006.tif" />

0082where C=0 denotes a positive; C=1 denotes a negative.

0083The calculation result D of the present cascade will be delayed a clock period and then output to the next cascade ALU.

0084To use which one of the formulas depends on the position of the ALU. For example, according to <figref idref="DRAWINGS">FIG. 4</figref>, ALUs <b>105</b>₁, <b>105</b>₃, . . . , <b>105</b>₁₅should apply formula (9), while ALUs <b>105</b>₂, <b>105</b>₄, . . . , <b>105</b>₁₆, ALUs <b>106</b>₁, <b>106</b>₃, . . . , <b>106</b>₁₅, ALUs <b>106</b>₂, <b>106</b>₄, . . . , <b>106</b>₁₆apply formula (8).

0085The results output from the final cascade ALUs <b>105</b>₁₅and <b>105</b>₁₆are Real 1 and Real 2, respectively. The two results are summed at adder <b>112</b>₁and output to obtain the Real of the despread data.

0086The results output from the final cascade ALUs <b>106</b>₁₅and <b>106</b>₁₆are Image 1 and Image 2, respectively. The two results are summed at the adder <b>112</b>₂and output to obtain the Image of the despread data.

0087A combination of the Real and the Imag is the final despread result.

0088<figref idref="DRAWINGS">FIG. 6</figref> shows an example of the inner structure of the ALU according to <figref idref="DRAWINGS">FIG. 5</figref>. The inner structures of each of the ALUs can be identical or similar so as to facilitate the production. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the ALU comprises negator <b>201</b>, alternative selector <b>202</b>, adder <b>203</b> and delayer <b>204</b>. The selector <b>202</b> comprises selecting input C for inputting a value of sign s, “1” input connected with the output of the negator, and “0” input connected with the input of the negator. The selector correspondingly selects the value input at “0” input or “1” input based on whether the value of the selecting input C is 0 or 1. The real/imaginary of I/Q component is input from inputting end A which is connected to “0” input of the selector <b>202</b>. The outputting end of the selector <b>202</b> is connected to an inputting end of the adder <b>203</b>. The output from the ALU of the upper cascade is input to another inputting end of the adder <b>203</b> via inputting end B, and the outputting end of the adder <b>203</b> is connected to the delayer <b>204</b> and is output from the output D after being delayed a clock period by the delayer. The delayer <b>204</b> can also be implemented by a flip-flop.

0089<figref idref="DRAWINGS">FIG. 7</figref> is a variation of the inner structure of the ALU as shown in <figref idref="DRAWINGS">FIG. 6</figref>, which will be explained in conjunction with <figref idref="DRAWINGS">FIGS. 6 and 7</figref>. The circuit structure of the ALU as shown in <figref idref="DRAWINGS">FIG. 6</figref> is used for the calculation of formula (8). If the calculation of formula (9) is to be performed, negator <b>201</b> should be put at “0” input of the selector, or else, a negator should be added between input C and the selecting input of selector <b>202</b>. It should be further noted that the structure of the ALU according to <figref idref="DRAWINGS">FIG. 6</figref> may be varied. If negator <b>201</b> is placed outside the ALU, then a similar structure as that shown in <figref idref="DRAWINGS">FIG. 4</figref> is obtained. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, the ALU consists of four inputs A<b>1</b>, A<b>2</b>, B and C and an output D, and performs calculation according to the following formula:

0090<maths id="MATH-US-00007" num="00007"><math overflow="scroll"><mtable><mtr><mtd><mrow><mi>D</mi><mo>=</mo><mrow><mo>{</mo><mrow><mtable><mtr><mtd><mrow><mrow><mi>A</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>1</mn></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>1</mn></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>A</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>0</mn></mrow></mtd></mtr></mtable><mo>⁢</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mrow><mi>o</mi><mo>⁢</mo><mi>r</mi></mrow></mrow><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>10</mn><mo>)</mo></mrow></mtd></mtr><mtr><mtd><mrow><mi>D</mi><mo>=</mo><mrow><mo>{</mo><mtable><mtr><mtd><mrow><mrow><mi>A</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>1</mn></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mi>A</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>1</mn></mrow><mo>+</mo><mi>B</mi></mrow></mtd><mtd><mrow><mi>C</mi><mo>=</mo><mn>0</mn></mrow></mtd></mtr></mtable></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>11</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0007.tif" />

0091The calculation result is output after being delayed for a clock period.

0092A<b>1</b> and A<b>2</b> receive the negated I/Q component simultaneously.

0093A cascade number of the ALUs depends on the spreading factor SF. Since the above example is given based on SF=16, the cascade number of the ALUs is 8. To further illustrate the principle of the present invention, a concrete example is given below to exhibit the calculation procedure of an ALU cascaded branch. Suppose there are 4 ALUs cascaded in total, and d denotes a value of Q or I, and “*” denotes the selecting calculation of the selector.

0094Suppose data input from moment 1 to moment 4 are d1, d3, d5 and d7 respectively, i.e., a datum is input at each moment, the output result from the adder of the ALU of each cascade is given in the following Table.

0095<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0" pgwide="1"><tgroup align="left" colsep="0" rowsep="0" cols="5"><colspec colname="1" colwidth="28pt" align="left" /><colspec colname="2" colwidth="49pt" align="left" /><colspec colname="3" colwidth="56pt" align="left" /><colspec colname="4" colwidth="84pt" align="left" /><colspec colname="5" colwidth="105pt" align="left" /><thead><row><entry namest="1" nameend="5" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row><row><entry /><entry>Output from the</entry><entry>Output from the</entry><entry>Output from the</entry><entry>Output from the</entry></row><row><entry /><entry>adder of the</entry><entry>adder of the</entry><entry>adder of the</entry><entry>adder of the</entry></row><row><entry>moment</entry><entry>first cascade</entry><entry>second cascade</entry><entry>third cascade</entry><entry>fourth cascade</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>1</entry><entry>d1 * s1</entry><entry>d1 * s3</entry><entry>d1 * s5</entry><entry>d1 * s7</entry></row><row><entry>2</entry><entry>d3 * s1</entry><entry>d1 * s1 + d3 * s3</entry><entry>d1 * s3 + d3 * s5</entry><entry>d1 * s5 + d3 * s7</entry></row><row><entry>3</entry><entry>d5 * s1</entry><entry>d3 * s1 + d5 * s3</entry><entry>d1 * s1 + d3 * s3 + d5 * s5</entry><entry>d1 * s3 + d3 * s5 + d5 * s7</entry></row><row><entry>4</entry><entry>d7 * s1</entry><entry>d5 * s1 + d7 * s3</entry><entry>d3 * s1 + d5 * s3 + d7 * s5</entry><entry>d1 * s1 + d3 * s3 + d5 * s5 + d7 * s7</entry></row><row><entry namest="1" nameend="5" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0096At the first moment, the output of an upper cascade is 0, hence the output from the adder of each cascade is the same as that of the selector of each cascade (as shown in the first line).

0097At the second, third and fourth moments, the output from the adder of each cascade is output from the ALU of each cascade to the ALU of next cascade after being delayed by the delayer for a clock period and is summed with the result output at the identical moment from the selector of the next cascade; the result of the fourth adder is the desired result.

0098When conjugate signs of the spreading code are s1, s3, s5 and s7, data d1, d3, d5 and d7 have sequentially been input at the fourth moment. The result at the fourth adder is the result desired by dispreading, namely d1*s1+d3*s3+d5*s5+d7*s7, which is consistent with the formula on the first line of formula (7). Table 1 shows how the subsequent moment uses the calculation result of the previous moment.

0099In the first and second embodiments, four different values of each of the units are distinguished by dividing each of the units of the spreading sequence into odd and even parts and judging whether the conjugate signs of each of the units of the spreading sequence are positive or negative. Alternatively, the values of each of the units of spreading sequence can be estimated by the preset means <b>10</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>, and then different values are expressed by preset selecting signals capable of representing state numerals corresponding to possible values. For example, in the case of only four possible values, the values' states can be expressed by a two-bit binary value. Hereinafter, the corresponding relationship between each of the component means as shown in <figref idref="DRAWINGS">FIG. 1</figref> and each of the components in the first and second embodiments.

0100The filter <b>101</b> as shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref> and its correlative circuit correspond to the preprocess means <b>20</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>. The means (not shown) for dividing data to be despread into I and Q components in <figref idref="DRAWINGS">FIGS. 4 and 5</figref> corresponds to the extraction means <b>30</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>. The ALU as shown in <figref idref="DRAWINGS">FIG. 5</figref> and the combining circuit containing the selector as shown in <figref idref="DRAWINGS">FIG. 6</figref> or <b>7</b> correspond to the selecting processing means <b>40</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>. Sign sequence [i] as shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref> corresponds to the preset selecting signal produced by the preset means <b>10</b> according to the spreading sequence as shown in <figref idref="DRAWINGS">FIG. 1</figref>. And the adder <b>112</b> as shown in <figref idref="DRAWINGS">FIGS. 4 and 5</figref> corresponds to the summing means <b>50</b> as shown in <figref idref="DRAWINGS">FIG. 1</figref>.

0101In addition to the above embodiments, there are various variations of the present invention. For example, if the signal situation is good enough to ensure the required signal-to-noise ratio, the filter <b>101</b> as shown in <figref idref="DRAWINGS">FIG. 4</figref> can be omitted. <figref idref="DRAWINGS">FIG. 4</figref> describes where the spreading factor SF=16; however, the spreading factor SF can also be in other values, which is usually 2 to the integer power. <figref idref="DRAWINGS">FIG. 4</figref> shows 4 blocks of memory <b>103</b>₀, <b>103</b>_e, <b>104</b>_oand <b>104</b>_efor storing odd and even components of I and Q; however, the memories can also be omitted, as long as the odd and even components of I and Q components are in sequence transmitted in different paths. The first and second embodiments are based on TD-SCDMA standard, whereas the present invention is not limited thereto. The present invention can be applied provided the value of spreading code is within a known limited set. For example, it is known that in the WCDMA standard, the value of spreading code is in the range of {I+j, 1−j, −I+j, −1−j}, it can be obtained by substituting the values into the formulas (3) and (4) to obtain:

0102<maths id="MATH-US-00008" num="00008"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>y</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><mrow><mi>z</mi><mo>⁡</mo><mrow><mo>[</mo><mrow><mrow><mrow><mo>(</mo><mrow><mi>n</mi><mo>-</mo><mn>1</mn></mrow><mo>)</mo></mrow><mo>×</mo><mi>SF</mi></mrow><mo>+</mo><mi>i</mi></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow><mo>=</mo><mrow><mrow><mrow><mi>w</mi><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>×</mo><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow></mrow><mo>=</mo><mrow><mo>{</mo><mrow><mtable><mtr><mtd><mrow><mrow><mo>(</mo><mrow><mi>I</mi><mo>-</mo><mi>Q</mi></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mi>j</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mi>I</mi><mo>+</mo><mi>Q</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mn>1</mn><mo>+</mo><mi>j</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>(</mo><mrow><mi>I</mi><mo>+</mo><mi>Q</mi></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mi>j</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mrow><mo>-</mo><mi>I</mi></mrow><mo>+</mo><mi>Q</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mn>1</mn><mo>-</mo><mi>j</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>(</mo><mrow><mrow><mo>-</mo><mi>I</mi></mrow><mo>-</mo><mi>Q</mi></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mi>j</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mi>I</mi><mo>-</mo><mi>Q</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><mo>-</mo><mn>1</mn></mrow><mo>+</mo><mi>j</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mrow><mo>(</mo><mrow><mrow><mo>-</mo><mi>I</mi></mrow><mo>+</mo><mi>Q</mi></mrow><mo>)</mo></mrow><mo>+</mo><mrow><mi>j</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mrow><mo>-</mo><mi>I</mi></mrow><mo>-</mo><mi>Q</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mrow><msup><mi>p</mi><mo>*</mo></msup><mo>⁡</mo><mrow><mo>(</mo><mi>i</mi><mo>)</mo></mrow></mrow><mo>=</mo><mrow><mrow><mo>-</mo><mn>1</mn></mrow><mo>-</mo><mi>j</mi></mrow></mrow></mtd></mtr></mtable><mo>.</mo></mrow></mrow></mrow></mrow></mrow></mtd><mtd><mrow><mo>(</mo><mn>12</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8958459B2_D0008.tif" />

0103It is evident that a corresponding element can be definitely selected from the set {(I−Q)+j(I+Q), (I+Q)+j(−I+Q), (−I−Q)+j(I−Q), (−I+Q)+j(−I−Q)} to serve as a despread result based on the value of the spreading code when the present invention is applied in the WCDMA standard.

0104Many other modifications and variations can be made without departing from the concept and scope of the present invention. It is understood that the present invention is not limited to the specific embodiments, and the scope thereof should be defined by the appended claims.