Image pickup apparatus having photoelectric conversion function
Summary by NHIP
CMOS Image Sensor with Shared Impurity Regions
The apparatus comprises pixel units containing photoelectric conversion elements, transfer transistors, and charge storage portions with multiple floating diffusions. Distinctive shared impurity regions connect the amplification and select transistors within each pixel, while coupling transistors link floating diffusions across different pixels under scanning circuit control.
Claim Score by NHIP
Abstract
An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode.
Term
3.4 yearsleft in the term
Expires 4 February 2030.
- Priority
- Filed
- Granted
- Today
- Expires
12 claims: 3 independent, 9 dependent
- 1Broadest claimClaim Score 50, average(NHIP)An image pickup apparatus comprising:a plurality of pixel units, wherein each of the pixel units includes: a photoelectric conversion element producing electric charges corresponding to incident light;a transfer transistor transferring the electric charges generated at the photoelectric conversion element;and a charge storage portion coupled with the photoelectric conversion element through the transfer transistor, the charge storage portion storing the electric charges generated at the photoelectric conversion element, the charge storing portion including multiple floating diffusions;an amplification transistor outputting a signal corresponding to the electric charge stored in the charge storage portion;and a select transistor coupled with the amplification transistor, the select transistor bringing each of the pixel units into a selected state, wherein the image pickup apparatus further includes a coupling transistor coupling together the floating diffusions of different pixel units, and wherein, in each of the pixel units, the amplification transistor and the select transistor have an impurity region common thereto.
- 6An image pickup apparatus comprising:a first photoelectric conversion element disposed in a first pixel unit, the first photoelectric conversion element producing electric charge corresponding to incident light;a first transfer transistor disposed in the first pixel unit, the first transfer transistor transferring the electric charge generated at the first photoelectric conversion element;a first charge storage portion disposed in the first pixel unit, the first charge storage portion coupled with the first photoelectric conversion element through the first transfer transistor, and storing the electric charge generated at the first photoelectric conversion element, the first charge storing portion including multiple first floating diffusions;a first amplification transistor disposed in the first pixel unit, the first amplification transistor outputting a signal corresponding to the electric charge stored in the first charge storage portion;a first select transistor disposed in the first pixel unit, the first select transistor coupled with the first amplification transistor and bringing the first pixel unit into a selected state;a second photoelectric conversion element disposed in a second pixel unit, the second photoelectric conversion element producing electric charge corresponding to incident light;a second transfer transistor disposed in the second pixel unit, the second transfer transistor transferring the electric charge generated at the second photoelectric conversion element;a second charge storage portion disposed in the second pixel unit, the second charge storage portion coupled with the second photoelectric conversion element through the second transfer transistor, and storing the electric charge generated at the second photoelectric conversion element, the second charge storing portion including multiple second floating diffusions;a second amplification transistor disposed in the second pixel unit, the second amplification transistor outputting a signal corresponding to the electric charge stored in the second charge storage portion;a second select transistor disposed in the second pixel unit, the second select transistor coupled with the second amplification transistor and bringing the second pixel unit into a selected state;a coupling transistor coupling the first floating diffusions and the second floating diffusions, wherein the first amplification transistor and the first select transistor have a common impurity region.
- 11An image pickup apparatus comprising:a first photoelectric conversion element disposed in a first pixel unit, the first photoelectric conversion element producing electric charge corresponding to incident light;a first transfer transistor disposed in the first pixel unit, the first transfer transistor transferring the electric charge generated at the first photoelectric conversion element;a first charge storage portion disposed in the first pixel unit, the first charge storage portion coupled with the first photoelectric conversion element through the first transfer transistor, and storing the electric charge generated at the first photoelectric conversion element, the first charge storing portion including multiple first floating diffusions;a first reset transistor disposed in the first pixel unit, the first reset transistor discharging the electric charges stored in the first charge storage portion;a second photoelectric conversion element disposed in a second pixel unit, the second photoelectric conversion element producing electric charge corresponding to incident light;a second transfer transistor disposed in the second pixel unit, the second transfer transistor transferring the electric charge generated at the second photoelectric conversion element;a second charge storage portion disposed in the second pixel unit, the second charge storage portion coupled with the second photoelectric conversion element through the second transfer transistor, and storing the electric charge generated at the second photoelectric conversion element, the second charge storing portion including multiple second floating diffusions;and a coupling transistor coupling together the first floating diffusions and the second floating diffusions, wherein the coupling transistor and the first reset transistor have a common impurity region which performs as a drain impurity region or a source impurity region.
Independent claims3
145 paragraphs in 6 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Continuation of U.S. application Ser. No. 12/700,316, filed Feb. 4, 2010, which in turn claims the benefit of Japanese Application No. 2009-53724, filed on Mar. 6, 2009, the disclosures of which applications are incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to an image pickup apparatus having a photoelectric conversion function.
Image sensors of CCD (Charge Coupled Device), CMOS (Complementary Metal-Oxide Semiconductor), and the like are required that their dynamic range should be widened with high sensitivity and a high S/N (Signal-to-Noise) ratio maintained. As image pickup apparatuses whose dynamic range can be widened, for example, the following technologies are known.
In the technology disclosed in Japanese Unexamined Patent Publication No. 2006-217410 (Patent Document 1), each pixel of an image pickup apparatus includes the following: a photodiode, a transfer transistor, a floating diffusion (floating area), an overflow gate, a storage capacitor, a reset transistor, a storage transistor, an amplification transistor, and a select transistor. (Refer to FIG. 1 in the document.)
The photodiode receives light and generates and stores photocharges. The transfer transistor is provided adjacently to the photodiode and transfers photocharges generated at the photodiode. The floating diffusion is coupled to the photodiode through the transfer transistor. The overflow gate is provided adjacently to the photodiode to transfer photocharges overflowing the photodiode in storage operation. The storage capacitor stores photocharges overflowing the photodiode in storage operation through the overflow gate. The reset transistor is so formed that it is coupled to the floating diffusion and discharges signal charges in the storage capacitor and the floating diffusion. The storage transistor is provided between the floating diffusion and the storage capacitor. The amplification transistor reads as voltage the signal charges of the floating diffusion or the signal charges of the floating diffusion and storage capacitor. The select transistor is coupled to the amplification transistor and selects a pixel or a pixel block.
In the technology disclosed in Japanese Unexamined Patent Publication No. 2006-245522 (Patent Document 2), each pixel of an image pickup apparatus includes the following: a photodiode, a transfer transistor, a floating diffusion, first and second storage capacitors, a reset transistor, first and second storage transistors, an amplification transistor, and a select transistor. (Refer to FIG. 1 in the document.)
The photodiode receives light and generates photocharges. The transfer transistor is provided adjacently to the photodiode and transfers photocharges generated at the photodiode. The floating diffusion is so provided that it is coupled to the photodiode through the transfer transistor. The first and second storage capacitors store photocharges overflowing the photodiode in exposure storage operation through the transfer transistor. The reset transistor is so formed that it is coupled to the first storage capacitor and discharges signal charges in the first storage capacitor, second storage capacitor, and floating diffusion. The first storage transistor is provided between the floating diffusion and the first storage capacitor. The second storage transistor is provided between the first storage capacitor and the second storage capacitor. The amplification transistor reads as voltage the signal charges of the floating diffusion, the signal charges of the floating diffusion and the first storage capacitor, or the signal charges of the floating diffusion, first storage capacitor, and second storage capacitor. The select transistor is coupled to the amplification transistor and selects a pixel or a pixel block.
PRIOR ART DOCUMENTS
Patent Documents
[Patent Document 1]
<ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0008">Japanese Unexamined Patent Publication No. 2006-217410 <br /> [Patent Document 2] </li><li id="ul0001-0002" num="0009">Japanese Unexamined Patent Publication No. 2006-245522</li></ul>
SUMMARY OF THE INVENTION
In the image pickup apparatuses described in the above documents, it is switched by a transistor switch whether to couple a capacitive element added to each pixel to a floating diffusion. A dynamic range is adjusted based on whether or not a capacitive element is coupled as mentioned above.
In these technologies, however, the percentage of the area occupied by a photodiode in a pixel is reduced as compared with conventional cases because of the addition of the capacitive element and it is suspected to be difficult to maintain high picture quality. Therefore, these technologies are unsuitable for applications such as digital cameras though they may be suitable for applications such as surveillance cameras and in-vehicle cameras in which dynamic range takes precedence over picture quality. In applications such as digital cameras, it is required to maintain high picture quality and further widen a dynamic range.
Therefore, it is an object of the invention to provide an image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range.
In sum, the invention is an image pickup apparatus including multiple pixel units, multiple coupling transistors, and a scanning circuit. Each of the pixel units includes multiple photoelectric conversion elements, multiple transfer transistors, and a charge storage portion.
In each of the pixel units, each photoelectric conversion element generates electric charges corresponding to incident light. The transfer transistors respectively correspond to the photoelectric conversion elements. Each transfer transistor transfers electric charges generated at the corresponding photoelectric conversion element. The charge storage portion is coupled with the photoelectric conversion elements through the transfer transistors and stores electric charges generated at each of the photoelectric conversion elements.
In the image pickup apparatus, each of the coupling transistors couples together the charge storage portions in two pixel unit of the multiple pixel units. In this case, each pixel unit is coupled with at least one of the coupling transistors. The scanning circuit switches on or off the transfer transistors and coupling transistors included in each of the pixel units.
According to the invention, the following processing is carried out when electric charges generated at each photoelectric conversion element are read: a coupling transistor is switched on or off according to light exposure. This makes it possible to vary the capacity of each charge storage portion and thus the dynamic range can be widened. The capacity of each charge storage portion can be made variable by adding one or less junction transistors per pixel unit; therefore, it is possible to maintain high picture quality without scarifying the light receiving area of each photoelectric conversion element.
BRIEF DESCRIPTION OF THE DRAWINGS
<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating the configuration of an image pickup apparatus <b>1</b> in a first embodiment of the invention;
<figref idref="DRAWINGS">FIG. 2</figref> is an equivalent circuit diagram illustrating one column in the pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 1</figref>;
<figref idref="DRAWINGS">FIG. 3</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in normal read mode;
<figref idref="DRAWINGS">FIG. 4</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in lower sensitivity read mode;
<figref idref="DRAWINGS">FIG. 5</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in two-pixel mixture read mode;
<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in three-pixel mixture read mode;
<figref idref="DRAWINGS">FIG. 7</figref> is a plan view schematically illustrating the layout of a pixel array portion <b>10</b>;
<figref idref="DRAWINGS">FIG. 8</figref> is a plan view schematically illustrating the layout of a pixel array portion <b>10</b>A; and
<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram schematically illustrating the configuration of a digital still camera <b>200</b> using the image pickup apparatus <b>1</b> in the first and second embodiments of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereafter, detailed description will be given to embodiments of the invention with reference to the drawings. The same or equivalent parts will be marked with the same reference numerals and the description thereof will not be repeated.
(First Embodiment)
(Configuration of Image Pickup Apparatus <b>1</b>)
<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram illustrating the configuration of an image pickup apparatus <b>1</b> in a first embodiment of the invention.
As illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, the image pickup apparatus <b>1</b> includes a pixel array portion <b>10</b>, a vertical scanning circuit <b>11</b>, a horizontal scanning circuit <b>12</b>, multiple control signal lines tx, rst, sel, sw, and multiple output signal lines vout.
The pixel array portion <b>10</b> includes a photodiode array PDA (photoelectric conversion element array) comprised of multiple photodiodes PD (photoelectric conversion elements) arranged in a matrix pattern. In <figref idref="DRAWINGS">FIG. 1</figref>, a photodiode array PDA of <b>10</b> rows and four columns is shown for the sake of simplicity. Specifically, photodiodes PD in the first column to the fourth column are shown from left to right in <figref idref="DRAWINGS">FIG. 1</figref> and photodiodes PD in the first row to the 10th row are shown from bottom up in <figref idref="DRAWINGS">FIG. 1</figref>. The left and right direction in <figref idref="DRAWINGS">FIG. 1</figref> will be designated as X direction, row direction, or horizontal direction and the top and bottom direction in <figref idref="DRAWINGS">FIG. 1</figref> will be designated as Y direction, column direction, or vertical direction. When the orientations (+side, −side) along each direction are discriminated, they will be discriminated by affixing a sign like +Y direction and −Y direction.
When the image pickup apparatus <b>1</b> is used for color images, a color filter is provided over the light receiving surface of each photodiode PD. In the common Bayer arrangement of color filters, the color filters are arranged as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>. That is, the color filters in green color (G) that are large in the percentage of contribution to luminance signals are arranged in a checkered pattern; and the color filters in red color (R) and blue color (B) are arranged in a checkered pattern in the remaining areas.
In the photodiode array PDA, every four photodiodes successively arranged in each column comprise one group. The four photodiodes PD in each group comprise a pixel unit PU together with multiple transistors. (These transistors are the transfer transistors TX, amplification transistors AMI, select transistors SEL, and reset transistors RST in <figref idref="DRAWINGS">FIG. 2</figref>.) The pixel array portion <b>10</b> operates by on a pixel unit PU-by-pixel unit PU basis.
The pixel array portion <b>10</b> further includes multiple coupling transistors SW. Each coupling transistor SW is provided between pixel units PU adjoining to each other in the column direction. When electric charges generated in each photodiode PD are read, each coupling transistor SW is switched on or off according to the read mode of the image pickup apparatus <b>1</b>. Hereafter, description will be given to the configuration and operation of each pixel unit PU.
<figref idref="DRAWINGS">FIG. 2</figref> is an equivalent circuit diagram of a circuit equivalent to one column of the pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 1</figref>. The pixel units PU coupled to the output signal lines vout<b>1</b> to vout<b>4</b> are identical in electrical circuitry. In <figref idref="DRAWINGS">FIG. 2</figref>, therefore, the pixel units PU<b>1</b>, PU<b>2</b> are coupled to an arbitrary output signal line vout. In this specification, components of the same kind are discriminated by suffixing a number to their reference numerals, like the photodiodes PD<b>1</b> to PD<b>8</b>. When the components of the same kind are generically referred to or any unspecified thing is referred to, their reference numerals are indicated without suffixing a number.
The pixel unit PU<b>1</b> includes: four photodiodes PD<b>1</b> to PD<b>4</b>, four transfer transistors TX<b>1</b> to TX<b>4</b>, four floating diffusions (also referred to as floating diffusion portions) FD<b>1</b> to FD<b>4</b>, one reset transistor RST<b>1</b>, one amplification transistor AMI<b>1</b>, and one select transistor SEL<b>1</b>. The pixel unit PU<b>1</b> further includes a metal wiring FDL<b>1</b> that electrically couples the floating diffusions FD<b>1</b> to FD<b>4</b> together. The floating diffusions FD<b>1</b> to FD<b>4</b> and the metal wiring FDL<b>1</b> forma charge storage portion FDU<b>1</b> that stores electric charges generated in each photodiode PD.
The configuration of the pixel unit PU<b>2</b> is identical. That is, the pixel unit PU<b>2</b> includes: four photodiodes PD<b>5</b> to PD<b>8</b>, four transfer transistors TX<b>5</b> to TX<b>8</b>, four floating diffusions FD<b>5</b> to FD<b>8</b>, one reset transistor RST<b>2</b>, one amplification transistor AMI<b>2</b>, one select transistor SEL<b>2</b>, and a metal wiring FDL<b>2</b>. The floating diffusions FD<b>5</b> to FD<b>8</b> and the metal wiring FDL<b>2</b> forma charge storage portion FDU<b>2</b>.
<figref idref="DRAWINGS">FIG. 2</figref> depicts an arbitrary column. When a column is discriminated from the others, a character representing a column number is added. In this case, characters a, b, c, . . . respectively represent first column, second column, third column, . . . For example, the metal wiring layers FDL in the first column are described as FDL<b>1</b><i>a</i>, FDL<b>2</b><i>a</i>, FDL<b>3</b><i>a</i>, . . . and the metal wiring layers FDL in the second column are described as FDL<b>1</b><i>b</i>, FDL<b>2</b><i>b</i>, FDL<b>3</b><i>b</i>, . . . (Refer to <figref idref="DRAWINGS">FIG. 7</figref>.)
The photodiodes PD<b>1</b> to PD<b>4</b> are photoelectric conversion elements that generate electric charges (electrons) according to received light. The generated electric charges are stored in the n-type impurity regions (diffusion regions) of the p-n junction diodes. The p-type impurity regions as the anodes of the photodiodes PD are grounded.
The floating diffusions FD<b>1</b> to FD<b>4</b> are n-type impurity regions respectively provided in correspondence with the photodiodes PD<b>1</b> to PD<b>4</b>. The impurity concentration of the floating diffusions FD is higher than that of the n-type impurity regions (also referred to as n layers) of the photodiodes PD. The floating diffusions FD<b>1</b> to FD<b>4</b> are respectively coupled with the cathodes (n layers) of the corresponding photodiodes PD through the transfer transistors TX<b>1</b> to TX<b>4</b> as NMOS (N-channel Metal-Oxide Semiconductor) transistors.
The floating diffusions FD<b>1</b> to FD<b>4</b> operate as charge storage portions that store electric charges generated in the photodiodes PD<b>1</b> to PD<b>4</b>. In this case, first, high potential (supply voltage) is applied to each floating diffusion FD and the electric charges are thereby all drawn and they are depleted. When the transfer transistors TX between them and the photodiodes PD are thereafter turned on, the electric charges stored in the n layers of the photodiodes PD are transferred to the floating diffusions FD. At this time, the floating diffusions FD having a higher impurity concentration are higher in depletion potential than the photodiodes PD. Therefore, the electric charges generated in the n layers of the photodiodes PD are all transferred to the floating diffusions FD.
In case of the example in <figref idref="DRAWINGS">FIG. 2</figref>, the floating diffusions FD<b>1</b> to FD<b>4</b> are coupled with one another through the metal wiring FDL<b>1</b>. Therefore, the floating diffusions FD<b>1</b> to FD<b>4</b> are brought to substantially the same potential. The whole of the floating diffusions FD<b>1</b> to FD<b>4</b> and the metal wiring FDL<b>1</b> forms the charge storage portion FDU<b>1</b> common to the individual photodiodes PD.
The amplification transistor AMI<b>1</b> as an NMOS transistor functions as a source follower circuit. The gate of the amplification transistor AMI<b>1</b> is coupled to the floating diffusions FD<b>1</b> to FD<b>4</b> through the metal wiring FDL<b>1</b> and its drain is coupled to a power supply wiring VDD. The source of the amplification transistor AMI<b>1</b> is coupled with an output signal line vout through the select transistor SEL<b>1</b> as an NMOS transistor.
When the select transistor SEL<b>1</b> is on, the amplification transistor AMI<b>1</b> outputs signal voltage corresponding to the potential of the floating diffusions FD<b>1</b> to FD<b>4</b> to the output signal line Vout. The potential of the floating diffusions FD<b>1</b> to FD<b>4</b> is determined according to the number of electric charges transferred from the respective photodiodes PD. At the above time, therefore, the output voltage of the amplification transistor AMI<b>1</b> is linearly varied according to the amount of light received of each photodiode PD.
The reset transistor RST<b>1</b> as an NMOS transistor is coupled between the power supply wiring VDD and the metal wiring FDL<b>1</b>. The reset transistor RST<b>1</b> is provided to discharge the electric charges stored in the floating diffusions FD<b>1</b> to FD<b>4</b>.
As mentioned above, each pixel unit PU includes the four photodiodes PD and the seven transistors comprised of transfer TX, amplification AMI, select SEL, and reset RST. Therefore, 1.75 transistors are provided per photodiode PD and thus the above configuration of the pixel unit PU is generally designated as 1.75 transistor architecture. The transistors of amplification AMI, select SEL, and reset RST are shared among the four photodiodes PD.
The pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 1</figref> further includes multiple coupling transistors SW as NMOS transistors. Each coupling transistor SW is provided between pixel units PU adjoining to each other in the column direction and couples together the respective charge storage portions FDU of these pixel units PU. In <figref idref="DRAWINGS">FIG. 2</figref>, specifically, a coupling transistor SW<b>1</b> coupling together the charge storage portion FDU<b>1</b> of the pixel unit PU<b>1</b> and the charge storage portion FDU<b>2</b> of the pixel unit PU<b>2</b> is depicted. In <figref idref="DRAWINGS">FIG. 2</figref>, further, a coupling transistor SW<b>2</b> coupling together the charge storage portion FDU<b>2</b> of the pixel unit PU<b>2</b> and the charge storage portion of the pixel unit next to the pixel unit PU<b>2</b> in the +Y direction is depicted.
When electric charges generated in each photodiode PD are read, the coupling transistors SW are switched on or off according to the read mode of the image pickup apparatus <b>1</b>. As described later, the read modes include, in addition to normal read mode, lower sensitivity read mode in which read operation is carried out with reduced sensitivity and mixture read mode in which the pixels in the same color are mixed when read operation is carried out.
It is generally thought that the sensitivity of each pixel corresponding to one photodiode PD is determined by the product of three values. A first value is quantum efficiency indicating to how many electrons one photon incident upon a photodiode PD is converted. A second value is conversion gain that refers to the ratio of variation in the potential of a photodiode PD to variation in the potential of a floating diffusion FD. A third value is the gain of an amplification transistor AMI. In general, when the structure of a pixel is determined, these values become constant. In the image pickup apparatus <b>1</b> in the first embodiment, the conversion gain, or the second value, is made variable by providing the coupling transistors SW that couple together charge storage portions FDU adjoining to each other.
To control the turn-on/off of the transfer transistors TX, select transistors SEL, reset transistors RST, and coupling transistors SW, the control signal lines tx, sel, rst, sw are coupled to the gate electrode of each transistor. More specific description will be given. The control signal lines tx<b>1</b> to tx<b>8</b> are respectively coupled to the gates of the transfer transistors TX<b>1</b> to TX<b>8</b>. The control signal lines sel<b>1</b>, sel<b>2</b> are respectively coupled to the gates of the select transistors SEL<b>1</b>, SEL<b>2</b>. The control signal lines rst<b>1</b>, rst<b>2</b> are respectively coupled to the gates of the reset transistors RST<b>1</b>, RST<b>2</b>. The control signal lines sw<b>1</b>, sw<b>2</b> are respectively coupled to the gates of the coupling transistors SW<b>1</b>, SW<b>2</b>.
Supplementary explanation will be given to the overall configuration of the image pickup apparatus <b>1</b> with reference to <figref idref="DRAWINGS">FIG. 1</figref> again. The image pickup apparatus <b>1</b> includes the control signal lines tx, rst, sel, sw extended in the row direction and the output signal lines vout extended in the column direction. The control signal lines tx, rst, sel, sw couple together the vertical scanning circuit <b>11</b> and the pixel array portion <b>10</b> and the output signal lines vout couple together the horizontal scanning circuit <b>12</b> and the pixel array portion <b>10</b>.
The control signal lines tx for the transfer transistors TX are provided individually in correspondence with the rows of the photodiode array PDA. Each control signal line tx is provided in common to the multiple photodiodes PD comprising the corresponding row. In <figref idref="DRAWINGS">FIG. 1</figref>, the control signal lines tx<b>1</b> to tx<b>10</b> respectively provided in correspondence with first row to the 10th row of the pixel array portion <b>10</b> are depicted.
The output signal lines vout are provided to read output voltage corresponding to signal charges generated at each photodiode PD. The output signal lines vout are provided in the order of the columns individually in correspondence with the columns of the photodiode array PDA. Each output signal line vout is coupled to the select transistor SEL of each pixel unit PU provided in the corresponding column. In <figref idref="DRAWINGS">FIG. 1</figref>, the output signal lines vout<b>1</b> to vout<b>4</b> provided in correspondence with the first column to the fourth column are depicted.
The control signal lines sel for the select transistors SEL include control signals line sel<b>1</b><i>o</i>, sel<b>2</b><i>o</i>, . . . for odd-numbered columns and control signal lines sel<b>1</b><i>e</i>, sel<b>2</b><i>e</i>, . . . for even-numbered columns. (The odd-numbered columns and the even-numbered columns are discriminated from each other by suffixing a character of o or e to their reference numerals.) Each of the control signal lines sel<b>1</b><i>o</i>, sel<b>2</b><i>o</i>, . . . for odd-numbered columns is coupled with the select transistor SEL of the pixel unit PU provided in the corresponding odd-numbered column. Each of the control signal lines sel<b>1</b><i>o</i>, sel<b>2</b><i>o</i>, . . . for even-numbered columns is coupled with the select transistor SEL of the pixel unit PU provided in the corresponding even-numbered column. The pixel units PU arranged in the row direction share a control signal line sel among them.
The control signal lines rst for the reset transistors RST include control signal lines rst<b>1</b><i>o</i>, rst<b>2</b><i>o</i>, . . . for odd-numbered columns and control signal lines rst<b>1</b><i>e</i>, rst<b>2</b><i>e</i>, . . . for even-numbered columns. The control signal lines rst<b>1</b><i>o</i>, rst<b>2</b><i>o</i>, . . . for odd-numbered columns are coupled with the reset transistors RST of the pixel units PU provided in the respective odd-numbered columns. The control signal lines rst<b>1</b><i>e</i>, rst<b>2</b><i>e</i>, . . . for even-numbered columns are coupled with the reset transistors RST of the pixel units PU provided in the respective even-numbered columns. The pixel units PU arranged in the row direction share a control signal line rst among them.
The control signal lines sw for the coupling transistors SW include control signal lines sw<b>1</b><i>o</i>, sw<b>2</b><i>o</i>, . . . for odd-numbered columns and control signal line sw<b>1</b><i>e</i>, sw<b>2</b><i>e</i>, . . . for even-numbered columns. Each of the control signal lines sw<b>1</b><i>o</i>, sw<b>2</b><i>o</i>, . . . for odd-numbered columns is coupled with the coupling transistor SW provided between pixel units PU adjoining to each other in the corresponding odd-numbered column. Each of the control signal lines sw<b>1</b><i>e</i>, sw<b>2</b><i>e</i>, . . . for even-numbered columns is coupled with the coupling transistor SW provided between pixel units PU adjoining to each other in the corresponding even-numbered column. The coupling transistors SW arranged in the row direction share a control signal line sw among them.
The vertical scanning circuit <b>11</b> sequentially switches the voltage of the control signal lines tx, rst, sel to the H level or the L level. At this time, the vertical scanning circuit <b>11</b> switches the control signal lines sw to the H level or the L level according to the read mode. As a result, the voltage corresponding to the amount of electric charges stored in each row of the photodiode array PDA is outputted to an output signal line vout with respect to each row of the photodiode array PDA. The horizontal scanning circuit <b>12</b> sequentially reads voltages outputted to the output signal lines vout and thereby detects the amount of light received of each photodiode PD.
(Read Operation of Image Pickup Apparatus <b>1</b>—Normal Read Mode)
Concrete description will be given to the procedure for reading the signal charges of each photodiode PD in the image pickup apparatus <b>1</b>. First, description will be given to normal read mode in which the electric charges generated in each photodiode PD are individually read on a photodiode PD-by-photodiode PD basis.
<figref idref="DRAWINGS">FIG. 3</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in normal read mode. <figref idref="DRAWINGS">FIG. 3</figref> indicates the following from top down: the opened/closed state of a mechanical shutter, the voltage waveforms of the control signal lines tx<b>1</b> to tx<b>8</b>, rst<b>1</b>, rst<b>2</b>, sw<b>1</b>, sw<b>2</b>, sel<b>1</b>, sel<b>2</b> in <figref idref="DRAWINGS">FIG. 2</figref>, and the voltage waveform of an output signal line vout. In normal read mode, the voltages of the control signal lines sw<b>1</b>, sw<b>2</b> are at the L level in every period of time and the coupling transistors SW<b>1</b>, SW<b>2</b> are kept off. Hereafter, description will be given to the procedure for reading the signal charges of each photodiode PD in the pixel units PU<b>1</b>, PU<b>2</b> in order of time with reference to <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 3</figref>.
At time t<b>1</b>, the voltages of the control signal lines tx<b>1</b> to tx<b>8</b>, rst<b>1</b>, rst<b>2</b> are at the H level and the voltages of the control signal lines sel<b>1</b>, sel<b>2</b> are at the L level. Therefore, the transfer transistors TX<b>1</b> to TX<b>8</b> and the reset transistors RST<b>1</b>, RST<b>2</b> are on. As a result, the electric charges in the n layers of the photodiodes PD<b>1</b> to PD<b>8</b> and the floating diffusions FD<b>1</b> to F<b>8</b> are all drawn and they are depleted. When the voltages of the control signal lines tx<b>1</b> to tx<b>8</b> are thereafter returned to the L level, the transfer transistors TX<b>1</b> to TX<b>8</b> are turned off.
At time t<b>2</b>, subsequently, the mechanical shutter is opened. While the shutter is open, electric charges are generated at the photodiodes PD<b>1</b> to PD<b>8</b> by incident light and stored in the n layers of the photodiodes PD<b>1</b> to PD<b>8</b>.
At time t<b>3</b> after the shutter is closed, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the L level; the voltage of the control signal line sel<b>1</b> is at the H level; and the voltage of the control signal line sel<b>2</b> is at the L level. As a result, the reset transistors RST<b>1</b>, RST<b>2</b> are turned off and the select transistor SEL<b>1</b> is turned on. Therefore, output voltage corresponding to the depletion potential of the floating diffusions FD<b>1</b> to FD<b>4</b> (the potential of the charge storage portion FDU<b>1</b>) is outputted to an output signal line vout. The horizontal scanning circuit <b>12</b> in the <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout at this time as dark level output.
At time t<b>4</b>, subsequently, the voltage of the control signal line tx<b>1</b> is brought to the H level and thus the transfer transistor TX<b>1</b> is turned on. As a result, the electric charges of the photodiode PD<b>1</b> are transferred to the floating diffusions FD<b>1</b> to FD<b>4</b>. The potential of the floating diffusions FD<b>1</b> to FD<b>4</b> is changed to a value corresponding to the number of electric charges transferred from the photodiode PD<b>1</b> and in conjunction therewith, the voltage of the output signal line vout is varied.
At time t<b>5</b> after the voltage of the control signal line tx<b>1</b> is returned to the L level, the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout at this time. The difference from the dark level output detected at time t<b>3</b> becomes the light reception signal of the photodiode PD<b>1</b>.
At time t<b>6</b>, subsequently, the voltage of the control signal line rst<b>1</b> is at the H level and the voltage of the control signal line sell is at the L level. As a result, the electric charges of the floating diffusions FD<b>1</b> to F<b>4</b> are all drawn and they are initialized. This terminates the readout of signal charges obtained by receiving light at the photodiode PD<b>1</b> and preparation for the readout of signal charges of the next photodiode PD<b>2</b> is completed.
During the period from time t<b>6</b> to time t<b>7</b>, subsequently, the same process as during the period from time t<b>3</b> to time t<b>6</b> is carried out on the photodiode PD<b>2</b> and the signal charges generated at the photodiode PD<b>2</b> are read. During the period from time t<b>7</b> to time t<b>8</b>, similarly, the signal charges generated at the photodiode PD<b>3</b> are read and during the period from time t<b>8</b> to time t<b>9</b>, the signal charges obtained by receiving light at the photodiode PD<b>4</b> are read. This completes the readout of the pixel unit PU<b>1</b>.
At time t<b>9</b>, the voltage of the control signal line rst<b>1</b> is at the L level and the voltage of the control signal line rst<b>2</b> is at the H level. Further, the voltages of the control signal lines sel<b>1</b>, sel<b>2</b> are at the L level. As a result, the reset transistor RST<b>2</b> is turned on and the electric charges of the floating diffusions FD<b>5</b> to FD<b>8</b> are all drawn and they are initialized. This completes preparation for reading the signal charges of the photodiode PD<b>5</b> of the next pixel unit PU<b>2</b>.
At time t<b>10</b>, subsequently, the voltage of the control signal line sel<b>2</b> is brought to the H level and a dark level signal of the floating diffusions FD<b>5</b> to FD<b>8</b> (charge storage portion FDU<b>2</b>) is thereby outputted. At time t<b>11</b>, thereafter, the control signal line tx<b>5</b> is brought to the H level and the transfer transistor TX<b>5</b> is thereby turned on. As a result, the electric charges of the photodiode PD<b>5</b> are transferred to the floating diffusions FD<b>5</b> to FD<b>8</b>. At time t<b>12</b>, subsequently, voltage corresponding to the transferred electric charges is read through the output signal line vout.
The same read operation is performed during the period from t<b>13</b> to time t<b>14</b>, during the period from time t<b>14</b> to time t<b>15</b>, and during the period from time t<b>15</b> to time t<b>16</b>. The signal charges generated in the photodiodes PD<b>6</b> to PD<b>8</b> are thereby sequentially read. This completes the readout of the pixel unit PU<b>2</b>.
(Read Operation of Image Pickup Apparatus <b>1</b>—Lower Sensitivity Read Mode)
Description will be given to lower sensitivity read mode in which readout is carried out with the sensitivity of the image pickup apparatus <b>1</b> reduced.
In general, image sensors for digital cameras are required to have a wide range of ISO sensitivity. At this time, it is required to obtain high-resolution picture quality in a low ISO sensitivity range within which light exposure is high. Further, it is required to increase an S/N ratio as much as possible to obtain an image with less noise in a high ISO sensitivity range within which light exposure is low.
To improve an S/N ratio in a high ISO sensitivity range, increasing photoelectric conversion efficiency is effective. If this is done, however, the signal level is early saturated in a low ISO sensitivity range (overexposure becomes excessive in images) and the dynamic range is narrowed.
Consequently, the following measure is taken in the image pickup apparatus <b>1</b> in lower sensitivity read mode: in a low ISO sensitivity range within which light exposure is high, the coupling transistor SW provided between a pixel unit PU provided with a photodiode PD to be read and the pixel unit PU adjacent thereto is turned on. This increases the capacity of the charge storage portion FDU; therefore, the saturation of signal level in the low ISO sensitivity range can be prevented.
<figref idref="DRAWINGS">FIG. 4</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in lower sensitivity read mode. The vertical axis in <figref idref="DRAWINGS">FIG. 4</figref> indicates the same items as that in <figref idref="DRAWINGS">FIG. 3</figref>. Hereafter, description will be given to the procedure for reading the signal charges of each photodiode PD in the pixel units PU<b>1</b>, PU<b>2</b> in order of time with reference to <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 4</figref>. The operations at time t<b>1</b> and time t<b>2</b> are the same as those in <figref idref="DRAWINGS">FIG. 3</figref> and the description thereof will not be repeated.
At time t<b>3</b> after the shutter is closed, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the L level; the voltages of the control signal lines sw<b>1</b>, sel<b>1</b> are at the H level; and the voltages of the control signal lines sw<b>2</b>, sel<b>2</b> are at the L level. Therefore, the reset transistors RST<b>1</b>, RST<b>2</b> are off and the coupling transistor SW<b>1</b> and the select transistor SEL<b>1</b> are on. As a result, the charge storage portions FDU<b>1</b> and FDU<b>2</b> are coupled together by the coupling transistor SW<b>1</b> in the on state. Therefore, output voltage corresponding to the depletion potential of the floating diffusions FD<b>1</b> to FD<b>8</b> (the potential of the entire charge storage portions FDU<b>1</b> and FDU<b>2</b>) is outputted to the output signal line vout. The horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout at this time as dark level output.
At time t<b>4</b>, subsequently, the voltage of the control signal line tx<b>1</b> is brought to the H level and thus the transfer transistor TX<b>1</b> is turned on. As a result, the electric charges of the photodiode PD<b>1</b> are transferred to the floating diffusion FD<b>1</b> to FD<b>8</b> (the entire charge storage portions FDU<b>1</b> and FDU<b>2</b>). The potential of the floating diffusions FD<b>1</b> to FD<b>8</b> is changed to a value corresponding to the number of electric charges transferred from the photodiode PD<b>1</b> and in conjunction therewith, the voltage of the output signal line vout is varied. At this time, the capacity of the charge storage portions FDU is approximately twice that in normal read mode; therefore, the potential of the charge storage portions FDU is substantially half of that in normal read mode. Consequently, the saturation of the output voltage vout can be prevented.
At time t<b>5</b> after the voltage of the control signal line tx<b>1</b> is returned to the L level, the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout at this time. The difference from the dark level output detected at time t<b>3</b> becomes the light reception signal of the photodiode PD<b>1</b>.
At time t<b>6</b>, subsequently, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the H level and the voltages of the control signal lines sw<b>1</b>, sw<b>2</b>, sel<b>1</b>, sel<b>2</b> are at the L level. As a result, the electric charges of the floating diffusions FD<b>1</b> to FD<b>8</b> are all drawn and they are initialized. This terminates the readout of signal charges obtained by receiving light at the photodiode PD<b>1</b> in lower sensitivity read mode and preparation for the readout of signal charges of the next photodiode PD<b>2</b> in lower sensitivity read mode is completed.
During the period from time t<b>6</b> to time t<b>7</b>, subsequently, the same process as during the period from time t<b>3</b> to time t<b>6</b> is carried out on the photodiode PD<b>2</b> and the signal charges generated at the photodiode PD<b>2</b> are read. During the period from time t<b>7</b> to time t<b>8</b>, similarly, the signal charges generated at the photodiode PD<b>3</b> are read and during the period from time t<b>8</b> to time t<b>9</b>, the signal charges obtained by receiving light at the photodiode PD<b>4</b> are read. This completes the readout of the pixel unit PU<b>1</b> in lower sensitivity read mode.
Also with respect to the pixel unit PU<b>2</b>, the signal charges of the photodiodes PD<b>5</b> to PD<b>8</b> are similarly read when the voltage of the control signal line sw<b>1</b> is at the H level (the coupling transistor SW<b>1</b> is on). That is, the same read operation as in the pixel unit PU<b>1</b> is carried out during the following periods: the period from time t<b>9</b> to time t<b>10</b>, the period from time t<b>10</b> to time t<b>11</b>, the period from time t<b>11</b> to time t<b>12</b>, and the period from time t<b>12</b> to time t<b>13</b>. As a result, the signal charges of the photodiodes PD<b>5</b> to PD<b>8</b> are read. This completes the readout of the pixel unit PU<b>2</b> in lower sensitivity read mode.
(Read Operation of Image Pickup Apparatus <b>1</b>—Two-Pixel Mixture Read Mode)
Description will be given to two-pixel mixture read mode in which two pixels in the same color are mixed when read operation is performed.
The number of pixels of each recent digital still camera has been significantly increased and that of some cameras exceeds 10 million (10M) pixels. When a digital camera is used to take not only freeze-frame pictures but also moving video pictures, however, a problem arises. When all the 10 million (10M) pixels are used to take a moving video picture, the number of pixels is too large and this is not practical. This is apparent from the fact that even the full-HD (Full High Definition) digital television is approximately two million (2M) pixels in the number of pixels.
When it is required to carry out high-speed readout as in taking a moving video picture as mentioned above, pixel mixture readout is an effective means. In the pixel mixture readout, the electric charges generated in multiple pixels (photodiodes PD) in the same color are mixed when they are read. The pixel mixture readout is an effective technique also to enhance an S/N ratio to obtain an image with less noise in a high ISO sensitivity range within which the readout light exposure is low.
Hereafter, description will be given to two-pixel mixture read mode. In this case, the following operation is performed, for example, at each pixel unit PU in the first column in <figref idref="DRAWINGS">FIG. 1</figref>: two pixels in green color (G) or red color (R) are mixed and read. At each pixel unit PU in the second column, two pixels in green color (G) or blue color (B) are mixed and read. Therefore, when two-pixel mixture readout is carried out with the 1.75 transistor architecture, it can be carried out with each coupling transistor SW kept off.
<figref idref="DRAWINGS">FIG. 5</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in two-pixel mixture read mode. The vertical axis in <figref idref="DRAWINGS">FIG. 5</figref> indicates the same items as that in <figref idref="DRAWINGS">FIG. 3</figref>. In two-pixel mixture read mode, the voltages of the control signal lines sw<b>1</b>, sw<b>2</b> are at the L level in every period of time and the coupling transistors SW<b>1</b>, SW<b>2</b> are kept off. Hereafter, description will be given to the procedure for reading the signal charges of each photodiode PD in the pixel units PU<b>1</b>, PU<b>2</b> in order of time with reference to <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 5</figref>. The operation during the period from time t<b>1</b> to time t<b>3</b> is the same as that in <figref idref="DRAWINGS">FIG. 3</figref> and the description thereof will not be repeated.
At time t<b>4</b>, the voltages of the control signal lines tx<b>1</b>, tx<b>3</b> are brought to the H level and thus the transfer transistors TX<b>1</b>, TX<b>3</b> are turned on. As a result, the mixed electric charges of the photodiodes PD<b>1</b>, PD<b>3</b> are transferred to the floating diffusions FD<b>1</b> to FD<b>4</b>. (In case of odd-numbered columns in <figref idref="DRAWINGS">FIG. 1</figref>, the photodiodes PD<b>1</b>, PD<b>3</b> correspond to red color (R); and in case of even-numbered columns, the photodiodes PD<b>1</b>, PD<b>3</b> correspond to green color (G).) The potential of the floating diffusions FD<b>1</b> to FD<b>4</b> is changed to a value corresponding to the number of electric charges transferred from the photodiodes PD<b>1</b>, PD<b>3</b> and in conjunction therewith, the voltage of the output signal line vout is varied.
At time t<b>5</b> after the voltages of the control signal lines tx<b>1</b>, tx<b>3</b> are returned to the L level, the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout. The difference from the dark level output detected at time t<b>3</b> becomes a signals arising from the mixed electric charges of the photodiodes PD<b>1</b>, PD<b>3</b>.
At time t<b>6</b>, subsequently, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the H level and the voltages of the control signal lines sel<b>1</b>, sel<b>2</b> are at the L level. As a result, the electric charges of the floating diffusions FD<b>1</b> to FD<b>8</b> are all drawn and they are initialized. This terminates the readout of signal charges obtained by receiving light at the photodiodes PD<b>1</b>, PD<b>3</b> and preparation for the readout of signal charges of the next photodiodes PD<b>2</b>, PD<b>4</b> is completed. (In case of odd-numbered columns in <figref idref="DRAWINGS">FIG. 1</figref>, the photodiodes PD<b>2</b>, PD<b>4</b> correspond to green color (G); and in case of even-numbered columns, the photodiodes PD<b>2</b>, PD<b>4</b> correspond to blue color (B).)
During the period from time t<b>6</b> to time t<b>10</b>, subsequently, the same process as during the period from time t<b>3</b> to time t<b>6</b> is carried out on the photodiodes PD<b>2</b>, PD<b>4</b> and the signal charges generated at the photodiodes PD<b>2</b>, PD<b>4</b> are read. More specific description will be given. At time t<b>7</b>, the voltage of the control signal line sell is at the H level and a dark level voltage signal is outputted to the output signal line vout. At time t<b>8</b>, the control signal lines tx<b>2</b>, tx<b>4</b> are brought to the H level. Therefore, the mixed electric charges of the electric charges generated at the photodiodes PD<b>2</b>, PD<b>4</b> are transferred to the floating diffusions FD<b>1</b> to FD<b>4</b> (charge storage portion FDU<b>1</b>). At time t<b>9</b> after the control signal lines tx<b>2</b>, tx<b>4</b> are returned to the L level, the voltage of the output signal line vout corresponding to the mixed electric charges of the photodiodes PD<b>2</b>, PD<b>4</b> is detected by the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref>. The difference from the dark level output detected at time t<b>7</b> becomes a signal arising from the mixed electric charges of the photodiodes PD<b>2</b>, PD<b>4</b>. This completes the readout of the signal charges of the pixel unit PU<b>1</b> in two-pixel mixture mode.
Subsequently, the similar operation is performed. That is, during the period from time t<b>10</b> to time t<b>11</b>, the voltage of the control signal line sel<b>2</b> is at the H level and the voltages of the control signal lines tx<b>5</b>, tx<b>7</b> are brought to the H level. As a result, voltage corresponding to the mixed electric charges of the photodiodes PD<b>5</b>, PD<b>7</b> is outputted to the output signal line vout. During the period from time t<b>11</b> to time t<b>12</b>, voltage corresponding to the mixed electric charges of the photodiodes PD<b>6</b>, PD<b>8</b> is outputted to the output signal line vout. This completes the readout of the signal charges of the pixel unit PU<b>2</b> in two-pixel mixture mode.
(Read Operation of Image Pickup Apparatus <b>1</b>—Three-Pixel Mixture Read Mode)
Description will be given to three-pixel mixture read mode in which three pixels in the same color are mixed when read operation is performed.
In case of three-pixel mixture readout, the following operation is performed, for example, at the pixel units PU in the first column in <figref idref="DRAWINGS">FIG. 1</figref>: three pixels in green color (G) or red color (R) are mixed and read. At the pixel units PU in the second column, three pixels in green color (G) or blue color (B) are mixed and read. Therefore, when three-pixel mixture readout is carried out with the 1.75 transistor architecture, it is required to turn on the coupling transistor SW between pixel units PU adjoining to each other.
<figref idref="DRAWINGS">FIG. 6</figref> is a timing chart explaining the read operation of the image pickup apparatus <b>1</b> in three-pixel mixture read mode. The vertical axis in <figref idref="DRAWINGS">FIG. 6</figref> indicates the same items as that in <figref idref="DRAWINGS">FIG. 3</figref>. Hereafter, description will be given to the procedure for reading the signal charges of each photodiode PD in the pixel units PU<b>1</b>, PU<b>2</b> in order of time with reference to <figref idref="DRAWINGS">FIG. 2</figref> and <figref idref="DRAWINGS">FIG. 6</figref>. The operation during the period from time t<b>1</b> to time t<b>3</b> is the same as that in <figref idref="DRAWINGS">FIG. 4</figref> and the description thereof will not be repeated.
At time t<b>4</b>, the voltages of the control signal lines tx<b>1</b>, tx<b>3</b>, tx<b>5</b> are brought to the H level and thus the transfer transistors TX<b>1</b>, TX<b>3</b>, TX<b>5</b> are turned on. Since the coupling transistor SW<b>1</b> is on, the mixed electric charges of the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b> are transferred to the floating diffusions FD<b>1</b> to FD<b>8</b> (the entire charge storage portions FDU<b>1</b> and FDU<b>2</b>). (In case of odd-numbered columns in <figref idref="DRAWINGS">FIG. 1</figref>, the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b> correspond to red color (R); and in case of even-numbered columns, the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b> correspond to green color (G).) The potential of the floating diffusions FD<b>1</b> to FD<b>8</b> is changed to a value corresponding to the number of electric charges transferred from the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b> and in conjunction therewith, the voltage of the output signal line vout is varied.
At time t<b>5</b> after the voltages of the control signal lines tx<b>1</b>, tx<b>3</b>, tx<b>5</b> are returned to the L level, the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref> detects the voltage of the output signal line vout at this time. The difference from the dark level output detected at time t<b>3</b> becomes a signal arising from the mixed electric charges of the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b>.
At time t<b>6</b>, subsequently, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the H level and the voltages of the control signal lines sw<b>1</b>, sw<b>2</b>, sel<b>1</b>, sel<b>2</b> are at the L level. As a result, the electric charges of the floating diffusions FD<b>1</b> to FD<b>8</b> are all drawn and they are initialized. This terminates the readout of signal charges obtained by receiving light at the photodiodes PD<b>1</b>, PD<b>3</b>, PD<b>5</b> and preparation for the readout of signal charges of the next photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> is completed. (In case of odd-numbered columns in <figref idref="DRAWINGS">FIG. 1</figref>, the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> correspond to green color (G); and in case of even-numbered columns, the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> correspond to blue color (B).)
During the period from time t<b>6</b> to time t<b>10</b>, subsequently, the same process as during the period from time t<b>3</b> to time t<b>6</b> is carried out on the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> and signal charges generated at the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> are read. More specific description will be given. At time t<b>7</b>, the voltages of the control signal lines sw<b>1</b>, sell are at the H level and a dark level voltage signal is outputted to the output signal line vout. At time t<b>8</b>, the control signal lines tx<b>2</b>, tx<b>4</b>, tx<b>6</b> are brought to the H level. Therefore, the mixed electric charges of the electric charges generated at the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> are transferred to the floating diffusions FD<b>1</b> to FD<b>8</b> (the entire charge storage portions FDU<b>1</b> and FDU<b>2</b>). At time t<b>9</b> after the control signal lines tx<b>2</b>, tx<b>4</b>, tx<b>6</b> are returned to the L level, the voltage of the output signal line vout corresponding to the mixed electric charges of the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> is detected by the horizontal scanning circuit <b>12</b> in <figref idref="DRAWINGS">FIG. 1</figref>. The difference from the dark level output detected at time t<b>7</b> becomes a signal arising from the mixed electric charges of the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b>.
At time t<b>10</b>, subsequently, the voltages of the control signal lines rst<b>1</b>, rst<b>2</b> are at the H level and the voltages of the control signal lines sw<b>1</b>, sw<b>2</b>, sel<b>1</b>, sel<b>2</b> are at the L level. As a result, the electric charges of the floating diffusions FD<b>1</b> to FD<b>8</b> are all drawn and they are initialized. This terminates the readout of signal charges obtained by receiving light at the photodiodes PD<b>2</b>, PD<b>4</b>, PD<b>6</b> and preparation for the readout of signal charges of three pixels of the next photodiode PD<b>7</b> and the following diodes. (In case of odd-numbered columns in <figref idref="DRAWINGS">FIG. 1</figref>, the three pixels correspond to red color (R); and in case of even-numbered columns, the three pixels correspond to green color (G).)
During the period from time t<b>10</b> to time t<b>11</b>, the mixed electric charges of three pixels of the photodiode PD<b>7</b> and the following diodes are read. At this time, the voltage of the control signal line tx<b>2</b>, in place of the control signal line tx<b>1</b>, is brought to the H level to carry out three-pixel mixture. As a result, the coupling transistor SW<b>2</b> is turned on.
The above mentioned mixture readout of pixels in the same color is not limited to two-pixel or three-pixel and more pixels can be read.
(Layout of Pixel Array Portion <b>10</b>)
Description will be given to the layout of the photodiodes PD, floating diffusions FD, and transistors AMI, SEL, RST, SW in the pixel array portion <b>10</b>.
<figref idref="DRAWINGS">FIG. 7</figref> is a plan view schematically illustrating the layout of the pixel array portion <b>10</b>. <figref idref="DRAWINGS">FIG. 7</figref> depicts the arrangement of the photodiodes PD in the first columns to the third column (C<b>1</b> to C<b>3</b>) and in the fourth row to the ninth row (R<b>4</b> to R<b>9</b>) in the pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 1</figref>. In <figref idref="DRAWINGS">FIG. 7</figref>, a numeral representing a row number and a character representing a column number are suffixed to the reference numeral of each photodiode PD. The characters a, b, c . . . respectively represent first column, second column, third column . . . .
Further, <figref idref="DRAWINGS">FIG. 7</figref> depicts the arrangement of the floating diffusions FD, transfer transistors TX, amplification transistors AMI, select transistors SEL, reset transistor RST, and coupling transistors SW related to these photodiodes PD. The areas of the floating diffusions FD and the areas of the gate electrodes of the transfer transistors TX are hatched for the sake of simplicity of the drawing.
Further, the <figref idref="DRAWINGS">FIG. 7</figref> also depicts the relation of coupling between each transistor TX, SEL, RST, SW and the control signal lines tx, sel, rst and output signal line vout. In the drawing, the position of a contact hole CH at each point of coupling is indicated. The position of a contact hole (indicated by reference mark VDD) coupled with a power supply wiring is also indicated.
In <figref idref="DRAWINGS">FIG. 7</figref>, further, the areas where a pixel unit PU is provided are defined by broken line. As already described, each pixel unit PU includes four photodiodes PD successively arranged in the column direction. In <figref idref="DRAWINGS">FIG. 7</figref>, the positions of three pixel units PU<b>2</b><i>a</i>, PU<b>2</b><i>b</i>, PU<b>2</b><i>c </i>are indicated.
The pixel units PU are discriminated from one another by suffixing a character representing a column and a numeral representing their order in the respective columns to their reference numerals. (The characters a, b, c, . . . respectively correspond to first column, second column, third column, . . . ) For example, the pixel units PU in the first column are discriminated from one another by sequentially adding reference marks from the lower side (−Y direction side) of the drawing, like PU<b>1</b><i>a</i>, PU<b>2</b><i>a</i>, PU<b>3</b><i>a</i>, . . . .
Hereafter, description will be sequentially given to the arrangement of each component in <figref idref="DRAWINGS">FIG. 7</figref>. The photodiodes PD are arranged over a semiconductor substrate at equal intervals both in the column direction and in the row direction. This is intended to match the optical center of each pixel with the center of the corresponding photodiode PD.
The floating diffusions FD individually correspond to the photodiodes PD and are provided in a position adjacent to the corresponding photodiode PD in the +Y direction. The transfer transistors TX are provided between a photodiode PD and a floating diffusion FD corresponding to each other.
In each row of the photodiode array PDA, the following measure is taken: in every two photodiodes PD, the corresponding floating diffusions FD comprise a pair (reference mark FDP) (referred to as floating diffusion pair, floating diffusion portion pair, or FD pair). For example, the floating diffusions FD corresponding to the photodiodes PD<b>4</b><i>a</i>, PD<b>4</b><i>b </i>comprise an FD pair (FDP). In <figref idref="DRAWINGS">FIG. 7</figref>, similarly, the floating diffusions FD corresponding to each of sets of (PD<b>5</b><i>b</i>, PD<b>5</b><i>c</i>), (PD<b>6</b><i>a</i>, PD<b>6</b><i>b</i>), (PD<b>7</b><i>b</i>, PD<b>7</b><i>c</i>), (PD<b>8</b><i>a</i>, PD<b>8</b><i>b</i>), and (PD<b>9</b><i>b</i>, PD<b>9</b><i>c</i>) comprise an FD pair (FDP).
As illustrated in <figref idref="DRAWINGS">FIG. 7</figref>, the floating diffusions FD comprising an FD pair (FDP) are placed in proximity to each other. In other words, the interval between two floating diffusions FD respectively corresponding two photodiodes PD adjoining to each other in the row direction is shorter in cases where they comprise an FD pair (FDP) than in cases where they do not comprise an FD pair (FDP).
The interval between floating diffusions FD that do not comprise an FD pair (FDP) in the row direction can be lengthened by the above configuration. In the pixel array portion <b>10</b>, the areas between floating diffusions FD that do not comprise an FD pair (FDP) are used as transistor areas TRA (TRA<b>1</b>, TRA<b>2</b>) for placing the transistors AMI, SEL, RST, SW. The width of each transistor area TRA in the row direction is equivalent to the interval between adjoining floating diffusions FD that do not comprise an FD pair (FDP). Its width in the column direction is equivalent to the interval between rows of the photodiode array PDA adjoining to each other.
An area for the photodiodes PD enough to take in a sufficient amount of light received can be ensured by increasing the empty areas to place the transistors AMI, SEL, RST as mentioned above. As a result, the light receiving efficiency of the image pickup apparatus can be enhanced.
Further, the pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 7</figref> is characterized in that as viewed in the column direction, the transfer transistors TX in each column are arranged in a staggered pattern. In other words, the FD pairs (FDPs) are arranged in a staggered pattern. That is, in adjoining rows of the photodiode array PDA, corresponding floating diffusions FD comprise an FD pair (FDP) every two photodiodes PD shifted by one column. In case of the example in <figref idref="DRAWINGS">FIG. 7</figref>, specifically, the FD pairs are comprised as described below. In the fourth, sixth, and eighth rows (R<b>4</b>, R<b>6</b>, R<b>8</b>), an FD pair (FDP) is comprised of floating diffusions FD corresponding to photodiodes PD in the first and second columns (C<b>1</b>, C<b>2</b>). In the fifth, seventh, and ninth rows (R<b>5</b>, R<b>7</b>, R<b>9</b>), meanwhile, an FD pair (FDP) is comprised of floating diffusions FD corresponding to photodiodes PD in the second and third columns (C<b>2</b>, C<b>3</b>).
As a result, it is possible to enhance the symmetrical property of the shape of the active region of each pixel including a photodiode PD and a floating diffusion FD corresponding thereto. In case of the pixel array portion <b>10</b> in <figref idref="DRAWINGS">FIG. 7</figref>, that is, the following is understood: the active regions of pixels adjoining to each other in an oblique direction are in the relation of translational symmetry; and the active regions of pixels adjoining to each other in the row direction are in the relation of line symmetry.
As already described, the following measure is taken in the Bayer arrangement of color filters: the color filters in green color (G) are arranged in a checkered pattern and the color filters in red color (R) and in blue color (B) are arranged in a checkered pattern in the remaining areas. In case of the example in <figref idref="DRAWINGS">FIG. 7</figref>, the shape of the active regions of pixels in green color (G) obliquely adjoining to each other is in the relation of translational symmetry. Therefore, it is possible to minimize the signal output difference between photodiodes PD for green color obliquely adjoining to each other. As a result, it is possible to reduce variation in characteristics from pixel to pixel.
Concrete description will be given to the arrangement of transistors AMI, SEL, RST, XT in transistor areas TRA (TRA<b>1</b>, TRA<b>2</b>). In each transistor area TRA, transistors AMI, SEL, RST, XT are placed two by two. At this time, the amplification transistor AMI and select transistor SEL corresponding to an identical pixel unit PU are placed in an identical first transistor area TRA<b>1</b>. The amplification transistor AMI and the select transistor SEL are coupled in series with the respective gate length directions substantially matched with the row direction and provided in a first transistor area TRA<b>1</b>. The reset transistor RST in each pixel unit PU is combined with the coupling transistor SW provided between it and the adjacent pixel unit PU and placed in a second transistor area TRA<b>2</b>. (The transistor areas are classified into first and second transistor areas TRA<b>1</b>, TRA<b>2</b> according to the type of a transistor placed there.)
Description will be given with, for example, the pixel unit PU<b>2</b><i>a </i>taken as representative. The amplification transistor AMI and select transistor SEL corresponding to the pixel unit PU<b>2</b><i>a </i>are provided in the transistor area TRA<b>1</b> adjoining to the photodiode PD<b>7</b><i>a</i>, which is one of the photodiodes PD comprising the pixel unit PU<b>2</b><i>a</i>, in the +Y direction. The amplification transistor AMI is provided on the side closer to the floating diffusion FD corresponding to the photodiode PD<b>7</b><i>a </i>and the select transistor SEL is provided on the side farther from the same. The source region of the amplification transistor AMI and the drain region of the select transistor SEL are integrated with each other. This makes it possible to reduce a space required for arranging the transistors.
In case of the pixel unit PU<b>2</b><i>a</i>, the reset transistor RST is provided in the transistor area TRA<b>2</b> adjoining to the photodiode PD<b>9</b><i>a </i>in the +Y direction. When it is provided, the reset transistor RST is combined with the coupling transistor SW coupling together the metal wiring FDL<b>2</b><i>a </i>and the adjacent metal wiring FDL<b>3</b><i>a</i>. The reset transistor RST and the coupling transistor SW are also series coupled and placed with their gate length directions substantially matched with the row direction. The source region of the reset transistor RST and the drain region of the coupling transistor SW are integrated with each other. This makes it possible to reduce a space required for arranging the transistors. The shape of the active regions of the reset transistor RST and coupling transistor SW is substantially identical with the shape of the active regions of the amplification transistor AMI and select transistor SEL.
When the whole of <figref idref="DRAWINGS">FIG. 7</figref> is viewed, the first transistor area TRA<b>1</b> where the amplification transistor AMI and the select transistor SEL are provided is placed in the following position: a position adjoining to the photodiodes PD in the sixth row (R<b>6</b>) and in the seventh row (R<b>7</b>) in the +Y direction. Meanwhile, the second transistor area TRA<b>2</b> where the reset transistor RST and the coupling transistor SW are provided is placed in the following position: a position adjoining to the photodiodes PD in the fourth row (R<b>4</b>), fifth row (R<b>5</b>), eighth row (R<b>8</b>), and ninth row (R<b>9</b>) in the +Y direction. That is, a row in which the first transistor area TRA<b>1</b> is placed in a position adjoining in the +Y direction and a row in which the second transistor area TRA<b>2</b> is placed alternately occur every two rows of the pixel array portion <b>10</b>.
Wiring of the control signal lines sel, rst, sw is facilitated by placing the transistors AMI, SEL, RST, SW as mentioned above. More specific description will be given. With respect to the fourth row (R<b>4</b>), fifth row (R<b>5</b>), eighth row (R<b>8</b>), and ninth row (R<b>9</b>) in which the second transistor area TRA<b>2</b> is placed adjacently in the +Y direction, the following measure is taken: the control signal lines sw, rst are so wired that they run in proximity to the second transistor area TRA<b>2</b>. With respect to the sixth row (R<b>6</b>) and the seventh row (R<b>7</b>) in which the first transistor area TRA<b>1</b> is placed adjacently in the +Y direction, the following measure is taken: the control signal line sel is so wired that it runs in proximity to the first transistor area TRA<b>1</b>.
The control signal lines tx (tx<b>4</b> to tx<b>9</b>) are wired along in the row direction so that they run in proximity to the gate electrodes of the transfer transistors TX corresponding to photodiodes PD in each row. Each control signal line sel is coupled with the gate electrode of a select transistor SEL through a contact hole CH.
The output signal lines vout (vout<b>1</b> to vout<b>3</b>), except the endmost output signal line vout, are provided in intercolumn areas. The intercolumn areas are areas where a photodiode is not provided between a column and a column adjoining to each other in the photodiode array PDA. Each output signal line vout is coupled with the source region of the select transistor SEL comprising each pixel unit PU provided in a corresponding column.
Each pixel unit PU is further provided with a metal wiring FDL for coupling floating diffusions FD. In case of the pixel unit PU<b>2</b><i>a </i>in <figref idref="DRAWINGS">FIG. 7</figref>, for example, the metal wiring FDL<b>2</b><i>a </i>for coupling the floating diffusions FD respectively corresponding to the photodiodes PD<b>5</b><i>a</i>, PD<b>6</b><i>a</i>, PD<b>7</b><i>a</i>, PD<b>8</b><i>a </i>is provided. The metal wiring FDL<b>2</b><i>a </i>is also coupled with the source region of the corresponding reset transistor RST and the gate electrode layer of the amplification transistor AMI through a contact hole CH. (The above source region also functions as the drain region of a coupling transistor SW coupling adjoining pixel units PU together.)
Similarly, the pixel unit PU<b>1</b><i>a </i>in the first column is provided with the metal wiring FDL<b>1</b><i>a </i>and the pixel unit PU<b>3</b><i>a </i>is provided with the metal wiring FDL<b>3</b><i>a</i>. The pixel units PU<b>1</b><i>b</i>, PU<b>2</b><i>b</i>, . . . in the second column are respectively provided with the metal wirings FDL<b>1</b><i>b</i>, FDL<b>2</b><i>b</i>, . . . and the pixel units PU<b>1</b><i>c</i>, PU<b>2</b><i>c</i>, . . . in the third column are respectively provided with the metal wirings FDL<b>1</b><i>c</i>, FDL<b>2</b><i>c</i>, . . . .
According to the image pickup apparatus <b>1</b> in the first embodiment, as described up to this point, the following can be implemented by adding a twist to the transistor arrangement in the pixel array portion <b>10</b>: it is possible to place coupling transistors SW coupling together the charge storage portions FDU of pixel units PU adjoining to each other in the column direction with substantially no area penalty. Use of this coupling transistor SW makes it possible to obtain images with high picture quality over a wide ISO sensitivity range. More specific description will be given. In a low ISO sensitivity range within which light exposure is high, the saturation of signal level can be prevented by lower sensitivity readout in which a coupling transistor SW provided between adjacent pixel units PU is turned on. In a high ISO sensitivity range within which light exposure is low, an S/N ratio can be enhanced by two-pixel mixture readout. Further, when a moving image is recorded, the readout speed can be enhanced by three or more-pixel mixture readout.
(Second Embodiment)
<figref idref="DRAWINGS">FIG. 8</figref> is a plan view schematically illustrating the layout of a pixel array portion <b>10</b>A. The layout of the pixel array portion <b>10</b>A in <figref idref="DRAWINGS">FIG. 8</figref> is a modification to the layout of the pixel array portion <b>10</b> in the first embodiment illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. <figref idref="DRAWINGS">FIG. 8</figref> depicts photodiodes PD in the first and second columns (C<b>1</b>, C<b>2</b>) and in the fifth row to the eighth row (R<b>5</b> to R<b>8</b>) of the photodiode array PDA. The photodiodes PD are arranged over a semiconductor substrate at equal intervals both in the column direction and in the row direction. In the following description, the same or equivalent parts as in <figref idref="DRAWINGS">FIG. 7</figref> will be marked with the same reference marks and the description thereof may not be repeated.
In the pixel array portion <b>10</b>A, four photodiodes PD in each column of the photodiode array PDA comprise a group and each group corresponds to a pixel unit PU. In case of the example in <figref idref="DRAWINGS">FIG. 8</figref>, specifically, the pixel unit PU<b>2</b><i>a </i>includes the photodiodes PD<b>5</b><i>a</i>, PD<b>6</b><i>a</i>, PD<b>7</b><i>a</i>, PD<b>8</b><i>a </i>and the pixel unit PU<b>2</b><i>b </i>includes the photodiodes PD<b>5</b><i>b</i>, PD<b>6</b><i>b</i>, PD<b>7</b><i>b</i>, PD<b>8</b><i>b. </i>
The floating diffusions FD individually correspond to the photodiodes PD and each floating diffusion FD is provided in a position adjacent to the corresponding photodiode PD in the +X direction. Each transfer transistor TX is provided between a photodiode PD and a floating diffusion FD corresponding to each other.
The transistors AMI, SEL, RST, SW are provided in an interrow area GPA that is an area where a photodiode PD is not provided between a row and a row of the photodiode array PDA adjoining to each other. At this time, the amplification transistor AMI and the select transistor SEL included in an identical pixel unit PU are arranged in an identical interrow area GPA so that they share an impurity region between them. It is more desirable that the directions of the respective gate lengths of the amplification transistor AMI and select transistor SEL should be substantially matched with the row direction.
The coupling transistors SW are provided in interrow areas GPA where neither the amplification transistor AMI nor the select transistor SEL is provided at intervals of four rows. The reset transistors RST are provided in interrow areas GPA where the amplification transistor AMI, select transistor SEL, or coupling transistor SW is not provided.
The control signal lines rst, sel, sw extended in the row direction are wired in an interrow area GPA so that they run substantially over the respective corresponding transistors RST, SEL, SW. The control signal lines tx are provided in correspondence with the individual rows of the photodiode array PDA and one control signal line tx is provided for one interrow area GPA.
The output signal lines vout extended in the column direction, except the endmost output signal line vout, are provided one by one in proximity to intercolumn areas GPB. The intercolumn areas GPB are areas where a photodiode PD is not provided between a column and a column of the photodiode array PDA adjoining to each other.
Each pixel unit PU is further provided with a metal wiring FDL for coupling floating diffusions FD. Each metal wiring FDL is coupled with the source region of the corresponding reset transistor RST and the gate electrode layer of the amplification transistor AMI through a contact hole CH.
In case of the pixel array portion <b>10</b> in the first embodiment, there is the following difference between the pixel units PU provided in the odd-numbered columns of the photodiode array PDA and the pixel units PU provided in the even-numbered columns: they are different in the control signal lines to which the respective transistors SEL, RST, SW are coupled. In case of the pixel array portion <b>10</b>A in the second embodiment, meanwhile, the following measure is taken with respect to the pixel units PU arranged in the row direction: only one control signal line is coupled to each of the transistors SEL, RST, SW. Therefore, the number of the control signal lines rst, sel, sw can be reduced as compared with the first embodiment.
(Example of Application of Image Pickup Apparatus in First or Second Embodiment to Camera)
<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram schematically illustrating the configuration of a digital still camera <b>200</b> using an image pickup apparatus <b>1</b> in the first or second embodiment of the invention.
As illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, the digital still camera <b>200</b> includes: the above image pickup apparatus <b>1</b>; an image pickup lens <b>201</b> as an imaging optical system for providing an image of a subject on the pixel array portion <b>10</b>, <b>10</b>A of this image pickup apparatus <b>1</b>; and a signal processing circuit <b>202</b> that processes the output signals of the image pickup apparatus <b>1</b>. The digital still camera <b>200</b> can obtain picture signals with high picture quality over a wide dynamic range by using the above image pickup apparatus <b>1</b>. The above application is not limited to the digital still camera <b>200</b> and the same effect can be obtained by using the above image pickup apparatus <b>1</b> for any other image pickup system such as a digital video camera.
It should be understood that the embodiments disclosed in this application are just examples in every respect and are not limitative. The scope of this invention is indicated not by the above description but by claims. It is intended to include all the modifications within the meaning and scope equivalent to claims.
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| Japanese Office Action issued in Japanese Patent Application No. 2009-053724, mailed on Jan. 22, 2013, with English translation. | Non-patent | – | Applicant |
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Numbers
- Publication
- 08947567
- Publication, DOCDB
- 8947567
- Publication, EPODOC
- US8947567
- Application
- 13864703
- Application, DOCDB
- 201313864703
- Application, EPODOC
- US201313864703
Titles
- English
- Image pickup apparatus having photoelectric conversion function
Patent term adjustment
- Net adjustment
- 0 days
Classification
- CPC, 16
- H04N5/335
- H10F39/802
- H04N25/00
- H04N25/46
- H04N25/59
- H01L27/14609
- H04N25/778
- H04N5/347
- H04N25/771
- H04N5/3559
- H04N25/78
- H04N5/37452
- H04N5/37457
- H10F39/803
- H10F39/813
- H10F39/182
- IPC, 7
- H01L27 146
- H04N25 00
- H04N25 46
- H04N5 335
- H04N5 347
- H04N5 355
- H04N5 3745
- USPC, 4
- 348294000
- 348230100
- 348250000
- 348300000