US8941222B2

Wafer level semiconductor package and manufacturing methods thereof

Summary by NHIP

Wafer-level semiconductor package

The semiconductor package includes a die, interposer, and redistribution layers connected by vias. Distinctive via structures feature an inner conductive interconnect surrounded by an outer dielectric layer, which either protrudes beyond or remains coplanar with the interposer lower surface.

Claim Score by NHIP

Read claim 16, the broadest

Abstract

A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

US8941222B2, drawing sheet 1 — Sheet 1 of 12

Term

7.2 yearsleft in the term

Expires 19 November 2033, including 1,104 days of term adjustment.

20 claims: 3 independent, 17 dependent

1
A semiconductor package, comprising:at least one semiconductor die having an active surface;an interposer element having an upper surface and a lower surface, the interposer element having at least one conductive via extending between the upper surface and the lower surface;a package body encapsulating portions of the semiconductor die and portions of the interposer element;and a lower redistribution layer that electrically connects the interposer element to the active surface of the semiconductor die.
11
A semiconductor package, comprising:at least one semiconductor die having an active surface;an interposer element having an upper surface and a lower surface, the interposer element having at least one conductive via extending between the upper surface and the lower surface;a package body encapsulating portions of the semiconductor die and portions of the interposer element;a lower redistribution layer that electrically connects the interposer element to the active surface of the semiconductor die;and an electrical contact exposed from a lower periphery of the semiconductor package, wherein: the lower redistribution layer electrically connects the electrical contact to the active surface of the semiconductor die and the interposer element;and the lower redistribution layer is disposed adjacent to the active surface of the semiconductor die.
16
Broadest claimClaim Score 79, broad(NHIP)A semiconductor package, comprising:at least one semiconductor die having an active surface;a package body encapsulating portions of the semiconductor die;an interposer element having an upper surface and a lower surface, the interposer element having at least one conductive via extending between the upper surface and the lower surface and surrounding the package body;and a lower redistribution layer that electrically connects the interposer element to the active surface of the semiconductor die.

Independent claims3

61 paragraphs in 4 sections, as filed

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The invention relates generally to semiconductor packages and manufacturing methods thereof. More particularly, the invention relates to a wafer level semiconductor package and manufacturing methods thereof.

00032. Description of Related Art

0004Semiconductor devices have become progressively more complex, driven at least in part by the demand for smaller sizes and enhanced processing speeds. To support increased functionality, semiconductor packages including these devices often have an large number of contact pads for external electrical connection, such as for inputs and outputs. These contact pads can occupy a significant amount of the surface area of a semiconductor package.

0005In the past, wafer level packaging could be restricted to a fan-in configuration in which electrical contacts and other components of a resulting semiconductor device package can be restricted to an area defined by a periphery of a semiconductor device. To address the increasing number of contact pads, wafer level packaging is no longer limited to the fan-in configuration, but can also support a fan-out configuration. For example, in a fan-out configuration, contact pads can be located at least partially outside an area defined by a periphery of a semiconductor device. The contact pads may also be located on multiple sides of a semiconductor package, such as on both a top surface and a bottom surface of the semiconductor package.

0006However, forming and routing the electrically connections from a semiconductor device to this increasing number of contact pads can result in greater process complexity and cost. It is against this background that a need arose to develop the wafer level semiconductor package and related methods described herein.

SUMMARY OF THE INVENTION

0007One aspect of the invention relates to a semiconductor package. In one embodiment, the semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

0008In another embodiment, the semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, a lower redistribution layer, and an electrical contact exposed from a lower periphery of the semiconductor package. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die, and electrically connects the electrical contact to the active surface of the semiconductor die and the interposer element. The lower redistribution layer is disposed adjacent to the active surface of the semiconductor die.

0009Another aspect of the invention relates to a method of forming a semiconductor package. In one embodiment, the method includes providing a semiconductor die having an active surface, and placing an interposer element adjacent to the die. The interposer element has an upper surface and a lower surface, and has at least one first conductive via extending to the lower surface. The method further includes encapsulating portions of the semiconductor die and portions of the interposer element with an encapsulant such that the active surface of the semiconductor die, the lower surface of the interposer element, and portions of the encapsulant form a substantially coplanar surface. The method further includes forming a lower redistribution layer on the substantially coplanar surface, the lower redistribution layer electrically connecting the interposer element to the active surface of the semiconductor die.

0010Other aspects and embodiments of the invention are also contemplated. The foregoing summary and the following detailed description are not meant to restrict the invention to any particular embodiment but are merely meant to describe some embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

0011<figref idref="DRAWINGS">FIG. 1</figref> is a cross section view of a stacked package assembly, according to an embodiment of the invention;

0012<figref idref="DRAWINGS">FIG. 2</figref> is a top cross section view of a semiconductor package in a plane A-A shown in <figref idref="DRAWINGS">FIG. 1</figref>, according to an embodiment of the invention;

0013<figref idref="DRAWINGS">FIG. 3</figref> is a cross section view of various conductive via embodiments within an interposer;

0014<figref idref="DRAWINGS">FIGS. 4A through 4B</figref> are cross section views of a portion of a semiconductor package including an interposer, according to an embodiment of the invention;

0015<figref idref="DRAWINGS">FIG. 5</figref> is a bottom view of an interposer, according to an embodiment of the invention;

0016<figref idref="DRAWINGS">FIG. 6</figref> is a cross section view of a semiconductor device including vias exposed adjacent to a back surface of the semiconductor device, according to an embodiment of the invention;

0017<figref idref="DRAWINGS">FIG. 7</figref> is a top cross section view of a semiconductor package, according to an embodiment of the invention; and

0018<figref idref="DRAWINGS">FIG. 8A</figref> through <figref idref="DRAWINGS">FIG. 8G</figref> are views showing a method of forming a semiconductor package, according to an embodiment of the invention.

0019The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of some embodiments of the invention. Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer to the same or like features.

DETAILED DESCRIPTION OF THE INVENTION

0020Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a cross section view is shown of a stacked package assembly 100 according to an embodiment of the invention. The stacked package assembly 100 includes a semiconductor package 192 and a semiconductor package 194 positioned above the semiconductor package 192. The semiconductor package 194 is electrically connected to the semiconductor package 192 through conductive bumps 193. It is contemplated that the semiconductor package 194 may be any form of semiconductor package, such as a wafer-level package, a BGA package, and a substrate-level package. The semiconductor package 194 may also include a combination of one or more semiconductor packages and/or one or more passive electrical components. The semiconductor package 192 includes a semiconductor device 102, which includes a lower surface 104 which in the illustrated embodiment is an active surface, i.e. the active surface having die bond pads 111, an upper surface 106, and lateral surfaces 108 disposed adjacent to a periphery of the semiconductor device 102 and extending between the lower surface 104 and the upper surface 106. In the illustrated embodiment, each of the surfaces 104, 106, and 108 is substantially planar, with the lateral surfaces 108 having a substantially orthogonal orientation with respect to the lower surface 104 or the upper surface 106, although it is contemplated that the shapes and orientations of the surfaces 104, 106, and 108 can vary for other implementations. In one embodiment, the upper surface 106 is a back surface of the semiconductor device 102, while the lower surface 104 is an active surface of the semiconductor device 102. The lower surface 104 may include the die bond pads 111 that provide input and output electrical connections for the semiconductor device 102 to conductive structures included in the package 192, such as a patterned conductive layer 150 (described below). In the illustrated embodiment, the semiconductor device 102 is an integrated circuit, although it is contemplated that the semiconductor device 102, in general, can be any active device including for example an optical or other type of sensor, a micro electro-mechanical system (MEMS), any passive device, or a combination thereof. The semiconductor device 102 may be an active die. While one semiconductor device is shown in the semiconductor package 192, it is contemplated that more than one semiconductor device can be included in the semiconductor package 192 for other implementations.

0021As shown in <figref idref="DRAWINGS">FIG. 1</figref>, the package 192 also includes a package body 114 that is disposed adjacent to the semiconductor device 102. In the illustrated embodiment, the package body 114 covers or encapsulates portions of the semiconductor device 102 and portions of one or more interposers 170, such as interposer elements 170 (described below). The package body 114 can provide mechanical stability as well as protection against oxidation, humidity, and other environmental conditions. In this embodiment, the package body 114 substantially covers the upper surface 106 and the lateral surfaces 108 of the semiconductor device 102, with the lower surface 104 of the semiconductor device 102 being substantially exposed or uncovered by the package body 114. The package body 114 includes a lower surface 116 and an upper surface 118. In the illustrated embodiment, each of the surfaces 116 and 118 is substantially planar, although it is contemplated that the shapes and orientations of the surfaces 116 and 118 can vary for other implementations.

0022In one embodiment, the package body 114 can be formed from a molding material. The molding material can include, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant. Suitable fillers can also be included, such as powdered SiO2. The molding material may be a pre-impregnated (prepreg) material, such as a pre-impregnated dielectric material.

0023The package 192 further includes the one or more interposers 170. The interposer(s) 170 may be positioned adjacent to a perimeter 177 (i.e., a lateral periphery, see <figref idref="DRAWINGS">FIG. 2</figref>) of the semiconductor device 102. The interposer 170 may be a contiguous interposer that extends around the perimeter 177 of the semiconductor die (see <figref idref="DRAWINGS">FIG. 7</figref>) or may be uncontiguous, discrete interposer elements as shown in <figref idref="DRAWINGS">FIG. 2</figref>. Each interposer 170 is comprised of a substrate material that can be glass, silicon, a metal, a metal alloy, a polymer, or another suitable structural material. The interposers 170 in the package 192 can be formed from the same material, or from different materials. In one embodiment, each interposer 170 may define one or more openings 171 extending from a lower surface 172 of the interposer 170 to an upper surface 173 of the interposer 170. A conductive via 174 is formed in each of the openings 171.

0024Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the interposer 170 may include a plurality of conductive vias 174. In one embodiment, a conductive via 174A is formed in each opening 171, and may be exposed at the lower surface 172 and the upper surface 173. In another embodiment, a conductive via 174B may protrude beyond the lower surface 172 and the upper surface 173. Further embodiments of the conductive vias are illustrated in <figref idref="DRAWINGS">FIG. 3</figref>. The conductive via 174 may be directly connected to the patterned conductive layer 150. The conductive via 174 may include an inner conductive interconnect 275. The inner conductive interconnect 275 is a conductive element that may be formed from a metallic material, typically by plating, conductive paste, or other methods known to those of ordinary skill in the art. Depending upon the substrate material of a substrate portion 271 of the interposer 170, the conductive via 174 may include an outer dielectric layer 282 of dielectric material formed between the inner conductive interconnect 275 and the substrate 271 (see <figref idref="DRAWINGS">FIGS. 2 and 3</figref>). The outer dielectric layer 282 may be in the form of an annular insulator.

0025In one embodiment, the diameter of the conductive via 174 may be in the range from about 10 μm to about 50 μm, such as from about 10 μm to about 20 μm, and from about 20 μm to about 50 μm. For diameters of the conductive via 174 in the range from about 10 μm to about 20 μm, the structure of conductive vias 174B can be used. For diameters of the conductive via 174 in the range from about 20 μm to about 50 μm, the structure of conductive vias 174A can be used.

0026The package 192 may include one or more redistribution layers (RDL) 151, where each RDL includes the patterned conductive layer 150 and a dielectric (or passivation) layer 130. The patterned conductive layer can be formed from copper, a copper alloy, or other metals. The redistribution layer 151 may be disposed adjacent (e.g., on, near, or adjoining) to the active surface 104 of the semiconductor device 102, and to the lower surface 116 of the package body 114. The redistribution layer 151 may include only the patterned conductive layer 150, or may be multi-layered. For example, in addition to the dielectric layer 130 and the patterned conductive layer 150, the redistribution layer 151 may include a dielectric layer 131 such that the patterned conductive layer 150 is disposed between the dielectric layers 130 and 131. It is contemplated that more or less dielectric layers may be used in other implementations. Each of the dielectric layers 130 and 131 can be formed from a dielectric material that is polymeric or non-polymeric. For example, at least one of the dielectric layers 130 and 131 can be formed from polyimide, polybenzoxazole, benzocyclobutene, or a combination thereof. The dielectric layers 130 and 131 can be formed from the same dielectric material or different dielectric materials. For certain implementations, at least one of the dielectric layers 130 and 131 can be formed from a dielectric material that is photoimageable or photoactive.

0027The patterned conductive layer 150 may extend through openings 136 in the dielectric layer 130 to electrically connect to the conductive vias 174, and through openings 146 in the dielectric layer 130 to electrically connect to the die bond pads 111. Package contact pads 175 for electrical connection outside of the stacked package assembly 100 may be formed from portions of the patterned conductive layer 150 exposed by openings 137 in the dielectric layer 131.

0028In one embodiment, the package 192 may provide a two-dimensional fan-out configuration in which the patterned conductive layer 150 extends substantially laterally outside of the periphery 177 (see <figref idref="DRAWINGS">FIG. 2</figref>) of the semiconductor device 102. For example, <figref idref="DRAWINGS">FIG. 1</figref> shows electrical contacts, including conductive bumps 190, at least partially outside the lateral periphery 177 (see <figref idref="DRAWINGS">FIG. 2</figref>) of the semiconductor device 102. The conductive bumps 190 may be exposed from a lower periphery 195 of the package 192. This allows the semiconductor package 192 to be electrically connected to devices external to the semiconductor package 192 via the redistribution layer 151 and the conductive bumps 190. The conductive bumps 190 may be electrically connected to the semiconductor device 102 via the patterned conductive layer 150, and may be disposed adjacent to the package contact pads 175. The conductive bumps 190 may be electrically connected to the interposers 170 via the patterned conductive layer 150.

0029The conductive vias 174 included in the interposer 170 can facilitate extending a two-dimensional fan-out to a three-dimensional fan-out and/or fan-in by providing electrical pathways from the semiconductor device 102 to electrical contacts, including the conductive bumps 193. The conductive bumps 193 may be exposed from an upper periphery 196 of the package 192. This allows the semiconductor package 192 to be electrically connected to devices external to the semiconductor package 192 via the redistribution layer 153 and the conductive bumps 193. The conductive bumps 193 may be electrically connected to upper contact pads 176. The upper contact pads 176 may be formed from portions of a patterned conductive layer 152 included in a redistribution layer 153 that is disposed adjacent to the upper surface 118 of the package body 114. The patterned conductive layer 152 may be disposed between a dielectric (or passivation) layer 132 and a dielectric layer 133. The patterned conductive layer 152 may extend through openings 139 in the dielectric layer 132 to electrically connect to the conductive vias 174. The upper contact pads 176 may be formed from portions of the patterned conductive layer 152 exposed by openings 138 in the dielectric layer 133. The redistribution layer 153 may have similar structural characteristics to those previously described for the redistribution layer 152.

0030In one embodiment, the redistribution layer 153 may not include the dielectric layer 132, so that the patterned conductive layer 152 and the dielectric layer 133 may be adjacent to the upper surface 118 of the package body 114. In this embodiment, the patterned conductive layer 152 is also adjacent to the interposer 170, so in this embodiment the interposer 170 should be made of a non-conductive material such as glass. Alternatively, the interposer 170 can include a first portion formed of a material such as silicon and a second portion formed of a non-conductive material such as glass or some other dielectric material, on long as the patterned conductive layer 152 is adjacent to the non-conductive portion of the interposer 170.

0031In one embodiment, a three-dimensional fan-out configuration can be created by electrically connecting conductive bump 193A to the semiconductor device 102 through the patterned conductive layer 152, the conductive vias 174, and the patterned conductive layer 150. Alternatively or in addition, a three-dimensional fan-in configuration can be created by electrically connecting conductive bump 193B to the semiconductor device 102 through the patterned conductive layer 152, the conductive vias 174, and the patterned conductive layer 150. These three-dimensional fan-out and/or fan-in configurations can advantageously increase flexibility beyond that provided by two-dimensional fan-out in terms of the arrangement and spacing of electrical contacts both above the upper surface 118 of the package body 114, and below the lower surface 116 of the package body 114. This can reduce dependence upon the arrangement and spacing of the contact pads of the semiconductor device 102. In accordance with a fan-out configuration, the conductive bump 193A is laterally disposed at least partially outside of the periphery of the semiconductor device 102. In accordance with a fan-in configuration, the conductive bump 193B is laterally disposed within the periphery of the semiconductor device 102. It is contemplated that the conductive bumps 190 and 193, in general, can be laterally disposed within that periphery, outside of that periphery, or both, so that the package 100 may have a fan-out configuration, a fan-in configuration, or a combination of a fan-out and a fan-in configuration. In the illustrated embodiment, the conductive bumps 190 and 193 may be solder bumps, such as reflowed solder balls.

0032The patterned conductive layer 150, the conductive vias 174, and the patterned conductive layer 152 can be formed from a metal, a metal alloy, a matrix with a metal or a metal alloy dispersed therein, or another suitable electrically conductive material. For example, at least one of the patterned conductive layer 150, the conductive vias 174, and the patterned conductive layer 152 can be formed from aluminum, copper, titanium, or a combination thereof. The patterned conductive layer 150, the conductive vias 174, and the patterned conductive layer 152 can be formed from the same electrically conductive material or different electrically conductive materials.

0033<figref idref="DRAWINGS">FIG. 2</figref> is a top cross section view of the semiconductor package 192 in a plane A-A shown in <figref idref="DRAWINGS">FIG. 1</figref>, according to an embodiment of the invention. The cross section view shows discrete interposer elements 170 disposed on each of the four sides of the semiconductor die 102 and encapsulated in the package body 114. The discrete interposer elements 170 may be disposed inwardly from a lateral periphery 115 of the package body 114. The package body 114 may extend around a lateral periphery 178 of each of the interposer elements 170, such that the lateral periphery 178 of each of the interposer elements 170 is embedded in the package body 114. Also illustrated are portions of the conductive vias 174 associated with the interposers 170, such as the inner conductive interconnects 275 and the outer dielectric layers 282 disposed adjacent to the inner conductive interconnects 275 in some embodiments. The outer dielectric layer 282 may in the form of an annular insulator. The inner conductive interconnects 275 can be made of conductive materials similar to those used to form portions of the conductive via 174 described with reference to <figref idref="DRAWINGS">FIG. 1</figref>. The outer dielectric layer 282 can be made of materials similar to those used to form the dielectric layers 130 and 131 described with reference to <figref idref="DRAWINGS">FIG. 1</figref>. The cross section view also shows the upper surface 106 of the die 102. In this embodiment, unused conductive vias 174 may be left electrically unconnected.

0034The discrete interposer elements 170 can be singulated from an interposer wafer such that the interposer elements 170 have varying sizes and shapes based on the number and positions of through via connections required for any given semiconductor package (see <figref idref="DRAWINGS">FIG. 8B</figref>). This approach provides the flexibility to enable manufacturing of multiple package types with different numbers and positions of through via connections from the same interposer wafer. In addition, the interposer elements 170 can be sized to correspond to each package type so that unused through via connections are reduced or eliminated. Since there is no need, for example, to form a custom substrate for each package type to reduce the amount of unused substrate area, this approach can reduce manufacturing cost and complexity.

0035In addition, since the discrete interposer elements 170 may be small relative to the package body 114, the discrete interposer elements 170 may have little or no effect on the coefficient of thermal expansion (CTE) of the package 192. Instead, the CTE of the package body 114 can be adjusted to better match the CTE of the semiconductor device 102, and therefore to increase reliability. For example, filler content of the mold compound used to form the package body 114 can be adjusted so that the CTE of the package body 114 more closely matches the CTE of the semiconductor device 102.

0036<figref idref="DRAWINGS">FIG. 3</figref> is a cross section view of various conductive via embodiments within the interposer 170. In one embodiment, the interposer 170 defines the opening 171, and includes the conductive via 174A at least partially disposed in the opening 171, where the conductive via 174A includes the inner conductive interconnect 275A. The conductive via 174A may be a through silicon via (TSV). The conductive via 174A includes inner conductive interconnect 275A exposed at the upper surface 173 and the lower surface 172 of the interposer 170, and the outer dielectric layer 282 surrounding the inner conductive interconnect 275A. The outer dielectric layer 282 may be disposed adjacent to a lateral surface 381 of the opening 171. In this embodiment, the outer dielectric layer 282 and the inner conductive interconnect 275A may substantially fill the opening 171.

0037In another embodiment, the conductive via 174B includes an inner conductive interconnect 275B that protrudes beyond the upper surface 173 and the lower surface 172 of the interposer 170. In this embodiment, the outer dielectric layer 282 may also protrude beyond the upper surface 173 and the lower surface 172. A conductive layer 383 may be disposed adjacent to protruding portions of the inner conductive interconnect 275B and the outer dielectric layer 282.

0038In a further embodiment, a conductive via 174C includes an inner conductive interconnect 275C that is an annular plating layer, and the outer dielectric layer 282. The inner conductive interconnect 275C may define an opening 384. Alternatively, the inner conductive interconnect 275C may be filled by an inner dielectric layer (not shown).

0039In a further embodiment, a conductive via 174D includes an inner conductive interconnect 275D that is disposed directly adjacent to the substrate 271 of the interposer 170. In this embodiment, the interposer 170 is made of a non-conductive material such as glass. The inner conductive interconnect 275D may define an opening (not shown) similar to the opening 384.

0040In other respects, the conductive vias 174A, 174B, 174C, and 174D are similar to the conductive via 174 and perform a similar function of routing I/O from the top package 194 to the bottom package 192 and to the conductive bumps 190 to distribute I/O outside the package 100 to other devices (see <figref idref="DRAWINGS">FIG. 1</figref>).

0041Employment of interposers 170 to provide electrical connectivity between a redistribution layer adjacent to an upper surface of a semiconductor package (such as the redistribution layer 153 of <figref idref="DRAWINGS">FIG. 1</figref>) and a redistribution layer adjacent to a lower surface of a semiconductor package (such as the redistribution layer 151 of <figref idref="DRAWINGS">FIG. 1</figref>) may result in reduced via diameter compared to other approaches. For example, the conductive vias 174 may have a diameter in the range from about 10 μm to about 50 μm, such as in the range from about 10 μm to about 20 μm, about 20 μm to about 30 μm, or in the range from about 30 μm to about 50 μm. These diameters are smaller than a typical diameter (greater than 75 μm) of through package vias, which may be formed by laser drilling through a mold compound. Because of the reduced diameter of the conductive vias 174, corresponding capture pads for the conductive vias 174, such as portions of the patterned conductive layers 150 and 152 of <figref idref="DRAWINGS">FIG. 1</figref>, can be of reduced size and pitch. This results in higher density redistribution routing traces, such as between the die 102 and the interposers 170, and may enable routing to be performed without adding additional redistribution layers. The reduced diameter of each conductive via 174 can also can allow for higher connectivity density than would be possible with the larger laser-drilled vias through the mold compound. In addition, because of their smaller diameter, the conductive vias 174 can be easier to fill with conductive and/or non-conductive material while avoiding undesirable effects such as processor solution and polymer leakage and entrapment.

0042<figref idref="DRAWINGS">FIGS. 4A through 4B</figref> are cross section views of a portion of a semiconductor package 400 including an interposer 470, according to an embodiment of the invention. The semiconductor package 400 and the interposer 470 are generally similar to the semiconductor package 192 and the interposer 170 of <figref idref="DRAWINGS">FIG. 1</figref>, except that the interposer 470 includes a conductive interconnect 440. Referring to <figref idref="DRAWINGS">FIG. 4A</figref>, in one embodiment of a semiconductor package 400A, the conductive interconnect 440 may be disposed on and extend substantially laterally along a lower surface 472A of an interposer 470A. In this embodiment, a dielectric layer 441 is disposed between the conductive interconnect 440 and the substrate 271 of the interposer 470A. Referring to <figref idref="DRAWINGS">FIG. 4B</figref>, in one embodiment of a semiconductor package 400B, the conductive interconnect 440 may be disposed on and extend substantially laterally along a lower surface 472B of an interposer 470B. In this embodiment, the conductive interconnect 440 is adjacent to the substrate 271 of the interposer 470B, so in this embodiment the interposer 470B should be made of a non-conductive material such as glass. Alternatively, the interposer 470B can include a first portion formed of a material such as silicon and a second portion formed of a non-conductive material such as glass or another dielectric material, so long as the conductive interconnect 440 is adjacent to the non-conductive portion of the interposer 470B.

0043One advantage of the conductive interconnect 440 is that the conductive interconnect 440 can serve as an additional trace layer for redistribution trace routing, which can reduce the number of redistribution layers in the semiconductor package 400 needed for this purpose. A reduction in the number of redistribution layers in the semiconductor package 400 can result in reduced manufacturing process complexity and cost. In addition, the conductive interconnect 440 can be buried under a redistribution layer, and therefore does not take up space on an external surface of the semiconductor package 402.

0044In the embodiments of <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, a semiconductor device (such as the semiconductor device 102 of <figref idref="DRAWINGS">FIG. 1</figref>) is electrically connected to the upper redistribution layer 153 through the patterned conductive layer 150 included in a lower redistribution layer 151, the conductive interconnect 440, and the conductive via 174 included in the interposer 470. The lower redistribution layer 151 may cover the conductive interconnect 440. Alternatively, a protective layer (not shown) may be disposed between the conductive interconnect 440 and the lower redistribution layer 151. In one embodiment, the conductive interconnect 440 may electrically connect the semiconductor device 102 to a passive electrical component (see <figref idref="DRAWINGS">FIG. 5</figref>).

0045Referring to <figref idref="DRAWINGS">FIG. 4B</figref>, in one embodiment, the dielectric layer 132 (see <figref idref="DRAWINGS">FIG. 1</figref>) may be omitted from the upper redistribution layer 153, so that the patterned conductive layer 152 is disposed adjacent to the substrate 271 of the interposer 470B. In this embodiment, the interposer 470B is made of a non-conductive material such as glass.

0046<figref idref="DRAWINGS">FIG. 5</figref> is a bottom view of the interposer 470, according to an embodiment of the invention. The interposer 470 includes multiple conductive vias 174 (such as conductive vias 174D and 174E) and multiple conductive interconnects 440. The conductive interconnects 440 may form a routing layer. In one embodiment, the routing layer is on the lower surface of the interposer 470. The conductive interconnects 440 may connect the conductive via 174D to the conductive via 174E. In one embodiment, the conductive via 174D may provide electrical connectivity through a semiconductor package such as the semiconductor package 400 of <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, while the conductive via 174E may provide electrical connectivity to a patterned conductive layer such as the patterned conductive layer 150. The conductive interconnects 440 may allow for crossing over of conductors during redistribution layer routing by routing across the interposer 470 on a surface of the interposer 470.

0047In one embodiment, the conductive interconnects 440 may electrically connect the conductive vias 174 to one or more passive electrical components known to one of ordinary skill in the art, such as a resistor 500, an inductor 502, and a capacitor 504. These passive electrical components, like the conductive interconnects 440, are disposed on the lower surface 472 of the interposer 470.

0048<figref idref="DRAWINGS">FIG. 6</figref> is a cross section view of a semiconductor device 602 including conductive vias 608 exposed adjacent to a back surface 606 of the semiconductor device 602, according to an embodiment of the invention. The semiconductor device 602 is in most respects similar to the semiconductor device 102 of <figref idref="DRAWINGS">FIG. 1</figref>, except for the conductive vias 608. The conductive vias 608 are similar to the conductive vias 174. One advantage of the conductive vias 608 is that the conductive vias 608 are formed in the semiconductor device 602. This can reduce or eliminate the need for separate interposers, which can save space in a semiconductor package such as the semiconductor package 192 of <figref idref="DRAWINGS">FIG. 1</figref>. In one embodiment, the conductive via 608 can electrically connect the semiconductor device 602 to a redistribution layer such as the redistribution layer 153 of <figref idref="DRAWINGS">FIG. 1</figref>. The conductive via 608 may electrically connect a die bonding pad 611 to circuitry external to the semiconductor device 602, such as the conductive layer 152 (see <figref idref="DRAWINGS">FIG. 1</figref>) included in the redistribution layer 153. Alternatively or in addition, the conductive via 608 may electrically connect circuitry 610 internal to the semiconductor device 602 to circuitry external to the semiconductor device 602, such as the conductive layer 152 included in the redistribution layer 153.

0049<figref idref="DRAWINGS">FIG. 7</figref> is a top cross section view of a semiconductor package 700, according to an embodiment of the invention. The cross section view shows an interposer 770 surrounding a package body 714 encapsulating the semiconductor device 102. The cross section view shows conductive vias 774 associated with the interposer 770. The semiconductor package 700 is in most respects similar to the semiconductor package 192 described with reference to <figref idref="DRAWINGS">FIG. 1</figref> except for the shape of the interposer 770. In this embodiment, the interposer 770 is a contiguous interposer extending around the lateral periphery 177 of the semiconductor die 102. In particular, the conductive vias 774 and the package body 714 are similar to the conductive vias 174 and the package body 114 described with reference to <figref idref="DRAWINGS">FIG. 1</figref>.

0050The interposer 770 defines an opening 772 substantially filled with the package body 714. The package body 714 can decouple the semiconductor package 700 from any stresses imposed by the interposer 770. In this embodiment, unused conductive vias 774 may be left electrically unconnected.

0051<figref idref="DRAWINGS">FIG. 8A</figref> through <figref idref="DRAWINGS">FIG. 8G</figref> are views showing a method of forming a semiconductor package, according to an embodiment of the invention. For ease of presentation, the following manufacturing operations are described with reference to the package 192 of <figref idref="DRAWINGS">FIG. 1</figref>. However, it is contemplated that the manufacturing operations can be similarly carried out to form other semiconductor packages that may have different internal structure from the package 192. In addition, it is contemplated that these manufacturing operations can form an array of connected semiconductor packages that can be separated, such as through singulation, to form multiple individual semiconductor packages.

0052<figref idref="DRAWINGS">FIG. 8A</figref> shows an interposer wafer (or interposer panel) 800. The interposer wafer 800 can be formed from glass, silicon, a metal, a metal alloy, a polymer, or another suitable structural material. The interposer wafer 800 includes conductive vias 804 that are similar to the conductive vias 174 of <figref idref="DRAWINGS">FIGS. 1 through 3</figref>. In one embodiment, the conductive vias 804 may extend entirely through the interposer wafer 800, and may protrude beyond an interposer 870. The interposer 870 may be a discrete, uncontiguous interposer element. Alternatively, the conductive vias 804 may be exposed at a lower surface 806 of the interposer wafer 800, but may extend only partially through the interposer wafer 800. The shape of the interposer wafer 800 may be circular, rectangular, square, or any other shape determined to be feasible for manufacturing operations by one of ordinary skill in the art.

0053Next, <figref idref="DRAWINGS">FIG. 8B</figref> shows the interposer 870. The interposer 870 may be separated from the interposer wafer 800, such as by singulation including singulation methods known to those of ordinary skill in the art such as saw singulation. One advantage of separating the interposer 870 from the interposer wafer 800 is that a standard size interposer wafer or panel 800 is can be used. The interposer wafer 800 can be singulated into interposers of varying sizes and shapes based on the number and positions of through via connections required for any given semiconductor package. The conductive vias 804 may extend entirely through the interposer 870, and may protrude beyond the interposer 870. Alternatively, as described for the interposer wafer 800 of <figref idref="DRAWINGS">FIG. 8A</figref>, the conductive vias 804 may extend only partially through the interposer 870.

0054Next, <figref idref="DRAWINGS">FIG. 8C</figref> shows a molded structure 810. In one embodiment, the die 102 and one or more of the interposers 870 are disposed adjacent to a carrier 812. Advantageously, the die 102 and the interposers 870 are placed or located on the carrier using commercially available pick and place and/or die attach equipment. The die 102 and the interposers 870 may be attached to the carrier 812 by an adhesive layer 814. In one embodiment, the interposer 870 includes a conductive via 874A that is exposed at a lower surface 872 of the interposer 870. In another embodiment, the interposer 870 includes a conductive via 874B that protrudes beyond the lower surface 872 into the adhesive layer 814. Then, the die 102 and the interposers 870 are encapsulated by molding material to form the molded structure 810. The molding material may surround a lateral periphery 878 of the interposer 870. The molded structure 810 is made of materials similar to those forming the package body 114 of <figref idref="DRAWINGS">FIG. 1</figref>. The molded structure 810 can be formed using any of a number of molding techniques, such as transfer molding, injection molding, or compression molding. To facilitate proper positioning of the molded structure 810 during subsequent singulation operations, fiducial marks can be formed in the molded structure 810 by various methods, such as laser marking.

0055Next, <figref idref="DRAWINGS">FIG. 8D</figref> shows a molded structure 820. The molded structure 820 is formed by first removing the molded structure 810 from the carrier 812 in <figref idref="DRAWINGS">FIG. 8C</figref>. Then, a redistribution layer including the redistribution layer 151 (see <figref idref="DRAWINGS">FIG. 1</figref>) is formed adjacent to the active surface 104 of the die 102, the lower surface 816 of the package body 817, and the lower surface 872 of each of the interposers 870. A dielectric material is applied using any of a number of techniques, such as printing, spinning, or spraying, and is then patterned to form a dielectric layer including the dielectric layer 130 (see <figref idref="DRAWINGS">FIG. 1</figref>). As a result of patterning, the dielectric layer 130 is formed with openings, including openings that are aligned with the active surface 104 and sized so as to at least partially expose the die bond pads 111 of the semiconductor device 102. In one embodiment, the dielectric layer further includes openings that are aligned and sized so as to at least partially expose the conductive vias 874A. In another embodiment, the dielectric layer includes openings through which the conductive vias 874B extend. Patterning of the dielectric material to form the dielectric layer 130 can be carried out in any of a number of ways, such as photolithography, chemical etching, laser drilling, or mechanical drilling, and the resulting openings can have any of a number of shapes, such as a cylindrical shape, such as a circular cylindrical shape, an elliptic cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape, or a non-cylindrical shape, such as a cone, a funnel, or another tapered shape. It is also contemplated that lateral boundaries of the resulting openings can be curved or roughly textured.

0056An electrically conductive material is then applied to the dielectric layer 130 and drawn into the openings defined by the dielectric layer 130 using any of a number of techniques, such as chemical vapor deposition, electroless plating, electrolytic plating, printing, spinning, spraying, sputtering, or vacuum deposition, and is then patterned to form an electrically conductive layer including the patterned conductive layer 150 (see <figref idref="DRAWINGS">FIG. 1</figref>). As a result of patterning, the patterned conductive layer 150 is formed with electrical interconnects that extend laterally along certain portions of the dielectric layer 130 and with gaps between the electrical interconnects that expose other portions of the dielectric layer 130. The patterned conductive layer 150 included in the redistribution layer 151 may be electrically connected to the die bond pads 111 and the conductive vias 874. Patterning of the electrically conductive layer 150 can be carried out in any of a number of ways, such as photolithography, chemical etching, laser drilling, or mechanical drilling.

0057A dielectric material is then applied to the patterned conductive layer 150 and the exposed portions of the dielectric layer 130 using any of a number of techniques, such as printing, spinning, or spraying, and is then patterned to form a dielectric layer including the dielectric layer 131 (see <figref idref="DRAWINGS">FIG. 1</figref>). As a result of patterning, the dielectric layer 131 is formed with openings that are aligned with the electrically conductive layer 150, including openings that are aligned so as to at least partially expose the electrically conductive layer 150 and are sized so as to accommodate solder bumps. Patterning of the dielectric material 131 can be carried out in any of a number of ways, such as photolithography, chemical etching, laser drilling, or mechanical drilling, and the resulting openings can have any of a number of shapes, including a cylindrical shape, such as a circular cylindrical shape, an elliptic cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape, or a non-cylindrical shape, such as a cone, a funnel, or another tapered shape. It is also contemplated that lateral boundaries of the resulting openings can be curved or roughly textured.

0058Next, <figref idref="DRAWINGS">FIG. 8E</figref> shows a molded structure 830. In one embodiment, a portion of each interposer 870 is removed to form the interposers 170, along with a portion of the molding material. This is typically done by backgrinding, CMP, or other techniques resulting in a substantially coplanar surface 832.

0059In an alternative embodiment to <figref idref="DRAWINGS">FIG. 8E</figref>, <figref idref="DRAWINGS">FIG. 8F</figref> shows a molded structure 840. The molded structure 840 is similar to the molded structure 830 of <figref idref="DRAWINGS">FIG. 8E</figref>, except that additional backgrinding or other removal techniques are performed to expose the back surface 606 of the semiconductor die 602, resulting in a substantially coplanar surface 836 between the die 602, the package body 114, and the interposer 170. In one embodiment, if the die corresponds to the die 602 of <figref idref="DRAWINGS">FIG. 6</figref>, enough molding material is removed to expose the back surface 606 of the die 602 and the conductive interconnects 610 (see <figref idref="DRAWINGS">FIG. 6</figref>).

0060Next, <figref idref="DRAWINGS">FIG. 8G</figref> shows the semiconductor package 192 of <figref idref="DRAWINGS">FIG. 1</figref>. To form the semiconductor package 192, a redistribution layer 153 is formed adjacent to an upper surface 832 of the molded structure 830 (see <figref idref="DRAWINGS">FIG. 8E</figref>). The redistribution layer 153 is formed similarly to the redistribution layer 151, and is electrically connected to the conductive vias 174. In one embodiment, singulation is next carried out along the dashed lines 890 to separate the semiconductor packages 192.

0061While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be necessarily be drawn to scale, and that there may be other embodiments of the present invention which are not specifically illustrated. Thus, the specification and the drawings are to be regarded as illustrative rather than restrictive. Additionally, the drawings illustrating the embodiments of the present invention may focus on certain major characteristic features for clarity. Furthermore, modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. In particular, while the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.

Contents4

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TW201220450A	Taiwan Province of China	A	2012-05-16
US2012119373A1	United States of America	A1	2012-05-17
CN102468257A	China	A	2012-05-23
US8941222B2This record	United States of America	B2	2015-01-27
US2015140737A1	United States of America	A1	2015-05-21
TWI495064B	Taiwan Province of China	B	2015-08-01
US9343333B2	United States of America	B2	2016-05-17
US2016233169A1	United States of America	A1	2016-08-11
CN102468257B	China	B	2016-11-23
CN106449547A	China	A	2017-02-22

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	Event	Code
2022-07-27	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2018-07-27	Payment of Maintenance Fee, 4th Year, Large EntityM1551	M1551
2015-01-27	Recordation of Patent Grant MailedPGM/	PGM/
2015-01-27	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2015-01-08	Email NotificationEML_NTR	EML_NTR
2015-01-07	Issue Notification MailedAllowedWPIR	WPIR
2014-12-23	Dispatch to FDCD1935	D1935
2014-12-23	Application Is Considered Ready for IssuePILS	PILS
2014-12-15	Response to Reasons for AllowanceREAS	REAS
2014-12-15	Issue Fee Payment VerifiedN084	N084
2014-12-15	Issue Fee Payment ReceivedIFEE	IFEE
2014-09-19	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2014-09-19	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2014-09-19	Case Docketed to Examiner in GAUDOCK	DOCK
2014-09-18	Reasons for AllowanceEX.R	EX.R
2014-09-17	Information Disclosure Statement consideredIDSC	IDSC
2014-09-17	Date Forwarded to ExaminerFWDX	FWDX
2014-09-17	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2014-09-12	Reference capture on IDSRCAP	RCAP
2014-09-12	Information Disclosure Statement (IDS) FiledM844	M844
2014-09-12	Request for Continued Examination (RCE)RCEX	RCEX
2014-09-12	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-09-12	Workflow - Request for RCE - BeginBRCE	BRCE
2014-07-18	Mail Ex Parte Quayle Action (PTOL - 326)MCTEQ	MCTEQ
2014-07-15	Quayle actionCTEQ	CTEQ
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-07-02	Information Disclosure Statement consideredIDSC	IDSC
2014-06-23	Date Forwarded to ExaminerFWDX	FWDX
2014-06-18	Information Disclosure Statement (IDS) FiledM844	M844
2014-06-18	Response to Election / Restriction FiledELC.	ELC.
2014-06-18	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2014-04-18	Mail Restriction RequirementMCTRS	MCTRS
2014-04-15	Restriction/Election RequirementCTRS	CTRS
2014-04-15	Case Docketed to Examiner in GAUDOCK	DOCK
2014-03-17	Information Disclosure Statement (IDS) FiledM844	M844
2014-03-17	Reference capture on IDSRCAP	RCAP
2014-03-17	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-08-09	Reference capture on IDSRCAP	RCAP
2013-08-09	Information Disclosure Statement (IDS) FiledM844	M844
2013-08-09	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-06-21	Reference capture on IDSRCAP	RCAP
2013-06-21	Information Disclosure Statement (IDS) FiledM844	M844
2013-06-21	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-10-18	Reference capture on IDSRCAP	RCAP
2012-10-18	Information Disclosure Statement (IDS) FiledM844	M844
2012-10-18	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-09-20	Reference capture on IDSRCAP	RCAP
2012-09-20	Information Disclosure Statement (IDS) FiledM844	M844
2012-09-20	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-08-15	Information Disclosure Statement (IDS) FiledM844	M844
2012-08-15	Reference capture on IDSRCAP	RCAP
2012-08-15	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-05-17	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2012-04-18	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2012-04-17	Correspondence Address ChangeC.AD	C.AD
2012-02-13	Mail-Petition Decision - GrantedMP033	MP033
2012-02-13	Petition Decision - GrantedP033	P033
2012-02-13	Correspondence Address ChangeC.AD	C.AD
2012-02-13	Petition EnteredPET.	PET.
2012-01-20	Case Docketed to Examiner in GAUDOCK	DOCK
2011-09-16	Reference capture on IDSRCAP	RCAP
2011-09-16	Information Disclosure Statement (IDS) FiledM844	M844
2011-09-16	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-08-24	Case Docketed to Examiner in GAUDOCK	DOCK
2010-12-28	Application Dispatched from OIPEOIPE	OIPE
2010-11-29	Application Is Now CompleteCOMP	COMP
2010-11-29	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2010-11-29	Sent to Classification ContractorPGPC	PGPC
2010-11-29	Filing ReceiptFLRCPT.O	FLRCPT.O
2010-11-17	Cleared by OIPE CSRL194	L194
2010-11-11	Electronic Information Disclosure StatementEIDS.	EIDS.
2010-11-11	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2010-11-11	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2010-11-11	Initial Exam Team nnIEXX	IEXX

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	Event	Code
2022-07-27	Maintenance fee paymentMAFP	MAFP
2018-07-27	Maintenance fee paymentMAFP	MAFP
2015-01-07	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2010-11-12	AssignmentAS	AS