Light-emitting device

REFERENCE TO RELATED APPLICATION

0001This application is a continuation-in-part of U.S. patent application Ser. No. 11/581,439, entitled “LIGHT-EMITTING APPARATUS”, filed Oct. 17, 2006, and is a continuation application of U.S. patent application Ser. No. 13/178,323, entitled “OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME”, filed Jul. 7, 2011, and is a continuation application of U.S. patent application Ser. No. 13/772,149, entitled “LIGHT-EMITTING DEVICE”, filed Feb. 20, 2013, now pending, the entire content of which is incorporated herein by reference in its entirety.

BACKGROUND

00021. Technical Field

0003This application relates to a light-emitting diode device, and more particularly to a high light extraction light-emitting diode device.

00042. Description of the Related Art

0005Light-emitting diode (LED) devices are widely used in different fields such as displays, traffic lights, data storage apparatus, communication apparatus, lighting apparatus, and medical apparatus. One important task for engineers is to increase the brightness of the LED devices.

0006In a known LED device, the semiconductor layer of the LED device having a textured surface can have higher light extraction efficiency. However, the textured surface can lower lateral current conduction and current spreading so the forward voltage is higher.

SUMMARY

0007A light-emitting device, comprising: a semiconductor contact layer having a rough top surface, wherein the rough top surface comprises any two adjacent crests having a highest point respectively and a trough having a lowest point between the two adjacent crests; and a transparent current spreading layer having a top surface on the semiconductor contact layer; wherein the top surface of the transparent current spreading layer comprises any two adjacent crests having a highest point respectively and a trough having a lowest point between the two adjacent crests; wherein the rough top surface of the semiconductor contact layer is substantially directly under the top surface of the transparent current spreading layer; wherein two oblique lines formed by connecting the highest points and the lowest point of the rough top surface on the semiconductor contact layer, and a first angle θ₁formed between the two oblique lines; wherein two oblique lines formed by connecting the highest points and the lowest point of the top surface on the transparent current spreading layer, and a second angle θ₂formed between the two oblique lines; wherein a difference between the first angle θ₁and the second angle θ₂is not greater than 10 degrees, or the first angle θ₁is substantially the same as the second angle θ₂.

BRIEF DESCRIPTION OF THE DRAWINGS

0008The accompanying drawings are included to provide easy understanding of the application, and are incorporated herein and constitute a part of this specification. The drawings illustrate embodiments of the application and, together with the description, serve to illustrate the principles of the application.

0009<figref idref="DRAWINGS">FIG. 1A-FIG</figref>. <b>1</b>F illustrate a process flow of a method of fabricating a light emitting device in accordance with a first embodiment of the present application.

0010<figref idref="DRAWINGS">FIG. 1G</figref> is a top view of a second semiconductor layer in accordance with a first embodiment of the present application.

0011<figref idref="DRAWINGS">FIG. 1H</figref> is an SEM diagram showing a surface morphology of an ITO layer in accordance with a first embodiment of the present application.

0012<figref idref="DRAWINGS">FIGS. 2A-2D</figref> are cross-sectional views of a light-emitting device in accordance with a horizontal type embodiment of the present application.

0013<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a light-emitting device in accordance with a third embodiment of the present application.

0014<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a light-emitting device in accordance with a fourth embodiment of the present application.

0015<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of a light-emitting device in accordance with a fifth embodiment of the present application.

0016<figref idref="DRAWINGS">FIGS. 6A-6B</figref> are top views of a second semiconductor layer in accordance with a first embodiment of the present application.

0017<figref idref="DRAWINGS">FIGS. 7A-7B</figref> are top views second semiconductor layer in accordance with a second embodiment of the present application.

0018<figref idref="DRAWINGS">FIGS. 8A-8C</figref> are cross-sectional views of a light emitting device in accordance with a third embodiment of the present application.

0019<figref idref="DRAWINGS">FIGS. 9A to 9C</figref> illustrates an LED module of an embodiment in the present disclosure.

0020<figref idref="DRAWINGS">FIGS. 10A-10B</figref> illustrates a lighting apparatus of an embodiment in the present disclosure.

0021<figref idref="DRAWINGS">FIG. 11</figref> is an explosive diagram of a bulb in accordance with an embodiment of the present application.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0022Reference is made in detail to the preferred embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

0023The present disclosure describes a light emitting device and a method of fabricating the light emitting device. In order to have a thorough understanding of the present disclosure, please refer to the following description and the illustrations of <figref idref="DRAWINGS">FIG. 1A</figref> to <figref idref="DRAWINGS">FIG. 7</figref>.

0024<figref idref="DRAWINGS">FIGS. 1A to 1F</figref> illustrate a process flow of the method of fabricating a light emitting device in accordance with a first embodiment of the present application. Referring to <figref idref="DRAWINGS">FIG. 1A</figref>, a light-emitting device comprises a conductive substrate <b>10</b>; a light emitting stack <b>12</b> including a first conductivity type semiconductor layer <b>124</b>, a light-emitting layer <b>122</b> and a second conductivity type semiconductor layer <b>120</b> sequentially formed on the first surface <b>101</b> of the conductive substrate wherein the upper surface <b>1201</b> of the second conductivity type semiconductor layer <b>120</b> has a textured surface formed by an epitaxy method, an etching method, or the combination thereof. The material of the light emitting stack <b>12</b> contains one or more elements selected from the group consisting of Ga, Al, In, As, P, N and Si, such as aluminum gallium indium phosphide (AlGaInP) series material, aluminum gallium indium nitride (AlGaInN) series material and so on. The light-emitting layer <b>122</b> can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MWQ). Besides, the wavelength of the emitting light can also be adjusted by changing the number of the pairs of the quantum well.

0025Referring to <figref idref="DRAWINGS">FIG. 1B</figref>, a first planarization layer <b>13</b> is formed to cover and fill the textured spaces of the upper surface <b>1201</b> of the second conductivity type semiconductor layer <b>120</b>. The first planarization layer <b>13</b> can be formed by spin coating method such as spin-on glass (SOG) or benzocyclobutene (BCB). In one embodiment of this application, the SOG can be a dielectric material mixture of SiO₂and dopants (either boron or phosphorous) that is suspended in a solvent solution. The SOG can also be polymers such as HSQ (Hydrogen silesquioxane) or MSQ (Methylsequioxane).

0026Referring to <figref idref="DRAWINGS">FIG. 1C</figref>, the first planarization layer <b>13</b> is patterned and solidified to form a second planarization layer <b>131</b> by etching or lithography method wherein part of the upper surface <b>1201</b> of the second conductivity type semiconductor layer <b>120</b> is exposed and not covered by the second planarization layer <b>131</b>. The position of the second planarization layer <b>131</b> is not specified and can be formed in the middle or the edge of the second conductivity type semiconductor layer <b>120</b>.

0027Referring to <figref idref="DRAWINGS">FIG. 1D</figref>, a first transparent conductive oxide layer <b>14</b> is formed to cover the entire second planarization layer <b>131</b> and part of the upper surface second conductivity type semiconductor layer <b>1201</b>. The first transparent conductive oxide layer <b>14</b> includes a first portion <b>141</b> and a second portion <b>142</b>, wherein the first portion <b>141</b> is formed in contact with the entire second planarization layer <b>131</b> which is substantially flat, and the second portion <b>142</b> is formed on the upper surface of the second conductivity type semiconductor layer <b>1201</b> having a first plurality of cavities <b>1421</b> in contact with the upper surface of the second conductivity type semiconductor layer <b>1201</b> and a second plurality of cavities <b>1422</b> formed in the upper surface of the second portion <b>142</b> which is opposite to the first plurality of cavities <b>1421</b>. The first plurality of cavities <b>1421</b> are shaped into cones or pyramids (as shown in <figref idref="DRAWINGS">FIGS. 1G-1H</figref>) and formed by an epitaxy method, an etching method, or the combination thereof. The second plurality of cavities <b>1422</b> are shaped into a cone or a pyramid by an etching process and extended downwards to the first plurality of cavities <b>1421</b> of the first transparent conductive layer <b>14</b>, wherein the direction of the extension is preferably perpendicular to the top surface of the conductive substrate <b>10</b>.

0028Referring to <figref idref="DRAWINGS">FIG. 1E</figref>, a first electrode <b>15</b> is formed on the first portion <b>141</b> of the first transparent conductive oxide layer <b>14</b>; and a second electrode <b>16</b> is formed on the second surface <b>102</b> of the conductive substrate <b>10</b>. The material of the electrode structure mentioned above can be metal material such as Cr, Ti, Ni, Pt, Cu, Au, Al, or Ag.

0029Referring to <figref idref="DRAWINGS">FIG. 1F</figref>, in another embodiment of this application, a first reflective metal layer <b>17</b> can be formed on the first portion <b>141</b> of the first transparent conductive oxide layer <b>14</b>; a first electrode <b>15</b> can be formed on the first reflective metal layer <b>17</b> to improve the light-emitting efficiency.

0030In accordance with the first embodiment of the present application, by forming the second planarization layer <b>131</b> the part of the transparent conductive oxide layer <b>14</b>, the first electrode <b>15</b> and the first reflective metal layer <b>17</b> can be formed on a substantially flat surface, and the impedance and the forward voltage can be decreased and the lateral current conduction, current spreading and efficiency can be increased.

0031Besides, the first plurality of cavities <b>1421</b> are extended downwards from the surface of the second semiconductor layer <b>120</b> and make the upper surface of the second portion <b>142</b> of the first transparent conductive oxide layer <b>14</b> conformally formed on the second semiconductor layer <b>120</b> and have the second plurality of cavities <b>1422</b>. The adhesion strength between the first reflective metal layer <b>17</b> and the first transparent conductive oxide layer <b>14</b> has been improved by the first plurality of cavities <b>1421</b>. The result of a peeling test for the device made in accordance with the first embodiment and the conventional LED device without cavities on the surface of the first transparent oxide layer shows that all the devices in accordance with the first embodiment passed the peeling test, but more than 80% of the conventional LED devices failed in the peeling test. By the combination of the flat and textured first transparent oxide layer, the lower efficiency and peeling issues are solved.

0032<figref idref="DRAWINGS">FIGS. 2A-2D</figref> are cross-sectional views of a light-emitting device in accordance with a horizontal type embodiment of the present application. Referring to <figref idref="DRAWINGS">FIG. 2A</figref>, a light-emitting device comprises a substrate <b>20</b>; a light emitting stack <b>22</b> including a first conductivity type semiconductor layer <b>224</b>, a light-emitting layer <b>222</b> and a second conductivity type semiconductor layer <b>220</b> sequentially formed on the first surface <b>201</b> of the substrate <b>20</b> wherein the upper surface <b>2201</b> of the second conductivity type semiconductor layer <b>220</b> has a textured surface formed by an epitaxy method, an etching method, or the combination thereof. The light emitting stack <b>22</b> is etched, and part of the first conductivity type semiconductor layer <b>224</b> is exposed to form a horizontal type light emitting device.

0033The material of the light emitting stack <b>22</b> contains one or more elements selected from the group consisting of Ga, Al, In, As, P, N and Si, such as aluminum gallium indium phosphide (AlGaInP) series material, aluminum gallium indium nitride (AlGaInN) series material and so on. The light-emitting layer <b>222</b> can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MWQ). Besides, the wavelength of the emitting light can also be adjusted by changing the number of the pairs of the quantum well.

0034Following a similar process as the first embodiment, a first planarization layer (not shown) is formed by spin coating method such as spin-on glass (SOG) or benzocyclobutene (BCB) to cover and fill the textured spaces of the upper surface <b>2201</b> of the second conductivity type semiconductor layer <b>220</b>. The first planarization layer <b>23</b> can be formed by spin coating method such as spin-on glass (SOG) or benzocyclobutene (BCB). In one embodiment of this application, the SOG can be a dielectric material mixture of SiO₂and dopants (either boron or phosphorous) that is suspended in a solvent solution. The SOG can also be polymers such as HSQ (Hydrogen silesquioxane) or MSQ (Methylsequioxane).

0035Then, the first planarization layer (not shown) is patterned and solidified to form a second planarization layer <b>231</b> by etching or lithography method wherein part of the upper surface <b>2201</b> of the second conductivity type semiconductor layer <b>220</b> is exposed and not covered by the second planarization layer <b>231</b>. The position of the second planarization layer <b>231</b> is not specified and can be formed in the middle or the edge of the second conductivity type semiconductor layer <b>220</b>.

0036Following, a first transparent conductive oxide layer <b>24</b> is formed to cover the entire second planarization layer <b>231</b> and part of the upper surface second conductivity type semiconductor layer <b>2201</b>. The first transparent conductive oxide layer <b>24</b> includes a first portion <b>241</b> and a second portion <b>242</b>, wherein the first portion <b>241</b> is formed in contact with the entire second planarization layer <b>231</b> which is substantially flat, and the second portion <b>242</b> is formed on the upper surface of the second conductivity type semiconductor layer <b>2201</b> having a first plurality of cavities <b>2421</b> in contact with the upper surface of the second conductivity type semiconductor layer <b>2201</b> and a second plurality of cavities <b>2422</b> formed in the upper surface of the second portion <b>242</b> which is opposite to the first plurality of cavities <b>2421</b>. The first plurality of cavities <b>2421</b> are shaped into cones or pyramids and formed by an epitaxy method, an etching method, or the combination thereof. The second plurality of cavities <b>2422</b> are shaped into a cone or a pyramid by an etching process and extended downwards to the first plurality of cavities <b>2421</b> of the first transparent conductive layer <b>24</b>, wherein the direction of the extension is preferably perpendicular to the top surface of the substrate <b>20</b>.

0037Finally, a first electrode <b>25</b> is formed on the first portion <b>241</b> of the first transparent conductive oxide layer <b>24</b>; and a second electrode <b>26</b> is formed on the exposed first conductivity type semiconductor layer <b>224</b>. The material of the electrode structure mentioned above can be metal material such as Cr, Ti, Ni, Pt, Cu, Au, Al, Ag, or the alloy thereof. By the combination of the flat and textured first transparent oxide layer, the lower efficiency issues are solved.

0038Referring to <figref idref="DRAWINGS">FIG. 2B</figref>, In another embodiment of this application, a first reflective metal layer <b>27</b> can be formed on the first portion <b>241</b> of the first transparent conductive oxide layer <b>24</b>; a first electrode <b>25</b> can be formed on the first reflective metal layer <b>27</b> to improve the light-emitting efficiency.

0039The first plurality of cavities <b>2421</b> are extended downwards from the surface of the second semiconductor layer <b>220</b> and make the upper surface of the second portion <b>242</b> of the first transparent conductive oxide layer <b>24</b> conformally formed on the second semiconductor layer <b>220</b> and have the second plurality of cavities <b>2422</b>. The adhesion strength between the first reflective metal layer <b>27</b> and the first transparent conductive oxide layer <b>24</b> has been improved by the first plurality of cavities <b>2421</b>. The result of a peeling test for the device made in accordance with the first embodiment and the conventional LED device without cavities on the surface of the first transparent oxide layer shows that all the devices in accordance with the first embodiment passed the peeling test, but more than 80% of the conventional LED devices failed in the peeling test. By the combination of the flat and textured first transparent oxide layer, the lower efficiency and peeling issues are solved.

0040Referring to <figref idref="DRAWINGS">FIG. 2C</figref>, in another embodiment of this application, the difference between the <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2C</figref> is that the first conductivity type semiconductor layer <b>224</b> is etched to form a textured surface <b>2241</b>. Following, a similar process as the embodiment in <figref idref="DRAWINGS">FIG. 2A</figref>, a third planarization layer (not shown) is formed by spin coating method such as spin-on glass (SOG) or benzocyclobutene (BCB) to cover and fill the textured spaces of the upper surface <b>2241</b> of the first conductivity type semiconductor layer <b>220</b> and then the third planarization layer (not shown) is patterned and solidified to form a fourth planarization layer <b>291</b> by etching or lithography method wherein part of the upper surface <b>2241</b> of the first conductivity type semiconductor layer <b>224</b> is exposed. The position of the fourth planarization layer <b>291</b> is not specified and can be formed in the middle or the edge of the second conductivity type semiconductor layer <b>224</b>.

0041Following, a second transparent conductive oxide layer <b>28</b> is formed to cover the entire fourth planarization layer <b>291</b> and part of the upper surface first conductivity type semiconductor layer <b>2241</b>. The second transparent conductive oxide layer <b>28</b> includes a first portion <b>281</b> and a second portion <b>282</b> wherein the first portion <b>281</b> is formed in contact with the entire fourth planarization layer <b>291</b> which is substantially flat and the second portion <b>282</b> is formed on the upper surface of the first conductivity type semiconductor layer <b>2241</b> having a first plurality of cavities <b>2821</b> in contact with the upper surface of the first conductivity type semiconductor layer <b>2241</b> and a second plurality of cavities <b>2822</b> formed in the upper surface of the second portion <b>282</b> which is opposite to the first plurality of cavities <b>2821</b>. The first plurality of cavities <b>2821</b> are shaped into cones or pyramids and formed by an epitaxy method, an etching method, or the combination thereof. The second plurality of cavities <b>2822</b> are shaped into a cone or a pyramid by an etching process and extended downwards to the first plurality of cavities <b>2821</b> of the second transparent conductive layer <b>28</b>, wherein the direction of the extension is preferably perpendicular to the top surface of the substrate <b>20</b>.

0042Finally, a first electrode <b>25</b> is formed on the first portion <b>241</b> of the first transparent conductive oxide layer <b>24</b>; and a second electrode <b>26</b> is formed on the first portion <b>281</b> of the second transparent conductive oxide layer <b>28</b>. The material of the electrode structure mentioned above can be metal material such as Cr, Ti, Ni, Pt, Cu, Au, Al, or Ag. By the combination of the flat and textured first transparent oxide layer and the flat and textured second transparent oxide layer, the lower efficiency issues are solved.

0043Referring to <figref idref="DRAWINGS">FIG. 2D</figref>, in another embodiment of this application, a second reflective metal layer <b>30</b> can be formed on the first portion <b>281</b> of the second transparent conductive oxide layer <b>28</b>; a first electrode <b>25</b> can be formed on the first reflective metal layer <b>27</b> and a second electrode <b>26</b> can be formed on the second reflective layer <b>30</b> to improve the light-emitting efficiency.

0044<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of a light-emitting device in accordance with a third embodiment of the present application. The difference between the third embodiment and the first embodiment is that an additional Distributed Bragg Reflector (DBR) layer <b>38</b> is formed between the conductive substrate <b>30</b> and the first conductivity type semiconductor layer <b>324</b>.

0045<figref idref="DRAWINGS">FIG. 4</figref> is a cross-sectional view of a light-emitting device in accordance with a fourth embodiment of the application. The difference between the fourth embodiment and the first embodiment is that a metal bonding layer <b>41</b>, a reflective layer <b>49</b> and a second transparent conductive oxide layer <b>48</b> is formed between the conductive substrate <b>40</b> and the first conductivity type semiconductor layer <b>424</b>.

0046<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view of a light-emitting device in accordance with a fifth embodiment of the present application. The difference between the fourth embodiment and the second embodiment is that a metal bonding layer <b>51</b>, a reflective layer <b>59</b> and a second transparent conductive oxide layer <b>58</b> is formed between the substrate <b>50</b> and the first conductivity type semiconductor layer <b>524</b> and the second electrode <b>56</b> is formed on the second transparent conductive oxide layer <b>58</b>.

0047<figref idref="DRAWINGS">FIGS. 6A-6B</figref> are top views of a second semiconductor layer in accordance with a first embodiment of the present application. <figref idref="DRAWINGS">FIG. 6A</figref> is a top view of a second semiconductor layer <b>120</b>, the second planarization layer (not shown) can be formed on part of the second semiconductor layer <b>120</b>. After forming the second planarization layer, the first transparent conductive oxide layer <b>14</b> is formed on part of the second planarization layer and having a first portion <b>141</b> in contact with the entire second planarization layer which is substantially flat and a second portion formed on the second semiconductor layer <b>120</b> with a textured surface. Following, a first electrode <b>15</b> is formed on the first portion <b>141</b> of the first transparent conductive oxide layer <b>14</b>. In this embodiment, part of the first transparent conductive oxide layer <b>14</b> is not covered by the first electrode <b>15</b> and is extended toward the other end of the light emitting chip as a finger to spread the current.

0048Referring to <figref idref="DRAWINGS">FIG. 6B</figref>, in another embodiment, the first electrode <b>15</b> can have a secondary branch <b>151</b> having a finger-like pattern extended toward the other end of the light emitting device to have better current spreading. The first transparent conductive oxide layer <b>14</b> can further have a secondary branch <b>1411</b> having a finger-like pattern extended toward the other end of the light emitting device and a third class branch <b>1412</b> extended from the secondary branch <b>1411</b> as a transparent finger to increase the current spreading efficiency. In this embodiment, part of the secondary branch <b>1411</b> and the third class branch <b>1412</b> of the first transparent conductive oxide layer is not covered by the secondary branch of the first electrode <b>151</b>. Since the secondary branch of the first transparent conductive oxide layer <b>1411</b> and the third class branch <b>1412</b> of the first transparent conductive oxide layer is formed on the second planarization layer (not shown), the structure is also substantially flat and can have a better current spreading efficiency.

0049<figref idref="DRAWINGS">FIGS. 7A-7B</figref> are top views of a second semiconductor layer in accordance with a first embodiment of the present application. <figref idref="DRAWINGS">FIG. 7A</figref> is a top view of a second semiconductor layer <b>220</b>, the second planarization layer (not shown) can be formed on part of the second semiconductor layer <b>220</b>. After forming the second planarization layer, the first transparent conductive oxide layer <b>24</b> is formed on part of the second planarization layer and having a first portion <b>241</b> in contact with the entire second planarization layer which is substantially flat and a second portion formed on the second semiconductor layer <b>220</b> with a textured surface. Following, a first electrode <b>25</b> is formed on the first portion <b>241</b> of the first transparent conductive oxide layer <b>24</b>. In this embodiment, part of the first transparent conductive oxide layer <b>24</b> is not covered by the first electrode <b>25</b> and is extended toward the other end of the light emitting chip as a finger to spread the current.

0050Referring to <figref idref="DRAWINGS">FIG. 7B</figref>, in another embodiment, the first electrode <b>25</b> can have a secondary branch <b>251</b> having a finger-like pattern extended toward the other end of the light emitting device to have better current spreading. The first transparent conductive oxide layer <b>24</b> can further have a secondary branch <b>2411</b> having a finger-like pattern extended toward the other end of the light emitting device and a third class branch <b>2412</b> extended from the secondary branch <b>2411</b> as a transparent finger to increase the current spreading efficiency. In this embodiment, part of the secondary branch <b>2411</b> and the third class branch <b>2412</b> of the first transparent conductive oxide layer is not covered by the secondary branch of the first electrode <b>251</b>. Since the secondary branch of the first transparent conductive oxide layer <b>2411</b> and the third class branch <b>2412</b> of the first transparent conductive oxide layer is formed on the second planarization layer (not shown), the structure is also substantially flat and can have a better current spreading efficiency.

0051<figref idref="DRAWINGS">FIGS. 8A-8C</figref> are cross-sectional views of a light emitting device <b>1200</b> in accordance with a third embodiment of the present application. <figref idref="DRAWINGS">FIG. 8A</figref> illustrates a substrate <b>1210</b>, a light-emitting structure <b>1250</b> formed on the substrate <b>1210</b>, a semiconductor contact layer <b>1260</b> having a rough top surface formed on the light-emitting structure <b>1250</b>, and a transparent current spreading layer <b>1270</b> having a top surface formed on the semiconductor contact layer <b>1260</b>. The light-emitting structure <b>1250</b> includes a first conductivity type semiconductor layer <b>1220</b>, an active layer <b>1230</b>, and a second conductivity type semiconductor layer <b>1240</b>. The rough top surface of the semiconductor contact layer <b>1260</b> is substantially directly under the top surface of the transparent current spreading layer <b>1270</b>. The substrate <b>1210</b> is a growth base or a carrier base. The material of the semiconductor contact layer <b>1260</b> and the light-emitting structure <b>1250</b> comprise one or more elements selected from a group consisting of gallium, aluminum, indium, arsenic, phosphorous, nitrogen, and silicon. The transparent current spreading layer <b>1270</b> comprises a metal oxide or a metal nitride.

0052Following, <figref idref="DRAWINGS">FIG. 8B</figref> illustrates an enlarged diagram of a partial region of the semiconductor contact layer <b>1260</b> and of the transparent current spreading layer <b>1270</b>. The rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> comprises any two adjacent crests having a highest point A₁, A₂respectively and a trough having a lowest point B₁between the two adjacent crests. The top surface <b>1320</b> of the transparent current spreading layer <b>1270</b> comprises any two adjacent crests having a highest point A₃, A₄respectively and a trough having a lowest point B₂between the two adjacent crests. Two oblique lines L₂, L₄are formed by connecting the highest points A₁, A₂and the lowest point B₁of the rough top surface <b>1310</b> on the semiconductor contact layer <b>1260</b>. A first angle θ₁is formed between the two oblique lines L₂, L₄. Two oblique lines L₁, L₃are formed by connecting the highest points A₃, A₄and the lowest point B₂of the top surface <b>1320</b> on the transparent current spreading layer <b>1270</b>. A second angle θ₂is formed between the two oblique lines L₁, L₃. A difference between the first angle θ₁and the second angle θ₂is greater than 10 degrees. In another embodiment, the first angle θ₁is substantially the same as the second angle θ₂. A height difference H₁between the lowest point B₂on the trough of the top surface <b>1320</b> of the transparent current spreading layer <b>1270</b> and the lowest point B₁on the trough of the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> is greater than 0. A height difference H₂between the highest point A₃on the crest of the top surface <b>1320</b> of the transparent current spreading layer <b>1270</b> and the highest point A₁on the crest of the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> is greater than 0. A height difference H₃between the highest point A₄on the crest of the top surface <b>1320</b> of the transparent current spreading layer <b>1270</b> and the highest point A₂on the crest of the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> is greater than 0. The height difference H₂is the same as or different from the height difference H₃. A ratio of the height difference H₁and the height difference H₂is between 0.1 and 10. A ratio of the height difference H₁and the height difference H₃is between 0.1 and 10. In another embodiment, the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> comprises a cavity shaped as cone or pyramid, wherein the cavity extends from the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> downwards to inner of the semiconductor contact layer <b>1260</b>.

0053<figref idref="DRAWINGS">FIG. 8C</figref> illustrates another enlarged diagram of a partial region of the semiconductor contact layer <b>1260</b> and of the transparent current spreading layer <b>1270</b>. A flat region C₁is on the trough of the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b>. A flat region C₂is on the trough of the top surface <b>1320</b> of the transparent current spreading layer <b>1270</b>. A height difference H₁between the flat region C₂on the trough of the top surface <b>1320</b> of the transparent current spreading layer <b>1270</b> and the flat region C₁on the trough of the rough top surface <b>1310</b> of the semiconductor contact layer <b>1260</b> is greater than 0.

0054<figref idref="DRAWINGS">FIGS. 9A-9C</figref> illustrates an LED module of an application in the present disclosure. <figref idref="DRAWINGS">FIG. 9A</figref> is an external perspective view illustrating an optoelectronic device module <b>900</b> including a submount <b>902</b>, an optoelectronic device (not illustrated) described above, a plurality of lens <b>904</b>, <b>906</b>, <b>908</b>, <b>910</b>, and two power supply terminals <b>912</b>, <b>914</b>. The optoelectronic device module <b>900</b> is attached to a lighting unit <b>1000</b> (mentioned later).

0055<figref idref="DRAWINGS">FIG. 9B</figref> is a plan view illustrating the optoelectronic device module <b>900</b>, and <figref idref="DRAWINGS">FIG. 9C</figref> is an enlarged view illustrating a portion E illustrated in <figref idref="DRAWINGS">FIG. 9B</figref>. As <figref idref="DRAWINGS">FIG. 9B</figref> illustrates, the submount <b>902</b> including an upper subunit <b>903</b> and a lower subunit <b>901</b>, and at least one surface of the lower subunit <b>901</b> is contacted with the upper subunit <b>903</b>. The lens <b>904</b>, <b>908</b> are formed on the upper subunit <b>903</b>. At least one through hole <b>915</b> is formed on the upper subunit <b>903</b> and at least one of the optoelectronic device <b>800</b> is formed inside the through hole <b>915</b> and contacted with the lower subunit <b>901</b>. Besides, the optoelectronic device <b>800</b> is encapsulated by an encapsulating material <b>921</b> and a lens <b>908</b> is formed on the encapsulating material <b>921</b> wherein the material of the encapsulating material <b>921</b> may be a silicone resin, an epoxy resin or the like. In one embodiment, a reflecting layer <b>919</b> is formed on the sidewall of the through hole <b>915</b> to increase the light emitting efficiency. A metal layer <b>917</b> can be formed on the lower surface of the lower subunit <b>901</b> for improving heat dissipation.

0056<figref idref="DRAWINGS">FIGS. 10A-10B</figref> illustrate a lighting apparatus of an embodiment in the present disclosure. The lighting apparatus <b>1000</b> includes an optoelectronic device module <b>900</b>, a case <b>1040</b>, a power supply circuit (not illustrated) to supply current to the optoelectronic device module <b>900</b>, and a control unit (not illustrated) to control the power supply circuit. The lighting apparatus <b>1000</b> can be an illumination device, such as street lamps, headlights or indoor illumination light source, and can be a traffic sign or a backlight module of the display panel.

0057<figref idref="DRAWINGS">FIG. 11</figref> illustrates an explosive diagram of a bulb in accordance with another application of the present application. The bulb <b>1100</b> comprises a cover <b>1121</b>, a lens <b>1122</b>, a lighting module <b>1124</b>, a lamp holder <b>1125</b>, a heat sink <b>1126</b>, a connecting part <b>1127</b>, and an electrical connector <b>1128</b>. The lighting module <b>1124</b> comprises a carrier <b>1123</b> and a plurality of optoelectronic devices <b>800</b> of any one of the above mentioned embodiments on the carrier <b>1123</b>.

0058Specifically, the optoelectronic device comprises light-emitting diode (LED), photodiode, photo resister, laser diode, infrared emitter, organic light-emitting diode, and solar cell. The substrate <b>10</b>, <b>20</b>, <b>30</b>, <b>40</b>, <b>50</b>, <b>80</b> can be a growing or carrying base. The material of the substrate <b>10</b>, <b>20</b>, <b>30</b>, <b>40</b>, <b>50</b>, <b>80</b> comprises an electrically conductive substrate, electrically insulating substrate, transparent substrate, or opaque substrate. The material of the electrically conductive substrate can be metal such as Ge and GaAs, oxide such as LiAlO₂and ZnO, nitrogen compound such as GaN and AlN, phosphide such as InP, silicon compound such as SiC, or Si. The material of the transparent substrate can be chosen from sapphire (Al₂O₃), LiAlO₂, ZnO, GaN, AlN, glass, diamond, CVD diamond, diamond-like carbon (DLC), spinel (MgAl₂O₃), SiO_x, or LiGaO₂.

0059The first conductivity type semiconductor layer <b>124</b>, <b>224</b>, <b>324</b>, <b>424</b>, <b>524</b>, <b>821</b> and the second conductivity type semiconductor layer <b>120</b>, <b>220</b>, <b>823</b> are different in electricity, polarity or dopant, or are different semiconductor materials used for providing electrons and holes, wherein the semiconductor material can be single semiconductor material layer or multiple semiconductor material layers. The polarity can be chosen from any two of p-type, n-type and i-type. The active layer <b>122</b>, <b>222</b>, <b>822</b> is disposed between the first conductivity type semiconductor layer <b>124</b>, <b>224</b>, <b>324</b>, <b>424</b>, <b>524</b>, <b>821</b> and the second conductivity type semiconductor layer <b>120</b>, <b>220</b>, <b>823</b> respectively where the electrical energy and the light energy can be converted or stimulated converted. The devices which can convert or stimulated convert the electrical energy into the light energy are like light-emitting diode, liquid crystal display, and organic light-emitting diode. The devices which can convert or stimulated convert the light energy into the electrical energy are like solar cell and light emitting diode. The material of the first conductivity type semiconductor layer <b>124</b>, <b>224</b>, <b>324</b>, <b>424</b>, <b>524</b>, <b>821</b> the active layer <b>122</b>, <b>222</b>, <b>822</b> and the second conductivity type semiconductor layer <b>120</b>, <b>220</b>, <b>823</b> comprises one element selected from the group consisting of Ga, Al, In, As, P, N, Si, and the combination thereof.

0060The optoelectronic device of another embodiment in the application is a light-emitting diode, of which the light spectrum can be adjusted by changing the essentially physical or chemical factor of the single semiconductor material layer or the multiple semiconductor material layers. The material of the single semiconductor material layer or the multiple semiconductor material layers can contain elements selected from Al, Ga, In, P, N, Zn, O, or the combination thereof. The structure of the active layer (not illustrated) can be single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH) or multi-quantum well (MQW), wherein the wavelength of the light emitted from the active layer (not illustrated) can be changed by adjusting the number of the pairs of MQW.

0061In one embodiment of the application, a buffer layer (not illustrated) can be selectively disposed between the first conductivity type semiconductor layer <b>124</b>, <b>224</b>, <b>324</b>, <b>424</b>, <b>524</b>, <b>821</b> and the substrate <b>10</b>, <b>20</b>, <b>30</b>, <b>40</b>, <b>50</b>, <b>80</b> The buffer layer is between the two material systems to transit the material system of the substrate <b>10</b>, <b>20</b>, <b>30</b>, <b>40</b>, <b>50</b>, <b>80</b> to the material system of the first conductivity type semiconductor layer <b>124</b>, <b>224</b>, <b>324</b>, <b>424</b>, <b>524</b>, <b>821</b>. For the structure of the light-emitting diode, the buffer layer is used to reduce the crystal mismatch between two materials. On the other hand, the buffer layer comprises a single layer, multiple layers or a structure which comprises two materials or two separated structures. The material of the buffer layer can be selected from organic material, inorganic material, metal or semiconductor material. The structure of the buffer layer can be a reflector layer, a thermally conductive layer, an electrically conductive layer, an ohmic contact layer, an anti-deformation layer, a stress release layer, a bonding layer, a wavelength conversion layer or a mechanically fixing structure. In one embodiment, the material of the buffer layer can be AlN or GaN, and the buffer layer can be formed by sputtering or atomic layer deposition (ALD).

0062In the aforementioned embodiments, the first transparent conductive oxide layer <b>14</b> and <b>24</b>, the second transparent conductive oxide layer <b>28</b>, <b>48</b>, <b>58</b>, the transparent conductive oxide layer <b>83</b> can be made of indium tin oxide (ITO), cadmium tin oxide (CTO), antimony tin oxide, zinc indium oxide, aluminum zinc oxide, zinc antimony oxide, or the combinations thereof; and is formed by an E-beam evaporation method, an ion-sputtering method, a thermal-evaporation method, or any combination thereof. Taking ITO as an example, the thickness of the first transparent conductive oxide layer <b>14</b> and <b>24</b>, the second transparent conductive oxide layer <b>28</b>, <b>48</b>, <b>58</b>, the transparent conductive oxide layer <b>83</b> is from 50 μm to 1 μm and the transmissivity is above 50% when the range of the related wavelength is from 300 μm to 700 μm.

0063In the aforementioned embodiments, the metal bonding layer <b>41</b>, <b>51</b> is made of indium (In), tin (Sn), gold-tin (AuSn), or the combination thereof.

0064The DBR layer <b>38</b> is formed by stacked semiconductor layers and the reflective layers <b>49</b>, <b>59</b> are made of In, Sn, Ai, Au, Pt, Zn, Ag, Ti, Pb, Pd, Ge, Cu, AuBe, AuGe, Ni, PbSn, AuZn, or the combination thereof. The first and second reflective metal layers <b>17</b>, <b>27</b>, <b>30</b>, the reflective layer <b>86</b> are made of Al or Ag.

0065It will be apparent to those having ordinary skill in the art that various modifications and variations can be made to the devices in accordance with the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure covers modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.

0066Although the drawings and the illustrations above are corresponding to the specific embodiments individually, the element, the practicing method, the designing principle, and the technical theory can be referred, exchanged, incorporated, collocated, coordinated except they are conflicted, incompatible, or hard to be put into practice together.

0067Although the present application has been explained above, it is not the limitation of the range, the sequence in practice, the material in practice, or the method in practice. Any modification or decoration for present application is not detached from the spirit and the range of such.