Display device and electronic equipment therewith

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from Japanese Patent Application No. 2007-042568, the content of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

This invention relates to a display device provided with a power supply circuit and electronic equipment provided with the display device.

2. Description of the Related Art

In an active matrix type liquid crystal display device that is manufactured by a low temperature polysilicon TFT (Thin Film Transistor) technology, a power supply circuit that generates a positive power supply electric potential and a negative power supply electric potential to control turning on/off of pixel TFTs has been formed on a glass substrate of a liquid crystal panel in order to reduce a cost of a drive signal IC (Integrated Circuit). A horizontal transfer clock that drives a horizontal drive circuit, a vertical transfer clock that drives a vertical drive circuit or a dedicated clock is supplied from a driver IC as a drive clock to drive the power supply circuit. This kind of active matrix type liquid crystal display device is disclosed in Japanese Patent Application Publication No. 2004-146082.

When the power supply circuit is formed on the glass substrate of the liquid crystal panel, the power supply circuit is placed in an unused space in a frame of the glass substrate. The drive clock to drive the power supply circuit and a power supply electric potential are supplied to the power supply circuit through wirings from a terminal portion that is also placed on the glass substrate.

SUMMARY

When the power supply circuit is disposed at a location far from the terminal portion, however, a wiring load (resistive and capacitive loads associated with the wirings to provide the power supply and the drive clock) is increased to cause problems such as reduction in efficiency of the power supply circuit, increase in power consumption and display failures.

This invention offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a drive circuit to drive the pixel transistors, a positive power supply generation circuit to generate a positive power supply electric potential to drive the drive circuit, a negative power supply generation circuit to generate a negative power supply electric potential to drive the drive circuit, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the positive power supply generation circuit and the negative power supply generation circuit are placed closer to the terminal portion than the pixel portion and the drive circuit and are placed at substantially the same distance from the terminal portion.

With the structure described above, a wiring load can be reduced to prevent reduction in efficiency of the power supply generation circuits as well as preventing reduction in efficiency of either the positive power supply generation circuit or the negative power supply generation circuit due to an unbalanced wiring load, since the positive power supply generation circuit and the negative power supply circuit are placed close to the terminal portion and are placed at substantially the same distance from the terminal portion.

This invention also offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a positive power supply generation circuit to generate a positive power supply electric potential to control switching of the pixel transistors, a negative power supply generation circuit to generate a negative power supply electric potential to control switching of the pixel transistors, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the positive power supply generation circuit and the negative power supply generation circuit are placed at substantially the same distance from the terminal portion.

With the structure described above, reduction in efficiency of either the positive power supply generation circuit or the negative power supply generation circuit due to an unbalanced wiring load can be prevented, since the positive power supply generation circuit and the negative power supply circuit are placed at substantially the same distance from the terminal portion.

This invention also offers a display device including a pixel portion in which a plurality of pixel transistors are arrayed in a matrix form, a positive power supply generation circuit to generate a positive power supply electric potential to control switching of the pixel transistors, a negative power supply generation circuit to generate a negative power supply electric potential to control switching of the pixel transistors, a terminal portion to externally apply a drive clock and a power supply electric potential to drive the positive power supply generation circuit and the negative power supply generation circuit, and a wiring disposed between the terminal portion and both the positive power supply generation circuit and the negative power supply generation circuit in order to supply the drive clock and the power supply electric potential, wherein the negative power supply generation circuit is placed closer to the terminal portion than the positive power supply generation circuit.

With the structure described above, a leakage due to reduction in circuit efficiency of the negative power supply generation circuit can be prevented because the negative power supply generation circuit that has a small margin of a rise in the negative power supply electric potential due to a wiring load is placed closer to the terminal portion than the positive power supply generation circuit.

This invention also offers electronic equipment using the display device described above. This invention offers excellent electronic equipment that does not cause an increase in power consumption or a display failure because the efficiency of the power supply circuit is not reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a layout of a liquid crystal display device according to a first embodiment of this invention.

<figref idrefs="DRAWINGS">FIG. 2</figref> is a circuit diagram of a horizontal drive circuit.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a waveform chart showing an operation of the liquid crystal display device according to the first embodiment of this invention.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a circuit diagram of a positive power supply generation circuit.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a waveform chart showing an operation of the positive power supply generation circuit.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a circuit diagram of a negative power supply generation circuit.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a waveform chart showing an operation of the negative power supply generation circuit.

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a layout of a liquid crystal display device according to a second embodiment of this invention.

<figref idrefs="DRAWINGS">FIG. 9</figref> shows a layout of a liquid crystal display device according to a third embodiment of this invention.

DETAILED DESCRIPTION

Embodiments of this invention will be described referring to the drawings.

First Embodiment

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a layout (plan view) of a liquid crystal display device according to a first embodiment of this invention. A pixel portion <b>105</b>, a horizontal drive circuit <b>110</b> and a vertical drive circuit <b>120</b> are formed on a TFT glass substrate <b>100</b>. A plurality of pixels (Only four pixels are shown in <figref idrefs="DRAWINGS">FIG. 1</figref>.) is arrayed in a matrix form in the pixel portion <b>105</b>.

The horizontal drive circuit <b>110</b> is provided with a shift register SR that is made of a plurality of flip-flops FF and transfers a horizontal start signal STH based on a horizontal clock CKH and its reverse clock *CKH and a plurality of horizontal switches HSW, each of which is turned on based on an output of each of the flip-flops FF, as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>. Each of the horizontal switches HSW is made of a TFT having a gate to which the output of corresponding each of the flip-flops FF is applied, a source to which a video signal Vsig is applied and a drain connected with a data line DL. That is, each of the horizontal switches HSW is turned on in a sequential order based on the output of corresponding each of the flip-flops FF to sample and output the video signal Vsig to the data line DL.

The vertical drive circuit <b>120</b> is a shift register that sequentially transfers a vertical start signal STV based on a vertical transfer clock CKV and provides each of gate lines GL with a gate signal corresponding to its output.

A pixel transistor GT in each of the pixels is made of a TFT having a drain connected with corresponding each of the data lines DL and a gate connected with corresponding each of the gate lines GL, and is controlled to turn on/off by the gate signal. A source of the pixel transistor GT is connected with a pixel electrode <b>121</b>. The pixel electrode <b>121</b> is usually provided with a retention capacitor (not shown) to retain its electric potential.

A counter glass substrate <b>200</b> is disposed to face the TFT glass substrate <b>100</b>. A common electrode <b>122</b> is formed on the counter glass substrate <b>200</b> so as to face the pixel electrodes <b>121</b>. A liquid crystal LC is sealed between the TFT glass substrate <b>100</b> and the counter glass substrate <b>200</b>.

A driver IC disposed on the TFT glass substrate <b>100</b> of the liquid crystal panel or outside the liquid crystal panel provides the common electrode <b>122</b> with a common electrode signal VCOM that alternates between an H level and an L level once every horizontal period for line inversion drive.

In the case where the pixel transistor GT is of N-channel type, the pixel transistor GT is turned on when the gate signal turns to an H level. As a result, the video signal Vsig is applied from the data line DL to the pixel electrode <b>121</b> through the pixel transistor GT, and the display is performed by controlling alignment of the liquid crystal LC.

Since the common electrode signal VCOM alternates between the H level and the L level as described above, the electric potential of the pixel electrode <b>121</b> is changed by capacitive coupling through the liquid crystal LC. Regarding the above, the H level of the gate signal to turn on the pixel transistor GT is set at a positive power supply electric potential that is generated by boosting, and an L level of the gate signal to turn off the pixel transistor GT is set at a negative power supply electric potential. In order to generate the gate signal, a positive power supply generation circuit <b>131</b> that generates the positive power supply electric potential and a negative power supply generation circuit <b>132</b> that generates the negative power supply electric potential are formed on the TFT glass substrate <b>100</b>.

The positive power supply generation circuit <b>131</b> boosts an input power supply electric potential VDD to generate an output electric potential VPP=2VDD that is equal to twice of the input power supply electric potential VDD. The negative power supply generation circuit <b>132</b> generates an output electric potential VBB=−VDD that is equal to the input power supply electric potential VDD multiplied by minus one. Note that this is for the case where circuit efficiency is 100%. In the embodiment of this invention, the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are disposed close to a terminal portion <b>140</b>, to which a drive clock and the input power supply electric potential are applied externally, so that wiring loads (resistive and capacitive loads associated with wirings to provide the power supply and the drive clock) of the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are reduced to suppress reduction in the circuit efficiency. The terminal portion <b>140</b> is formed in an edge portion of the TFT glass substrate <b>100</b>. That is, the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are placed closer to the terminal portion <b>140</b> than primary circuits of the liquid crystal display device, which are the pixel portion <b>105</b>, the horizontal drive circuit <b>110</b> and the vertical drive circuit <b>120</b>. With this, a layout that minimizes the wiring loads is obtained.

It is preferable that the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are placed next to each other at substantially the same distance from the terminal portion <b>140</b> and parallel to an edge of the TFT glass substrate <b>100</b>, along which the terminal portion <b>140</b> is formed, so that the wiring loads are made equal to each other and the circuit efficiencies of the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are balanced.

An operation of the liquid crystal display device and an influence of the reduction in the circuit efficiency due to the wiring loads on the operation are described hereafter referring to <figref idrefs="DRAWINGS">FIG. 3</figref>. Now, when the input power supply electric potential VDD is 4.5 V and the circuit efficiency is assumed to be 100%, there is derived that VPP is 9.0 V and VBB is −4.5 V. In reality, however, VPP is about 8.5 V and VBB is about −4.2 V, for example, because there are voltage loss in the transistors in the circuit and voltage loss due to the wiring loads as described above. VPP makes the H level of the gate signal and VBB makes the L level of the gate signal.

The H level of the common electrode signal VCOM is 3.9 V and the L level of the common electrode signal VCOM is −0.1 V. A polarity of the video signal Vsig against the common electrode signal VCOM is inverted once every horizontal period. An H level of the video signal Vsig is set at 4.1 V and an L level of the video signal Vsig is set at 0.1 V. Because of a voltage drop due to a resistance of the horizontal switch HSW, the H level is reduced to 3.9 V and the L level is reduced to −0.1 V after passing through the horizontal switch HSW. The pixel transistors GT are of N-channel type in the explanation below.

When the video signal Vsig is to be written into a pixel in a certain row in the pixel portion <b>105</b> during a certain horizontal period, the gate signal corresponding to the row is set at the H level. Then, the pixel transistors GT in the row are turned on and the video signal Vsig is written into each of the pixels through the pixel transistor GT and retained in the pixel electrode <b>121</b>.

In a subsequent horizontal period, the gate signal of the row turns to the L level and the pixel transistors GT are turned off. At that time, in the case where the common electrode signal VCOM changes from the L level to the H level, an electric potential of the pixel electrode <b>121</b> is changed by +4.0 V toward positive direction by the capacitive coupling, and in the case where the common electrode signal VCOM changes from the H level to the L level, the electric potential of the pixel electrode <b>121</b> is changed by −4.0 V by the capacitive coupling.

When VDD is reduced by increased loads of the wirings to provide the input power supply electric potential VDD and the drive clock, the output electric potential VPP from the positive power supply generation circuit <b>131</b> is reduced and the H level of the gate signal is also reduced accordingly. As a result, a voltage margin of the video signal Vsig in the programming operation is reduced. In the example shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, there is a margin comparatively large enough to turn on the pixel transistor GT, since VPP is 8.5 V and the highest electric potential of the video signal Vsig is 4.1 V (3.9 V after passing through the horizontal switch HSW). When the wiring loads are increased, however, VPP is further reduced to reduce the margin and the programming operation may end up in a malfunction.

Also, when the output electric potential VBB from the negative power supply generation circuit <b>132</b> is raised by the same reason, the L level of the gate signal is raised accordingly and the pixel transistor GT is not sufficiently turned off to prevent the leakage through the pixel transistor GT. When such a pixel leakage occurs, there are caused problems such that a correct picture is not displayed because the level of the video signal Vsig written into the pixel is changed.

In the example shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, when the electric potential of the pixel <b>121</b> is changed toward negative direction by the capacitive coupling after the video signal Vsig has been written in, the lowest electric potential of the pixel electrode <b>121</b> becomes −4.1 V which leaves only a small margin of −0.1 V against VBB=−4.2 V. That is, VBB has only a small margin against VPP. It is especially important for prevention of the pixel leakage that the negative power supply generation circuit <b>132</b> is placed close to the terminal portion <b>140</b> to minimize the wiring load.

Next, an example of concrete circuit structures of the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are described. <figref idrefs="DRAWINGS">FIG. 4</figref> is a circuit diagram showing the positive power supply generation circuit <b>131</b>. A clock generation circuit <b>10</b> in the positive power supply generation circuit <b>131</b> is a buffer circuit composed of a plurality of inverters, and generates based on an input clock CLK (drive clock) a clock CPCLK<b>1</b> having amplitude of VDD (H level=VDD and L level=VSS=0 V) and a reverse clock XCPCLK<b>1</b> that is an inversion of the clock CPCLK<b>1</b>. The horizontal transfer clock CKH, the vertical transfer clock CKV, the common electrode signal VCOM or the like can be used as the input clock CLK. The clock CPCLK<b>1</b> is applied to a first terminal of a flying capacitor C<b>1</b> while the reverse clock XPCLK<b>1</b> is applied to a first terminal of a flying capacitor C<b>2</b>. The buffer circuit such as the clock generation circuit <b>10</b> in the positive power supply generation circuit <b>131</b> is not necessarily required when the input clock CLK (drive clock) is directly inputted from an external IC through the terminal portion <b>140</b>.

An N-channel type charge transfer transistor MN<b>1</b> and a P-channel type charge transfer transistor MP<b>1</b> are connected in series and a connecting node between them is connected with a second terminal of the flying capacitor C<b>1</b>. A gate of the N-channel type charge transfer transistor MN<b>1</b> and a gate of the P-channel type charge transfer transistor MP<b>1</b> are connected with a second terminal of the flying capacitor C<b>2</b>.

An N-channel type charge transfer transistor MN<b>2</b> and a P-channel type charge transfer transistor MP<b>2</b> are connected in series and a connecting node between them is connected with the second terminal of the flying capacitor C<b>2</b>. A gate of the N-channel type charge transfer transistor MN<b>2</b> and a gate of the P-channel type charge transfer transistor MP<b>2</b> are connected with the second terminal of the flying capacitor C<b>1</b>. The flying capacitor C<b>1</b> is connected between external connection terminals P<b>1</b> and P<b>2</b> and placed outside the TFT glass substrate <b>100</b>. (hereafter referred to as an external capacitor) The flying capacitor C<b>2</b> is an external capacitor connected between external connection terminals P<b>3</b> and P<b>4</b>.

The positive input power supply electric potential VDD is applied as an input electric potential to a common source of the N-channel type charge transfer transistors MN<b>1</b> and MN<b>2</b>. Assuming that the circuit efficiency is 100%, a positive electric potential of 2VDD is outputted as the output electric potential VPP as well as an output current Ivpp from a common drain (output terminal) of the P-channel type charge transfer transistors MP<b>1</b> and MP<b>2</b> by charge transfer operation in a steady state. A smoothing capacitor C<b>3</b> is another external capacitor, and is connected with an external connection terminal P<b>5</b> that is an output terminal of the positive power supply generation circuit <b>131</b>.

The external connection terminals P<b>1</b>-P<b>5</b> are placed in the terminal portion <b>140</b>. In addition, an external connection terminal P<b>6</b> to apply the input power supply electric potential VDD from outside and an external connection terminal P<b>7</b> to apply the input clock CLK from outside are placed in the terminal portion <b>140</b>. A power supply wiring <b>133</b> to supply the input power supply electric potential VDD connects between the external connection terminal P<b>6</b> and the common source of the N-channel type charge transfer transistors MN<b>1</b> and MN<b>2</b>. A drive clock wiring <b>134</b> to supply the input clock CLK connects between the external connection terminal P<b>7</b> and the clock generation circuit <b>10</b> in the positive power supply generation circuit <b>131</b>. According to the layout described above, wiring lengths of the power supply wiring <b>133</b> and the drive clock wiring <b>134</b> are minimized to minimize the wiring loads.

An operation of the positive power supply generation circuit <b>131</b> in a steady state of VPP=2VDD is described hereafter, referring to a waveform chart shown in <figref idrefs="DRAWINGS">FIG. 5</figref>. When the clock CPCLK<b>1</b> is at an H level (VDD), the reverse clock XCPCLK<b>1</b> is at an L level (VSS), MN<b>1</b> and MP<b>2</b> are turned off, MN<b>2</b> and MP<b>1</b> are turned on and an electric potential V<b>1</b> at the connecting node between MN<b>1</b> and MP<b>1</b> is boosted by the capacitive coupling to 2VDD that is outputted through MP<b>1</b>. Meantime, an electric potential V<b>2</b> at the connecting node between MN<b>2</b> and MP<b>2</b> is charged to VDD.

Next, when the clock CPCLK<b>1</b> turns to the L level (VSS), MN<b>1</b> and MP<b>2</b> are turned on, MN<b>2</b> and MP<b>1</b> are turned off, and the electric potential V<b>2</b> is boosted by capacitive coupling through the flying capacitor C<b>2</b> to 2VDD that is outputted through MP<b>2</b>. Meantime, the electric potential V<b>1</b> is charge to VDD. That is, the electric potential 2VDD is outputted alternately from left and right serially connected transistor circuits in the positive power supply generation circuit <b>131</b>. Note that this is for the case where the circuit efficiency is 100%.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a circuit diagram showing the negative power supply generation circuit <b>132</b>. A clock generation circuit <b>20</b> in the negative power supply generation circuit <b>132</b> generates based on the input clock CLK a clock CPCLK<b>2</b> having amplitude of VDD and a reverse clock XCPCLK<b>2</b> that is an inversion of the clock CPCLK<b>2</b>. The clock generation circuit <b>20</b> does not need to be provided separately, and the clock generation circuit <b>10</b> may be shared by both the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>131</b>.

An N-channel type charge transfer transistor MN<b>11</b> and a P-channel type charge transfer transistor MP<b>11</b> are connected in series and a connecting node between them is connected with a second terminal of a flying capacitor C<b>11</b>. A gate of the N-channel type charge transfer transistor MN<b>11</b> and a gate of the P-channel type charge transfer transistor MP<b>11</b> are connected with a second terminal of a flying capacitor C<b>12</b>.

An N-channel type charge transfer transistor MN<b>12</b> and a P-channel type charge transfer transistor MP<b>12</b> are connected in series and a connecting node between them is connected with the second terminal of the flying capacitor C<b>12</b>. A gate of the N-channel type charge transfer transistor MN<b>12</b> and a gate of the P-channel type charge transfer transistor MP<b>12</b> are connected with the second terminal of the flying capacitor C<b>11</b>. The flying capacitor C<b>11</b> is an external capacitor connected between external connection terminals P<b>11</b> and P<b>12</b>. The flying capacitor C<b>12</b> is an external capacitor connected between external connection terminals P<b>13</b> and P<b>14</b>.

The ground electric potential VSS is applied to a common source of the P-channel type charge transfer transistors MP<b>11</b> and MP<b>12</b> as an input electric potential. When electric potential loss in the transistor is neglected, a negative electric potential of −VDD is outputted as the output electric potential VBB as well as an output current Ivbb from a common drain (output terminal) of the N-channel type charge transfer transistors MN<b>11</b> and MN<b>12</b> in a steady state. A smoothing capacitor C<b>13</b> is another external capacitor, and is connected with an external connection terminal P<b>15</b> that is the output terminal of the negative power supply generation circuit <b>132</b>.

The external connection terminals P<b>11</b>-P<b>15</b> are placed in the terminal portion <b>140</b>. In addition, an external connection terminal P<b>16</b> to apply the input power supply electric potential VSS from outside and an external connection terminal P<b>17</b> to apply the input clock CLK from outside are placed in the terminal portion <b>140</b>. The external connection terminal P<b>7</b> for the positive power supply generation circuit <b>131</b> may be shared by the negative power supply generation circuit <b>132</b> to replace the external connection terminal P<b>17</b>.

A power supply wiring <b>135</b> to supply the input power supply electric potential VSS connects between the external connection terminal P<b>16</b> and the common source of the P-channel type charge transfer transistors MP<b>11</b> and MP<b>12</b>. A drive clock wiring <b>136</b> to supply the input clock CLK connects between the external connection terminal P<b>17</b> and the clock generation circuit <b>20</b> in the negative power supply generation circuit <b>132</b>. According to the layout described above, wiring lengths of the power supply wiring <b>135</b> and the drive clock wiring <b>136</b> are minimized to minimize the wiring loads.

An operation of the negative power supply generation circuit <b>132</b> in a steady state of VBB=−VDD is described hereafter, referring to <figref idrefs="DRAWINGS">FIG. 7</figref>. When the clock CPCLK<b>2</b> is at the H level (VDD), the reverse clock XCPCLK<b>2</b> is at the L level (VSS), MN<b>11</b> and MP<b>12</b> are turned off, MN<b>12</b> and MP<b>11</b> are turned on, an electric potential V<b>3</b> at the connecting node between MN<b>11</b> and MP<b>11</b> is charged to VSS and an electric potential V<b>4</b> at the connecting node between MN<b>12</b> and MP<b>12</b> is lowered by the capacitive coupling through the flying capacitor C<b>12</b> to −VDD that is outputted through MN<b>12</b>.

When the clock CPCLK<b>2</b> turns to the L level (VSS), MN<b>11</b> and MP<b>12</b> are turned on, MN<b>12</b> and MP<b>11</b> are turned off, and the electric potential V<b>3</b> is lowered by capacitive coupling through the flying capacitor C<b>11</b> to −VDD that is outputted through MN<b>11</b>. Meantime, the electric potential V<b>4</b> is charge to Vss. That is, the electric potential −VDD is outputted alternately from left and right serially connected transistor circuits in the negative power supply generation circuit <b>132</b>. Note that this is for the case where the circuit efficiency is 100%.

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a layout (plan view) of a liquid crystal display device according to a second embodiment of this invention. The layout according to the second embodiment is effective in the case where it is difficult to place the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> closer to the terminal portion <b>140</b> than other circuits as in the liquid crystal display device according to the first embodiment. That is, when the shift register SR in the horizontal drive circuit <b>110</b> is mounted as an LSI chip on the TFT glass substrate <b>100</b>, i.e. as a COG (Chip on Glass), there is a case in which the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>32</b> can not be placed as close to the terminal portion <b>140</b> as in the liquid crystal display device according to the first embodiment because the frame area is increased accordingly.

Thus, the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are arrayed next to each other in a direction (Y direction) of an edge of the TFT glass substrate <b>100</b>, on which the terminal portion <b>140</b> is placed, and placed along an edge that is perpendicular to the edge of the TFT glass substrate <b>100</b>, on which the terminal portion <b>140</b> is placed, as shown in <figref idrefs="DRAWINGS">FIG. 8</figref>. Although the positive power supply generation circuit <b>131</b> is placed on the edge portion of the TFT glass substrate <b>100</b> and the negative power supply generation circuit <b>132</b> is placed between the positive power supply generation circuit <b>131</b> and the pixel portion <b>105</b> in <figref idrefs="DRAWINGS">FIG. 8</figref>, the negative power supply generation circuit <b>132</b> may be placed on the edge portion of the TFT glass substrate <b>100</b> and the positive power supply generation circuit <b>131</b> may be placed between the negative power supply generation circuit <b>132</b> and the pixel portion <b>105</b>. With the layout described above, the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are placed at substantially the same distance from the terminal portion <b>140</b>. As a result, the reduction in the circuit efficiency of either the positive power supply generation circuit <b>131</b> or the negative power supply generation circuit <b>132</b> due to the unbalanced wiring loads can be prevented.

Third Embodiment

<figref idrefs="DRAWINGS">FIG. 9</figref> shows a layout (plan view) of a liquid crystal display device according to a third embodiment of this invention. In this embodiment, the positive power supply generation circuit <b>131</b> and the negative power supply generation circuit <b>132</b> are placed side by side along the edge perpendicular to the edge of the TFT glass substrate <b>100</b>, on which the terminal portion <b>140</b> is placed, i.e. along X direction in <figref idrefs="DRAWINGS">FIG. 9</figref>, and the negative power supply generation circuit <b>132</b> is placed closer to the terminal portion <b>140</b> than the positive power supply generation circuit <b>131</b>. The layout described above is effective in the case where a left portion of the frame area in <figref idrefs="DRAWINGS">FIG. 9</figref> is too narrow to apply the layout as described in the second embodiment.

As described in the first embodiment, the pixel leakage would be caused when the output electric potential VBB generated by the negative power supply generation circuit <b>132</b> rises. And there is only a small margin against the rise in VBB. On the other hand, although insufficient programming of the video signal Vsig into the pixel would occur when the output electric potential VPP generated by the positive power supply generation circuit <b>131</b> falls, the margin against the fall in VPP is relatively large.

In the third embodiment of this invention, noting a difference between the margin regarding the positive power supply generation circuit <b>131</b> and the margin regarding the negative power supply generation circuit <b>132</b>, the negative power supply generation circuit <b>132</b> that has less margin is placed closer to the terminal portion <b>140</b> than the positive power supply generation circuit <b>131</b> to prevent the problem due to the reduction in the circuit efficiency.

[Electronic Equipment]

The liquid crystal display device according to each of the embodiments described above is used as a display device mounted on electronic equipment. The electronic equipment means a monitor, a TV, a note PC, a PDA (Personal Digital Assistant), a digital still camera, a camcorder, a mobile telephone, a mobile photo viewer, a mobile video player, a mobile DVD player, a mobile audio player or the like.

The liquid crystal display devices are taken up as examples and explained in the embodiments described above. However, this invention is not limited to the above and is applicable to display devices other than the liquid crystal display devices such as an LED (Light Emitting Diode), an EL (Electro-Luminescence), a VFD (Vacuum Fluorescent Display) and a PDP (Plasma Display Panel), for example, since this invention is related to placement of the power supply circuit.

With the display device and the electronic equipment according to the embodiments of this invention, the reduction in the efficiency of the power supply circuit is prevented so that the increase in the power consumption, the malfunction of the display device and the like can be prevented.