US8895992B2

High electron mobility transistor and method of forming the same

Summary by NHIP

High electron mobility transistor

The semiconductor structure includes a carrier channel between two distinct III-V compound layers with embedded fluorine. A gate dielectric layer covers a third III-V compound layer and contains a fluorine segment on the embedded fluorine region.

Claim Score by NHIP

Read claim 10, the broadest

Abstract

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

US8895992B2, drawing sheet 1 — Sheet 1 of 6

Term

6.4 yearsleft in the term

Expires 22 February 2033.

19 claims: 3 independent, 16 dependent

1
A semiconductor structure comprising:a first III-V compound layer;a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;a source feature and a drain feature disposed on the second III-V compound layer;a gate electrode disposed over the second III-V compound layer between the source feature and the drain feature, wherein a fluorine region is embedded in the second III-V compound layer under the gate electrode;a third III-V compound layer disposed over the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer;and a gate dielectric layer disposed over portions of the second III-V compound layer and over an entire top surface of the third III-V compound layer.
10
Broadest claimClaim Score 57, average(NHIP)A semiconductor structure comprising:a gallium nitride (GaN) layer disposed on a substrate;an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer, wherein a fluorine region is embedded in the AlGaN layer;an indium gallium nitride (InGaN) layer disposed on the AlGaN layer;a P-type GaN layer disposed on the InGaN layer;a source feature and a drain feature spaced apart and disposed on the AlGaN layer;a gate electrode disposed over the AlGaN layer between the source feature and the drain feature, wherein the gate electrode is overlying the fluorine region;and a portion of a gate dielectric layer disposed between the gate electrode and the AlGaN layer, wherein the portion of the gate dielectric layer substantially covers the P-type GaN layer.
18
A method of forming a semiconductor structure, the method comprising:epitaxially growing a second III-V compound layer on a first III-V compound layer, the second III-V compound layer being a different composition than the first III-V compound layer, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer;forming a source feature and a drain feature on the second III-V compound layer;forming a third III-V compound layer on the second III-V compound layer, wherein a diffusion barrier layer is located between the second III-V compound layer and the third III-V compound layer;depositing a gate dielectric layer on a portion of the second III-V compound layer and an entire top surface of the third III-V compound layer;treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a fluorine in the second III-V compound layer under the gate electrode;and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

Independent claims3

44 paragraphs in 4 sections, as filed

TECHNICAL FIELD

0001This disclosure relates generally to a semiconductor structure and, more particularly, to a high electron mobility transistor (HEMT) and method for forming a high electron mobility transistor.

BACKGROUND

0002In semiconductor technology, due to their characteristics, Group III-Group V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of a doped region, as is generally the case for metal oxide semiconductor field effect transistors (MOSFETs). In contrast with MOSFETs, HEMTs have a number of attractive properties including high electron mobility, the ability to transmit signals at high frequencies, etc.

0003From an application point of view, enhancement-mode (E-mode) HEMTs have many advantages. E-mode HEMTs allow elimination of negative-polarity voltage supply, and, therefore, reduction of the circuit complexity and cost. Despite the attractive properties noted above, a number of challenges exist in connection with developing III-V semiconductor compound-based devices. Various techniques directed at configurations and materials of these III-V semiconductor compounds have been implemented to try and further improve transistor device performance.

0004Frequently, layers of a semiconductor are doped in the manufacturing process. Magnesium (Mg) is a common dopant for a P-type gallium nitride (p-GaN). Mg always diffuses into active layers and impacts performance, specifically in the 2-dimensional electron gas (2 DEG) and current density of HEMT devices.

BRIEF DESCRIPTION OF THE DRAWINGS

0005Aspects of the present disclosure may be understood from the following detailed description and the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

0006<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of a semiconductor structure having a high electron mobility transistor (HEMT) according to one or more embodiments of this disclosure.

0007<figref idref="DRAWINGS">FIG. 2</figref> is a flowchart of a method of forming a semiconductor structure having a HEMT according to one or more embodiments of this disclosure.

0008<figref idref="DRAWINGS">FIGS. 3 to 7</figref> are cross-sectional views of a semiconductor structure having a HEMT at various stages of manufacture according to one embodiment of the method of <figref idref="DRAWINGS">FIG. 2</figref>.

DETAILED DESCRIPTION

0009The making and using of illustrative embodiments are discussed in detail below. It should be appreciated, however, that the disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

0010A plurality of semiconductor chip regions is marked on the substrate by scribe lines between the chip regions. The substrate will go through a variety of cleaning, layering, patterning, etching and doping steps to form integrated circuits. The term “substrate” herein generally refers to the bulk substrate on which various layers and device structures are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor, such as GaAs, InP, Si/Ge, or SiC. Examples of such layers include dielectric layers, doped layers, polysilicon layers, diffusion barrier layers, or conductive layers. Examples of device structures include transistors, resistors, and/or capacitors, which may be interconnected through an interconnect layer to additional integrated circuits.

0011<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view of a semiconductor structure 100 having a high electron mobility transistor (HEMT) and an InGaN diffusion barrier layer 130 according to one or more embodiments of this disclosure.

0012Referring to <figref idref="DRAWINGS">FIG. 1</figref>, the semiconductor structure 100 having a HEMT is illustrated. The semiconductor structure 100 includes a substrate 102. In some embodiments, the substrate 102 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate.

0013The semiconductor structure 100 also includes a heterojunction formed between two different semiconductor material layers, such as material layers with different band gaps. For example, the semiconductor structure 100 includes a non-doped narrow-band gap channel layer and a wide-band gap n-type donor-supply layer. In at least one embodiment, the semiconductor structure 100 includes a first III-V compound layer (or referred to as a channel layer) 104 formed on the substrate 102 and a second III-V compound layer (or referred to as a donor-supply layer) 106 formed on the channel layer 104. The channel layer 104 and the donor-supply layer 106 are compounds made from the III-V groups in the periodic table of elements. However, the channel layer 104 and the donor-supply layer 106 are different from each other in composition. The channel layer 104 is undoped or unintentionally doped (UID). In the present example of the semiconductor structure 100, the channel layer 104 includes a gallium nitride (GaN) layer (also referred to as the GaN layer 104). The donor-supply layer 106 includes an aluminum gallium nitride (AlGaN) layer (also referred to as AlGaN layer 106). The GaN layer 104 and AlGaN layer 106 directly contact each other. In another example, the channel layer 104 includes a GaAs layer or InP layer. The donor-supply layer 106 includes an AlGaAs layer or an AlInP layer.

0014The GaN layer 104 is undoped. Alternatively, the GaN layer 104 is unintentionally doped, such as lightly doped with n-type dopants due to a precursor used to form the GaN layer 104. In one example, the GaN layer 104 has a thickness in a range from about 0.5 microns to about 10 microns.

0015The AlGaN layer 106 is unintentionally doped. In one example, the AlGaN layer 106 has a thickness in a range from about 5 nanometers (nm) to about 50 nm.

0016The InGaN diffusion barrier layer 130 may prevent the degradation of the HEMT device. The direction of the polarization-induced field formed in the InGaN is opposite to that in AlGaN thereby lifting the conduction band in the InGaN capped HEMTS. This design may decrease the 2 DEG channel density and may create a positive Vth when compared to conventional AlGaN/GaN HEMTs.

0017The band gap discontinuity exists between the AlGaN layer 106 and the GaN layer 104. The electrons from a piezoelectric effect in the AlGaN layer 106 drop into the GaN layer 104, creating a very thin layer 108 of highly mobile conducting electrons in the GaN layer 104. This thin layer 108 is referred to as a two-dimensional electron gas (2-DEG), forming a carrier channel (also referred to as the carrier channel 108). The thin layer 108 of 2-DEG is located at an interface of the AlGaN layer 106 and the GaN layer 104. Thus, the carrier channel has high electron mobility because the GaN layer 104 is undoped or unintentionally doped, and the electrons can move freely without collision or with substantially reduced collisions with impurities.

0018The semiconductor structure 100 may also include an InGaN diffusion barrier layer 130 disposed between an AlGaN layer and a p-GaN layer. The InGaN diffusion barrier layer 130 may prevent diffusion into the HEMT active layer because the diffusion coefficient of Mg in InGaN is lower than in AlGaN. In one example, the InGaN diffusion barrier layer 130 has a thickness in a range from about 3 nm to about 15 nm.

0019The semiconductor structure 100 also includes a source feature and a drain feature disposed on the AlGaN layer 106 and configured to electrically connect to the carrier channel 108. Each of the source feature and the drain feature comprises a metal feature 112. In one example, the metal feature 112 is free of Au and comprises Al, Ti, or Cu.

0020The semiconductor structure 100 further includes a dielectric cap layer 110 disposed on a top surface of the AlGaN layer 106 not occupied by the metal features 112. The dielectric cap layer 110 further includes an opening that exposes a portion of the AlGaN layer 106 for a gate electrode formation, and a P-type GaN structure 123. The width of the opening in the dielectric cap layer 110 is greater than the width of the P-type GaN structure 123. The dielectric cap layer 110 protects the underlying AlGaN layer 106 from damage in the following process having plasma.

0021The semiconductor structure 100 further includes isolation regions 114 in the first III-V compound layer 104 and the second III-V compound layer 106. The isolation regions 114 isolate the HEMT in the structure 100 from other devices in the substrate 102. In one example, the isolation region 114 includes a doped region with species of oxygen or nitrogen.

0022The semiconductor structure 100 further includes a gate dielectric layer 119 deposited on the dielectric cap layer 110 and top surfaces of the source feature and the drain feature. The gate dielectric layer 119 is also disposed along an interior surface of the opening and on the exposed portion of the AlGaN layer 106. In one example, the gate dielectric layer 119 has a thickness in a range from about 3 nm to about 20 nm. In some examples, the gate dielectric layer 119 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide.

0023In some embodiments, the semiconductor structure 100 further includes a protection layer (not shown). The protection layer is disposed on top surfaces of the metal features 112 and under the gate dielectric layer 119. The protection layer further includes an opening that aligns with the opening in the dielectric cap layer 110. The combined opening of the opening in the protection layer and the opening in the dielectric cap layer 110 exposes the portion of the AlGaN layer 106 and a P-type GaN structure 123 for the gate electrode formation. The protection layer also covers the source feature and the drain feature, and prevents the source feature and the drain feature from exposure during an annealing process in the formation of the isolation regions 116.

0024The semiconductor structure 100 also includes a gate electrode 128 disposed on the opening over AlGaN layer 106 between the source and drain features. The gate electrode 128 includes a conductive material layer configured for voltage bias and electrical coupling with the carrier channel 108. In various examples, the conductive material layer includes a refractory metal or its compounds, e.g., titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW) and tungsten (W). In another example, the conductive material layer includes nickel (Ni), gold (Au) or copper (Cu).

0025The semiconductor structure 100 also includes a depletion region 126 in the carrier channel 108 under the opening in the dielectric cap layer 110. The carrier channel 108 becomes normally-off because of the depletion region 126. A positive gate voltage should be applied to turn on the carrier channel 108 of this HEMT. This HMET is also called an enhanced-mode HEMT that is opposite to a depletion-mode HEMT. The depletion-mode HEMT has a normally-on carrier channel and a negative gate voltage should be applied to turn off the carrier channel.

0026In the above described embodiments, the gate electrode 128, the source/drain features, and the carrier channel 108 in the GaN layer 104 are configured as a transistor. When a voltage is applied to the gate stack, a device current of the transistor could be modulated.

0027<figref idref="DRAWINGS">FIG. 2</figref> is a flowchart of a method 200 of forming a semiconductor structure having a HEMT according to one or more embodiments of this disclosure. Referring now to <figref idref="DRAWINGS">FIG. 2</figref>, the flowchart of the method 200, at operation 201, a first III-V compound layer is provided. The first III-V compound layer is formed on a substrate. Next, the method 200 continues with operation 202 in which a second III-V compound layer is epitaxially grown on the first III-V compound layer. The method 200 continues with operation 203 in which a source feature and a drain feature are formed on the second III-V compound layer. The method 200 continues with operation 204 in which a gate dielectric layer is deposited on a portion of the second III-V compound layer. The method 200 continues with operation 206 in which a gate electrode is formed on the treated gate dielectric layer between the source feature and the drain feature. It should be noted that additional processes may be provided before, during, or after the method 200 of <figref idref="DRAWINGS">FIG. 2</figref>.

0028<figref idref="DRAWINGS">FIGS. 3 to 7</figref> are cross-sectional views of the semiconductor structure 100 having a HEMT at various stages of manufacture according to various embodiments of the method 200 of <figref idref="DRAWINGS">FIG. 2</figref>. Various figures have been simplified for a better understanding of the inventive concepts of the present disclosure.

0029Referring to <figref idref="DRAWINGS">FIG. 3</figref>, which is an enlarged cross-sectional view of a portion of a substrate 102 of a semiconductor structure 100 after performing operations 201, 202 and 203. In some embodiments, the substrate 102 includes a silicon carbide (SiC) substrate, sapphire substrate or a silicon substrate. A first III-V compound layer 104, also referred to as a channel layer, is grown on the substrate 102. In the embodiment of <figref idref="DRAWINGS">FIGS. 2-7</figref> the first III-V compound layer 104 refers to a gallium nitride (GaN) layer (also referred to as the GaN layer 104). The GaN layer 104 can be epitaxially grown by metal organic vapor phase epitaxy (MOVPE) using gallium-containing precursor and nitrogen-containing precursor. The gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical. The nitrogen-containing precursor includes ammonia (NH3), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemical. In the embodiment of <figref idref="DRAWINGS">FIGS. 2-7</figref>, the GaN layer 104 has a thickness in a range from about 0.5 micron to about 10 microns. In other embodiments, the first III-V compound layer 104 may include a GaAs layer or InP layer.

0030A second III-V compound layer 106, also referred to as donor-supply layer, is grown on first III-V compound layer 104. An interface is defined between the first III-V compound layer 104 and the second III-V compound layer 106. A carrier channel 108 of 2-DEG is located at the interface. In at least one embodiment, the second III-V compound layer 106 refers to an aluminum gallium nitride (AlGaN) layer (also referred to as the AlGaN layer 106). In the embodiment of <figref idref="DRAWINGS">FIGS. 2-7</figref>, the AlGaN layer 106 is epitaxially grown on the GaN layer 104 by MOVPE using aluminum-containing precursor, gallium-containing precursor, and nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), triethylaluminium (TEA), or other suitable chemical. The gallium-containing precursor includes TMG, TEG, or other suitable chemical. The nitrogen-containing precursor includes ammonia, TBAm, phenyl hydrazine, or other suitable chemical. In the embodiment of <figref idref="DRAWINGS">FIGS. 2-7</figref>, the AlGaN layer 106 has a thickness in a range from about 5 nanometers to about 50 nanometers. In other embodiments, the second III-V compound layer 106 may include an AlGaAs layer, or AlInP layer.

0031Further, the second III-V compound layer 106 may include an InGaN diffusion barrier layer 130. The InGaN diffusion barrier layer 130 may be grown at a range of about 300 mbar to about 500 mbar and in a range of about 700° C. to about 900° C. The Indium composition of the InGaN diffusion barrier layer 130 may be in a range from about 5% to about 10%.

0032Thereafter, a P-type GaN layer is disposed onto the second III-V compound layer 106. A patterned mask layer (i.e., a photoresistive layer not shown) is formed on the top surface of the P-type GaN layer and an etching process is performed to remove a portion of the P-type GaN layer. As a result of this lithographic process, a P-type GaN structure 123 is formed.

0033Next, a dielectric cap layer 110 is deposited on a top surface 107 of the second III-V compound layer 106 and over the top surface of the P-type GaN structure 123. Therefore, the P-type GaN structure 123 is effectively embedded in the dielectric cap layer 110. In the embodiment of <figref idref="DRAWINGS">FIGS. 2-7</figref>, the dielectric cap layer 110 has a thickness in a range from about 100 Å to about 5000 Å. In some embodiments, the dielectric cap layer 110 includes SiO2 or Si3N4. In one example, the dielectric cap layer 110 is Si3N4 and is formed by performing a low pressure chemical vapor deposition (LPCVD) method without plasma using SiH4 and NH3 gases. An operation temperature is in a range of from about 650° C. to about 800° C. An operation pressure is in a range of about 0.1 Torr and about 1 Torr. The dielectric cap layer 110 protects the underlying second III-V compound layer 106 from damage in the following processes having plasma. Next, two openings in the dielectric cap layer 110 are defined by lithography and etching processes to expose a portion of the second III-V compound layer 106.

0034A metal layer is deposited over the dielectric cap layer 110, overfills the openings and contacts the second III-V compound layer 106. A photoresist layer (not shown) is formed over the metal layer and developed to form a feature over the openings. The metal layer not covered by the feature of the photoresist layer is removed by a reactive ion etch (RIE) process that etches the exposed portions of the metal layer down to the underlying the dielectric cap layer 110. Metal features 112 are generated after the etching process. The metal features 112 are configured as the source feature or the drain feature for the HEMT. The photoresist layer is removed after the formation of the metal features 112. The dielectric cap layer 110 protects the underlying second III-V compound layer 106 from damage during the etching process to form metal features 112. The carriers in carrier channel 108 of 2-DEG underlying the second III-V compound layer 106 would not be affected during the etching process. The electrical performances of the semiconductor structure 100 would be positively affected. Therefore, the yield of the overall assembly could increase.

0035In some embodiments, the metal layer of the metal features 112 includes one or more conductive materials. In at least one example, the metal layer is free of gold (Au) and comprises titanium (Ti), titanium nitride (TiN), or aluminum copper (AlCu) alloy. In another example, the metal layer includes a bottom Ti/TiN layer, an AlCu layer overlying the bottom Ti/TiN layer, and a top Ti layer overlying the AlCu layer. The formation methods of the metal layer include atomic layer deposition (ALD) or physical vapor deposition (PVD) processes. Without using Au in the metal features 112, the method 200 could also be implemented in the production line of integrated circuits on silicon substrate. The contamination concern from Au on the silicon fabrication process could be eliminated.

0036Next, a protection layer (not shown) is optionally deposited on top surfaces of the metal features 112 and the dielectric cap layer 110. In some embodiments, the protection layer includes dielectric materials such as SiO2 or Si3N4. In one example, the protection layer is Si3N4 and is formed by performing a plasma enhanced chemical vapor deposition (PECVD) method.

0037<figref idref="DRAWINGS">FIG. 4</figref> illustrates the structure 100 after forming isolation regions 114 in the first III-V compound layer 104 and the second III-V compound layer 106. The isolation regions 114 isolate the HEMT in the structure 100 from other devices in the substrate 102. In one example, the isolation region 114 is formed by an implantation process with species of oxygen or nitrogen. The protection layer covers the source feature and the drain feature, and prevents the source feature and the drain feature from exposure during an annealing process after the implantation process for the isolation region 114 formation.

0038<figref idref="DRAWINGS">FIG. 5</figref> illustrates the structure 100 after forming an opening 116 in the dielectric cap layer 110 (also in the protection layer if the protection layer exists). A patterned mask layer (not shown) is formed on a top surface of the dielectric cap layer 110 and an etching process is performed to remove a portion of the dielectric cap layer 110 (also remove a portion of the protection layer if the protection layer exists). The opening 116 exposes a portion of the top surface 107 of the second III-V compound layer 106, and exposes the top surface of P-type GaN structure 123. In particular, the width of the opening 116 is greater than the width of the P-type GaN structure 123, so that some portion of the second III-V compound layer 106 is exposed on either side of the P-type GaN structure 123. The opening 116 is configured as a location for the later gate electrode formation.

0039<figref idref="DRAWINGS">FIG. 6</figref> illustrates the structure 100 after depositing a gate dielectric layer 118 in operation 204. The gate dielectric layer 118 is deposited on the dielectric cap layer 110, along an interior surface of the opening 116 and on the exposed portion of the second III-V compound layer 106, and the top surface of the P-type GaN structure 122. The gate dielectric layer 118 is also deposited over the source feature and the drain feature. In some embodiments, the gate dielectric layer 118 is in a thickness range from about 3 nm to about 20 nm. In some examples, the gate dielectric layer 118 comprises silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In one embodiment, the gate dielectric layer 118 is formed by an atomic layer deposition (ALD) method. The ALD method is based on the sequential use of a gas phase chemical process. The majority of ALD reactions use two chemicals, typically called precursors. These precursors react with a surface one-at-a-time in a sequential manner. By exposing the precursors to the growth surface repeatedly, the gate dielectric layer 118 is deposited. The ALD method provides an uniform thickness of the gate dielectric layer 118 with high quality. In one example, the gate dielectric layer 118 is zirconium oxide. In some embodiments, a first precursor includes tetrakis[ethylmethylamino]zirconium (TEMAZr) or zirconium chloride (ZrCl4). In some embodiments, a second precursor includes oxygen in order to oxidize the first precursor material to form a monolayer. In some examples, the second precursor includes ozone (O3), oxygen, water (H2O), N2O or H2O—H2O2. In other embodiments, the gate dielectric layer 118 is formed by a plasma enhanced chemical vapor deposition (PECVD) or a low pressure chemical vapor deposition (LPCVD).

0040Various embodiments of the present disclosure may be used to improve the performance of a semiconductor structure having a high electron mobility transistor (HEMT). For example, in conventional methods, a portion of the second III-V compound layer 106 is etched to form a recess for an enhanced-mode HEMT. During etching the recess, the etching uniformity among the semiconductor chip regions on the same substrate 102 is hard to control. The electrical performances of each HEMT in the same semiconductor chip region or the same substrate 102 could not be accurately controlled. In this disclosure, the fluorine region 124 depletes the electrons in the carrier channel 108 for an enhanced-mode HEMT. The fluorine region 124 in the opening 116 eliminates the drawbacks in conventional methods. The fluorine-treated gate dielectric layer 119 also improves stability of the threshold voltage (Vt) of the HEMT in the structure 100. The metal feature 112 is free of Au and comprises Al, Ti or Cu. Without using Au in the metal feature 112, the method 200 can be implemented in the production line of integrated circuits on silicon substrate, because the contamination concern from Au on the silicon-Fab process is eliminated. Compared with the HEMT with Au in source/drain feature, the cost for manufacturing the HEMT according to the present application is reduced. Both the III-V semiconductor compounds process and the silicon-fabrication process can be implemented in the same production line. It increases the flexibility to allocate different products for the production line.

0041One aspect of the disclosure describes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

0042A further aspect of the disclosure describes a semiconductor structure. The semiconductor structure includes a GaN layer disposed on a substrate. An AlGaN layer is disposed on the GaN layer. A source feature and a drain feature spaced apart are disposed on the AlGaN layer. A gate electrode is disposed over the AlGaN layer between the source feature and the drain feature. A portion of a gate dielectric layer is disposed between the gate electrode and the AlGaN layer. An InGaN diffusion barrier layer 130 may be disposed on top of the AlGaN layer and beneath an Magnesium doped p-GaN cap layer.

0043The present disclosure also describes an aspect of a method of forming a semiconductor structure. The method includes providing a first III-V compound layer. A second III-V compound layer is epitaxially grown on the first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are formed on the second III-V compound layer. A gate dielectric layer is deposited on a portion of the second III-V compound layer. The gate dielectric layer on the portion of the second III-V compound layer is treated with fluorine. A gate electrode is formed on the treated gate dielectric layer between the source feature and the drain feature.

0044Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

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US2015021667A1	United States of America	A1	2015-01-22
US9236465B2	United States of America	B2	2016-01-12
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2014-11-25	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2014-11-06	Email NotificationEML_NTR	EML_NTR
2014-11-05	Issue Notification MailedAllowedWPIR	WPIR
2014-10-23	Dispatch to FDCD1935	D1935
2014-10-23	Application Is Considered Ready for IssuePILS	PILS
2014-10-22	Issue Fee Payment VerifiedN084	N084
2014-10-22	Issue Fee Payment ReceivedIFEE	IFEE
2014-08-29	Email NotificationEML_NTR	EML_NTR
2014-08-28	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2014-07-23	Electronic ReviewELC_RVW	ELC_RVW
2014-07-23	Email NotificationEML_NTF	EML_NTF
2014-07-23	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2014-07-20	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2014-07-11	Reasons for AllowanceEX.R	EX.R
2014-07-11	Examiner's Amendment CommunicationEX.A	EX.A
2014-07-07	Date Forwarded to ExaminerFWDX	FWDX
2014-07-03	Response after Ex Parte Quayle ActionA.QU	A.QU
2014-05-05	Electronic ReviewELC_RVW	ELC_RVW
2014-05-05	Email NotificationEML_NTF	EML_NTF
2014-05-05	Mail Ex Parte Quayle Action (PTOL - 326)MCTEQ	MCTEQ
2014-04-28	Quayle actionCTEQ	CTEQ
2014-04-28	Information Disclosure Statement consideredIDSC	IDSC
2014-04-16	Date Forwarded to ExaminerFWDX	FWDX
2014-04-15	Response to Election / Restriction FiledELC.	ELC.
2014-02-28	Electronic ReviewELC_RVW	ELC_RVW
2014-02-28	Email NotificationEML_NTF	EML_NTF
2014-02-28	Mail Restriction RequirementMCTRS	MCTRS
2014-02-23	Restriction/Election RequirementCTRS	CTRS
2013-11-05	Case Docketed to Examiner in GAUDOCK	DOCK
2013-07-10	Information Disclosure Statement (IDS) FiledM844	M844
2013-07-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-06-24	Case Docketed to Examiner in GAUDOCK	DOCK
2013-05-13	Application Dispatched from OIPEOIPE	OIPE
2013-04-18	Application Is Now CompleteCOMP	COMP
2013-04-18	Email NotificationEML_NTR	EML_NTR
2013-04-18	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2013-04-17	Sent to Classification ContractorPGPC	PGPC
2013-04-05	Preliminary AmendmentA.PE	A.PE
2013-04-05	Additional Application Filing FeesADDFLFEE	ADDFLFEE
2013-04-05	Applicant has submitted new drawings to correct Corrected Papers problemsCORRDRW	CORRDRW
2013-03-21	Electronic ReviewELC_RVW	ELC_RVW
2013-03-21	Email NotificationEML_NTR	EML_NTR
2013-03-21	Email NotificationEML_NTR	EML_NTR
2013-03-21	Email NotificationEML_NTF	EML_NTF
2013-03-21	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2013-03-21	Filing ReceiptFLRCPT.O	FLRCPT.O
2013-03-21	Corrected PaperCPAP	CPAP
2013-02-26	Cleared by OIPE CSRL194	L194
2013-02-22	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2013-02-22	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2013-02-22	Initial Exam Team nnIEXX	IEXX

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Events

Legal events, newest first
	Event	Code
2026-07-13	Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP
2022-05-11	Maintenance fee paymentMAFP	MAFP
2018-05-10	Maintenance fee paymentMAFP	MAFP
2014-11-05	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2013-02-22	AssignmentAS	AS