Method to improve nucleation of materials on graphene and carbon nanotubes

STATEMENT OF GOVERNMENT RIGHTS

0001This invention was made with Government support under Contract number FA8650-08-C-7838 awarded by (DARPA) Defense Advanced Research Projects Agency. The Government has certain rights in this invention.

FIELD OF THE INVENTION

0002The present invention relates to carbon-based materials, and more particularly, to techniques for forming a thin coating of a material, such as a high-k dielectric, on a carbon-based material, such as graphene.

BACKGROUND OF THE INVENTION

0003Graphene, a one carbon atom thick material, has a very high carrier mobility, making it suitable for use in high speed, high performance electronic devices. Current trends towards feature size scaling generally involve use of a high-k dielectric in these scaled graphene-based devices.

0004However, nucleation of high-k dielectrics on carbon-based materials such as graphene is problematic since bonding of the dielectric occurs by electrostatic forces. Specifically, carbon-based materials with honeycomb crystalline structures like graphene are chemically inert. The inertness makes it almost impossible to uniformly coat a thin layer of any material onto the carbon surface. Deposited material will only form clumps or clusters on the carbon surface rather than a uniform coating. While a uniform coating can eventually be achieved by adding more of the material, depositing enough material to gain complete coverage results in a layer that is too thick for some applications. This is the case with thin materials such as high-k dielectrics.

0005A conventional solution to this problem is to use nitrogen dioxide functionality to facilitate the bonding by exposing the carbon-based material to nitrogen dioxide gas prior to high-k dielectric deposition. This technique, however, shows degraded device performance due to low electron mobility. Namely, it has been suggested that a dipole forms at the interface of the dielectric and the carbon-based material, degrading device performance.

0006Therefore, techniques that improve nucleation of a thin coating of materials, such as high-k dielectrics, on carbon-based materials, such as graphene, without degrading device performance would be desirable.

SUMMARY OF THE INVENTION

0007The present invention provides techniques for forming a thin coating of a material on a carbon-based material. In one aspect of the invention, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

0008In another aspect of the invention, a method of fabricating a field-effect transistor (FET) device is provided. The method includes the following steps. A substrate is provided. A carbon-based material is formed on the substrate. Source and drain region electrodes are formed on a surface of the carbon-based material, spaced apart from one another so as to permit a gate electrode to be formed therebetween. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of a dielectric layer on the surface of the carbon-based material. The dielectric layer is deposited over the ultra thin silicon layer. The gate electrode is formed over the dielectric layer between the source and drain region electrodes.

0009In yet another aspect of the invention, a FET device is provided. The FET device includes a substrate; a carbon-based material on the substrate; source and drain region electrodes on a surface of the carbon-based material, spaced apart from one another so as to permit a gate electrode to be placed therebetween; an ultra thin silicon nucleation layer having a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of a dielectric layer on the surface of the carbon-based material; the dielectric layer over the ultra thin silicon layer; and the gate electrode over the dielectric layer between the source and drain region electrodes.

0010A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0011<figref idref="DRAWINGS">FIGS. 1 and 2</figref> are cross-sectional diagrams illustrating an exemplary methodology for forming a thin coating on a surface of a carbon-based material according to an embodiment of the present invention;

0012<figref idref="DRAWINGS">FIG. 3</figref> is a graph illustrating index of refraction n and extinction coefficient k as a function of wavelength for ultra thin deposited amorphous silicon according to an embodiment of the present invention;

0013<figref idref="DRAWINGS">FIGS. 4-9</figref> are diagrams illustrating an exemplary methodology for fabricating a field-effect transistor (FET) device according to an embodiment of the present invention;

0014<figref idref="DRAWINGS">FIG. 10</figref> is a top-down scanning electron micrograph (SEM) image depicting a graphene flake deposited on a substrate according to an embodiment of the present invention;

0015<figref idref="DRAWINGS">FIG. 11</figref> is an atomic force microscope (AFM) image of the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref> according to an embodiment of the present invention;

0016<figref idref="DRAWINGS">FIG. 12</figref> is a top-down SEM image of source and drain region electrodes formed to the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref> according to an embodiment of the present invention;

0017<figref idref="DRAWINGS">FIG. 13</figref> is a top-down optical image of the source and drain region electrodes of <figref idref="DRAWINGS">FIG. 12</figref> according to an embodiment of the present invention;

0018<figref idref="DRAWINGS">FIG. 14</figref> is a graph illustrating current-voltage (I-V) characteristics of the device structure of <figref idref="DRAWINGS">FIGS. 12 and 13</figref> using back gate measurements according to an embodiment of the present invention;

0019<figref idref="DRAWINGS">FIG. 15</figref> is a graph illustrating experimental ellipsometric spectra of angle of polarization Ψ collected at 65 degrees and at 75 degrees according to an embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 16</figref> is a tilted cross-sectional SEM image of a graphene flake post amorphous silicon/high-k dielectric deposition according to an embodiment of the present invention;

0021<figref idref="DRAWINGS">FIG. 17</figref> is a 90 degree cross-sectional image of a graphene flake post amorphous silicon/high-k dielectric deposition according to an embodiment of the present invention;

0022<figref idref="DRAWINGS">FIG. 18</figref> is a top-down SEM image of a device structure post amorphous silicon/high-k dielectric deposition and post top gate electrode formation according to an embodiment of the present invention; and

0023<figref idref="DRAWINGS">FIG. 19</figref> is a graph illustrating current versus top gate voltage for the device structure of <figref idref="DRAWINGS">FIG. 18</figref> according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

0024The present teachings address the above-described problems associated with thin coating chemically inert carbon-based materials. Examples of carbon-based materials as they are described herein include, but are not limited to, graphene, carbon nanotubes and carbon fibers. Advantageously, it has been determined by way of the present teachings that an ultra thin silicon nucleation layer on the surface of the carbon-based material can facilitate nucleation of the coating to achieve complete coverage of the surface, without affecting the electrical properties of the carbon-based material. By way of example only, <figref idref="DRAWINGS">FIGS. 1 and 2</figref> are cross-sectional diagrams illustrating an exemplary methodology for forming a thin coating on a surface of a carbon-based material. As shown in <figref idref="DRAWINGS">FIG. 1</figref>, an ultra thin silicon nucleation layer <b>104</b> is deposited on a surface of carbon-based material <b>102</b>. Silicon layer <b>104</b> may or may not be a continuous layer, i.e., silicon layer <b>104</b> does not have to fully cover the surface of carbon-based material <b>102</b> to serve as a nucleation center for the thin coating.

0025According to an exemplary embodiment, silicon layer <b>104</b> comprises amorphous silicon. As highlighted above, the purpose of silicon layer <b>104</b> is to facilitate nucleation of the thin coating on carbon-based material <b>102</b>. However, silicon layer <b>104</b> should be thin enough so as not to affect the electrical characteristics of the carbon-based material. For example, depositing silicon layer <b>104</b> to a thickness of from about two angstroms (Å) to about 10 Å, e.g., from about three Å to about eight Å, will serve to facilitate nucleation of the thin coating but will not affect the electrical characteristics of the carbon-based material.

0026Silicon layer <b>104</b> can be deposited on the surface of carbon-based material <b>102</b> by a variety of methods. According to one exemplary embodiment, silicon layer <b>104</b> is deposited on the surface of carbon-based material <b>102</b> in a vacuum chamber using low pressure (e.g., about 20 milliTorr (mTorr)), low power (e.g., low power radio frequency (RF) plasma at about 30 milliwatts per square centimeter (mW/cm²)) plasma-enhanced chemical vapor deposition (PECVD) in the presence of a gas mixture containing two percent (%) silane diluted in helium, for a duration of about three minutes. The substrate is heated to a temperature T of, e.g., about 350 degrees Celsius (° C.) and is grounded during the deposition.

0027The use of a low pressure, low power PECVD process serves to minimize plasma damage. Such a process has been proven to produce very low interface states (D_it) on both silicon and gallium arsenide substrates. Alternatively, a less intrusive (no plasma) technique may be used to deposit silicon layer <b>104</b> on carbon-based material <b>102</b>. For example, according to another exemplary embodiment, silicon layer <b>104</b> is deposited using molecular beam epitaxy (MBE) or rapid thermal chemical vapor deposition (RTCVD) (for example, at a temperature of from about 450° C. to about 900° C. with silane and/or dichlorosilane as the silicon source).

0028Depending on the particular application, it may be desirable to create a neutral charge state in silicon layer <b>104</b>. For instance, an example will be presented in detail below wherein the carbon-based material serves as the body of a transistor device and the silicon layer is used to facilitate coating a thin gate dielectric, e.g., a high-k dielectric, on the surface of the carbon-based material. In such a device, performance can be degraded due to low electron mobility at the interface of the dielectric and the surface of the carbon-based material. To this point, conventional processes use a nitrogen dioxide monolayer to nucleate high-k dielectrics on carbon surfaces. However, interface trap charges have been observed at the high-k/carbon interface where the nitrogen dioxide layer is located. The dipole nature of nitrogen dioxide is suspected to be responsible for the trapped charges.

0029Advantageously, according to the present teachings, a neutral charge state can be created in silicon layer <b>104</b> to minimize, or eliminate, the problems associated with interface trap charges, e.g., by either oxidation or nitridation of silicon layer <b>104</b>. This step is optional. By way of example only, exposing silicon layer <b>104</b> to an oxygen environment, such as to ambient air will, by way of oxidation, result in the formation of silicon dioxide a neutral charge molecule.

0030As shown in <figref idref="DRAWINGS">FIG. 2</figref>, a thin coating <b>106</b> is deposited over silicon layer <b>104</b>, e.g., to a thickness of from about two Å to about 100 Å. The present teachings are generally applicable to forming any type of thin coating on the surface of a carbon-based material. By way of example only, the coating can comprise a nitride material, an oxide material, a metal or as highlighted above, a dielectric. According to one exemplary embodiment, the coating comprises a high-k dielectric, such as aluminum oxide.

0031Any suitable deposition process may be used to deposit thin coating <b>106</b> over silicon layer <b>104</b>. According to an exemplary embodiment, thin coating <b>106</b> is deposited over silicon layer <b>104</b> using atomic layer deposition (ALD), for example, in 50 cycles at 250° C. The presence of silicon layer <b>104</b> facilitates nucleation of thin coating <b>106</b>, permitting thin coating <b>106</b> to form a continuous layer over the surface of carbon-based material <b>102</b>. Without silicon layer <b>104</b> as a nucleation center, forming a continuous layer of such a thin coating on the surface of carbon-based material <b>102</b> would not be possible. The above-described techniques for forming a carbon-based material/ultra thin silicon nucleation layer/thin coating material can be used to form a coating on a carbon-based material for a variety of different applications. See examples below.

0032To illustrate the efficacy of the present techniques to produce an ultra thin silicon layer for high-k dielectric nucleation, an ultra thin amorphous silicon layer was deposited on a silicon dioxide layer according to the above-described process. Ellipsometric analysis of the sample was then conducted. The results of the analysis are shown in <figref idref="DRAWINGS">FIG. 3</figref>. Namely, <figref idref="DRAWINGS">FIG. 3</figref> is a graph <b>300</b> illustrating index of refraction n and extinction coefficient k as a function of wavelength (measured in nanometers (nm)) for the deposited amorphous silicon (a-Si). The dotted line in graph <b>300</b> is extinction coefficient k, and the solid line is index of refraction n.

0033One exemplary implementation of the above-described process involves forming a thin coating of a dielectric on the carbon-based material of a field-effect transistor (FET) device. <figref idref="DRAWINGS">FIGS. 4-9</figref> are diagrams illustrating an exemplary methodology for fabricating such a device. In general, a FET comprises a source region and a drain region connected by a channel, and a gate (separated from the channel by a gate dielectric) which regulates electron flow between the source and drain. As shown in <figref idref="DRAWINGS">FIG. 4</figref>, fabrication of the device begins with a carbon-based material <b>402</b> being formed (e.g., deposited or grown) on a provided substrate <b>404</b>. According to an exemplary embodiment, the carbon-based material comprises graphene which is deposited on substrate <b>404</b> using a standard process, such as an exfoliation method as described in K. S. Novoselov et al., “Electric Field Effect in Atomically Thin Carbon Films,” Science, vol. 306, pgs. 666-669 (2004), the contents of which are incorporated by reference herein. The carbon-based material can also be grown on substrate <b>404</b>. Growth of a carbon-based material is described, for example, in C. Berger et al., “Electronic Confinement and Coherence in Patterned Epitaxial Graphene,” Science, vol. 312, pgs. 1191-1196 (2006), and in C. Berger et al., “Ultrathin Epitaxial Graphite: 2D Electron Gas Properties and a Route Toward Graphene-based Nanoelectronics,” J. Phys. Chem., vol. 108, no. 52, pgs. 19912-19916 (2004), the contents of both of which are incorporated by reference herein. Carbon-based material <b>402</b> effectively serves as the body or channel of the device.

0034Any suitable substrate can be used as substrate <b>404</b>, including, but not limited to, a bulk silicon wafer. The substrate may, or may not serve as part of the device. For example, substrate <b>404</b> can be a doped silicon substrate that serves as a bottom/back gate of the device. In that instance, an insulating layer, e.g., a silicon dioxide layer <b>406</b>, can be formed on substrate <b>404</b> (e.g., to a thickness of about 300 nm) prior to deposition of the carbon-based material. Standard techniques may be employed to form the silicon dioxide layer on the substrate. Carbon-based material <b>402</b> would then be formed on insulating layer <b>406</b>. The insulating layer is however optional, and would not be necessary in cases where substrate <b>404</b> does not serve as part of the device.

0035At this point in the process, an analysis of the properties of the carbon-based material formed may optionally be performed. By way of example only, optical, atomic force microscope (AFM) and/or scanning electron microscope (SEM) analysis of carbon-based material <b>402</b> may be conducted, e.g., to determine the thickness of the carbon-based material sample. Such analysis techniques are known to those of skill in the art and thus are not described further herein. An AFM image of a graphene sample is shown in <figref idref="DRAWINGS">FIG. 11</figref>, described below.

0036As shown in <figref idref="DRAWINGS">FIG. 5</figref>, source and drain region electrodes, i.e., metal contacts, <b>502</b> and <b>504</b> (the source and drain regions of the device) are formed on a surface of carbon-based material <b>402</b> opposite substrate <b>404</b>. Exemplary techniques for forming source and drain region electrodes on a carbon-based material are presented below. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, source and drain region electrodes <b>502</b> and <b>504</b> are spaced apart from one another so as to permit a gate electrode to be formed therebetween (see below).

0037At this point in the process, electrical measurements (e.g., electrical characteristics and mobility) may optionally be performed to verify the quality of carbon-based material <b>402</b>. Exemplary results of these electrical measurements performed on a sample are shown in <figref idref="DRAWINGS">FIG. 14</figref>, described below.

0038As shown in <figref idref="DRAWINGS">FIG. 6</figref>, an ultra thin silicon nucleation layer <b>602</b> is deposited over the surface of carbon-based material <b>402</b> to facilitate nucleation of a dielectric layer that will be deposited on the surface of carbon-based material <b>402</b>. The use of an ultra thin silicon layer to facilitate nucleation of a thin coating on the surface of a carbon-based material, including the composition, thickness and methods for deposition of the ultra thin silicon nucleation layer were described in detail above. Further, as described above, silicon layer <b>602</b> may be a continuous or discontinuous layer.

0039In this example, it is desirable to create a neutral charge state in silicon layer <b>602</b>, so as to avoid trap charges at the interface of the dielectric layer and the carbon-based material, as described above. A neutral charge state can be created in silicon layer <b>602</b> in several different ways. One way is to oxidize silicon layer <b>602</b> by exposing silicon layer <b>602</b> to an oxygen environment, such as to the ambient air, prior to depositing the dielectric layer (i.e., thus creating silicon dioxide a neutral charge molecule). If the dielectric layer includes an oxide, such as aluminum oxide, then another way to create a neutral charge state in silicon layer <b>602</b> is to deposit the oxide dielectric in-situ. Namely, as highlighted above, the silicon nucleation layer can be deposited in a vacuum chamber using low pressure, low power PECVD. The oxide dielectric can then be deposited without breaking the vacuum. The oxide dielectric deposition typically involves oxygen which will then oxidize silicon layer <b>602</b> (again forming silicon dioxide). If the dielectric layer includes a nitride, such as aluminum nitride, then yet another way to create a neutral charge state in silicon layer <b>602</b> is through nitridation, e.g., by depositing the nitride dielectric in-situ. Namely, the nitride dielectric deposition will convert the silicon in silicon layer <b>602</b> into silicon nitride a neutral charge molecule.

0040As shown in <figref idref="DRAWINGS">FIG. 7</figref>, a dielectric layer <b>702</b> is deposited over silicon layer <b>602</b>. According to an exemplary embodiment, dielectric layer <b>702</b> comprises a high-k dielectric, such as aluminum oxide or aluminum nitride, and is deposited over silicon layer <b>602</b> using ALD (as described above) to a thickness of from about two Å to about 100 Å. In this example, dielectric layer <b>702</b> will serve as the gate dielectric. As shown in <figref idref="DRAWINGS">FIG. 7</figref>, dielectric layer <b>702</b> can be etched away locally in the source and drain regions to expose source and drain region electrodes <b>502</b> and <b>504</b>.

0041At this point in the process, SEM analysis post dielectric deposition may optionally be conducted. Exemplary results of such an analysis conducted on a sample graphene-based device are shown in <figref idref="DRAWINGS">FIGS. 16 and 17</figref>, described below.

0042A gate electrode, i.e., metal contact, (the gate of the device) is then formed over dielectric layer <b>702</b> between source and drain region electrodes <b>502</b> and <b>504</b>, and separated from carbon-based material <b>402</b> by dielectric layer <b>702</b> (and by silicon layer <b>602</b> which is however thin enough so as not to affect the electrical properties of the carbon-based material). The gate electrode formed can be either a partial gate electrode or a full gate electrode. For example, as shown in <figref idref="DRAWINGS">FIG. 8</figref>, a partial gate electrode <b>802</b> is formed over dielectric layer <b>702</b> between source and drain region electrodes <b>502</b> and <b>504</b>. The same techniques used to form the source and drain region electrodes may be used to form a partial gate electrode. As shown in <figref idref="DRAWINGS">FIG. 9</figref>, a full gate electrode <b>902</b> is formed over dielectric layer <b>702</b> between source and drain region electrodes <b>502</b> and <b>504</b>. The same techniques used to form the source and drain region electrodes may be used to form a full gate electrode.

0043By way of reference to a non-limiting example, the above-described techniques are now used to form a specific type of FET device, i.e., a top and bottom gated FET device. <figref idref="DRAWINGS">FIG. 10</figref> is a top-down SEM image <b>1000</b> depicting a graphene flake <b>1002</b> which was deposited on a substrate by an exfoliation method. The term “graphene flake” is a common nomenclature used to describe graphene areas prepared by an exfoliation method. Graphene flakes can consist of many different graphene structures. Thickness (number of layers) and shape of the graphene can vary significantly across the flake due to the preparation method. An area of a graphene flake which is suitable for device fabrication consists of one or two layer thick graphene material and is usually situated near the edge of the flake. In <figref idref="DRAWINGS">FIG. 10</figref>, the graphene flake <b>1002</b> includes both a long and thin graphene bar-like structure (to which the left arrow points) and a large and thick graphene area (to which the right arrow points) (i.e., both the long and thin graphene bar-like structure and the large and thick graphene area belong to the same graphene flake <b>1002</b>). The long and thin graphene bar-like structure portion of the flake was chosen to fabricate the graphene device, as the large and thick graphene area is likely not suitable for device fabrication.

0044On the other hand, if a graphene layer is formed by an epitaxial growth method where graphene thickness and uniformity can be controlled, then the device can be fabricated anywhere on the layer. The term graphene flake is not used to describe a graphene layer prepared by an epitaxial growth technique.

0045In this example, the substrate (subs.) is a doped silicon substrate having a silicon dioxide (SiO₂) insulator layer <b>1004</b> (visible in image <b>1000</b>) on which graphene flake <b>1002</b> is deposited. Through doping, the substrate is rendered conductive and thus serves as a bottom gate electrode (also referred to herein as a back gate) of the device. Silicon dioxide layer <b>1004</b> has a thickness of about 300 nm.

0046As highlighted above an analysis of the properties, such as thickness, of the carbon-based material formed may be performed. Accordingly, <figref idref="DRAWINGS">FIG. 11</figref> is an AFM image <b>1100</b> of the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref>. The thickness of the graphene flake was found to be from about two nm to about three nm by AMF analysis. This corresponds to from about one layer to about two layers of graphene taking into account the weak interaction between the silicon dioxide and the graphene.

0047<figref idref="DRAWINGS">FIG. 12</figref> is a top-down SEM image <b>1200</b> of source and drain region electrodes <b>1202</b> formed to the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref> (i.e., the graphene flake serves as a body/channel of the device). <figref idref="DRAWINGS">FIG. 13</figref> is a top-down optical image <b>1300</b> of source and drain region electrodes <b>1202</b>. In this example, source and drain region electrodes <b>1202</b> are formed using electron beam (e-beam) lithography with a poly(methyl methacrylate) (PMMA) resist process and contact metal (e.g., titanium/palladium/gold) evaporation. Specifically, a PMMA resist is deposited over the graphene flake and patterned using e-beam lithography with a shape and location of the source and drain region electrodes. E-beam lithography using a PMMA resist is known to those of skill in the art and thus is not described further herein.

0048Contact metals, e.g., a one nm thick layer of titanium, followed by a 40 nm thick layer of palladium, followed by a 20 nm thick layer of gold, are then deposited over the patterned resist using an evaporation process at room temperature. The parameters and steps for depositing these contact metals using an evaporation process are well known to those of skill in the art and thus are not described further herein. After contacts formation, the remaining PMMA resist is removed by a conventional lift-off process in an 80° C. acetone bath.

0049As highlighted above, electrical measurements (e.g., electrical characteristics and mobility) may be performed to verify the quality of the carbon-based material. Accordingly, <figref idref="DRAWINGS">FIG. 14</figref> is a graph <b>1400</b> illustrating current-voltage (I-V) characteristics of the device structure of <figref idref="DRAWINGS">FIGS. 12 and 13</figref> using back gate measurements (i.e., with the doped substrate acting as the bottom/back gate electrode). Namely, device current (i.e., the current passing through the graphene flake) as a function of the back gate voltage is measured to extract the mobility of the graphene channel. In graph <b>1400</b>, back gate voltage V_bg(measured in volts (V)) is plotted on the x-axis and current I (measured in amps (A)) is plotted on the y-axis. A source-drain voltage V_dsof −5 millivolts (mV) was employed in the measurements. As shown in graph <b>1400</b>, the device structure showed good electrical characteristics and mobility of about 1,357 square centimeter per volt second (cm²/Vs).

0050Once the source and drain region electrodes have been formed, an ultra thin amorphous silicon nucleation layer and a high-k dielectric layer are deposited on the graphene flake according to the processes and parameters set forth in detail above. As presented above, the ultra thin amorphous silicon layer can be deposited in a vacuum chamber using low pressure, low power PECVD in the presence of a gas mixture containing two % silane diluted in helium. In this particular example, prior to amorphous silicon deposition, the vacuum chamber was pumped down to a pressure of about 1×10⁻⁶Ton using a turbo molecular pump. The amorphous silicon deposition was carried out at a power of seven watts (W) (30 mW/cm²), 20×10⁻³Ton of pressure at a flow of 50 standard cubic centimeters per minute (sccm) for three minutes. Substrate temperature was about 350° C. This amorphous silicon deposition process was found to produce low interface states on gallium arsenide devices, significantly improving electrical characteristics. See, for example, J. P. deSouza et al., “Inversion Mode n-Channel GaAs Field Effect Transistor With High-k/Metal Gate,” Applied Physics Letters, 92, 153508 (2008) and A. Callegari et al., “Properties of SiO₂/Si/GaAs Structures Formed by Solid Phase Epitaxy of Amorphous Silicon on GaAs,” Applied Physics Letters, 58, 2540 (1991), the contents of both of which are incorporated by reference herein.

0051Ellipsometric measurements were performed on a reference sample which included a silicon substrate, a silicon dioxide layer on the substrate and an amorphous silicon layer on the silicon dioxide layer. It was found that the amorphous silicon layer was about 0.3 nm thick. <figref idref="DRAWINGS">FIG. 15</figref> is a graph <b>1500</b> illustrating experimental ellipsometric spectra of angle of polarization Ψ collected at 65 degrees (dash line) and at 75 degrees (dotted line). In graph <b>1500</b>, wavelength (measured in nm) is plotted on the x-axis and Ψ in degrees is plotted on the y-axis. These experimental data were compared with the modeled data (solid line) to determine the amorphous silicon layer thickness, the index of refraction n and the extinction coefficient k. Index of refraction n and extinction coefficient k of an amorphous silicon layer as a function of wavelength is shown in <figref idref="DRAWINGS">FIG. 3</figref>, described above.

0052As highlighted above, SEM analysis post amorphous silicon/high-k dielectric deposition may also be conducted. <figref idref="DRAWINGS">FIG. 16</figref> is a tilted cross-sectional SEM image <b>1600</b> of a graphene flake, such as the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref>, post amorphous silicon/high-k dielectric deposition. A 90 degree cross-section of the flake in <figref idref="DRAWINGS">FIG. 16</figref> which highlights the amorphous silicon/high-k dielectric is shown in <figref idref="DRAWINGS">FIG. 17</figref>. Namely, <figref idref="DRAWINGS">FIG. 17</figref> is a 90 degree cross-sectional image <b>1700</b> of the graphene flake, such as the graphene flake of <figref idref="DRAWINGS">FIG. 10</figref>, post amorphous silicon/high-k dielectric deposition. Images <b>1600</b> and <b>1700</b> illustrate that the high-k dielectric and the ultra thin silicon layer are present over both the graphene flake and the silicon dioxide layer of the doped substrate.

0053Following deposition of the high-k dielectric layer, a gate electrode is then formed over the high-k dielectric layer between the source and drain region electrodes. In this particular example, the gate electrode presently formed is referred to herein as a top gate electrode, so as to differentiate it from the bottom/back gate (see above). More specifically, the top gate electrode is a metal gate defined by a lithographic process, whereas the doped silicon substrate serves as the bottom/back gate.

0054<figref idref="DRAWINGS">FIG. 18</figref> is a top-down SEM image <b>1800</b> of the device structure (e.g., of <figref idref="DRAWINGS">FIG. 12</figref>) post amorphous silicon/high-k dielectric deposition and post top gate electrode formation. In image <b>1800</b>, the source and drain region electrodes are labeled “S” and “D,” respectively, and the top gate electrode is labeled “Gate.” The gate electrode is formed using the procedures, described above, that were used to form the source and drain region electrodes. Namely, the top gate electrode is formed using e-beam lithography with a PMMA resist process and contact metal (e.g., titanium/palladium/gold) evaporation.

0055Following top gate electrode formation, electrical measurements (e.g., electrical characteristics and mobility) were again performed to verify the quality of the carbon-based material. <figref idref="DRAWINGS">FIG. 19</figref> is a graph <b>1900</b> illustrating current versus top gate voltage for the device structure of <figref idref="DRAWINGS">FIG. 18</figref>. In graph <b>1900</b>, top gate voltage V_tg(measured in V) is plotted on the x-axis and source-drain current I_ds(measured in A) is plotted on the y-axis. A source-drain voltage V_dsof −5 mV was employed in the measurements. Device mobility after top gate formation is about 20 cm²/Vs. Mobility degradation is likely to be reduced with adjustments of the silicon layer and ALD deposition conditions.

0056Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.