Memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The present invention will describe a memory element having an organic compound, a memory device having the memory element, and a method for manufacturing them.

00032. Description of the Related Art

0004In these days, an RFID (Radio Frequency Identification) has been developed and researched as a technology to recognize and identify things and people. Such the RFID is used to prevent counterfeiting of securities or to identify individual, and many applications are expected.

0005An IC (Integrated Circuit) chip formed using a silicon wafer is used for the conventional RFID, and it forms a memory circuit such as ROM or RAM, a control circuit such as CPU (refer to Patent Document 1). <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0006">Patent Document 1</li><li id="ul0001-0002" num="0007">Japanese Patent Laid-Open No. 2000-20665 (<figref idref="DRAWINGS">FIG. 2</figref>)</li></ul>

0008As described above, a chip of an RFID which is formed using a silicon wafer is non-transmissive. Further, the size of a chip tends to be made smaller in order to increase impact resistance, however the chip is not considered to be thinned, and when it is mounted for securities or an individual identification, it is often noticeable.

0009Such the RFID is considered to be used for an area of a tag for goods, and its cost is expected to be lowered so that it is disposable. Therefore, the RFID is formed by taking out many planes from a silicon wafer having a circular shaped mother body, however limit for lowering the cost with increasing a taking-out efficiency has begun to appear.

0010It is an object of the present invention to provide a memory element and a memory circuit having the element with lowered cost and reduced manufacturing steps. In addition, it is an object of the present invention to provide a memory element having the circuit and a semiconductor device having the memory element.

SUMMARY OF THE INVENTION

0011In view of the objects described above, the present invention has a feature of a memory element having an organic compound sandwiched between electrodes, and an electrode connected to a semiconductor element which controls the memory element, in other words a source or drain electrode, functioning as a lower electrode of the memory element. Accordingly, an electrode for a memory element is not necessary, and thus the number of steps can be reduced.

0012In an aspect of the present invention, an insulator included in a memory element is formed inside an opening portion for forming an electrode electrically connected to a semiconductor element. Accordingly, an insulating film, and a so-called isolating layer, which is necessary for making and dividing an organic compound, is not formed.

0013In addition, an extremely thin semiconductor film formed on an insulated surface is used in the present invention; therefore low cost can be attempted. The insulated surface indicates other than a silicon wafer, for example a surface of a glass substrate or a synthetic resin substrate such as plastic.

0014Hereinafter, specific modes of the present invention will be described.

0015In an aspect of the present invention, a memory device includes a semiconductor film having an impurity region formed on an insulated surface; an insulating film which is in contact with the semiconductor film and provided with an opening portion on the impurity region; a conductive film functioning as a source or drain electrode electrically connected to the impurity region and functioning as a lower electrode at the opening portion; an insulator provided on the conductive film at the opening portion; and an upper electrode provided on the insulator.

0016In another aspect of the present invention, a memory device includes a semiconductor film having an impurity region formed on an insulated surface; a first insulating film which is in contact with the semiconductor film and provided with a first opening portion on the impurity region; a first conductive film functioning as a source or drain electrode electrically connected to the impurity region at the first opening portion; a second insulating film which is provided so as to cover the edge of the conductive film and provided with a second opening portion on the impurity region; a second conductive film which is connected to the first conductive film and functions as a lower electrode; an insulator provided on the second conductive film at the first and second opening portions; and an upper electrode provided on the insulator.

0017In the present invention, an insulator is a material whose property is changed by an optical effect or a thermal effect, and which can short-circuit a lower electrode and an upper electrode. In order to change the property by the optical effect or the thermal effect, the film thickness may be 5 to 100 nm, preferably 10 to 60 nm. In a case of using an organic compound material for the insulator, the glass transition temperature may be 80 to 300° C., preferably 100 to 250° C.

0018A method for manufacturing a memory device of the present invention is characterized by forming an impurity region in a semiconductor film on an insulated surface; forming an insulating film to be in contact with the semiconductor film; forming an opening portion in the insulating film so as to expose the impurity region; forming a conductive film functioning as a source or drain electrode and a lower electrode electrically connected to the impurity region at the opening portion; forming an insulator on the conductive film; and forming an upper electrode on the insulator.

0019Another mode of a method for manufacturing a memory device of the present invention is characterized by forming an impurity region in a semiconductor film on an insulated surface; forming an insulating film to be in contact with the semiconductor film; forming an opening portion in the insulating film so as to expose the impurity region; forming a conductive film functioning as a source or drain electrode and a lower electrode electrically connected to the impurity region at the opening portion; forming an insulator on the conductive film; and forming an upper electrode on the insulator, wherein surface modification is carried out to the conductive film and the insulating film.

0020Another mode of a method for manufacturing a memory device of the present invention is characterized by forming an impurity region in a semiconductor film on an insulated surface; forming an insulating film to be in contact with the semiconductor film; forming an opening portion in the insulating film so as to expose the impurity region; forming a conductive film functioning as a source or drain electrode and a lower electrode electrically connected to the impurity region at the opening portion; forming an insulator on the conductive film; and forming an upper electrode on the insulator, wherein surface modification is carried out to the conductive film by a sputtering method.

0021As described above, since the insulator is formed in extremely thin, adhesiveness of the insulator can be improved by carrying out the surface modification.

0022An another mode of a method for manufacturing a memory device of the present invention is characterized by forming an impurity region in a semiconductor film on an insulated surface; forming an insulating film to be in contact with the semiconductor film; forming an opening portion so as to expose the impurity region at the insulating film; forming a conductive film functioning as a source or drain electrode and a lower electrode electrically connected to the impurity region at the opening portion; forming an insulator on the conductive film; and forming an upper electrode on the insulator, wherein after modification is carried out only to an upper surface of the conductive film provided at the periphery of the opening portion, the insulator is formed by a droplet discharging method.

0023By the present invention, an electrode for a memory is not necessary, and thus the number of manufacturing steps is reduced, and a memory element and a memory circuit having the element with lowered cost are provided.

BRIEF DESCRIPTION OF THE DRAWINGS

0024In the accompanying drawings:

0025<figref idref="DRAWINGS">FIGS. 1A to 1D</figref> are views showing manufacturing steps of a memory element;

0026<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are top views showing manufacturing steps of a memory element;

0027<figref idref="DRAWINGS">FIG. 3</figref> is a view showing a manufacturing step of a memory element;

0028<figref idref="DRAWINGS">FIG. 4</figref> is a top view showing a manufacturing step of a memory element;

0029<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are views showing manufacturing steps of a memory element;

0030<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are views showing manufacturing steps of a memory element;

0031<figref idref="DRAWINGS">FIGS. 7A to 7C</figref> are views showing manufacturing steps of a memory element;

0032<figref idref="DRAWINGS">FIG. 8</figref> is a view showing a manufacturing step of a memory element;

0033<figref idref="DRAWINGS">FIG. 9</figref> is a view showing a manufacturing step of a memory element;

0034<figref idref="DRAWINGS">FIG. 10</figref> is a view showing a structure of a memory element;

0035<figref idref="DRAWINGS">FIG. 11</figref> is a view showing a structure of a writing circuit;

0036<figref idref="DRAWINGS">FIG. 12</figref> is a view showing a structure of a reading circuit;

0037<figref idref="DRAWINGS">FIGS. 13A and 13B</figref> are views showing circuit structures of memory elements;

0038<figref idref="DRAWINGS">FIG. 14</figref> is a view showing a structure of a semiconductor device;

0039<figref idref="DRAWINGS">FIG. 15</figref> is a view showing an I-V characteristic of a memory element; and

0040<figref idref="DRAWINGS">FIGS. 16A and 16B</figref> are top views showing a manufacturing step of a memory element.

DETAILED DESCRIPTION OF THE INVENTION

0041Hereinafter, embodiment modes of the present invention will be described based on the accompanying drawings. However, the present invention can be carried out in many different modes, and it is easily understood by those skilled in the art that modes and details herein disclosed can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiment modes to be given below. Note that in all drawings for describing the embodiment modes, the same reference numerals are used for the same portions or the portions having similar functions, and the repeated description thereof is omitted.

Embodiment Mode 1

0042In this embodiment mode, a manufacturing process of a memory element will be described.

0043As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, a base film <b>101</b> is formed on a substrate <b>100</b> having an insulated surface. For the substrate <b>100</b>, a glass substrate such as a barium borosilicate glass and an alumino borosilicate glass; a quartz substrate; a stainless steel (SUS) substrate; and the like can be used, for example. In addition, a substrate formed from a plastic typified by PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyether sulfone), or a synthetic resin having flexibility such as acrylic, generally has a low heat resistance as compared with other substrates; however it can be used as long as it can withstand a processing temperature in manufacturing steps.

0044The base film <b>101</b> is provided to prevent an alkali metal such as Na, or an alkaline earth metal included in the substrate <b>100</b> from diffusing in a semiconductor film and adversely affecting characteristics of a semiconductor element. Therefore, the base film is formed using an insulating film such as silicon oxide, silicon nitride or silicon nitride oxide, which can suppress the diffusion of the alkali metal or the alkaline earth metal into the semiconductor film.

0045In a case of using a substrate in which an alkali metal or an alkaline earth metal is included in any way, such as a glass substrate, a stainless steel substrate or a plastic substrate, providing a base film is effective for prevention of the diffusion of an impurity. On the other hand, in a case that the impurity diffusion is not a big problem, like a quartz substrate, the base film is not necessarily provided.

0046Next, an amorphous semiconductor film is formed on the base film <b>101</b>. Silicon germanium as well as silicon can be used for the amorphous semiconductor film. In a case of using silicon germanium, the concentration of germanium is preferably approximately 0.01 to 4.5 atomic %. In this embodiment mode, a semiconductor film mainly containing silicon of 66 nm (also referred to as an amorphous silicon film or amorphous silicon) is used.

0047Then, the amorphous semiconductor film is crystallized to form a crystalline semiconductor film. As a method for crystallization, a heating furnace, laser irradiation, or light irradiation emitted from a lamp (lamp annealing) or a method which is a combination of the foregoing methods, can be used.

0048For example, the crystalline semiconductor film is formed by adding a metal element to the amorphous semiconductor film and conducting a heat treatment using a heating furnace. In this manner, by adding the metal element, crystallization can be performed at low temperature, which is preferable. Addition here indicates that a metal element is formed on the surface of the amorphous semiconductor film at least so as to promote crystallization of the amorphous semiconductor film. For example, Ni solution (including water solution and acetic acid solution) is applied on the amorphous semiconductor film by an application method such as a spin coating method or a dipping method, and that a film containing Ni (however, there is a case that it cannot be observed as a film because it is extremely thin) is formed. At this time, wettability of the surface of the amorphous semiconductor film is preferably improved in order to spread the solution over the entire surface of the amorphous semiconductor film. For example, an oxide film is formed to have a thickness of 1 to 5 nm by UV light irradiation in oxygen atmosphere, a thermal oxidation method, a treatment with ozone water including hydroxy radical or hydrogen peroxide, or the like, and therefore the wettability can be improved.

0049Thereafter, the amorphous semiconductor film is heated at 500 to 550° C. for 2 to 20 hours, and the amorphous semiconductor film is crystallized; therefore a crystalline semiconductor film is formed. At this time, it is preferable that heating temperature be gradually changed. In addition, hydrogen or the like in the amorphous semiconductor film comes out by a low temperature heating step, and therefore roughness of the film at the time of the crystallization is decreased, a so-called dehydrogenation can be carried out. For example, after the amorphous semiconductor film is heated at 500° C. for 1 hour using a vertical furnace, crystallization can be carried out by a heat treatment at 550° C. for 4 hours.

0050In a case of carrying out the crystallization using the metal element in this manner, a gettering step is performed in order to reduce or remove the metal element. For example, the amorphous semiconductor film is formed as a gettering sink and is heated; therefore the metal element can be captured.

0051Thereafter, a heat treatment is conducted under nitrogen atmosphere at 550° C. for 4 hours, and the metal element is reduced or removed. Then, the amorphous semiconductor film which has become a gettering sink, and the oxide film are removed by hydrofluoric acid or the like, and therefore a crystalline semiconductor film in which the metal element is reduced or removed, can be obtained.

0052The amorphous semiconductor film is irradiated with a laser light (laser beam) as another crystallization method. One or more from an Ar laser, a Kr laser, an excimer laser, a YAG laser, a Y₂O₃laser, a YVO₄laser, a YLE laser, a YAIO₃laser, a glass laser, a ruby laser, an alexandrite laser, a Ti: sapphire laser, a copper vapor laser and a gold vapor laser, can be used. A laser oscillation has a continuous oscillation type (also referred to as a CW laser) and a pulsed oscillation type (also referred to as a pulsed laser), and these can be used. Furthermore, a fundamental wave of laser or the second to the fourth harmonic of the fundamental wave individually or a combination of thereof, can be used.

0053The shape of laser beam is preferably linear. Accordingly, throughput can be improved. Further, a semiconductor film is preferably irradiated with a laser light having an incidence angle θ)(0°&lt;θ&lt;90°). It is because that an interference of the laser can be prevented.

0054The crystalline semiconductor film formed in this manner is processed (or patterned) into a predetermined shape as shown in <figref idref="DRAWINGS">FIG. 1A</figref> to form an island shaped semiconductor film <b>102</b>. At a time of patterning, a photo resist is applied on the crystalline semiconductor film and a predetermined mask shape is exposed to form a mask. By using this mask, the crystalline semiconductor film can be patterned by a dry etching method.

0055Thereafter, a gate insulating film <b>104</b> is formed so as to cover the semiconductor film <b>102</b>. The gate insulating film <b>104</b> may be a single layer or a stacked layer. An insulating material which becomes the gate insulating film <b>104</b> may be an inorganic material or an organic material. For example, silicon oxide silicon nitride and silicon oxynitride can be used. Note that the surface of the island shaped semiconductor film is preferably washed with hydrofluoric acid or the like before forming the gate insulating film <b>104</b>. It is because that interface contamination of the semiconductor film and the gate insulating film adversely affects an electric characteristic of a thin film transistor. Therefore, the semiconductor film and the gate insulating film may be formed continuously without being exposed to atmospheric air, and then the semiconductor film and the gate insulating film may be patterned into predetermined shapes concurrently.

0056A conductive film which becomes a gate electrode <b>105</b> is formed on the semiconductor film <b>102</b> through the gate insulating film <b>104</b>. The gate electrode <b>105</b> may be a single layer or a stacked layer. The edge of the gate electrode <b>105</b> may be taper shaped. As the conductive film which becomes the gate electrode <b>105</b>, an element selected from Ta, W, Ti, Mo, Al or Cu; an alloy material or a compound material mainly containing the foregoing element, can be used.

0057An impurity region <b>103</b> is formed using the gate electrode <b>105</b> as a mask in a self alignment manner. In a case of forming an n-type thin film transistor, phosphine (PH₃) is added, and then an impurity region in which phosphorus (P) is added is formed. In a case of forming a p-type thin film transistor, diborane (B₂H₆) is added, and then an impurity region in which boron (B) is added, is formed.

0058The impurity region <b>103</b> is classified into a high concentration impurity region and a low concentration impurity region, in accordance with impurity concentration. For example, in a taper portion of the gate electrode <b>105</b>, there is less amount of addition of an impurity element; therefore a low concentration impurity region is formed and a high concentration impurity region can be formed in a region where the gate electrode <b>105</b> is not formed. A structure in which a gate electrode and a part of the impurity region are overlapped, is called a GOLD (Gate Overlapped Drain) structure.

0059In addition, a structure in which an insulator is provided at the side of the gate electrode <b>105</b>, a so-called offset structure, can also be used. In the offset structure, a distance between a channel formation region and the impurity region <b>103</b> can be set in accordance with the width of the insulator.

0060A first insulating film <b>106</b> is formed so as to cover the gate insulating film <b>104</b> and the gate electrode <b>105</b>. The first insulating film can be formed from any of silicon oxide, silicon nitride or silicon oxynitride. Specifically, it is preferable that the first insulating film be an insulating film containing hydrogen; therefore the first insulating film is preferably formed by a CVD method.

0061Thereafter, a heat treatment is preferably conducted in order to activate the impurity region <b>103</b>. The heat treatment is conducted under nitrogen atmosphere at 400 to 550° C. using a heating furnace, for example. Accordingly, a dangling bond and the like of the semiconductor film <b>102</b> can be reduced by hydrogen from the first insulating film <b>106</b>.

0062Then, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, a second insulating film <b>108</b> is formed so as to cover the first insulating film <b>106</b>. The flatness can be enhanced by the second insulating film <b>108</b>. The second insulating film <b>108</b> can be formed using an organic material or an inorganic material. As the organic material, polyimide; acrylic; polyamide; polyimide amide; resist; benzocyclobutene; siloxane; or polysilazane can be used. Siloxane has a skeleton structure formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group and aromatic hydrocarbon) is used. A fluoro group may also be used as a substituent. In addition, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed by a liquid material including a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. As the inorganic material, silicon oxide; silicon nitride; silicon oxynitride; or the like can be used. In addition, the second insulating film <b>108</b> may have a single layer structure or a stacked layer structure. Specifically when the second insulating film is formed using an organic material, the flatness is enhanced, whereas moisture or oxygen is absorbed by the organic material. In order to prevent this, the second insulating film may have a stacked layer structure in which an inorganic material is formed on an organic material.

0063Thereafter, an opening potion, a so-called contact hole <b>110</b>, is formed in the gate insulating film <b>104</b>, the first insulating film <b>106</b>, and the second insulating film <b>108</b>. The contact hole <b>110</b> can be formed by a dry etching method or a wet etching method. An etchant which can have a selection ratio between the gate insulating film <b>104</b>, the first insulating film <b>106</b>, and the second insulating film <b>108</b> and the semiconductor film <b>102</b> at the time of forming the contact hole <b>110</b>, is preferable as the etchant used for such etching methods. At this time, the edge of the second insulating film <b>108</b> around the contact hole <b>110</b> may be rounded off. Accordingly, disconnection of a conductive film which is subsequently formed can be prevented.

0064Note that a memory element is formed using interior of the contact hole <b>110</b> in the present invention, and therefore the diameter, the depth, the taper angle and the like of the contact hole <b>110</b> are determined. For example, the contact hole <b>110</b> at the side where the memory element is formed, is set to have a larger diameter as compared with the contact hole at the side where the memory element is not formed. For example, the diameter is set to be 1 to 3 μm.

0065Thereafter, a conductive film which becomes an electrode <b>109</b> is formed in the contact hole <b>110</b>. The electrode <b>109</b> can have a single layer structure or a stacked layer structure. The conductive film may be formed from an element of aluminum (Al); titanium (Ti); molybdenum (Mo); tungsten (W); or silicon (Si); or an alloy containing these elements. Also, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing zinc oxide of 2 to 20% can be used as the conductive film. Such the conductive film is formed by a sputtering method, a droplet discharging method or the like, and is patterned into a predetermined shape; therefore the electrode <b>109</b> is formed. Note that in an aspect of the present invention, the electrode <b>109</b> connected to the impurity region <b>103</b> functions as a source or drain electrode, and also functions as a lower electrode of the memory element. In the present invention, it is not necessary to newly form a conductive film as the lower electrode; therefore the number of steps can be reduced and cost can be reduced.

0066The steps up to this point are shown by a top view in <figref idref="DRAWINGS">FIG. 2A</figref>. As is clear from <figref idref="DRAWINGS">FIG. 2A</figref>, in order to keep the diameter of the contact hole <b>110</b> at the side where the memory element is formed large, the semiconductor film <b>102</b> may be patterned into an oblong shape. In addition, as shown in <figref idref="DRAWINGS">FIG. 2A</figref>, by patterning the conductive film, a wiring connected to the electrode is formed at the same time. For example, a word line is formed at the same time as the gate electrode <b>105</b>. A selection signal is inputted to the word line from a control circuit. In addition, a signal line is formed at the same time as the source electrode and the drain electrode.

0067The source electrode and the drain electrode are formed in this manner, and then a thin film transistor <b>107</b> can be completed.

0068As shown in <figref idref="DRAWINGS">FIG. 1C</figref>, an insulator <b>112</b> constituting a memory element is formed inside the contact hole <b>110</b>. The insulator <b>112</b> may have a thickness of 5 to 100 nm, preferably 10 to 60 nm.

0069The insulator <b>112</b> can be formed from an inorganic material or an organic material. Also, the insulator <b>112</b> can be formed from these materials by an evaporation method, a spin coating method, a droplet discharging method or the like. The insulator <b>112</b> may be formed from a material whose property is changed by an optical effect, a thermal effect or the like. For example, a material, whose property is changed by fusion by Joule heat, dielectric breakdown or the like and which can short-circuit the electrode <b>109</b> functioning as a lower electrode and an upper electrode formed thereafter, is preferable.

0070As the inorganic material, silicon oxide, silicon nitride, silicon oxynitride and the like are given. Dielectric breakdown is generated in such inorganic materials by controlling the film thickness; therefore a lower electrode and an upper electrode can be short-circuited to each other.

0071As the organic material, for example an aromatic amine based (in other words, including benzene ring-nitrogen bond) compound such as 4,4′-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (abbreviation: α-NPD), 4,4′-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (abbreviation: TPD), 4,4′4″-tris(N,N-diphenylamino)triphenylamine (abbreviation: TDATA), 4,4′4″-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (abbreviation: MTDATA), and 4,4′-bis[N-{4-(N,N-di-m-tolylamino)phenyl}-N-phenylamino]biphenyl (abbreviation: DNTPD); polyvinylcarbazole (abbreviation: PVK); a phthalocyanine compound such as phthalocyanine (abbreviation: H₂Pc), copper phthalocyanine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. These materials have high hole transporting properties.

0072In addition, as the organic compound material, for example a material formed from a metal complex or the like having a quinoline skeleton or a benzoquinoline skeleton, such as tris(8-quinolinolato)aluminum (abbreviation: Alq₃), tris(4-methyl-8-quinolinolato)aluminum (abbreviation: Almq₃), bis(10-hydroxybenzo[h]quinolinato)beryllium (abbreviation: BeBq₂), bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum (abbreviation: BAlq), or a metal complex having a oxazole-based ligand or a thiazole-based ligand, such as bis [2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX)₂) or bis[2-(2-hydroxyphenyl)benzothiazolato]zinc (abbreviation: Zn(BTZ)₂), can also be used. These materials have high electron transporting properties.

0073In order to change the properties of such organic materials by a thermal effect and the like, the glass-transition temperature (Tg) may be 80 to 300° C., preferably 100 to 250° C.

0074Furthermore, in addition to the metal complex, a compound such as 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation: PBD); 1,3-bis[5-(p-tert-buthylphenyl)-1,3,4-oxadiazole-2-yl]benzene (abbreviation: OXD-7); 3-(4-tert-buthylphenyl)-4-phenyl-5-(4-biphenylyl)-1,2,4-triazole (abbreviation: TAZ); 3-(4-tert-buthylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)1,2,4-triazole (abbreviation: p-EtTAZ); or bathophenanthroline (abbreviation: BPhen); or bathocuproin (abbreviation: BCP) can be used.

0075As one feature of a single layer structure or a stacked layer structure with the above materials, a light-emitting material such as 4-dicyanomethylene-2-methyl-6-[2-(1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]-4H-pyran (abbreviation: DCJT); 4-dicianomethylene-2-t-buthyl-6[2-(1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]-4H-pyran; periflanthene; 2,5-dicyano-1,4-bis[2-(10-methoxy-1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]benzene; N,N′-dimethylquinacridon (abbreviation: DMQd); coumarin 6; coumarin 545T; tris(8-quinolinolato)aluminum (abbreviation: Alq₃); 9,9′-bianthryl; 9,10-diphenylanthracene (abbreviation: DPA); 9,10-bis(2-naphthyl)anthracene (abbreviation: DNA); or 2,5,8,11-tetra-(tert-buthyl)perylene (abbreviation: IBP) can be used.

0076In a case of forming layer in which the above light-emitting material is dispersed, as a material which becomes a mother body, anthracene derivatives such as 9,10-di(2-naphthyl)-2-tert-buthylanthracene (abbreviation: t-BuDNA); carbazole derivatives such as 4,4-bis(N-carbazolyl)biphenyl (abbreviation: CBP); or a metal complex such as bis[2-(2-hydroxyphenyl)pyridinato]zinc (abbreviation: Znpp₂) or bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: ZnBOX) can be used. In addition, tris(8-quinolinolato)aluminum (abbreviation: Alq₃); 9,10-bis(2-naphthyl)anthracene (abbreviation: DNA); bis(2-methyl-8-quinolinolato)(4-phenylphenolato)aluminum (abbreviation: BAlq); or the like can be used.

0077In addition, a material in which metal oxide is mixed with the above organic materials and light-emitting materials may also be used. Note that the mixed material includes a state in which materials are mixed or a state in which the materials are stacked. Specifically, it indicates a state which is formed by a co-evaporation method using multiple evaporation sources.

0078In a case of mixing a substance having a high hole transporting property with a metal oxide, a vanadium oxide, a molybdenum oxide, a niobium oxide, a rhenium oxide, a tungsten oxide, a ruthenium oxide, a titanium oxide, a chromium oxide, a zirconium oxide, a hafnium oxide, and tantalum oxide can be used as the metal oxide.

0079In a case of mixing a substance having a high electron transporting property with a metal oxide, a lithium oxide, a calcium oxide, a sodium oxide, a kalium oxide and a magnesium oxide can be used as the metal oxide.

0080Also, as the insulator <b>112</b>, a material whose property is changed by an optical effect or a thermal effect, may be used; therefore a conjugated polymer in which a compound (photoacid generator) generating acidum by absorbing light is added, can also be used. As the conjugated polymer, polyacetylene group, polyphenylenevinylene group, polythiophene group, polyaniline group, polyphenyleneetylene group, and the like can be used. In addition, as the photoacid generator, arylsulfonium salt, aryliodonium salt, o-nitrobenzyltosylate, arylsulfonic acid, p-nitrobenzylester, sulfonylacetophenone group, Fe-arene complex PF₆salt, and the like can be used.

0081A top view of a state in which the insulator <b>112</b> is formed, is shown in <figref idref="DRAWINGS">FIG. 2B</figref>. As shown in <figref idref="DRAWINGS">FIG. 2B</figref>, the insulator <b>112</b> can be formed overall, however the insulator <b>112</b> can be formed selectively so as to cover the lower electrode, in the contact hole <b>110</b> region. In an aspect of the present invention, a memory element is formed inside the contact hole <b>110</b> region, and it can function as the memory element as long as the lower electrode and an upper electrode are not short-circuited to each other.

0082In addition, in this embodiment mode, the description is given focusing on one contact hole <b>110</b> region, however the memory element can be formed using the other contact hole.

0083Then, a conductive film which becomes an upper electrode <b>113</b> is formed covering the insulator <b>112</b>. The conductive film can be formed in the same manner as the electrode <b>109</b>, however the conductive film is not necessarily formed using the same materials and the same steps. The upper electrode <b>113</b> is electrically connected to a control circuit, and writing operation or reading operation of the memory element can be performed by the control circuit, in accordance with a change in a state of the insulator <b>112</b>. Specifically, the memory element can have a state in which the lower electrode and the upper electrode are not short-circuited (referred to as an initial state), and a state in which the lower electrode and the upper electrode are short-circuited (referred to as a short-circuited state). By this difference in the state, the memory element can have information of “0” or “1”. In the short-circuited state, the lower electrode and the upper electrode can be short-circuited at the side surface or the top surface of the contact hole, in addition to that the upper electrode and the lower electrode are short-circuited at the bottom surface of the contact hole. The thickness of the insulator at the side surface of the contact hole or a boundary region between the side surface and the top surface often becomes thin at a time of forming a film. Therefore, the upper electrode and the lower electrode can be easily short-circuited to each other.

0084<figref idref="DRAWINGS">FIG. 15</figref> shows a voltage-current characteristic of a memory element. In the initial state A, current does not flow in a memory element when certain voltage (V_B) or more is not applied. On the other hand, in the short-circuited state B, current flows in a memory element when even a little voltage (V_A: V_B&lt;V_A) is applied. Information of “0” or “1” can be provided in accordance with the difference in a voltage value. Note that voltage V_Ais a voltage value at the intersecting point of the voltage-current characteristic C of the thin film transistor <b>107</b> and the initial state A. Also, voltage V_Bis a voltage value at the intersecting point of the voltage-current characteristic C of the thin film transistor <b>107</b> and the short-circuited state B. The voltage value is read by the control circuit; therefore information of “0” or “1” can be provided. These operations will be described in detail in following embodiment modes.

0085Thereafter, a passivation film <b>115</b> is preferably formed as shown in <figref idref="DRAWINGS">FIG. 1D</figref>. The passivation film <b>115</b> can have a single layer structure or a stacked layer structure, and an inorganic material is preferably used. Especially, the passivation film <b>115</b> is preferably formed using silicon nitride or silicon oxynitride. It is because that an insulating film containing nitrogen has an effect to prevent an alkali metal from entering.

0086In order to short-circuit the lower electrode and the upper electrode, the thin film transistor <b>107</b> is turned on in accordance with the selection signal inputted from the word line, current flows between the source electrode and the drain electrode, and then the property of the insulator <b>112</b> is changed by the current flowing. For example, the property, in other words the state, of the insulator <b>112</b> is changed by Joule heat generated by the current flowing. In addition, dielectric breakdown is generated in the insulator <b>112</b> and the state is changed by the current flowing. The lower electrode and the upper electrode can be short-circuited by using such the change in the state.

0087As described above, the memory element controlled by the thin film transistor <b>107</b> can be formed. The memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

0088The case of using round shape as a contact hole has been described, however the shape is not limited to this, and an elliptical shape as shown in <figref idref="DRAWINGS">FIG. 16A</figref> and an oblong shape as shown in <figref idref="DRAWINGS">FIG. 16B</figref> may also be used.

Embodiment Mode 2

0089In this embodiment mode, a mode in which a plurality of memory elements are formed inside a contact hole, will be described.

0090As shown in <figref idref="DRAWINGS">FIG. 3</figref>, contact holes <b>110</b><i>a </i>and <b>110</b><i>b </i>are formed in the second insulating film <b>108</b> in the same manner as Embodiment Mode 1. The contact holes <b>110</b><i>a </i>and <b>110</b><i>b </i>can be formed by a dry etching method or a wet etching method.

0091A top view of this state is shown in <figref idref="DRAWINGS">FIG. 4</figref>. As shown in <figref idref="DRAWINGS">FIG. 3</figref> and <figref idref="DRAWINGS">FIG. 4</figref>, the diameter, the depth, the taper angle and the like of the contact holes <b>110</b><i>a </i>are equal to the diameter, the depth, the taper angle and the like of the contact hole <b>110</b><i>b </i>in this embodiment mode, however it is not necessarily limited thereto. In other words, in an aspect of the present invention, a memory element is formed inside a contact hole and a source or drain electrode functions as a lower electrode of the memory element; therefore the shape or the number of the contact hole are not limited. The memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element; therefore the number of steps can be reduced and cost can be reduced.

0092After that, an insulator <b>112</b>, an upper electrode <b>113</b> and a passivation film <b>115</b> are formed in the same manner as Embodiment Mode 1.

0093Since the memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 3

0094In this embodiment mode, a mode in which surface modification is carried out to a formation surface before forming an insulator <b>112</b>, will be described.

0095As shown in <figref idref="DRAWINGS">FIG. 5A</figref>, up to forming an electrode <b>109</b> is the same as Embodiment Mode 1. Then, the surface modification is carried out to the entire surface of the electrode <b>109</b> and the second insulating film <b>108</b>. In order to perform the surface modification to the entire surface, a plasma treatment may be conducted in oxygen atmosphere. Accordingly, the state of the surface shown by <b>125</b> is improved (it is referred to as surface modification).

0096The thickness of an insulator <b>112</b> is preferably thin in order to make it easy for a lower electrode and an upper electrode to be short-circuited to each other. For example, the insulator <b>112</b> is formed using an inorganic material, and the thickness of the insulator <b>112</b> may be 5 to 100 nm, preferably 10 to 60 nm. Therefore, when the insulator <b>112</b> is formed inside a contact hole <b>110</b> and the like, especially disconnection at the edge of the contact hole <b>110</b> is concerned. By conducting an oxygen plasma treatment to the formation surface of the insulator <b>112</b> like this embodiment mode, adhesiveness can be improved, and the disconnection is preferably prevented. Thus, it becomes easy to form the insulator <b>112</b> by carrying out the surface modification to the formation surface of the insulator <b>112</b>, which is preferable.

0097As a means for carrying out such surface modification, a film having high adhesiveness with the insulator <b>112</b> and the electrode <b>109</b> may be formed, in addition to the oxygen plasma treatment. It is because that a means to improve the adhesiveness of the insulator <b>112</b> can have an effect to prevent the disconnection of the insulator <b>112</b>.

0098In order to prevent the disconnection, it is preferable that the insulator <b>112</b> be formed by an evaporation method. It is because that accuracy of film formation to the side surface of the contact hole <b>110</b> is high when the insulator <b>112</b> is formed by an evaporation method as compared with a spin coating method.

0099After that, as shown in <figref idref="DRAWINGS">FIG. 5B</figref>, an upper electrode <b>113</b> and a passivation film <b>115</b> are formed in the same manner as Embodiment Mode 1.

0100The memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 4

0101In this embodiment mode, a mode in which a surface modification is selectively carried out before forming an insulator <b>112</b>, which is different from the above embodiment modes, will be described.

0102As shown in <figref idref="DRAWINGS">FIG. 6A</figref>, a surface modification is carried out at least to a surface of an electrode <b>109</b>. For example, a conductive film which becomes the electrode <b>109</b> is formed, and the surface modification is carried out by scratching a surface of the conductive film by a sputtering method. For example, an element substrate over which the conductive film is formed, is placed in a film formation chamber, and a treatment is carried out at the condition that the surface of the conductive film is scratched. For example, the treatment having pressure of 0.6 Pa ( 0.6/133 Torr) to 1.0 Pa ( 1/133 Torr) and power of 200 to 400 W is conducted for 3 to 15 minutes. Thereafter, the conductive film is patterned into a predetermined shape; therefore an electrode <b>109</b> having a surface <b>126</b> only to which the surface modification is carried out, can be formed. As described above, an adhesiveness of the insulator <b>112</b> can be held by the electrode <b>109</b> having the modified surface.

0103In this embodiment mode, since it is acceptable as long as the insulator <b>112</b> is formed inside the contact hole <b>110</b> without disconnection, only a selective surface modification is necessary for the formation surface of the insulator <b>112</b>. In addition, it is preferable that the insulator <b>112</b> be formed by an evaporation method in order to prevent the disconnection. It is because that accuracy of film formation to the side surface of the contact hole <b>110</b> is high when the insulator <b>112</b> is formed by an evaporation method as compared with a spin coating method.

0104In addition to scratching the formation surface of the insulator <b>112</b> using a sputtering method, the conductive film may be formed at the condition that the conductive film has roughness of its surface, asperity is formed on the formation surface of the conductive film and the conductive film may be formed so as to follow the asperity, and a scratch may be put physically using a dry etching method, a frost processing method, a sandblast method or the like. In a case of forming the conductive film by a sputtering method, the process can be simplified by also conducting a sputtering treatment to scratch the formation surface in the same film formation chamber.

0105After that, as shown in <figref idref="DRAWINGS">FIG. 6B</figref>, an upper electrode <b>113</b> and a passivation film <b>115</b> are formed in the same manner as Embodiment Mode 1.

0106Since the memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 5

0107In this embodiment mode, a mode in which an insulator <b>112</b> is formed by a droplet discharging method, will be described.

0108As shown in <figref idref="DRAWINGS">FIG. 7A</figref>, an electrode <b>109</b> is formed inside a contact hole <b>110</b> in the same manner as Embodiment Mode 1. Then, a droplet (dot) having a material for the insulator <b>112</b> is dropped inside the contact hole <b>110</b> from a predetermined nozzle <b>150</b>. Such the droplet discharging method is also called an ink jetting method. The droplet <b>151</b> may be only a material for the insulator <b>112</b> or may be a solvent in which the material is dispersed.

0109Note that a surface modification may be carried out to a formation surface of the insulator <b>112</b> before forming the insulator <b>112</b> as shown in Embodiment Mode 3 or 4.

0110Thereafter, the insulator <b>112</b> is formed inside the contact hole <b>110</b> as shown in <figref idref="DRAWINGS">FIG. 7B</figref>. At this time, the insulator <b>112</b> is formed so that the electrode <b>109</b> and an upper electrode which is formed afterward are not short-circuited inside the contact hole <b>110</b>. Therefore, it is not necessary that the contact hole <b>110</b> is filled with the insulator <b>112</b>. In addition, by using surface tension, the insulator <b>112</b> can be thinly formed at the edge of the electrode <b>109</b>. Accordingly, the edge of the electrode <b>109</b> and an upper electrode can be easily short-circuited.

0111Wettability with respect to the droplet <b>151</b> may be decreased at the periphery of the edge of the electrode <b>109</b>. Accordingly, the droplet <b>151</b> can be selectively dropped on the electrode <b>109</b>. As such a method for decreasing the wettability, a silane coupling agent may be selectively applied. As the silane coupling agent, a fluorine-based silane coupling agent (fuloroalkyl silane (FAS)) having a fluoroarkyl group is used. As a representative FAS, fluoroalkyl silane such as heptadecafluoro tetrahydrodecyl triethoxysilane, heptadecafluoro tetrahydrodecyl trichlorosilane, tridecafluoro tetrahydrooctyl trichlorosilane, or trifluoropropyl trimethoxysilane can be given.

0112It is preferable that the insulator <b>112</b> formed by a droplet discharging method be baked in some cases. Especially in a case that the droplet <b>151</b> includes solvent, the solvent may be removed by a heat treatment, and then the insulator <b>112</b> is baked.

0113As shown in <figref idref="DRAWINGS">FIG. 7C</figref>, an upper electrode <b>113</b> is formed. A droplet (dot) <b>153</b> having a material for the upper electrode <b>113</b> is dropped by using a nozzle <b>152</b>, and the upper electrode <b>113</b> is formed. In a case of forming the upper electrode <b>113</b> by a droplet discharging method, gold (Au); silver (Ag); copper (Cu); platinum (Pt); palladium (Pd); tungsten (W); nickel (Ni); tantalum (Ta); bismuth (Bi); lead (Pb); indium (In); tin (Sn); zinc (Zn); titanium (Ti); aluminum (Al); alloy including these elements; a dispersant nanoparticle of these elements; or a microparticle of silver halide is preferable, as the material.

0114In this embodiment mode, the upper electrode <b>113</b> is formed by a droplet discharging method, however the present invention is not limited to this, and a sputtering method or an evaporation method may also be used. In addition, the electrode <b>109</b> may be formed by a droplet discharging method.

0115It is preferable that the upper electrode <b>113</b> formed by a droplet discharging method be baked in some cases. Especially in a case that the droplet <b>153</b> includes solvent, the solvent may be removed, and then the upper electrode <b>113</b> may be baked.

0116As described above, by using a droplet discharging method, use efficiency of a material is increased, and it becomes possible that cost is reduced, manufacturing time is shortened, and the amount of a waste liquid treatment is reduced. Accordingly, manufacturing cost of the memory element can be reduced.

0117After that, a passivation film <b>115</b> is formed.

0118The memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 6

0119In this embodiment mode, a mode of a contact hole structure which is different from the above embodiment modes, will be described.

0120As shown in <figref idref="DRAWINGS">FIG. 8</figref>, a contact hole is formed and an electrode <b>109</b> is formed in the same manner as Embodiment Mode 1. At this time, a word line is formed as described above, however other wirings <b>209</b> can be formed. In order to increase added value of a memory element, a lot of wirings are required. In this case, forming a third insulating film <b>130</b> makes it possible to increase the degree of freedom in the layout and size of the wiring, the contact hole, the memory element, and the like. It is needless to say that the third insulating film <b>130</b> can be provided even in a case that the wiring <b>209</b> is not formed.

0121The third insulating film <b>130</b> can be formed using the similar material or method to the second insulating film <b>108</b> shown in Embodiment Mode 1.

0122Then, a contact hole <b>210</b> is formed in the third insulating film <b>130</b> according to the position of the contact hole formed in the second insulating film <b>108</b>. Thereafter, an insulator <b>112</b>, an upper electrode <b>113</b>, and a passivation film <b>115</b> are formed inside the contact hole <b>210</b>, and a memory element is completed in the same manner as Embodiment Mode 1. At this time, the edge of the third insulating film <b>130</b> around the contact hole <b>210</b> is preferably rounded off. It is because that the contact hole <b>210</b> is considered to be deeper as compared with the contact hole <b>110</b>, and an effect to prevent disconnection of the insulator <b>112</b> or the upper electrode <b>113</b> can be expected.

0123This embodiment mode can be freely combined with the above embodiment modes. For example, surface modification may be carried out before forming the insulator <b>112</b>, or the insulator <b>112</b>, the upper electrode <b>113</b> and the like may be formed by a droplet discharging method.

0124The memory element is formed inside the contact hole and the source or drain electrode functions as the lower electrode of the memory element in the present invention; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 7

0125In this embodiment mode, a mode in which an amorphous semiconductor film is used for a thin film transistor, will be described.

0126As shown in <figref idref="DRAWINGS">FIG. 9</figref>, a bottom gate type in which a gate electrode is provided on the lower side can be applied to a thin film transistor using an amorphous semiconductor film. A conductive film which becomes a gate electrode <b>205</b> is formed on a substrate <b>100</b> and is patterned into a predetermined shape. Thereafter, an insulating film which becomes a gate insulating film <b>204</b> is formed covering the gate electrode <b>205</b>. Then, an amorphous semiconductor film <b>206</b> and an n-type semiconductor film <b>208</b> are formed sequentially, and are patterned into predetermined shapes. Then, a conductive film which becomes a source or drain electrode <b>211</b> is formed, and is patterned into a predetermined shape. The n-type semiconductor film <b>208</b> is etched using the source or drain electrode <b>211</b>, and a part of the amorphous semiconductor film <b>206</b> is etched at the same time. Such the structure of the thin film transistor, in which a part of the amorphous semiconductor film is etched, can be called a channel etch type. In this way, a thin film transistor <b>207</b> having an amorphous semiconductor film can be formed.

0127Thereafter, a first insulating film <b>212</b> functioning as a protective film is preferably formed. In a channel etch structure, a part of the amorphous semiconductor film <b>206</b> is exposed, and therefore the first insulating film <b>212</b> may be provided to prevent an impurity element, moisture, or the like from entering. The first insulating film <b>212</b> achieving such the function may be formed using an insulating film having nitrogen, typically silicon nitride.

0128Then, a second insulating film <b>108</b> is formed and a contact hole <b>110</b> is formed in the same manner as Embodiment Mode 1. Then, an electrode <b>109</b> is formed inside the contact hole <b>110</b>. In this embodiment mode, the electrode <b>109</b> functions as a lower electrode.

0129Thereafter, an insulator <b>112</b>, an upper electrode <b>113</b>, and a passivation film <b>115</b> are formed in the same manner as Embodiment Mode 1.

0130This embodiment mode can be freely combined with the above embodiment modes. For example, surface modification may be carried out before forming the insulator <b>112</b>, and the insulator <b>112</b>, an upper electrode <b>113</b> and the like may be formed by a droplet discharging method.

0131The memory element is formed inside the contact hole and the electrode <b>109</b> functions as the lower electrode of the memory element in the present invention; further a crystallization step is not further necessary. Therefore, the number of steps can be reduced and cost can be reduced.

Embodiment Mode 8

0132In this embodiment mode, a structure of a device (memory device) having a memory element manufactured by the above embodiment modes, will be described.

0133As shown in <figref idref="DRAWINGS">FIG. 10</figref>, a memory device <b>508</b> has a memory cell array <b>506</b> and a control circuit. The control circuit has a column decoder <b>501</b>, a row decoder <b>502</b>, a reading circuit <b>504</b>, a writing circuit <b>505</b>, and a selector <b>503</b>.

0134The memory cell array <b>506</b> has a bit line Bm (m=1 to x), a word line Wn (n=1 to y), and a memory element <b>507</b> at an intersecting point of the bit line with the word line. In an aspect of the present invention, the memory element is manufactured by the above embodiment modes. In addition, the bit line is controlled by the selector <b>503</b>, and the word line is controlled by the row decoder <b>502</b>.

0135The column decoder <b>501</b> receives an address signal designating a column of the memory cell array, and a signal is given to the selector <b>503</b> of the designated column. The selector <b>503</b> receives the signal of the column decoder <b>501</b>, and a bit line of the designated column is selected. The row decoder <b>502</b> receives an address signal designating a row of the memory cell array, and a word line of the designated row is selected. One memory element <b>507</b> corresponding to the address signal is selected by the above operation. The reading circuit <b>504</b> reads data which the selected memory element has, and the data is preferably amplified and outputted. The writing circuit <b>505</b> produces voltage which is necessary for writing, a short-circuit state is made by applying the voltage to the selected memory element, and the data is written in.

0136A structure of the writing circuit <b>505</b> is shown in <figref idref="DRAWINGS">FIG. 11</figref>. The writing circuit <b>505</b> has a voltage generating circuit <b>701</b>, a timing control circuit <b>702</b>, switches SW<b>0</b> and SW<b>1</b>, and an output terminal Pw. The voltage generating circuit <b>701</b> is composed of a boosting circuit and the like, and voltage V<b>1</b> which is necessary for writing is produced, and is outputted from an output Pa. The timing control circuit <b>702</b> produces signals S<b>0</b> and S<b>1</b> controlling the switches SW<b>0</b> and SW<b>1</b> respectively, from a writing control signal (WE), a data signal (DATA), a clock signal (CLK) and the like, and the signals S<b>0</b> and S<b>1</b> are outputted from outputs P<b>0</b> and P<b>1</b>, respectively. Output voltage Vw from the output Pw of the writing circuit can be converted depending on any of connection status of the switch, which is a connection of the switch SW<b>0</b> with the ground or a connection of the SW<b>1</b> with the output Pa of the voltage generating circuit <b>701</b>.

0137Then, writing operation in a case of an initial state “0” which does not change conductivity of a memory element and a short-circuit state “1” which changes the conductivity of the memory element, is described. When WE becomes Hi (high voltage which allows writing), the column decoder <b>501</b> which receives an address signal designating a column gives a signal to the selector <b>503</b> of the designated column, and the selector <b>503</b> connects a bit line of the designated column to the output Pw of the writing circuit. A bit line which is not designated is non-connection (floating) state, and the output voltage Vw of the writing circuit is V<b>1</b>. In the same way, the row decoder <b>502</b> which receives an address signal designating a row, applies voltage V<b>2</b> to a word line of the designated row and applies 0V to a word line which is not designated. By the above operation, one memory element <b>507</b> corresponding to the address signal is selected. At this time, 0V is applied to an upper electrode.

0138At the same time, by receiving DATA=Hi, the voltage generating circuit <b>701</b> can produce voltage V<b>1</b> and output the voltage V<b>1</b> from the output Pa. The timing control circuit <b>702</b> can produce the signals S<b>0</b> and S<b>1</b> controlling the switches SW<b>0</b> and SW<b>1</b> from WE, DATA, CLK, power supply voltage (VDD), and the like, and output the signals S<b>0</b> and S<b>1</b> from the outputs P<b>0</b> and P<b>1</b>. The switches SW<b>0</b> and SW<b>1</b> are converted by the signals, and the writing circuit <b>505</b> can output the voltage V<b>1</b> as the output voltage Vw from the output Pw.

0139In the selected memory element, by the above operation, voltage V<b>2</b> is applied to the word line, the voltage V<b>1</b> is applied to the bit line, and 0V is applied to the upper electrode. Then, the impurity region of the thin film transistor <b>107</b> or <b>207</b> becomes conductive, and the voltage V<b>1</b> of the bit line is applied to the lower electrode of the memory element. Accordingly, the conductivity of the memory element changes and becomes a short-circuit state, and “1” is written in.

0140When WE becomes Lo (low voltage which inhibits writing), all of the word lines become 0V, and all of the bit lines and the upper electrode become floating states. At this time, the timing control circuit produces Lo as the signals S<b>0</b> and S<b>1</b>, and outputs them from the outputs P<b>0</b> and P<b>1</b>. The output Pw becomes a floating state. By the above operation, writing is not performed.

0141Next, writing of “0” is described. The writing of “0” does not change the conductivity of the memory element, and it does not apply voltage to the memory element, in other words it is realized by maintaining an initial state. First, when WE becomes Hi in the same manner as the writing of “1”, the column decoder <b>501</b> which receives the address signal designating a column gives a signal to the selector <b>503</b> of the designated column, and the selector <b>503</b> connects the bit line of the designated column to the output Pw of the writing circuit. At this time, a bit line which is not designated becomes a floating state. In the same manner, the row decoder <b>502</b> which receives the signal designating a row applies voltage V<b>2</b> to the word line of the designated row, and applies 0V to a word line which is not designated. By the above operation, one memory element <b>507</b> corresponding to the address signal is selected. At this time, 0V is applied to the upper electrode.

0142At the same time, the timing control circuit <b>702</b> receives DATA=Lo, and generates control signals S<b>0</b>=Hi, S<b>1</b>=Lo, and outputs the control signals from the outputs P<b>0</b> and P<b>1</b>, respectively. By the control signals, the switch SW<b>0</b> is turned on and the switch SW<b>1</b> is turned off, and 0V is outputted as the output voltage Vw from the output Pw.

0143In the selected memory cell, by the above operation, the voltage V<b>2</b> is applied to the word line, and 0V is applied to the bit line and a common electrode. Then, voltage is not applied to the memory element and the conductivity is not changed; therefore an initial state “0” is maintained.

0144When WE becomes Lo, all of the word lines become 0V, and all of the bit lines and the upper electrode become floating states. At this time, the timing control circuit produces Lo as the signals S<b>0</b> and S<b>1</b>, and outputs them from the outputs P<b>0</b> and P<b>1</b>, respectively. The output Pw becomes a floating state.

0145As described above, writing of “1” or “0” can be performed.

0146Next, reading operation is described. <figref idref="DRAWINGS">FIG. 12</figref> shows a memory device in which a necessary part to describe reading is extracted, and other structures are similar to <figref idref="DRAWINGS">FIG. 10</figref>. The reading circuit <b>504</b> which the memory device has, has a voltage generating circuit <b>307</b>, a sense amplifier <b>308</b>, a resistor element <b>309</b>, a data output circuit <b>310</b> and an input-output terminal Pr, and a point inputting to the sense amplifier <b>308</b> from between the resistor element <b>309</b> and the input-output terminal Pr is referred to as α.

0147The voltage generating circuit <b>307</b> produces voltage Vread and Vref which are necessary for the reading operation, and the voltage Vread and Vref are outputted from P<b>1</b> and P<b>2</b>, respectively. Low voltage is used to read data; therefore power the supply voltage (VDD) can be used as the voltage Vread. The voltage Vref is lower than the voltage Vread, and is produced by a resistor division of the power supply voltage and the ground voltage. Thus, the voltage generating circuit <b>307</b> which the reading circuit <b>504</b> has, has a different structure from the voltage generating circuit which the writing circuit <b>505</b> has. The sense amplifier <b>308</b> compares the voltage difference between the point cc and the voltage Vref, and outputs the result. The data output circuit <b>310</b> is controlled by a reading control signal (RE), and data which the memory element has is acquired from the output of the sense amplifier <b>308</b>, and the date is amplified to be outputted.

0148Next, an operation to read the data which the memory element <b>517</b> has in the m-th column and the n-th row, is described. First, the column decoder <b>501</b> which receives the address signal designating a column gives a signal to the selector <b>503</b> in the m-th column, and the selector <b>503</b> connects the bit line Bm in the m-th column to the input-output terminal Pr of the reading circuit <b>504</b>. At this time, a bit line which is not designated becomes a floating state. In the same manner, the row decoder <b>502</b> which receives the address signal designating a row applies voltage Vread to the word line Wn in the n-th row, and applies 0V to a word line which is not designated. At the same time, the voltage Vread and Vref are outputted from the outputs P<b>1</b> and P<b>2</b> of the voltage generating circuit <b>307</b>, respectively, and 0V is applied to an upper electrode <b>113</b>. By the above operation, a state in which the voltage Vread is applied to series resistance of a resistor element <b>309</b> and the memory element <b>517</b> is obtained, and the voltage of the point a takes a value which is divided by resistor which the resistor element <b>309</b> and the memory element <b>517</b> have.

0149Here, in order to describe voltage which can be taken by the point a, <figref idref="DRAWINGS">FIG. 15</figref> is again referred. The voltage which can be taken by the point a corresponds to a voltage value which is a horizontal axis. A characteristic A in <figref idref="DRAWINGS">FIG. 15</figref> is an I-V characteristic of the memory element in which “1” is written in, a characteristic B is an I-V characteristic of the memory element in which “0” is written in, and a characteristic C is an I-V characteristic of the thin film transistor. As for the characteristic A of the memory element in which “1” is written in, an upper electrode and a lower electrode are short-circuited and an electric resistance of the memory element is small; therefore a current value is drastically increased even when the voltage of the point a is small. On the other hand, as for the characteristic B of the memory element in which “0” is written in, the memory element shows a diode characteristic; therefore a current value finally begins to increase when the voltage of the point a takes a certain value or more. As for the characteristic C of the thin film transistor, a current value decreases when the voltage of the point a is increased, and the current value becomes 0 when the voltage of the point a is Vread.

0150According to <figref idref="DRAWINGS">FIG. 15</figref>, the voltage which can be taken by the point a can be described as follows. When “1” is written in the memory element, voltage V_Aof an intersecting point A of the I-V characteristic A of the memory element in which “1” is written in with the I-V characteristic C of the thin film transistor, becomes a voltage of the point α. Also, when “0” is written in the memory element, voltage V_Bof an intersecting point B of the I-V characteristic B of the memory element in which “0” is written in with the I-V characteristic C of the thin film transistor, becomes a voltage of the point α.

0151The sense amplifier <b>308</b> has a function to compare the amount of the voltage of the point a with Vref. Here, the voltage Vref is larger than the voltage V_Aand smaller than the voltage V_B, and preferably is (VA+VB)/2. In a case that the sense amplifier <b>308</b> finds the voltage of the point a is smaller than Vref by setting the voltage as described above, the voltage of the point a is considered to be the voltage V_A, and it shows that “1” is written in the memory element. On the other hand, in a case that the sense amplifier finds the voltage of the point a is larger than Vref, the voltage of the point a is considered to be the voltage V_B, and it shows that “0” is written in the memory element.

0152In the case that the voltage of the point a is smaller than Vref, the sense amplifier <b>308</b> outputs a signal showing “1”, and in the case that the voltage of the point a is larger than Vref, the sense amplifier <b>308</b> outputs a signal showing “0”. The data output circuit <b>310</b> has a function to load data from the output signal of the sense amplifier <b>308</b> in accordance with RE inputted from an exterior portion and to output the data by amplifying. By the above operation, reading can be performed.

0153In this embodiment mode, the resistance value of the memory element is read by replacing to the amount of the voltage, however the present invention is not limited to this. For example, a method by which the resistance value of the memory element is read by replacing to the amount of the current and a method by which the bit line is precharged, can also be adopted.

0154The control circuit having the memory cell array <b>506</b>, the column decoder <b>501</b>, the row decoder <b>502</b>, the reading circuit <b>504</b>, the writing circuit <b>505</b> and the selector <b>503</b>, can be formed by using a transistor which is formed on a same substrate. For example, the memory cell array and the control circuit can be formed using a thin film transistor formed on a glass substrate. Also, the control circuit can be formed by using an integrated circuit (hereinafter, referred to as an IC chip) formed using a silicon wafer. In this case, the IC chip may be mounted on a substrate on which the memory cell array is formed. Especially in a case of forming the memory cell array by using a thin film transistor using an amorphous semiconductor film, the control circuit may be formed using the IC chip.

Embodiment Mode 9

0155In this embodiment mode, a structure of a circuit having a memory element will be described.

0156As shown in <figref idref="DRAWINGS">FIG. 13A</figref>, one cell of a circuit having a memory element has a transistor <b>401</b> and a memory element <b>402</b>. In the transistor <b>401</b>, a gate electrode is connected to a word line Wn and one of the source and drain electrodes is connected to a bit line Bm, and the other is connected to the memory element <b>402</b>. As the transistor <b>401</b>, the thin film transistors <b>107</b> and <b>207</b> described in the above embodiment modes can be used, and a conductive film which becomes either a source electrode or a drain electrode functions as a lower electrode of the memory element <b>402</b>. As described above, the memory element <b>402</b> has a structure in which an insulator and an upper electrode are sequentially stacked over the lower electrode. An upper electrode <b>403</b> of the memory element <b>402</b> can be shared with an upper electrode of the memory element of each cell, and at the time of writing and reading, certain amount of voltage is applied.

0157The memory element <b>402</b> which can be selected by the transistor <b>401</b> can have an initial state and a short-circuit state, and “0” and “1” can be shown in accordance with the state.

0158As described above, the memory element <b>402</b> may have an insulator which shows a diode characteristic which is different before and after the voltage application. Therefore, as shown in <figref idref="DRAWINGS">FIG. 13B</figref>, a memory element <b>412</b> may constitute a memory circuit using a cell connected to a diode element <b>411</b>. A structure in which either a source electrode or a drain electrode of a transistor is connected to a gate electrode can be adopted to the diode element <b>411</b>; therefore a conductive film which becomes either a source electrode or a drain electrode can function as a lower electrode of the memory element <b>402</b>.

0159The memory element is formed inside the contact hole, and the source or drain electrode functions as the lower electrode of the memory element; therefore the number of steps can be reduced and cost can be reduced.

Embodiment Mode 10

0160In this embodiment mode, a mode of a semiconductor device which has a memory device, a control circuit and an antenna, and which transmits and receives information by radio, a so-called RFID, will be described.

0161<figref idref="DRAWINGS">FIG. 14</figref> shows a structure of a semiconductor device of the present invention. A semiconductor device <b>601</b> includes a resonance circuit <b>602</b> having an antenna and a resonant capacitor; a power supply circuit <b>603</b>; a clock generating circuit <b>604</b>; a demodulation circuit <b>605</b>; a control circuit <b>606</b>; a memory device <b>607</b>; an encoding circuit <b>608</b>; and a modulation circuit <b>609</b>. Note that the semiconductor device is not limited to the above structure, and the semiconductor device has a central processing unit (CPU), a congestion control circuit, and the like in some cases. In addition, the semiconductor device <b>601</b> is not limited to the structure having an antenna, and the semiconductor device may have only a wiring which connects an antenna. In this case, when information is transmitted to and received at the semiconductor device, an antenna which is separately provided, is used by connecting to the wiring. In other words, it is a contact type semiconductor device.

0162The semiconductor device <b>601</b> of the present invention has the resonance circuit <b>602</b> having an antenna; therefore electric power is supplied by a radio wave generated from a read/write <b>610</b>, and information can be transmitted to and received at the read/write <b>610</b> by radio. The read/write <b>610</b> is connected to a computer <b>612</b> through a communication line <b>611</b>, and electric power is supplied to the semiconductor device <b>601</b>, and information is transmitted to and received at the semiconductor device <b>601</b> under the control of the computer <b>612</b>.

0163The resonance circuit <b>602</b> receives the radio wave generated from the read/write <b>610</b>, and generates induced voltage. The induced voltage includes information transmitted from the read/write <b>610</b> as well as becoming electric power of the semiconductor device <b>601</b>. Power supply circuit <b>603</b> rectifies the induced voltage generated to the resonance circuit <b>602</b> in diode, and it is stabilized using a capacitor to be supplied to each circuit. The clock generating circuit <b>604</b> produces a clock signal of necessary frequency based on the induced voltage generated to the resonance circuit <b>602</b>. The demodulation circuit <b>605</b> demodulates data from the induced voltage generated to the resonance circuit <b>602</b>. The control circuit <b>606</b> controls the memory device <b>607</b>. Therefore, the control circuit <b>606</b> includes an information determination circuit and the like which reads data from the read/write <b>610</b> as well as producing a memory control signal. The memory device <b>607</b> has a writing circuit or a reading circuit. In addition, the memory device <b>607</b> holds data which is specific to the semiconductor device <b>601</b>. Here, the memory device <b>607</b> is manufactured as shown in the above embodiment modes. The encoding circuit <b>608</b> converts the data included in the memory device <b>607</b> into an encoded signal. The modulation circuit <b>609</b> modulates a carrier wave based on the encoded signal.

0164This embodiment mode shows an example in which electric power is supplied to the semiconductor device <b>601</b> from the read/write <b>610</b>, however the present invention is not limited to this mode. For example, the semiconductor device <b>601</b> has a battery and the like inside, and the electric power is supplied by the battery, and information can be transmitted to and received at the read/write by radio.

0165Conductivity of even a small-sized memory element can be changed with low voltage and short voltage application time, by continuously applying voltage of multiple steps to the memory element. Also, consumption current at a time of writing can be reduced, and the time when the current consumption becomes a maximum level can be shortened by a means of the present invention; therefore a downsized voltage generating circuit and a downsized semiconductor device which the writing circuit has, can be realized. When high pulse voltage is applied to a memory element, variation in a variation amount of the conductivity is occurred, and the reliability of the semiconductor device is decreased. However, by continuously applying the voltage of the multiple steps like the present invention, the variation amount of the conductivity of the memory element becomes constant, and the reliability of the semiconductor device can be increased. Furthermore, an organic compound is used for a material for the memory element in the present invention; therefore a semiconductor device can be manufactured over a large-sized glass substrate or a flexible substrate with a low-temperature process, and an inexpensive semiconductor device can be provided.

0166Note that this embodiment mode can be freely combined with the above embodiment modes.

0167The memory element is formed inside the contact hole, and the source or drain electrode functions as the lower electrode of the memory element; therefore the number of steps can be reduced and cost can be reduced.