Memristive adaptive resonance networks

BACKGROUND

p-0002Artificial neural networks attempt to replicate the structure and/or function of biological neural networks. Biological neural networks typically include a number of neurons which are interconnected by chemical synapses. These chemical synapses are specialized junctions through which neurons transmit signals within the biological neural network. The combination of neurons and synapses provide for biological computations that underlie perceptions, thought, and learning. As the biological neural network is exposed to an input stimulus, some of the neurons and/or synapses undergo a self-learning process using locally available information. This self learning allows the network to adapt to new stimulus while retaining a memory of previous stimulus.

p-0003Implementing an artificial neural network within a computer architecture can be challenging. The elementary components of a silicon based computer, the capacitor, resistor, inductor and transistor, do not have intrinsic memory capabilities analogous to neurons or synapses. Consequently, many existing artificial neural networks rely on complex hardware implementations or software simulations. Another difference between biological neural networks and artificial neural networks is that while neural networks use locally available information, artificial neural networks typically rely on one or more global variables. These and other limitations have resulted in artificial neural networks which are complex, resource intensive, and have limited capabilities.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0004The accompanying drawings illustrate various embodiments of the principles described herein and are a part of the specification. The illustrated embodiments are merely examples and do not limit the scope of the claims.

p-0005<figref idrefs="DRAWINGS">FIGS. 1A-1D</figref> show basic operating principles of an illustrative two-terminal memristive device, according to one embodiment of principles described herein.

p-0006<figref idrefs="DRAWINGS">FIG. 2</figref> is a diagram of an illustrative artificial neural network, according to one embodiment of principles described herein.

p-0007<figref idrefs="DRAWINGS">FIG. 3</figref> is a diagram of an illustrative artificial neural network, according to one embodiment of principles described herein.

p-0008<figref idrefs="DRAWINGS">FIG. 4</figref> is a diagram showing complimentary coding of a binary input vector, according to one embodiment of principles described herein.

p-0009<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram showing phase operations which occur during various clocking cycles, according to one embodiment of principles described herein.

p-0010<figref idrefs="DRAWINGS">FIG. 6A</figref> is an electrical schematic of an accumulator which sums synaptic inputs at a neuron node, according to one embodiment of principles described herein.

p-0011<figref idrefs="DRAWINGS">FIG. 6B</figref> is a diagram of illustrative destructive interference method for synapse learning, according to one embodiment of principles described herein.

p-0012<figref idrefs="DRAWINGS">FIG. 7</figref> is a flow chart which shows one illustrative method for implementing a memristive adaptive resonance neural network, according to one embodiment of principles described herein.

p-0013Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

DETAILED DESCRIPTION

p-0014Adaptive resonance theory (ART) networks are designed to learn new memories in response to environmental stimuli without disrupting old memories. ART networks can take a variety of forms including nonlinear, dynamical systems or iterative algorithms which facilitate implementation on a digital computer. ART networks are attractive for hardware implementation because of their inherent parallelism and local communication.

p-0015According to one illustrative embodiment, an ART network can be implemented as an electronic circuit using memristive devices for synapses, and a combination of conventional analog components plus memristive devices for neurons. Memristive devices are a new type of component which retains a memory of past conditions. Throughout the specification, this implementation is called “mART” where the “m” refers to memristive components used in the implementation. The mART network is distinct from other ART implementations in a number of ways, including physical structure and operation.

p-0016In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present systems and methods. It will be apparent, however, to one skilled in the art that the present apparatus, systems and methods may be practiced without these specific details. Reference in the specification to “an embodiment,” “an example” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least that one embodiment, but not necessarily in other embodiments. The various instances of the phrase “in one embodiment” or similar phrases in various places in the specification are not necessarily all referring to the same embodiment.

p-0017According to one illustrative embodiment, a memristive device may be a programmable resistor or “memristor.” A memristor is the fourth fundamental circuit element, joining the capacitor, resistor, and inductor. The term “memristor” is derived from the combination of the two terms “memory” and “resistor.” The memristor has properties that cannot be duplicated by the combination of the other fundamental circuit elements. Unlike the other fundamental circuit elements, the memristor carries a memory of past electrical fields which have been applied. As described in U.S. Patent App. Pub. No. 2008/0079029, entitled “Multi-terminal Electrically Actuated Switch” and U.S. Patent App. Pub. No. 2008/0090337, entitled “Electrically Actuated Switch”, both to R. Stanley Williams, which are hereby incorporated in their entirety, memristor devices are based on dopant motion within a matrix material. Specifically, when an electrical field of sufficient magnitude is applied to a memristor, the dopants within the matrix material are displaced. When the electrical field is removed from the circuit, the displacement of the dopants allows the memristor to “remember” how much voltage was previously applied and for how long. The motion of these dopants alters the electrical resistance of the memristor. The dopants remain in this displaced state over long periods of time, thereby retaining a memory of the past electrical fields applied to the device. Until another electrical field is applied to the memristor which has sufficient intensity or duration to induce dopant motion, the resistance characteristics of the memristor are stable.

p-0018Memristors could be used in a variety of applications including data storage, circuit calibration, fuzzy logic, or neural networks which share fundamental functionalities with the human brain. In some circumstances, the flexibility in using memristive devices can be significantly enhanced by integrating them with other conventional electronic elements in an integrated circuit.

p-0019<figref idrefs="DRAWINGS">FIG. 1A</figref> shows an illustrative two-terminal memristive device (<b>100</b>). According to one embodiment, the two-terminal memristive device (<b>100</b>) is comprised of a first electrode (<b>110</b>) and second electrode (<b>115</b>) which are in electrical and physical contact with the memristive matrix (<b>105</b>). The memristive matrix (<b>105</b>) is comprised of an intrinsic semiconducting material (<b>125</b>) which is not intentionally doped and a highly doped secondary region (<b>120</b>). Throughout the specification and appended claims, the term “memristive matrix” describes a thin film of material that is electronically semiconducting or nominally electronically insulating and also a weakly ionic conductor. The memristive matrix is capable of transporting and hosting ions that act as dopants to control the flow of electrons through the memristive device. According to one illustrative embodiment, the basic mode of operation is to apply an electrical field (the drift field, which may exceed some threshold for enabling the motion of the ions in the memristive matrix) across the memristive device large enough to cause an ionic species to be transported within the memristive matrix via ionic transport. The ionic species are specifically chosen from those that act as electrical dopants for the memristive matrix, and thereby change the electrical conductivity of the matrix from low conductivity (i.e. not intentionally doped semiconductor or insulator—switch-OFF configuration) to high conductivity (doped to provide a higher conductivity—switch-ON configuration) or from high electrical conductivity to low conductivity (switch-ON to switch-OFF). Furthermore, the memristive matrix and the dopant species are chosen such that the drift of the dopants within the memristive matrix is possible but not too facile, to ensure that the memristive device will remain in whatever state it is set for a reasonably long time, perhaps many years at room temperature. This ensures that the memristive device is nonvolatile, that is, that it holds its state after the drift field has been removed.

p-0020The matrix material may be a thin film (generally less than 50 nm thick), and is in many cases nanocrystalline, nanoporous, or amorphous. Also, because the film is so thin, the amount of time required to drift enough dopants into or out of a local region of the film to substantially change its conductivity is relatively rapid. Another advantage of nanometer scale memristive devices is that a large electrical field can be produced by a relatively small applied voltage. For example, a dopant may require an electrical field intensity of 100,000 volts per centimeter to move within the matrix. If the distance between two electrodes is 100 nanometers, only a voltage bias of 1 Volt will produce the required electrical field intensity.

p-0021One of these properties of the matrix material is that it is a weakly ionic conductor. The definition of a weakly ionic conductor is based on the application for which a memristive device is designed. The mobility and the diffusion constant for a species in a lattice are directly proportional to one another, via the “Einstein relation”. Thus, if the mobility of ionized species in a lattice is very high, so is the diffusion constant. In general, it is desired for a memristive device to stay in a particular state, ON or OFF, for an amount of time that may range from a fraction of a second to years, depending on the application. Thus, the diffusion constant for such a device is, in an embodiment, low enough to ensure the desired level of stability, to avoid inadvertently turning the device from ON to OFF or vice versa via ionized species diffusion, rather than by intentionally setting the state of the memristive device with a voltage pulse. Therefore, a “weakly ionic conductor” is one in which the ion mobility, and thus the diffusion constant, is small enough to ensure the stability of the state of the device for as long as necessary under the desired conditions (e.g., the device does not change state because of diffusion of the dopants). “Strongly ionic conductors” would have large ionized species mobilities and thus would not be stable against diffusion.

p-0022According to one embodiment, the memristive matrix (<b>105</b>) may be initially comprised of two separate materials or layers. A first insulating layer (<b>125</b>) has very few dopants and prevents electrical current from flowing between the two electrodes (<b>110</b>, <b>115</b>). A second highly doped layer (<b>120</b>) is conductive and serves as a source of dopants which can be moved into the first insulating layer (<b>125</b>) to change the overall electrical conductivity of the memristive matrix (<b>105</b>). Consequently, in the configuration illustrated in <figref idrefs="DRAWINGS">FIG. 1A</figref>, the memristive device (<b>100</b>) is open.

p-0023<figref idrefs="DRAWINGS">FIG. 1B</figref> illustrates the movement of dopants from the highly doped region (<b>120</b>) into the intrinsic region (<b>125</b>) as a result of an applied electrical field. The polarity and voltage difference which is applied across the memristive matrix (<b>105</b>) may vary according to a variety of factors including, but not limited to: material properties, geometry, dopant species, temperature, and other factors. A negative voltage may also be applied to the left electrode (<b>110</b>) to further increase the electrical field and draw the positively charged vacancies toward the left electrode (<b>110</b>).

p-0024<figref idrefs="DRAWINGS">FIG. 1C</figref> illustrates the memristive device in the fully “ON” position, with the dopants fully distributed throughout the memristive matrix (<b>105</b>). The left and right electrodes (<b>110</b>, <b>115</b>) are electrically connected and can pass lower voltage electrical signals through the memristive matrix (<b>105</b>). As discussed above, the location and distribution of the dopants can remain stable over long periods of time or until another programming voltage is applied. The memristive matrix (<b>105</b>) is not a perfect conductor and still interposes an electrical resistance between the two electrodes (<b>110</b>, <b>115</b>) in the fully “ON” state. This electrical resistance may be influenced by a variety of factors, including, but not limited to the geometry of the memristive matrix and the electrodes, the dopant concentration, the distribution of the dopants throughout the memristive matrix, the species of dopant, the electrical characteristics of the matrix material, the temperature of the device, and other factors.

p-0025<figref idrefs="DRAWINGS">FIG. 1D</figref> illustrates the application of a programming voltage to the memristive device (<b>100</b>). In this case, the purpose of the programming voltage is to return the memristive device (<b>100</b>) to the fully “OFF” configuration similar to that illustrated in <figref idrefs="DRAWINGS">FIG. 1A</figref>. Consequently, the applied programming voltage has an opposite polarity from that illustrated in <figref idrefs="DRAWINGS">FIG. 1B</figref>. A positive voltage is applied to the left electrode (<b>110</b>) and negative voltage is applied to the right electrode (<b>115</b>), thereby driving the dopants toward the right electrode (<b>115</b>). This returns the left most portion of the memristive matrix (<b>105</b>) to its intrinsic and insulating state. The memristive device (<b>100</b>) is then in a fully “OFF” configuration.

p-0026The transition from the fully “OFF” to fully “ON” configuration or visa versa, is not instantaneous, but can have a number of intermediate states in which the memristive matrix acts as a finite resistance between the two electrodes. These intermediate states may be produced by varying the programming voltage applied across the two electrodes (<b>110</b>, <b>115</b>) and/or varying the time period during which the programming voltage is applied.

p-0027The memristive device (<b>100</b>) illustrated in <figref idrefs="DRAWINGS">FIG. 1</figref> may be particularly useful as an analogue to a biological synapse. For example, a connecting wire and left electrode (<b>110</b>) could be analogous to an axon which carries an electrical impulse to a synapse. The matrix (<b>105</b>) could represent the synaptic cleft with the right electrode (<b>115</b>) representing the electrical connection between the dendritic spine and its associated neuron.

p-0028The memristive device (<b>100</b>) illustrated in <figref idrefs="DRAWINGS">FIG. 1</figref> is only one example of a memristor. A variety of other memristor configurations could be constructed. For example, it may be desirable for memristive device to exhibit a more complex response to external stimulus. If a memristive device is intended to simulate chemical synapses, it may be desirable for the memristive device to have more than one state variable. By including more than one state variable, the memristive device can more closely simulate higher level synaptic functions such as desensitization, homosynaptic or hetrosynaptic plasticity, integration of synaptic inputs, pharmacological intervention, and other functions. By way of example and not limitation, these additional state variables may be created within a memristive device by including more than one dopant species within the memristive matrix, by including more than one type of memristive matrix in a memristive device, creating multiple electrodes which contact the memristive matrix, or through other methods.

p-0029As discussed above, one example of a neural network architecture which could be used in conjunction with memristors is a mART network. <figref idrefs="DRAWINGS">FIG. 2</figref> is a diagram of a portion of an illustrative mART network. For purposes of discussing fundamental concepts of the illustrative mART network, the diagram of <figref idrefs="DRAWINGS">FIG. 2</figref> has been simplified. mART networks are modeled as directed graphs, with nodes corresponding to neurons and edges corresponding to synapses. In <figref idrefs="DRAWINGS">FIG. 2</figref>, the nodes are illustrated as circles and the edges are illustrated as arrows which show directional communication between the neurons. A synapse (represented by an edge) relays signals from its source node to its destination node with the transfer function: <br /><i>s=wx</i>  Eq. 1<br /> where s is the signal received by the destination node, w is the conductive state or “weight” of the synapse, and x is the signal sent by the source node. According to one illustrative mART implementation, x is binary, restricted to the values 0 and 1, and w is a real number restricted to the interval [0, 1]. The synapse weight, w, evolves in time as a function of the source signal, x, and the state of the destination neuron, y:

p-0030<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mrow><mfrac><mrow><mo>ⅆ</mo><mi>w</mi></mrow><mrow><mo>ⅆ</mo><mi>t</mi></mrow></mfrac><mo>=</mo><mrow><mi>f</mi><mo>⁡</mo><mrow><mo>(</mo><mrow><mi>w</mi><mo>,</mo><mi>x</mi><mo>,</mo><mi>y</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow></mtd></mtr></mtable></math></maths>

p-0031In mART, y (along with x) is a binary variable. Eq. 2 is called the learning law for a synapse. According to one illustrative embodiment, the neurons (represented by circles) are created from a combination of CMOS circuitry and memristive elements. The edges (represented by arrows) are constructed from memristive elements. The weight (w_j) of a given edge corresponds to the internal electrical conductance of the memristive synapse. For example, a memristive synapse may have a low conductance (high electrical resistance) due to the distribution of dopants. When the memristive synapse receives an input (I), it would only transmit a very small signal to the neuron attached to the other side of the synapse. Thus the weight (w_j) would be a small value, with the transmitted signal being the product of the weight times the input signal.

p-0032As shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, each receiving neurons in F<b>2</b> (indexed by j) can be connected to a number of transmitting neurons in F<b>0</b> (indexed by i). When a non-zero input vector, I, is presented to F<b>0</b>, the center neuron receives the net excitatory signal

p-0033<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>I</mi><mo>·</mo><msub><mi>w</mi><mi>j</mi></msub></mrow><mo>=</mo><mrow><munder><mo>∑</mo><mi>i</mi></munder><mo>⁢</mo><mrow><msub><mi>I</mi><mi>j</mi></msub><mo>⁢</mo><msub><mi>w</mi><mi>ij</mi></msub></mrow></mrow></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>3</mn></mrow></mtd></mtr></mtable></math></maths>

p-0034For example, the input vector I may contain three binary values (1, 1, 0). The respective neurons in F<b>0</b> receive their corresponding input value and transmit the value through their corresponding memristive synapses which have weights of w_1j, w_2j, and <i>w</i>_3j. According to one illustrative embodiment, the memristive synapses in their lowest conductance state are almost perfect insulators (w≈0.0). In their highest conductive state, the memristive synapses may still have some residual resistance (w≈1.0). For convenience we normalize their maximum conductance to 1. Consequently, synapse weights range between d and 1, where d is a small, positive number less than 1. For example, the synapse weights [w<b>1</b><i>j</i>, w<b>2</b><i>j</i>, w<b>3</b><i>j</i>] may be [0.9, 0.5, 0.6]. Assuming I=(1, 1, 0) and using Eq. 3, the center synapse would then receive a net excitatory signal from the three transmitting neurons of 1*0.9+1*0.5+0*0.6=1.4.

p-0035<figref idrefs="DRAWINGS">FIG. 3</figref> is a diagram of an illustrative mART network which shows a more complete view of interactions between the various neurons in the network. In a neural network, each neuron may be synaptically connected to a number of other neurons and may be able to both receive and transmit signals along any of its synaptic connections. Consequently, the designation of a neuron as a transmitting or receiving neuron is arbitrary and is used for convenience in illustrating and describing the neural network.

p-0036In this diagram, each of the input neurons F<b>0</b> are shown as being connected to each of the receiving neurons F<b>2</b>. An input vector, I (composed of subvectors I₁′ and I₂′), is received by the transmitting neurons in F<b>0</b>, which then transmit the received signals along the various synapses [w₁₁. . . w₄₃] to the receiving neurons N₁, N₂, and N₃. The each of the receiving neurons receives a net excitatory signal as described by Eq. 3.

p-0037Each of the neurons in F<b>2</b> possesses internal state that is a function of the history of all received signals. Each neuron also emits a binary output signal that depends on the neuron's current internal state and all currently received signals. The F<b>2</b> neurons are interconnected to fight each other in a winner-take-all competition. At the conclusion of the competition, the sole winning neuron will output a 1 signal, and the losers will each output <b>0</b>. The winning neuron is determined by two functions called match and choice. The match function is defined as

p-0038<maths id="MATH-US-00003" num="00003"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><msub><mi>S</mi><mi>j</mi></msub><mo>⁡</mo><mrow><mo>(</mo><mi>I</mi><mo>)</mo></mrow></mrow><mo>=</mo><mfrac><mrow><mi>I</mi><mo>·</mo><msub><mi>w</mi><mi>j</mi></msub></mrow><mrow><mo></mo><mi>I</mi><mo></mo></mrow></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>4</mn></mrow></mtd></mtr></mtable></math></maths>

p-0039The match function scales the net excitatory signal I·w_jby the total magnitude |I| of the input vector. The choice function is defined as

p-0040<maths id="MATH-US-00004" num="00004"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><msub><mi>T</mi><mi>j</mi></msub><mo>⁡</mo><mrow><mo>(</mo><mi>I</mi><mo>)</mo></mrow></mrow><mo>=</mo><mfrac><mrow><mi>I</mi><mo>·</mo><msub><mi>w</mi><mi>j</mi></msub></mrow><mrow><mi>α</mi><mo>+</mo><mrow><mo></mo><msub><mi>w</mi><mi>j</mi></msub><mo></mo></mrow></mrow></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>5</mn></mrow></mtd></mtr></mtable></math></maths><br /> where I is the input vector, w_jis the synaptic weight vector, and α is a small constant. The choice function scales the net excitatory signal by the magnitude of the weight vector. This levels the playing field in the winner-takes-all competition so that receiving neurons which happen to be connected to transmitting neurons by synapses with high weighting coefficients do not automatically and repeatedly win the competition.

p-0041The winner of the competition is the neuron in F<b>2</b> with maximum Tj that also satisfies the match constraint equation: <br /><i>S</i>_j(<i>I</i>)≧ρ  Eq. 6<br /> where ρ is an externally defined parameter known as the “vigilance” (0≦ρ≦1). The winner's synaptic weights, w_j, undergo a learning process that drives the weights towards a state that more closely matches the input pattern, I. The α constant in Eq. 5 is used to solve a problem in distinguishing two patterns where one pattern is a subset of the other.

p-0042One of the challenges in implementing the mART network is to make the calculations required in Eq. 4 and Eq. 5 with locally available information in local circuitry.

p-0043The denominator of Eq. 4 is the magnitude of the input vector, I. The input vector is not known in advance and may be made up of a wide range of values. For an input vector in a binary system, each value in the input vector could be either a 1 or a 0. Without further information, the total magnitude of the input vector is not locally known at any receiving neuron. However, by compliment coding the input vector, additional information can be provided which will permit the local calculation of the magnitude of the input vector.

p-0044Complement coding of inputs in F<b>0</b> makes calculating the vector magnitude straightforward. In compliment coding, each binary input bit is paired with a second bit that is its logical complement. Thus an original input I with M components is transformed to (I₁, 1−I₁, I₂, 1−I₂, . . . , I_M, 1−I_M).

p-0045<figref idrefs="DRAWINGS">FIG. 4</figref> illustrates the complimentary coding of an input vector I into neurons within F<b>0</b>. Returning to the example above, the input vector I is (1,1,0) and the complimentary coding of this vector is (1,0,1,0,0,1) where each of the input bits is paired with its logical complement.

p-0046This normalizes the input vector, since it guarantees that exactly M of the 2M bits will be 1's and the remainder 0's. Because the length of the complimentary coded input vector is known (2M), M is also known. According to one illustrative embodiment, 2M is equal to the number of transmitting neurons.

p-0047According to one illustrative embodiment, the hardware implementation of the mART network could be implemented using synchronous circuitry. In this implementation, the mART network moves through time in a series of steps which are dictated by clocking cycles. Actions are taken in the various clocking cycles to determine various states of the neurons which make up the mART network.

p-0048According to one illustrative embodiment, each F<b>2</b> neuron contains two state variables. The first state variable, acc_j, can be thought of as a simple integrator that sums incoming, weighted spikes, thus computing I·w_j, which is the numerator of the both Eq. 4 and Eq. 5. This operates on a timescale of milliseconds, so it can be implemented using a CMOS capacitor.

p-0049The second state variable, weightNormj, is a long-time-scale variable representing the sum of the synaptic weights driving the neuron. This second state variable is used to control the gain of the sum of weighted input spikes when computing the choice function and represents the |w_j| value in the denominator of Eq. 5. According to one illustrative embodiment, the weightNormj value is stored in a memristive device.

p-0050Initially all synaptic weights are high, with small random variations resulting from fabrication, and the neurons are therefore broadly tuned to respond to nearly any pattern. As a neuron starts winning the winner-take-all competition, its synaptic weights start to decrease. To keep the competition fair, its gain is increased by a regulatory process interleaved with normal operation. The result is that all neurons wind up with synaptic weights that effectively are “normalized” by the division by weightNormj, with neurons becoming increasingly sharply tuned as they gradually transition from “uncommitted” to “committed.” This could be regarded as synaptic scaling of the second state variable. The “vigilance” parameter ρ, which can vary dynamically, controls how sharply tuned a given neuron can be become, and hence the number of categories that are formed by the network.

p-0051The neurons in F<b>0</b> and F<b>2</b> are clocked with a three-phase clocking protocol, where each clock cycle performs one set of operations in phase <b>1</b> (φ₁), a second set of operations in phase <b>2</b> (φ₂) and a third set in phase <b>3</b> (φ₃). Every R cycles, where R might be a number in the range of, say, 10 to 100, two new clock phases, phase <b>4</b> (φ₄), and phase <b>5</b> (φ₅), are inserted to do some regulatory functions (the “R” stands for regulatory).

p-0052<figref idrefs="DRAWINGS">FIG. 5</figref> shows an illustrative timing diagram for R=2. A number of clock cycles are shown along the bottom of the diagram. The phase operations (φ) are shown in a box which is divided by vertical lines. Each division contains the phase operations which take place in during a given clock cycle. For example, in clocking cycle 0, phase operations φ₁, φ₂, and φ₃occur. During a regulatory cycle, phase operations φ₄and φ₅occur.

p-0053Each synaptic weight (represented by a memristive device's conductance) is initialized to its maximum value. For convenience, we choose units such that the maximum synaptic weight is 1. Neurons are then initialized by executing a regulatory cycle, described below. Each F<b>2</b> neuron has a hardwired value, inputNorm, which is the magnitude of the input vector. As discussed above, InputNorm is known at design time because of complement coding.

p-0054In phase <b>1</b> (φ₁), each F<b>0</b> neuron sends out a spike to its output synapses if its binary input bit is 1, and sends nothing if its binary input bit is 0. Each F<b>2</b> neuron collects all such incoming, weighted spikes and sums them in an accumulator. Thus at the end of phase <b>1</b>, each F<b>2</b> neuron has computed: <br /><i>acc</i>_j<i>=|I·w</i>_j|  Eq. 7

p-0055An illustrative circuit for which computes acc_jis shown in <figref idrefs="DRAWINGS">FIG. 6</figref>. The input vector I is received by through the memristive synapses (<b>605</b>) by input accumulator circuit (<b>620</b>) for neuron_jin F<b>2</b>. According to one illustrative embodiment, the accumulator circuit (<b>620</b>) includes an integrator comprising an op amp (<b>615</b>), a capacitor (<b>610</b>) and a switch (<b>625</b>). The positive terminal of the op amp (<b>615</b>) may be tied to ground. The negative terminal of the op amp (<b>615</b>) is tied to memristive synapses (<b>605</b>), the switch (<b>625</b>) and the capacitor (<b>610</b>). According to one illustrative embodiment, the switch (<b>625</b>) is used to discharge the capacitor and to reset the operation of the input circuit (<b>620</b>). The output of the integrating op amp (<b>615</b>) is the value accj.

p-0056In phase <b>4</b> (φ₄) all F<b>0</b> neurons are forced to spike unconditionally, thus driving each F<b>2</b> accumulator, accj, to the value |w_j|. In phase <b>5</b> (φ₅), the value accj (or a function of it) is stored in a memristive device within the neuron circuitry, and the accumulator, accj, is reset. Thus, at the end of a regulatory cycle, each F<b>2</b> neuron has computed: <br />weightNorm_j<i>=|w</i>_j|  Eq. 8

p-0057In phase <b>2</b> (φ₂), each F<b>2</b> neuron, N_jcomputes the match and choice functions using internal state and also computes output function, output_j:

p-0058<maths id="MATH-US-00005" num="00005"><math overflow="scroll"><mtable><mtr><mtd><mrow><msub><mi>S</mi><mi>j</mi></msub><mo>=</mo><mfrac><msub><mi>acc</mi><mi>j</mi></msub><msub><mi>inputNorm</mi><mi>j</mi></msub></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>9</mn></mrow></mtd></mtr><mtr><mtd><mrow><msub><mi>T</mi><mi>j</mi></msub><mo>=</mo><mfrac><msub><mi>acc</mi><mi>j</mi></msub><mrow><mi>α</mi><mo>+</mo><msub><mi>weightNorm</mi><mi>j</mi></msub></mrow></mfrac></mrow></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>10</mn></mrow></mtd></mtr><mtr><mtd><mtable><mtr><mtd><mrow><msub><mi>output</mi><mi>j</mi></msub><mo>=</mo><mi /><mo>⁢</mo><mrow><mo>-</mo><mn>1</mn></mrow></mrow></mtd><mtd><mrow><mi /><mo>⁢</mo><mrow><mrow><mi>if</mi><mo>⁢</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><msub><mi>S</mi><mi>j</mi></msub></mrow><mo>&lt;</mo><mi>ρ</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo>⁢</mo><msub><mi>T</mi><mi>j</mi></msub></mrow></mtd><mtd><mrow><mi /><mo>⁢</mo><mrow><mrow><mi>if</mi><mo>⁢</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><msub><mi>S</mi><mi>j</mi></msub></mrow><mo>≥</mo><mi>ρ</mi></mrow></mrow></mtd></mtr></mtable></mtd><mtd><mrow><mi>Eq</mi><mo>.</mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>⁢</mo><mn>11</mn></mrow></mtd></mtr></mtable></math></maths>

p-0059The value ρ, the vigilance parameter, is supplied by external circuitry and may be varied dynamically in the range [0, 1]. The α parameter is typically a very small number and, according to one illustrative embodiment, may be zero. The remainder of phase <b>2</b> (φ₂) is a winner-take-all competition between the outputj values of the F<b>2</b> neurons. Exactly one F<b>2</b> neuron will win the competition.

p-0060In phase <b>3</b> (φ₃), learning occurs only in the winning F<b>2</b> neuron. <figref idrefs="DRAWINGS">FIG. 6</figref><i>b </i>describes one illustrative embodiment of learning by “destructive interference” of spikes between pre- and post-synaptic neurons. During this phase, each F<b>0</b> neuron retransmits the spike it transmitted in phase <b>1</b> (if it had, in fact, transmitted a spike in phase <b>1</b>), and the winning F<b>2</b> neuron sends a spike of the same polarity backwards. If the two spikes overlap, no learning takes place. However, if only the winning F<b>2</b> neuron spikes on a given synapse, the conductivity of the synapse connected to the F<b>0</b> non-spiking neuron will slightly decrease. This weakens the connection between the winning neuron and the non-spiking neurons by reducing the weighting (w) of the synapses which connect the winning neuron to the non-spiking neurons. This weakening of connections to non-spiking neurons is a form of negative learning which tunes the neuron to be receptive to an input pattern or vector.

p-0061<figref idrefs="DRAWINGS">FIG. 7</figref> is a flow chart of an illustrative method for implementing an artificial neural network (<b>700</b>). According to one illustrative embodiment, a number of initialization steps (<b>765</b>) occur before the learning operations within the neural network begin. A first step may include connecting a receiving neuron to a plurality of transmitting neurons through memristive synapses (step <b>705</b>).

p-0062A magnitude of a complimentary coded input vector (inputNorm=|I|) is then determined (step <b>710</b>). As described above, the magnitude of the complimentary coded input vector may be related to the number of transmitting neurons and may be a fixed value for a given receiving neuron which is connected to fixed number of transmitting neurons.

p-0063The weights of the memristive synapses are initialized to a conductive state (step <b>715</b>). According to one illustrative embodiment, this may include distributing the mobile dopants within the memristive matrix so that a highly conductive electrical path is created between the two electrodes.

p-0064All transmitting neurons are forced spike unconditionally, thereby sending a high electrical pulse through all memristive synapses connected to the receiving neuron (step <b>720</b>). The electrical signals received by the receiving neuron are summed to produce a magnitude of the synapse weights (weightNorm_j=|w_j|) (step <b>725</b>). According to one illustrative embodiment, the magnitude of the synapse weights is stored in a memristive device which is separate from the memristive devices which make up the synapses. In a synchronous architecture, the above calibrations steps (<b>770</b>) can be performed during regulatory cycles, which may be periodically spaced through the clocking cycles.

p-0065According to one illustrative embodiment, a binary input vector (I) is presented through the memristive synapses to a receiving neuron (step <b>735</b>). As discussed above, the binary input vector may be complimentary coded. The signals received by the receiving neuron are summed to produce an accumulated magnitude of the received signals (acc_j←|I·w_j|) (step <b>740</b>).

p-0066The match function (S_j) is calculated by dividing the accumulated magnitude of the received signals by magnitude of a complimentary coded input vector (step <b>745</b>). The choice function (T_j) is calculated by dividing the accumulated magnitude of the received signals by the magnitude of the synapse weights (step <b>750</b>).

p-0067The winning neuron among a plurality of receiving neurons is calculated using a winner-take-all algorithm (step <b>755</b>). According to one illustrative embodiment, an output_jfunction is generated by each of receiving neurons and compared to determine the winning neuron. The synapses of the winning neuron are then altered to distance winning neuron from transmitting neurons which did not transmit a high signal during the winning round (step <b>760</b>). According to one illustrative embodiment, learning takes place by “destructive interference” which weakens the connection (i.e. increases the electrical resistance) between the winning neuron and the non-spiking neurons by reducing the weighting (w) of the synapses which connect the winning neuron to the non-spiking neurons.

p-0068The sense/modify steps (<b>775</b>) may be looped through a number of iterations and periodically return to the calibration steps (<b>770</b>), as shown by the arrow connecting the sense/modify steps (<b>755</b>) to the calibration steps (<b>770</b>). According to one illustrative embodiment, the memristive adaptive resonance network is operated synchronously with interleaved clock cycles, as shown in <figref idrefs="DRAWINGS">FIG. 5</figref>. The sense/modify steps (<b>775</b>) take place during one clock cycle and the calibration steps (<b>770</b>) take place during an interleaved regulatory clock cycle. This regulatory clock cycle may occur periodically, such as every 10 or 100 sense/modify clock cycles. Additionally or alternatively, the calibration steps (<b>770</b>) may occur infrequently during periods when the neural network is relatively stable, but may occur more frequently when large changes in synapse weights occur.

p-0069The method described above is only one illustrative example. A method for implementing memristive adaptive resonance networks could take a number of embodiments, including embodiments which have different steps, different step orders, or omit steps described above.

p-0070Chart 1, below, summarizes notation and an illustrative method for implementing memristive adaptive resonance networks.

p-0071<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="left" /><thead><row><entry namest="1" nameend="1" rowsep="1">CHART 1</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>Notation:</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="28pt" align="left" /><colspec colname="2" colwidth="189pt" align="left" /><tbody valign="top"><row><entry>  w_min</entry><entry>: minimum synaptic weight (0 < w_min< 1)</entry></row><row><entry>  1</entry><entry>: maximum synaptic weight</entry></row><row><entry>  M</entry><entry>: number of bits in input pattern, before complementary coding</entry></row><row><entry>  N</entry><entry>: number of neurons in F₂</entry></row><row><entry>  ρ</entry><entry> : vigilance parameter (may be dynamic)</entry></row><row><entry>  w_j</entry><entry>: synaptic weight vector driving neuron j in F₂(2M weights)</entry></row><row><entry>  I</entry><entry>: input pattern, with complementary coding (2M binary values)</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="91pt" align="left" /><colspec colname="2" colwidth="126pt" align="left" /><tbody valign="top"><row><entry>F₂neuron state variables:</entry><entry /></row><row><entry>  weightNorm_j← |w_j|</entry><entry>// every R cycles (regulatory)</entry></row><row><entry>  acc_j← |I · w_j|</entry><entry>// phase 1 and phase 4</entry></row><row><entry>Initialize:</entry><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="left" /><tbody valign="top"><row><entry>  for i in 1 to 2M; j in 1 to N</entry></row><row><entry>    w_ij= 1</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="1" colwidth="91pt" align="left" /><colspec colname="2" colwidth="126pt" align="left" /><tbody valign="top"><row><entry>    weightNorm = |w_j|</entry><entry>// regulatory process</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="1"><colspec colname="1" colwidth="217pt" align="left" /><tbody valign="top"><row><entry>Loop:</entry></row><row><entry>  present input I (complementary coding)</entry></row><row><entry>  // phase 1: accumulate spikes</entry></row><row><entry>  for j in 2 to N</entry></row><row><entry>    acc_j= I · w_j</entry></row><row><entry>  // phase 2: match, choice, winner-take-all competition</entry></row><row><entry>  for j in 2 to N</entry></row><row><entry>    S_j= acc_j/ inputNorm_j</entry></row><row><entry>    T_j= acc_j/ (α + M)</entry></row><row><entry>    output_j= if (S_j> ρ ) T_jelse −1</entry></row><row><entry>  winner = argmax_j(output_j)</entry></row><row><entry>  // phase 3: learn</entry></row><row><entry>  w_winner= w_winner− δ (1 − I) // stops at w_min</entry></row><row><entry namest="1" nameend="1" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

p-0072In sum, a memristive adaptive resonance neural network may use memristive devices in a number of ways to simplify and economically create a neural network. The memristive devices may be used to store long term state variables or other information and may be used as synapses between nodes. To calculate the magnitude of the weights of the memristive synapses, a high signal may be transmitted through all memristive synapses and summed at the receiving neuron. This allows the neuron to calculate scaling or normalizing functions using only locally available data. In one embodiment, the memristive adaptive resonance neural network may synchronously operate over a number of interleaved clock cycles, with the magnitude of the weights of the memristive synapses being calculated periodically during a regulator cycle.

p-0073The preceding description has been presented only to illustrate and describe embodiments and examples of the principles described. This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.