Semiconductor device and manufacturing method thereof
Summary by NHIP
Depressed Oxide Transistor Fabrication
The method manufactures a transistor by etching an indium, gallium, and zinc oxide semiconductor layer to create a depression. The oxide layer possesses a crystalline state and forms over an oxide insulating film before receiving a pixel electrode.
Claim Score by NHIP
Abstract
An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
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27 claims: 4 independent, 23 dependent
- 1Broadest claimClaim Score 77, broad(NHIP)A method of manufacturing a semiconductor device comprising a transistor, the method comprising the step of:forming an oxide semiconductor layer including a region to become a channel region of the transistor;and etching the oxide semiconductor layer so that the oxide semiconductor layer has a depression, wherein the oxide semiconductor layer has a crystalline state and comprises indium, gallium and zinc, and wherein the oxide semiconductor layer having the crystalline state and comprising indium, gallium and zinc is formed by sputtering.
- 8A method of manufacturing a semiconductor device comprising a transistor, the method comprising the steps of:forming an oxide semiconductor layer including a region to become a channel region of the transistor;etching the oxide semiconductor layer so that the oxide semiconductor layer has a depression;and forming a pixel electrode in electrical contact with a source or drain of the transistor, wherein the oxide semiconductor layer has a crystalline state and comprises indium, gallium and zinc, and wherein the oxide semiconductor layer having the crystalline state and comprising indium, gallium and zinc is formed by sputtering.
- 15A method of manufacturing a semiconductor device comprising a transistor, the method comprising the steps of:forming a gate electrode over a substrate;forming an insulating film over the gate electrode;forming an oxide semiconductor layer including a region to become a channel region of the transistor over the gate electrode with the insulating film interposed between the oxide semiconductor layer and the gate electrode;and etching the oxide semiconductor layer so that the oxide semiconductor layer has a depression, wherein the oxide semiconductor layer has a crystalline state and comprises indium, gallium and zinc, and wherein the oxide semiconductor layer having the crystalline state and comprising indium, gallium and zinc is formed by sputtering.
- 22A method of manufacturing a semiconductor device comprising a transistor, the method comprising the step of:forming an oxide semiconductor layer including a region to become a channel region of the transistor;forming a conductive film over the oxide semiconductor layer;and etching the oxide semiconductor layer so that the oxide semiconductor layer has a depression, wherein the oxide semiconductor layer has a crystalline state and comprises indium, gallium and zinc, and wherein the oxide semiconductor layer having the crystalline state and comprising indium, gallium and zinc is formed by sputtering.
Independent claims4
294 paragraphs in 4 sections, as filed
0001This application is a continuation of copending U.S. application Ser. No. 12/184,401, filed on Aug. 1, 2008 which is a continuation of U.S. application Ser. No. 11/524,549, filed on Sep. 21, 2006 (now U.S. Pat. No. 7,674,650 issued Mar. 9, 2010).
BACKGROUND OF THE INVENTION
00021. Field of the Invention
0003The present invention relates to a semiconductor device and a manufacturing method thereof and particularly relates to a semiconductor device using an oxide semiconductor. The present invention also relates to an electronic appliance equipped with the semiconductor device.
00042. Description of the Related Art
0005Flat panel displays (FPD), typified by liquid crystal displays (LCD) and EL displays, have attracted attention as the display device replacing conventional CRTs. The development of large screen liquid crystal television mounted with an active matrix-driven large scale liquid crystal panel is particularly an important challenge which liquid crystal panel makers should focus on. In addition, large screen EL television is also being developed.
0006In the conventional liquid crystal device or electroluminescence display device (hereinafter referred to as a light emitting display device or an EL display device), a thin film transistor (hereinafter referred to as TFT) is used, which uses crystalline silicon or amorphous silicon as a semiconductor element driving each pixel.
0007A TFT using a crystalline silicon film has a higher mobility by two digits or more compared to a TFT using an amorphous silicon film, and has potential for high speed operation when it is used for a scanning line driver circuit for selecting a pixel of a light emitting display device, a signal line driver circuit for sending video signals to a selected pixel, or the like. However, using crystalline silicon for a semiconductor film complicates manufacturing steps because of crystallization of the semiconductor film compared to using amorphous silicon for the semiconductor film; therefore, there are drawbacks of yield decrease by that much and increase in cost. Further, a heating temperature for the crystallization is 550° C. or higher, and it is difficult to use a substrate made of a resin with low melting point, a plastic substrate, or the like.
0008On the other hand, the TFT using amorphous silicon for a semiconductor film can be manufactured at low cost, since it is not heated at a high temperature and a resin substrate or a plastic substrate can be used. However, a mobility of only around 0.2 to 1.0 cm<sup>2</sup>/V·s at most can be obtained with a TFT of which a channel forming region is formed with a semiconductor film formed of amorphous silicon, and it also has high power consumption.
0009A plasma CVD method is commonly used when an amorphous silicon film is formed over a substrate. Film formation by a plasma CVD method requires heating under high vacuum, and damage to a plastic substrate or an organic resin film over a substrate is a concern. In addition to the concern in forming the amorphous silicon film by a plasma CVD method, there is also a concern in forming the film by a sputtering method which is that a thin insulating film might be formed over a surface of an amorphous silicon film when the amorphous silicon film is exposed to atmospheric air.
0010As a material to replace a semiconductor made of such silicon, forming a TFT using an oxide semiconductor such as zinc oxide for a channel forming region has been reported in recent years (for example, refer to Patent Document 1: Japanese Patent Laid-Open No. 2000-150900, and Non-Patent document 1: Elvira M. C. Fortunato, et al. Applied Physics Letters, Vol. 85, No. 13, P2541 (2004)). Since the oxide semiconductor has mobility equal to or higher than that of a TFT formed with a semiconductor including amorphous silicon, further characteristic improvement is demanded.
SUMMARY OF THE INVENTION
0011In view of the foregoing problems, an object of the present invention is to provide a semiconductor device including a semiconductor element with improved characteristics and a manufacturing method thereof.
0012On another front, size increase in substrate has advanced for manufacturing a large-area device by a cheaper process, as in liquid crystal television. However, with the size increase in substrate, there is a problem of being easily effected by bending and warping. Also, when a substrate is heated to a high temperature during a heat treatment step, a size of the substrate becomes distorted due to warping and shrinking, and there is a problem of a decrease in precision of alignment in a photolithography step.
0013Consequently, an object of the present invention is to provide a technique that makes it possible to manufacture with good yield a semiconductor device over, a large substrate, having for example a side longer than 1 meter, in a crystallization step of a semiconductor element used in a semiconductor device.
0014As mentioned above, an object of the present invention is to provide a semiconductor device including a semiconductor element with characteristics that are further improved, which can be manufactured at lower cost and more favorable productivity than before.
0015In the present invention, a compound semiconductor, more preferably an oxide semiconductor is used as a semiconductor. As the oxide semiconductor, for example, zinc oxide (ZnO), InGaO<sub>3</sub>(ZnO)<sub>5</sub>, magnesium zinc oxide (Mg<sub>x</sub>Zn<sub>1-x</sub>O), cadmium zinc oxide (Cd<sub>x</sub>Zn<sub>1-x</sub>O), cadmium oxide (CdO), an In—Ga—Zn—O based amorphous oxide semiconductor (a-IGZO), or the like is used. Also, the gist of the present invention is that by heating a gate electrode that is near the compound semiconductor by lamp rapid thermal annealing (LRTA; also simply called lamp heating), crystallization of the compound semiconductor is selectively promoted, and a TFT using a compound semiconductor having the region in which crystallization is promoted at least in a channel region can be manufactured.
0016One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, and an oxide semiconductor film formed over the insulating film. The oxide semiconductor film includes a first oxide semiconductor region and a second oxide semiconductor region, and the first oxide semiconductor region that is formed in a position which overlaps with the gate electrode has higher crystallinity than the second semiconductor region. Note that “crystallinity” expresses a degree of regularity of atomic arrangement inside of crystal, and when manufacturing a TFT using an oxide semiconductor film with favorable crystallinity (also expressed as having high crystallinity or with improved crystallinity), an electrical characteristic thereof is favorable.
0017One feature of the present invention is to have a gate electrode and an oxide semiconductor film over a substrate. In a region of the oxide semiconductor film which overlaps with the gate electrode via an insulating film, a portion of the region is crystallized.
0018One feature of the present invention is to have a gate electrode, an oxide semiconductor film, and a conductive film over a substrate. The conductive film is provided to be in contact with the oxide semiconductor film, and in a region of the oxide semiconductor film which overlaps with the gate electrode via an insulating film, a portion of the region is crystallized.
0019One feature of the present invention is to have a gate electrode over a substrate, an insulating film formed covering the gate electrode, and an oxide semiconductor film formed over the insulating film. The oxide semiconductor film is crystallized in at least a region which overlaps with the gate electrode. Note that “crystallization” refers to generation of crystal nuclei from an amorphous state, or growth of crystal grains from a state in which crystal nuclei have been generated.
0020One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, a conductive film formed over the insulating film, and an oxide semiconductor film formed over the insulating film and the conductive film. The oxide semiconductor film is crystallized in at least a region which overlaps with the gate electrode.
0021One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, a conductive film formed over the insulating film, and an oxide semiconductor film formed over the insulating film and the conductive film. The gate electrode has lower reflectivity with respect to a light source used for crystallization than the conductive film. Note that reflectivity comparison is used when the conductive film is a metal film or the like having a light shielding property.
0022One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, a conductive film formed over the insulating film, and an oxide semiconductor film formed over the insulating film and the conductive film. The gate electrode has higher heat absorption rate than the conductive film.
0023One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed over the gate electrode, and an oxide semiconductor film formed over the insulating film, and by performing LRTA on the gate electrode, a portion of the oxide semiconductor film that overlaps with the gate electrode is crystallized.
0024One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, and an oxide semiconductor film formed over the insulating film. By performing LRTA on the gate electrode, a first oxide semiconductor region and a second oxide semiconductor region are formed inside of the oxide semiconductor film, and the first oxide semiconductor region that is formed in a position which overlaps with the gate electrode has higher crystallinity than the second oxide semiconductor region.
0025One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed over the gate electrode, a conductive film formed over the insulating film, and an oxide semiconductor film formed over the insulating film and the conductive film. By performing LRTA on the gate electrode, a portion of the oxide semiconductor film is selectively crystallized.
0026One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, an oxide semiconductor film formed over the insulating film, and a conductive film formed over the oxide semiconductor film. By performing LRTA on the gate electrode, a portion of the oxide semiconductor film is selectively crystallized.
0027One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, a conductive film formed over the insulating film, and an oxide semiconductor film formed over the insulating film and the conductive film. By performing LRTA on the gate electrode, a first oxide semiconductor region and a second oxide semiconductor region are formed inside of the oxide semiconductor film. At this time, the first oxide semiconductor region that is formed in a position which overlaps with the gate electrode has higher crystallinity than the second oxide semiconductor region.
0028One feature of the present invention is to have a gate electrode formed over a substrate, an insulating film formed covering the gate electrode, an oxide semiconductor film formed over the insulating film, and a conductive film formed over the oxide semiconductor film. By lamp heating the gate electrode, a first oxide semiconductor region and a second oxide semiconductor region are formed inside of the oxide semiconductor film. At this time, the first oxide conductive region that is formed in a position which overlaps with the gate electrode has higher crystallinity than the second oxide semiconductor region.
0029Note that the foregoing conductive film is formed with one element or a plurality of elements selected from Al, Ti, Cu, Au, Ag, Mo, Ni, Ta, Zr, and Co.
0030Note that it is favorable that the foregoing oxide semiconductor film includes at least zinc oxide (ZnO). For example, InGaO<sub>3</sub>(ZnO)<sub>5</sub>, Mg<sub>x</sub>Zn<sub>1-x</sub>O, or Cd<sub>x</sub>Zn<sub>1-x</sub>O is given.
0031Note that the foregoing substrate is any one selected from an organic resin substrate, an inorganic resin substrate, a plastic substrate, and a glass substrate.
0032Note that the foregoing oxide semiconductor film is formed by a sputtering method.
0033Note that nitrogen may be added to the foregoing oxide semiconductor film. When adding nitrogen, nitrogen works as an acceptor impurity when the oxide semiconductor film shows an n-type semiconductor property. Consequently, a threshold voltage of a transistor manufactured using an oxide semiconductor film to which nitrogen is added, can be controlled.
0034One feature of the present invention is to use one of W, TaN, and Cr as a gate electrode, or an alloy including any one thereof.
0035One feature of the present invention is to perform crystallization of an oxide semiconductor film by irradiation with lamp light of a halogen lamp.
0036One feature of the present invention is to use light in a wavelength region of 800 nm to 2400 nm as lamp light. Also, wavelength in the visible light region or the infrared light region is used.
0037One feature of the present invention is a liquid crystal television or an EL television including the foregoing semiconductor device.
0038Also, in the present invention, a heating treatment may be performed by laser light irradiation instead of LRTA. For example, laser light irradiation may be performed using an infrared light laser, a visible light laser, an ultraviolet laser, or the like to selectively improve crystallinity of an oxide semiconductor film. Alternatively, laser light irradiation may be performed at the same time as performing lamp heating to selectively improve crystallinity of the oxide semiconductor film. When laser irradiation is used, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. A laser beam that can be used here is one or a plurality of that which oscillates from a gas laser such as an Ar laser, Kr laser, or an excimer laser; a laser of which a medium is a monocrystalline YAG, YVO<sub>4</sub>, forsterite (Mg<sub>2</sub>SiO<sub>4</sub>), YAlO<sub>3</sub>, or GdVO<sub>4 </sub>doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, or polycrystalline (ceramic) YAG, Y<sub>2</sub>O<sub>3</sub>, YVO<sub>4</sub>, YAlO<sub>3</sub>, or GdVO<sub>4</sub>, doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta; a glass laser; a ruby laser; an alexandrite laser; a Ti:sapphire laser; a copper vapor laser; and a gold vapor laser. By emitting a laser beam from the second harmonic to the fourth harmonic of the fundamental harmonic of such a laser beam, crystallinity can be made to be favorable. Note that it is preferable to use laser light having larger energy than a band gap of the oxide semiconductor film. For example, laser light emitted from a KrF, ArF, XeCl, or an XeF excimer laser oscillator may be used.
0039In the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode), and as the semiconductor device, an integrated circuit including a semiconductor element, a display device, a wireless tag, an IC tag, and the like are given. As the display device, a liquid crystal display device, a light emitting device, a DMD (digital micromirror device), a PDP (plasma display panel), an FED (field emission display), an electrophoresis display device (electronic paper), and the like are typically given.
0040In the present invention, a display device refers to a device using a display element, in other words, an image display device. Further, a module in which a connector, for example an FPC (flexible printed circuit), a TAB (tape automated bonding) tape, or a TCP (tape carrier package), is attached to a display panel; a module provided with a printed wiring, board at an end of the TAB tape or the TCP; and a module in which an IC (integrated circuit) or a CPU is directly mounted on a display element by COG (chip on glass) method are all included as the display device.
0041In the present invention, it is acceptable as long as crystallization of an oxide semiconductor film is caused or crystallinity is improved in at least a channel forming region. Further, the entire channel forming region is not required to be crystallized, and it is acceptable as long as at least a portion of the channel forming region on a gate electrode side is crystallized.
0042Note that as the compound semiconductor, a nitride semiconductor or a carbide semiconductor may be used other than the oxide semiconductor. Further, a semiconductor having a light transmitting property with respect to visible light can also be used.
0043In the present invention, crystallinity of a channel forming region of an oxide semiconductor film is made to be favorable by heating a gate electrode by LRTA. As a result, the oxide semiconductor film is only heated locally; consequently, most of a substrate is not heated, and a crystallization step can be performed as shrinking and bending of the substrate are controlled. Consequently, a semiconductor device including a semiconductor element with improved mobility characteristic can be manufactured as the step is simplified.
0044Also, when forming a gate electrode over the substrate, forming an insulating film functioning as a gate insulating film over the gate electrode, forming a wiring having higher reflectivity with respect to a light source of LRTA than the gate electrode over the insulating film, and forming a oxide semiconductor film over the wiring, and then LRTA is performed towards a front surface or a rear surface of a substrate, the wiring is not heated as much as the gate electrode since it has higher reflectivity with respect to the light source of LRTA than the gate electrode. Therefore, a conductive film having a relatively low melting point such as copper, aluminum, or silver, which has low resistance, can be used for the wiring. As a result, an inexpensive semiconductor device can be provided.
0045Also, unlike the amorphous silicon film, an insulating film does not form over a surface of the oxide semiconductor film due to oxidation even if the surface is exposed to an atmosphere containing oxygen. Therefore, even if the oxide semiconductor film is exposed to atmospheric air after formation, there is little change to the film.
0046Further, when ZnO is used as the oxide semiconductor film, a heat treatment temperature in a crystallization step of the oxide semiconductor film can be around 350° C. or lower. This is because crystallization is sufficiently promoted for ZnO at a heat treatment temperature of around 350° C. or lower. As a result, even if a resin substrate is used, shrinking of the substrate can be suppressed. Also, lamp heating is performed on the gate electrode using a material having lower reflectivity with respect to light emitted from a lamp than a source wiring and a drain wiring. Consequently, while crystallinity of at least a channel forming region of ZnO is improved due to heat conducted from the gate electrode, the source wiring and the drain wiring are not easily heated; therefore, a material having a relatively low melting point can be used for the source wiring and the drain wiring. For example, since a heat treatment temperature of 350° C. or lower is sufficient when Al is used for the source wiring and the drain wiring, diffusion of Al to a semiconductor layer can be suppressed.
0047As in the above, since a semiconductor device can be manufactured by a low temperature heat treatment (around 350° C. or lower), it is inexpensive as a process.
0048Further, since the oxide semiconductor has a light transmitting property, by forming the source electrode, the drain electrode, and the like with a conductive film having a light transmitting property and then forming a pixel electrode thereover, an aperture ratio of a pixel portion can be improved. When zinc oxide is used as the oxide semiconductor, since resource of zinc oxide is more abundant than that of indium tin oxide (ITO) and since zinc oxide has lower resistance, a more inexpensive semiconductor device can be obtained by using zinc oxide instead of ITO as the pixel electrode. When silicon is used for a semiconductor film, in order to prevent the channel forming region from being irradiated with light, it is necessary to provide a light shielding film so as to overlap the channel forming region. As a result, a decrease in aperture ratio of a pixel portion is unavoidable. On the other hand, when zinc oxide is used for an oxide semiconductor film, since resource of zinc oxide is relatively abundant and since zinc oxide has a light transmitting property, by forming each of a source electrode, a drain electrode, and a pixel electrode using a transparent conductive material including indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like each having a light transmitting property, a large scale display with high aperture ratio in a transmissive type display panel can be obtained. Also, light from a backlight can be effectively used to save power. For example, by sticking a display panel over a window of a building or a windshield of an automobile, a train, an airplane, or the like, a head-up display in which an image or text information is directly displayed can be realized.
BRIEF DESCRIPTION OF DRAWINGS
0049In the accompanying drawings:
0050<figref idref="DRAWINGS">FIGS. 1A</figref> and B are each a cross-sectional view describing a manufacturing step of a semiconductor device relating to the present invention;
0051<figref idref="DRAWINGS">FIG. 2</figref> is a diagram describing temperature dependency of crystallization of an oxide semiconductor film of the present invention;
0052<figref idref="DRAWINGS">FIGS. 3A to 3C</figref> are each a cross-sectional view describing a manufacturing step of a semiconductor device relating to the present invention;
0053<figref idref="DRAWINGS">FIGS. 4A to 4H</figref> are each a cross-sectional view describing a manufacturing step of a semiconductor device relating to the present invention;
0054<figref idref="DRAWINGS">FIGS. 5A to 5C</figref> are each a cross-sectional view describing a manufacturing step of a semiconductor device relating to the present invention;
0055<figref idref="DRAWINGS">FIGS. 6A to 6F</figref> are each a cross-sectional view describing a manufacturing step of a semiconductor device relating to the present invention;
0056<figref idref="DRAWINGS">FIG. 7</figref> is a cross sectional-view of a semiconductor device relating to the present invention;
0057<figref idref="DRAWINGS">FIGS. 8A to 8F</figref> are each a diagram showing a mode of a light emitting element relating to the present invention;
0058<figref idref="DRAWINGS">FIGS. 9A to 9F</figref> are each a diagram describing a pixel circuit of a display panel relating to the present invention and an operation configuration thereof;
0059<figref idref="DRAWINGS">FIGS. 10A to 10C</figref> are each a diagram describing mounting of a driver circuit relating to the present invention;
0060<figref idref="DRAWINGS">FIG. 11</figref> is a diagram describing a display module relating to the present invention;
0061<figref idref="DRAWINGS">FIGS. 12A to 12F</figref> are each a diagram describing one example of an electronic appliance;
0062<figref idref="DRAWINGS">FIGS. 13A and 13B</figref> are each a cross-sectional view of a semiconductor device relating to the present invention;
0063<figref idref="DRAWINGS">FIGS. 14A and 14B</figref> are each a circuit diagram and a cross-sectional view of a pixel in a semiconductor device of the present invention;
0064<figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional view of a semiconductor device relating to the present invention;
0065<figref idref="DRAWINGS">FIG. 16</figref> is a diagram showing one mode of an element substrate in a semiconductor device of the present invention;
0066<figref idref="DRAWINGS">FIGS. 17A and 17B</figref> are each a diagram showing one mode of an element substrate in a semiconductor device of the present invention;
0067<figref idref="DRAWINGS">FIGS. 18A and 18B</figref> are each a block diagram showing a structure of a semiconductor device of the present invention;
0068<figref idref="DRAWINGS">FIGS. 19A and 19B</figref> are each a diagram showing a structure of an LRTA device relating to the present invention;
0069<figref idref="DRAWINGS">FIG. 20</figref> describes one example of an electronic appliance relating to the present invention;
0070<figref idref="DRAWINGS">FIG. 21</figref> describes one example of an electronic appliance relating to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
0000Embodiment Mode
0071Embodiment modes of the present invention will hereinafter be described with reference to drawings. However, the invention is not limited to the following description, and it is easily understood by those skilled in the art that the modes and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the invention is not interpreted limited to the following description of embodiment modes.
0000(Embodiment Mode 1)
0072In this embodiment mode, a manufacturing step of a TFT using a channel forming as a region of an oxide semiconductor film in which crystallinity is improved by LRTA, is described with reference to <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>.
0073First, a base film <b>102</b> is formed over a substrate <b>101</b>. For the substrate <b>101</b>, glass, or plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, or polyimide can be used.
0074As the base film <b>102</b>, a single layer of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiO<sub>x</sub>N<sub>y</sub>) (x>y), or a silicon nitride oxide film (SiN<sub>x</sub>O<sub>y</sub>) (x>y), or stacked layers thereof are used. The base film <b>102</b> may be formed by a sputtering method or a CVD method. Note that the base film <b>102</b> is not always required to be provided, but it is preferable to form in the present invention. By forming the base film <b>102</b>, conduction of heat generated from an electrode or a wiring formed over the base film <b>102</b> to the substrate <b>101</b> can be suppressed. As the base film <b>102</b>, a silicon nitride oxide film with a thickness of 10 to 400 nm can be used, for example.
0075Subsequently, a gate electrode <b>103</b> is formed over the base film <b>102</b>. The gate electrode <b>103</b> with a thickness of 100 to 200 nm may be formed by a sputtering method. The gate electrode <b>103</b> can be formed using an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or an alloy material or a compound material mainly containing such an element. Further, the gate electrode <b>103</b> can also be formed with a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorous.
0076Subsequently, a gate insulating film <b>104</b> with a thickness of about 50 to 500 nm is formed to cover the gate electrode <b>103</b>. The gate insulating film <b>104</b> may be formed to have a single layer structure of a film containing an oxide of silicon or a nitride of silicon, or as a stacked layer structure thereof by a sputtering method or a variety of CVD methods such as a plasma CVD method. Specifically, a film containing silicon oxide (SiO<sub>x</sub>), a film containing silicon oxynitride (SiO<sub>x</sub>N<sub>y</sub>), or a film containing silicon nitride oxide (SiN<sub>x</sub>O<sub>y</sub>) is formed as a single layer structure, or these films are appropriately stacked to form the gate insulating film <b>104</b>. Also, the gate insulating film may be formed by performing high density plasma treatment on the gate electrode <b>103</b> under an atmosphere containing oxygen, nitrogen, or both oxygen and nitrogen and oxidizing or nitriding a surface of the gate electrode <b>103</b>. The gate insulating film formed by a high density plasma treatment has excellent uniformity in its film thickness, film quality, and the like and the film can be formed to be dense. As the atmosphere containing oxygen, a mixed gas of a noble gas, oxygen (O<sub>2</sub>), and nitrogen dioxide (NO<sub>2</sub>), or dinitrogen monoxide (N<sub>2</sub>O); or a mixed gas of a noble gas, hydrogen (H<sub>2</sub>), and oxygen (O<sub>2</sub>), nitrogen dioxide (NO<sub>2</sub>), or dinitrogen monoxide (N<sub>2</sub>O), can be used. Also, as the atmosphere containing nitrogen, a mixed gas of a noble gas and nitrogen (N<sub>2</sub>) or ammonia (NH<sub>3</sub>); or a mixed gas of a noble gas, hydrogen (H<sub>2</sub>), and nitrogen (N<sub>2</sub>) or ammonia (NH<sub>3</sub>), can be used. By an oxygen radical (may also include an OH radical) or a nitrogen radical (may also include a NH radical) generated by the high density plasma treatment, the surface of the gate electrode <b>103</b> can be oxidized or nitrided.
0077When the gate insulating film <b>104</b> is formed by performing the high density plasma treatment, the insulating film with a thickness of 1 to 20 nm, preferably 5 to 10 nm, is formed covering the gate electrode <b>103</b>. Since a reaction in this case is a solid-phase reaction, interface state density of between the gate insulating film <b>104</b> and the gate electrode <b>103</b> can be made to be extremely low. Further, since the gate electrode <b>103</b> is oxidized or nitrided directly, a thickness of the gate insulating film <b>104</b> to be formed can be uniform. Consequently, by solid-phase oxidation of the surface of the electrode by the high density plasma treatment shown here, an insulating film with favorable uniformity and low interface state density can be formed. Here, an oxide of an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like; or an oxide of an alloy material or a compound material mainly containing the element functions as the gate insulating film <b>104</b>.
0078Note that for the gate insulating film <b>104</b>, just an insulating film formed by the high density plasma treatment may be used, or at least one of an insulating film of silicon oxide, silicon nitride containing oxygen, silicon oxide containing nitrogen, and the like may be stacked in addition thereover by a CVD method utilizing plasma or heat reaction. Either way, transistors each of which a gate insulating film is partially or entirely an insulating film formed by high density plasma can be made to have little variations in characteristic.
0079The gate insulating film <b>104</b> may use the following which have favorable compatibility with the oxide semiconductor film: alumina (Al<sub>2</sub>O<sub>3</sub>), aluminum nitride (AlN), titanium oxide (TiO<sub>2</sub>), zirconia (ZrO<sub>2</sub>), lithium oxide (Li<sub>2</sub>O), potassium oxide (K<sub>2</sub>O), sodium oxide (Na<sub>2</sub>O), indium oxide (In<sub>2</sub>O<sub>3</sub>), yttrium oxide (Y<sub>2</sub>O<sub>3</sub>), or calcium zirconate (CaZrO<sub>3</sub>); or a material including at least two thereof. The gate insulating film <b>104</b> may be formed as a single layer or as stacked layers of two or more layers.
0080Subsequently, a wiring <b>105</b> with a thickness of 50 to 200 nm is formed over the gate insulating film <b>104</b>. As a wiring material, silver (Ag), aluminum (Al), gold (Au), copper (Cu), an alloy thereof, or the like is used. It is acceptable as long as the wiring material has higher reflectivity than that of the material used for the gate electrode <b>103</b>, and the wiring material is appropriately combined and used taking into consideration the gate electrode <b>103</b>. Note that the wiring may be formed to have a stacked layer structure. For example, aluminum and titanium may be stacked over the substrate in this order to form a wiring with a stacked layer structure. Titanium is effective in making an electrical contact property between the oxide semiconductor film and aluminum favorable. Titanium also takes on a role of suppressing diffusion of aluminum to the oxide semiconductor film. Also, the wiring may be formed with a transparent conductive film, such as for example indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), indium zinc oxide (IZO), indium oxide (In<sub>2</sub>O<sub>3</sub>), tin oxide (SnO<sub>2</sub>), zinc oxide (ZnO), zinc oxide added with aluminum (AlZnO), zinc oxide added with gallium (GaZnO), or zinc oxide. Note that for the wiring <b>105</b>, it is favorable to use a material having higher reflectivity or higher transmissivity (or lower heat absorption rate) with respect to lamp light than that of the gate electrode <b>103</b>.
0081Next, an oxide semiconductor film <b>106</b> is fanned over the gate insulating film <b>104</b> and the wiring <b>105</b>. For the oxide semiconductor film <b>106</b>, zinc oxide (ZnO) in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist, added with one type or a plurality of types of impurity elements selected from the following can be used: a Group 1 element (for example, lithium (Li), sodium (Na), potassium (K), rubidium (Rb), or cesium (Cs)), a Group 13 element (for example, boron (B), gallium (Ga), indium (In), or thallium (Tl)), a Group 14 element (for example, carbon (C), silicon (Si), germanium (Ge), tin (Sn), or lead (Pb)), a Group 15 element (for example, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi)), a Group 17 element (for example, fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)), or the like. Alternatively, zinc oxide (ZnO) in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist, which is not added with any impurity element can also be used. Further, any of the following can also be used: InGaO<sub>3</sub>(ZnO)<sub>5</sub>, magnesium zinc oxide (Mg<sub>x</sub>Zn<sub>1-x</sub>O), cadmium zinc oxide (Cd<sub>x</sub>Zn<sub>1-x</sub>O), cadmium oxide (CdO), or an In—Ga—Zn—O based amorphous oxide semiconductor (a-IGZO). The oxide semiconductor film <b>106</b> is formed by forming a film with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method under conditions of a pressure of 0.4 Pa and a flow rate of Ar(argon):O<sub>2</sub>=50:5 (sccm) to form into a desired pattern, then subsequently etching the film using fluorinated acid diluted to 0.05%. Compared to a semiconductor film using an amorphous silicon film, the oxide semiconductor film <b>106</b> does not need to be formed under high vacuum since there is no concern for oxidation, and is inexpensive as a process. Note that since an oxide semiconductor film containing zinc oxide is resistant against plasma, a plasma CVD (also called PCVD or PECVD) method may be used to form the film. Among CVD methods, the plasma CVD method in particular uses a simple device, and has favorable productivity.
0082Subsequently, LRTA is performed towards a rear surface of the substrate <b>101</b> (<figref idref="DRAWINGS">FIG. 1A</figref>). LRTA is performed at 250° C. to 570° C. (preferably 300° C. to 400° C., more preferably 300° C. to 350° C.) for 1 minute to 1 hour, preferably 10 minutes to 30 minutes. LRTA is performed with radiation from one type or a plurality types of lamps selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. Since a heat treatment in a short amount of time is possible with an LRTA method, a material with a relatively low melting point can be used if reflectivity or transmissivity of the wiring <b>105</b> is higher than that of the gate electrode <b>103</b>. For the LRTA method, light of a wavelength in the infrared light region, the visible light region, the ultraviolet light region, or the like can be used. Note that instead of LRTA, a heating treatment may be performed by laser light irradiation, and for example, laser light of an infrared light laser, a visible light laser, an ultraviolet laser, or the like may be used. Alternatively, LRTA and laser light irradiation may be combined to selectively improve crystallinity of the oxide semiconductor film. When laser irradiation is used, a continuous wave laser beam (CW laser beam) or a pulsed laser beam can be used. A laser beam that can be used here is one or a plurality of that which oscillates from a gas laser such as an Ar laser, Kr laser, or an excimer laser; a laser of which a medium is a monocrystalline YAG, YVO<sub>4</sub>, forsterite (Mg<sub>2</sub>SiO<sub>4</sub>), YAlO<sub>3</sub>, or GdVO<sub>4 </sub>doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, or polycrystalline (ceramic) YAG, Y<sub>2</sub>O<sub>3</sub>, YVO<sub>4</sub>, YAlO<sub>3</sub>, or GdVO<sub>4</sub>, doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta; a glass laser; a ruby laser; an alexandrite laser; a Ti:sapphire laser; a copper vapor laser; and a gold vapor laser. By emitting a laser beam from the second harmonic to the fourth harmonic of the fundamental harmonic of such a laser beam, crystallinity can be made to be favorable. Note that it is preferable to use laser light having larger energy than a band gap of the oxide semiconductor film. For example, laser light emitted from a KrF, ArF, WeCl, or an XeF excimer laser oscillator may be used.
0083At this time, since the gate electrode <b>103</b> is formed with a material that has lower reflectivity with respect to lamp light and that which absorbs more heat than that of the wiring <b>105</b>, the gate electrode <b>103</b> is heated to a higher temperature than the wiring <b>105</b>. For this reason, the oxide semiconductor film <b>106</b> in a periphery of the gate electrode <b>103</b> is heated; consequently, a second oxide semiconductor region <b>108</b> and a first oxide semiconductor region <b>107</b> with more favorable crystallinity than the second oxide semiconductor region <b>108</b> are formed (see <figref idref="DRAWINGS">FIG. 1B</figref>). Here, the gate electrode <b>103</b> is irradiated with lamp light so as to be heated to around 300° C., and by that heat, the oxide semiconductor film <b>106</b> is crystallized to improve crystallinity. At this time, since a material with higher reflectivity or transmissivity with respect to lamp light than that of the gate electrode <b>103</b> is used, a temperature of the wiring <b>105</b> is 300° C. or less even if the oxide semiconductor film <b>106</b> is crystallized.
0084Here, a heat treatment temperature dependency of a crystallinity of ZnO used as the oxide semiconductor film is shown in <figref idref="DRAWINGS">FIG. 2</figref>. <figref idref="DRAWINGS">FIG. 2</figref> shows a result of measuring an X-ray intensity of a (002) surface in each of the following cases: a case where a deposition gas with a flow rate ratio of Ar:O<sub>2</sub>=50:5 (sccm) is sprayed (as-deposited); and cases when the deposition gas is sprayed and then heated for 1 hour at each temperature of 200° C., 300° C., and 350° C. As heat treatment temperature rises, an intensity peak of the (002) surface is greater. Consequently, at least up to 350° C., crystallinity of ZnO increases as the heat treatment temperature rises. Since mobility increases in general as crystallization progresses, it is desirable to perform the heat treatment at around 350° C. Note that if there is no problem such as shrinking of the substrate, a heat treatment in which ZnO is heated to around 400° C. may be performed.
0085On the other hand in <figref idref="DRAWINGS">FIG. 1A</figref>, in a region in which the gate electrode <b>103</b> and the wiring <b>105</b> are not formed, in other words, in a region in which the substrate <b>101</b>, the base film <b>102</b>, the gate insulating film <b>104</b>, and the oxide semiconductor film <b>106</b> are stacked, lamp light is transmitted through compared to a region in which the wiring <b>105</b> and the gate electrode <b>103</b> are formed; consequently, heat is not easily absorbed and a heating temperature is lower than that of the wiring <b>105</b>. Consequently, since a large region of the substrate <b>101</b> is 350° C. or lower, shrinking does not occur easily. Note that the larger the region in which the gate electrode <b>103</b> is not formed, shrinking of the substrate <b>101</b> is suppressed.
0086Next, a semiconductor device is manufactured by forming an interlayer insulating film, a source electrode, a drain electrode, a pixel electrode, a light emitting element, and the like over the oxide semiconductor film <b>106</b>.
0087In the present invention, when ZnO is used as a semiconductor, crystallinity of a ZnO layer is improved with a heat treatment temperature of about 300° C.; therefore, compared to when a crystalline silicon film is used as a semiconductor film, the heat treatment temperature is suppressed. Also, since an oxide semiconductor film having a high light transmitting property is used and a gate electrode is selectively heated by LRTA, most of a substrate is not heated and shrinking of the substrate can be suppressed. Further, since a material used for a wiring has higher reflectivity with respect to lamp light than that of the gate electrode, crystallinity of the oxide semiconductor film can be improved even if a temperature to which the wiring is heated is suppressed to around 350° C. Therefore, an Al wiring which has a low melting point can be used. Also, formation of an insulating film due to diffusion of oxygen in the oxide semiconductor film to the Al can be prevented. Since the Al wiring is inexpensive and has low resistance, a semiconductor device with favorable performance can be manufactured at low cost and with favorable productivity.
0000(Embodiment Mode 2)
0088In this embodiment mode, a structure that is different from that in Embodiment Mode 1 is described with reference to <figref idref="DRAWINGS">FIGS. 3A to 3C</figref>. Note that steps of forming a base film <b>302</b>, a gate electrode <b>303</b>, and a gate insulating film <b>304</b> over a substrate <b>301</b> corresponds to the steps of forming the base film <b>102</b>, the gate electrode <b>103</b>, and the gate insulating film <b>104</b> over the substrate <b>101</b> of Embodiment Mode 1, respectively; therefore, refer to Embodiment Mode 1 for the steps.
0089A first oxide semiconductor film <b>305</b> is formed over the gate insulating film <b>304</b>. For the oxide semiconductor film <b>305</b>, zinc oxide (ZnO) in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist, added with one type or a plurality of types of impurity elements selected from Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, and Group 17 elements can be used. Alternatively, zinc oxide (ZnO) in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist, which is not added with any impurity element can also be used. Further, any of the following can also be used: InGaO<sub>3</sub>(ZnO)<sub>5</sub>, magnesium zinc oxide (Mg<sub>x</sub>Zn<sub>1-x</sub>O), cadmium zinc oxide (Cd<sub>x</sub>Zn<sub>1-x</sub>O), cadmium oxide (CdO), or an In—Ga—Zn—O based amorphous oxide semiconductor (a-IGZO). Here, zinc oxide is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm) as the first oxide semiconductor film <b>305</b> by a sputtering method.
0090Subsequently, LRTA is performed towards a substrate surface to make crystallinity favorable (<figref idref="DRAWINGS">FIG. 3A</figref>). LRTA may be performed at 250° C. to 570° C. (preferably at 300° C. to 400° C., and more preferably at 300° C. to 350° C.) for 1 minute to 1 hour, preferably 10 minutes to 30 minutes. LRTA is performed with radiation from one type or a plurality of types of lamps selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. In this embodiment mode, lamp heating is performed on the gate electrode <b>303</b> for 30 minutes in an oxygen atmosphere so that the gate electrode becomes about 300° C., in order to improve crystallinity of a region of the first oxide semiconductor film <b>305</b> which overlaps the gate electrode <b>303</b> with the gate insulating film therebetween. Since the first oxide semiconductor film <b>305</b> has a light transmitting property, the gate electrode <b>303</b> is heated with priority, and crystallinity of the first oxide semiconductor film <b>305</b> increases from a periphery of the gate electrode <b>303</b> towards the outside. Then, as shown in <figref idref="DRAWINGS">FIG. 3B</figref>, a second oxide semiconductor film including a second oxide semiconductor region <b>309</b> and a first oxide semiconductor region <b>308</b> with more favorable crystallinity than the second oxide semiconductor region <b>309</b> are formed. Note that in <figref idref="DRAWINGS">FIG. 3A</figref>, although lamp heating is performed towards a front surface side of the substrate <b>301</b>, LRTA may be performed towards a rear surface of the substrate. Since the oxide semiconductor film <b>305</b> has a light transmitting property, most region of the substrate is not easily heated even if LRTA is performed. Consequently, deformation such as shrinking of the substrate can be suppressed even if a resin with a low melting point or the like is used for the substrate. Note that crystallinity of a surface of the oxide semiconductor film and a periphery thereof may be improved directly by performing lamp heating towards the substrate surface with LRTA with increased output. Also, for the oxide semiconductor film overlapping with the gate electrode, a surface of the oxide semiconductor film or a gate insulating layer <b>304</b> side and a periphery thereof may be crystallized with priority when performing lamp heating towards the substrate surface, by adjusting wavelength of lamp light, reflectivity of the gate electrode, and film thickness of the oxide semiconductor film, so that lamp light reflecting off of the gate electrode is absorbed by the surface of the oxide semiconductor film on the gate insulating layer <b>304</b> side and the periphery thereof. Further, when a glass substrate is used for the substrate, lamp light used is of the visible light region to the infrared light region. Since light in these wavelength regions is not easily absorbed by the glass substrate, heating of the glass substrate can be suppressed to a minimum. Note that lamp heating may be performed a plurality of times. By performing lamp heating a plurality of times, heating time can be gained at the same time as suppressing a rise in a temperature of the substrate.
0091Note that instead of LRTA, crystallinity of the oxide semiconductor film may be selectively improved by laser light irradiation, ultraviolet irradiation, or by a combination thereof. When laser irradiation is used, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. A laser beam that can be used here is one or a plurality of that which oscillates from a gas laser such as an Ar laser, Kr laser, or an excimer laser; a laser of which a medium is a monocrystalline YAG, YVO<sub>4</sub>, forsterite (Mg<sub>2</sub>SiO<sub>4</sub>), YAlO<sub>3</sub>, or GdVO<sub>4 </sub>doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, or polycrystalline (ceramic) YAG, Y<sub>2</sub>O<sub>3</sub>, YVO<sub>4</sub>, YAlO<sub>3</sub>, or GdVO<sub>4</sub>, doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta; a glass laser; a ruby laser; an alexandrite laser; a Ti:sapphire laser; a copper vapor laser; and a gold vapor laser. By emitting a laser beam from the second harmonic to the fourth harmonic of the fundamental harmonic of such a laser beam, crystallinity can be made to be favorable. Note that it is preferable to use laser light having larger energy than a band gap of the oxide semiconductor film. For example, laser light emitted from a KrF, ArF, XeCl, or an XeF excimer laser oscillator may be used.
0092Subsequently, over the first oxide semiconductor region <b>308</b> and the second oxide semiconductor region <b>309</b>, Ti and Al are deposited by a sputtering method to form a Ti layer and an Al layer. After that, a wiring <b>306</b> and a wiring <b>307</b> are formed as a source wiring and a drain wiring by performing dry etching on the Ti layer and the Al layer using photolithography and Cl<sub>2 </sub>gas (<figref idref="DRAWINGS">FIG. 3C</figref>). The wirings <b>306</b> and <b>307</b> are each formed to have a thickness of 10 to 200 nm by using an acceleration voltage of 1.5 kw, a pressure of 0.4 Pa, and Ar (flow rate of 30 sccm). Note that although the wirings <b>306</b> and <b>307</b> are formed as stacked layers, if materials used for the wiring <b>306</b> and <b>307</b> have favorable compatibility with the oxide semiconductor film <b>305</b>, the wirings <b>306</b> and <b>307</b> may be formed in a single layer. As the material for each of the wirings <b>306</b> and <b>307</b>, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), or neodymium (Nd), or an alloy or a metal nitride thereof can be appropriately used. Alternatively, a material having a light transmitting property such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide (In<sub>2</sub>O<sub>3</sub>), tin oxide (SnO<sub>2</sub>), zinc oxide (ZnO), zinc oxide added with aluminum (AlZnO), zinc oxide added with gallium (GaZnO), or the like can be appropriately used.
0093Subsequently, a semiconductor device is manufactured by forming an interlayer insulating film, a wiring, a pixel electrode, a light emitting element and the like over the oxide semiconductor film <b>305</b>, the wiring <b>306</b> and the wiring <b>307</b>.
0094In this embodiment mode, a wiring is formed after performing LRTA on the oxide semiconductor film <b>305</b> to improve crystallinity. Therefore, a material having lower reflectivity with respect to lamp light than that of the gate electrode <b>303</b> may be used for the wiring <b>306</b>, and the material for the wiring is not limited to those mentioned in Embodiment Mode 1 as long as it has favorable compatibility with the oxide semiconductor film <b>305</b>.
0095Note that after the oxide semiconductor film <b>305</b> is formed, heating by LRTA may be performed before or after processing the oxide semiconductor film <b>305</b> into a desirable shape.
0096In the present invention, when zinc oxide is used for a semiconductor film, since crystallinity of the semiconductor film improves at a heat treatment temperature of around 300° C., heat treatment temperature can be suppressed and a crystallization step can be performed at low cost compared to when a crystalline silicon film is used as the semiconductor film. Further, since a gate electrode is selectively heated by LRTA using an oxide semiconductor film having a high light transmitting property, most of a substrate is not heated and shrinking of the substrate can be suppressed.
0000(Embodiment Mode 3)
0097An embodiment mode of the present invention is described with reference to <figref idref="DRAWINGS">FIGS. 4A to 5C</figref>. This embodiment mode is an example of a semiconductor device including a channel protective thin film transistor.
0098As a substrate <b>400</b>, a glass substrate including barium borosilicate glass, alumino borosilicate glass, or the like; a silicon substrate; a plastic substrate having heat resistance; or a resin substrate is used. As the plastic substrate or the resin substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, polyimide, or the like can be used. Also, a surface of the substrate <b>400</b> may be polished by a CMP method so that the surface is planarized. Note that an insulating layer may be formed over the substrate <b>400</b>. The insulating layer is formed to have a single layer structure or a stacked layer structure using at least one of an oxide material including silicon and a nitride material including silicon, by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer is not necessarily formed, but it has effects of blocking contaminants and the like from the substrate <b>400</b>, as well as suppressing conduction of heat to the substrate.
0099A conductive film <b>401</b> is formed over the substrate <b>400</b>. The conductive film <b>401</b> is processed into a desired shape and becomes a gate electrode. The conductive film <b>401</b> is preferably formed by a method such as a printing method, an electrolytic plating method, or an evaporation method, using a material having a low reflectivity with respect to a wavelength of a light source used for LRTA heating (a material which easily absorbs heat, in other words, that which is easily heated). By using the material having a low reflectivity, a subsequent heating step becomes possible. As the conductive film <b>401</b>, a metal such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), or neodymium (Nd), or an alloy or a metal nitride thereof can be appropriately used. Further, the conductive film <b>401</b> may have a stacked layer structure of a plurality of these layers. Typically, a tantalum nitride film may be stacked over a substrate surface, and then a tungsten film may be stacked thereover. Further, silicon added with an impurity element imparting one conductivity type may also be used. For example, an n-type silicon film, of an amorphous silicon film including an impurity element imparting n-type such as phosphorus (P) can be used. The conductive film <b>401</b> is formed to have a thickness of 10 nm to 200 nm.
0100In this embodiment mode, the conductive film <b>401</b> is formed to have a thickness of 150 nm by a sputtering method using tungsten (W).
0101A mask made of a resist is formed over the conductive film <b>401</b> using a photolithography step, and the conductive film <b>401</b> is processed into a desired shape using the mask to form a gate electrode <b>402</b> (see <figref idref="DRAWINGS">FIG. 4B</figref>).
0102Subsequently, a gate insulating film <b>403</b><i>a </i>and a gate insulating film <b>403</b><i>b </i>are formed over the gate electrode <b>402</b> so as to have a stacked layer structure of two layers. The stacked insulating films may be formed consecutively in the same chamber without breaking a vacuum and under the same temperature, by changing reaction gases. By forming the insulating films consecutively without breaking the vacuum, contamination of an interface between the stacked films can be prevented.
0103For the gate insulating film <b>403</b><i>a </i>and the gate insulating film <b>403</b><i>b</i>, silicon oxide (SiO<sub>x</sub>), silicon nitride (SiN<sub>x</sub>), silicon oxynitride (SiO<sub>x</sub>N<sub>y</sub>) (x>y), silicon nitride oxide (SiN<sub>x</sub>O<sub>y</sub>) (x>y), or the like can be appropriately used. Also, instead of the gate insulating film <b>403</b><i>a</i>, the gate electrode <b>402</b> may be oxidized to form an oxide film. Note that to prevent diffusion of impurities and the like from the substrate, the gate insulating film <b>403</b><i>a </i>is preferably formed using silicon nitride (SiN<sub>x</sub>), silicon nitride oxide (SiN<sub>x</sub>O<sub>y</sub>) (x>y), or the like. Further, the gate insulating film <b>403</b><i>b </i>is desirably formed using silicon oxide (SiO<sub>x</sub>), silicon oxynitride (SiO<sub>x</sub>N<sub>y</sub>) (x>y), or the like. Note that in order to form a dense insulating film with little gate leak current at a low deposition temperature, it is favorable to include a noble gas element such as argon in a reaction gas so that the noble gas element is incorporated in the insulating film to be formed. In this embodiment mode, the gate insulating film <b>403</b><i>a </i>is formed using a silicon nitride film with a thickness of 50 nm to 140 nm that is formed with SiH<sub>4 </sub>and NH<sub>3 </sub>as reaction gases, and the gate insulating film <b>403</b><i>b </i>is formed using a silicon oxide film with a thickness of 100 nm that is formed with SiH<sub>4 </sub>and N<sub>2</sub>O as reaction gases, and stacked thereover. Note that it is preferable that the gate insulating film <b>403</b><i>a </i>and the gate insulating film <b>403</b><i>b </i>each have a thickness of 50 nm to 100 nm.
0104Alternatively, the gate insulating film <b>403</b><i>b </i>may be formed using alumina (Al<sub>2</sub>O<sub>3</sub>) or aluminum nitride (AlN) each having favorable compatibility with an oxide semiconductor film to be subsequently formed. In this case, by using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like having a high insulating property for the gate insulating film <b>403</b><i>a</i>, and using alumina or aluminum nitride having a favorable interface property with respect to the oxide semiconductor film for the gate insulating film <b>403</b><i>b</i>, a high reliability gate insulating film can be formed. The gate insulating film may have three layers, and the third layer may be a gate insulating film using alumina or aluminum nitride.
0105Subsequently, an oxide semiconductor film <b>404</b> is formed over the gate insulating film <b>403</b><i>b</i>. The oxide semiconductor film <b>404</b> may be formed to have a thickness of 100 nm by a sputtering, method under the following conditions: a flow rate of Ar:O<sub>2</sub>=50:5 (sccm), and a pressure of 0.4 Pa.
0106For the oxide semiconductor film <b>404</b>, ZnO in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist, added with one type or a plurality of types of impurity elements selected from Group 1 elements, Group 13 elements, Group 14 elements, Group 15 elements, and Group 17 elements can be used. Alternatively, ZnO in an amorphous state, a polycrystalline state, or a microcrystalline state in which both amorphous and polycrystalline states exist which is not added with any impurity element can also be used. Further, any of the following can also be used: InGaO<sub>3</sub>(ZnO)<sub>5</sub>, magnesium zinc oxide (Mg<sub>x</sub>Zn<sub>1-x</sub>O), cadmium zinc oxide (Cd<sub>x</sub>Zn<sub>1-x</sub>O), cadmium oxide (CdO), or an In—Ga—Zn—O based amorphous oxide semiconductor (a-IGZO).
0107Note that when ZnO is used for the oxide semiconductor film <b>404</b>, it is favorable that ZnO is added (doped) with nitrogen. ZnO normally shows an n-type semiconductor property. By adding nitrogen, since nitrogen works as an acceptor with respect to ZnO, a threshold voltage can be suppressed as a result.
0108Subsequently, heating of the oxide semiconductor film <b>404</b> is performed towards a front surface or a rear surface of the substrate <b>400</b> by an LRTA method (see <figref idref="DRAWINGS">FIG. 4D</figref>). LRTA is performed with radiation from one or a plurality of lamps selected from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. LRTA is performed at 250° C. to 570° C. (preferably 300° C. to 400° C., more preferably 300° C. to 350° C.) for 1 minute to 1 hour, preferably 10 minutes to 30 minutes. In this embodiment mode, lamp heating is performed with a halogen lamp as a light source, and in an oxygen atmosphere at 300° C. for 30 minutes.
0109By performing LRTA, the gate electrode <b>402</b> is selectively heated in a short amount of time, and a first oxide semiconductor region with improved crystallinity is formed by heat thereof in a region <b>434</b> formed in a periphery of the gate electrode <b>402</b>, which is indicated by a dotted line. On the other hand, a region <b>424</b> that is not the region <b>434</b> indicated by the dotted line is barely heated since there is little absorption of lamp light, and a second oxide semiconductor region having a different crystallinity from that of the first oxide semiconductor region (see <figref idref="DRAWINGS">FIG. 4E</figref>). Consequently, since only a region in which the gate electrode <b>402</b> is formed is selectively heated and the other region is not heated, shrinking and bending of the substrate <b>400</b> can be suppressed. Note that crystallinity in a periphery of the surface of the oxide semiconductor film may be improved directly by performing lamp heating towards the substrate surface with LRTA with increased output. Also, for the oxide semiconductor film overlapping with the gate electrode, a surface of the oxide semiconductor film on a gate insulating layer <b>403</b><i>b </i>side and a periphery thereof may be crystallized with priority when performing lamp heating towards the substrate surface, by adjusting wavelength of lamp light, reflectivity of the gate electrode, and film thickness of the oxide semiconductor film, so that lamp light reflecting off of the gate electrode is absorbed by the surface of the oxide semiconductor film on the gate insulating layer <b>403</b><i>b </i>side and the periphery thereof. Further, when a glass substrate is used for the substrate, lamp light used is of the visible light region to the infrared light region. Since light in these wavelength regions is not easily absorbed by the glass substrate, heating of the glass substrate can be suppressed to a minimum. Note that lamp heating may be performed a plurality of times. By performing lamp heating a plurality of times, heating time can be gained at the same time as suppressing a rise in a temperature of the substrate.
0110Note that instead of LRTA, crystallinity of the oxide semiconductor film may be selectively improved by laser light irradiation, ultraviolet irradiation, or by a combination thereof. When laser irradiation is used, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. A laser beam that can be used here is one or a plurality of that which oscillates from a gas laser such as an Ar laser, Kr laser, or an excimer laser; a laser of which a medium is a monocrystalline YAG, YVO<sub>4</sub>, forsterite (Mg<sub>2</sub>SiO<sub>4</sub>), YAlO<sub>3</sub>, or GdVO<sub>4 </sub>doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, or polycrystalline (ceramic) YAG, Y<sub>2</sub>O<sub>3</sub>, YVO<sub>4</sub>, YAlO<sub>3</sub>, or GdVO<sub>4</sub>, doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta; a glass laser; a ruby laser; an alexandrite laser; a Ti:sapphire laser; a copper vapor laser; and a gold vapor laser. By emitting a laser beam from the second harmonic to the fourth harmonic of the fundamental harmonic of such a laser beam, crystallinity can be made to be favorable. Note that it is preferable to use laser light having larger energy than a band gap of the oxide semiconductor film. For example, laser light emitted from a KrF, ArF, XeCl, or an XeF excimer laser oscillator may be used.
0111Subsequently, a protective film <b>405</b> is formed over the oxide semiconductor film <b>404</b>, and a resist <b>406</b> is formed over the protective film <b>405</b> (see <figref idref="DRAWINGS">FIG. 4F</figref>). By a photolithography step using the resist <b>406</b> as a mask, the protective film <b>405</b> is processed into a desired shape to form a channel protective film <b>407</b>. As the channel protective film, silicon oxide (SiO<sub>x</sub>), silicon nitride (SiN<sub>x</sub>), silicon oxynitride (SiO<sub>x</sub>N<sub>y</sub>) (x>y), silicon nitride oxide (SiN<sub>x</sub>O<sub>y</sub>) (x>y), or the like can be appropriately used. By forming the channel protective film <b>407</b>, a semiconductor layer of a channel portion can be prevented from being etched when a source electrode and a drain electrode are formed. In this embodiment mode, silicon nitride is formed as the protective film <b>405</b>, and then the channel protective film <b>407</b> is formed (see <figref idref="DRAWINGS">FIG. 4G</figref>).
0112Subsequently, a mask <b>408</b> is manufactured with a resist (<figref idref="DRAWINGS">FIG. 4H</figref>), and etching is performed on the oxide semiconductor film <b>404</b> to process into a desired shape by a photolithography step using the mask <b>408</b>, to form an oxide semiconductor film <b>409</b> (also called island-shaped oxide semiconductor film) (<figref idref="DRAWINGS">FIG. 5A</figref>). Note that diluted fluorinated acid is used for the etching. Subsequently, a first conductive film <b>411</b> and a second conductive film <b>412</b> are formed over the oxide semiconductor film <b>409</b>, and a mask <b>413</b> is formed by a photolithography step with a resist (<figref idref="DRAWINGS">FIG. 5B</figref>). The first conductive film <b>411</b> and the second conductive film <b>412</b> are processed into desired shapes using the mask <b>413</b>, and first conductive films <b>414</b><i>a </i>and <b>414</b><i>b</i>, and second conductive films <b>415</b><i>a </i>and <b>415</b><i>b </i>each functioning as a source electrode or a drain electrode are formed (<figref idref="DRAWINGS">FIG. 5C</figref>).
0113As the mask, a commercially available resist material including a photosensitizing agent may be used. For example, a typical positive type resist, such a novolac resin or a naphthoquinone diazide compound which is a photosensitizing agent; or a negative type resist, such as a base resin, diphenylsilanediol, or an acid generator may be used. In using any of the materials, surface tension and viscosity thereof is appropriately adjusted by adjusting a concentration of a solvent, or by adding a surfactant or the like. Also, when a conductive material including a photosensitive substance having photosensitivity is used for the conductive films, the conductive films can be processed into desired shapes by being subjected to direct laser light irradiation, exposure, and removal with an etchant, without forming a mask from resist. In this case, there is an advantage that a step is simplified since a mask is not required to be formed.
0114As the conductive material including a photosensitive substance, a material including a metal such as Ag, Au, Cu, Ni, Al, or Pt, or an alloy thereof; an organic high molecular compound resin; a photo polymerization initiator; a photopolymerization monomer; and a photosensitive resin made of a solvent or the like, may be used. As the organic high molecular resin, a novolac resin, an acrylic copolymer, a methacrylic copolymer, a cellulose derivative, a cyclic rubber resin, or the like is used.
0115Note that before forming the first conductive film <b>411</b>, one more layer of a conductive film made of for example zinc oxide added with aluminum (AlZnO) or zinc oxide added with gallium (GaZnO) may be provided as an n-type semiconductor, over the oxide semiconductor film <b>404</b>. By forming the conductive film made of AlZnO or GaZnO, compatibility between the first conductive film <b>411</b> and the oxide semiconductor film <b>409</b> becomes favorable, and a contact resistance between the oxide semiconductor film <b>409</b> and a source electrode and a drain electrode can be reduced. Alternatively, for example, a stacked layer structure of forming Ti over GaZnO, or forming GaZnO over Ti may be provided.
0116As the first conductive films <b>414</b><i>a </i>and <b>414</b><i>b </i>and the second conductive films <b>415</b><i>a </i>and <b>415</b><i>b</i>, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), copper (Cu), chromium (Cr), cobalt (Co), nickel (Ni), platinum (Pt), titanium (Ti), or neodymium (Nd), or an alloy or a metal nitride thereof can be appropriately used. For example, the following combinations of the first conductive films <b>414</b><i>a</i>, <b>414</b><i>b </i>and the second conductive films <b>415</b><i>a</i>, <b>415</b><i>b </i>can be considered: Ti and Al; Ta and W; TaN and Al; and TaN and Cu; as the first conductive films and the second conductive films, respectively. Also, a combination of a third conductive film using Ti in addition to the first conductive films using Ti and the second conductive films using Al can be considered. Further, an AgPdCu alloy may be used for one of a first layer and a second layer. Furthermore, a structure may be a three-layer stacked layer structure of sequentially stacking W, an alloy of Al and Si (Al—Si), and TiN. Note that tungsten nitride, an alloy film of Al and Ti (Al—Ti), and Ti may be used instead of W, the alloy of Al and Si (Al—Si), and TiN, respectively. In order to improve heat resistance, an element such as titanium, silicon, scandium, neodymium, or copper may be added to aluminum at 0.5 to 5 atomic %.
0117As a conductive material to form the first conductive film <b>411</b> and the second conductive film <b>412</b>, a material having a light transmitting property such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide (In<sub>2</sub>O<sub>3</sub>), tin oxide (SnO<sub>2</sub>), or zinc oxide (ZnO), or an appropriate combination thereof may be used.
0118In this embodiment mode, the first conductive film <b>411</b> and the second conductive film <b>412</b> are formed after LRTA is performed on the oxide semiconductor film <b>305</b> and crystallinity thereof is improved. Therefore, a material having lower reflectivity with respect to lamp light than that of the gate electrode <b>402</b> may be used for the first conductive film <b>411</b> and the second conductive film <b>412</b>, and a conductive material for a wiring or an electrode is not limited to those mentioned in Embodiment Mode 1 as long as it has favorable compatibility with the oxide semiconductor film <b>305</b>.
0119In this embodiment mode, either plasma etching (dry etching) or wet etching may be employed for an etching process; however, plasma etching is suitable for treating a substrate with a large area. As an etching gas, a fluorinated acid based gas such as CF<sub>4</sub>, NF<sub>3</sub>, SF<sub>6</sub>, or CHF<sub>3</sub>; a chlorine based gas typified by Cl<sub>2</sub>, BCl<sub>3</sub>, SiCl<sub>4</sub>, CCl<sub>4</sub>, or the like; or an O<sub>2 </sub>gas may be used, to which an inert gas such as He or Ar may be appropriately added. Also, by applying an etching process using atmospheric pressure discharge, electric discharge machining is possible locally, and a mask layer is not required to be formed on the an entire surface of the substrate.
0120Before applying the resist in the photolithography step of this embodiment mode, an insulating film with a thickness of about several nm may be formed over a surface of the oxide semiconductor film. By this step, the oxide semiconductor film and the resist coming into direct contact with each other can be avoided, and entering of impurities included in the resist into the oxide semiconductor film can be prevented.
0121By the above steps, a bottom gate type (also called reverse staggered type) thin film transistor in which a semiconductor layer of a channel portion is not etched can be manufactured. Note that although a bottom gate type TFT is manufactured in this embodiment mode, a top gate type TFT may be formed as long as crystallinity of at least a channel forming region of an oxide semiconductor film can be improved by heating a gate electrode that is formed over an oxide semiconductor film formed over a substrate, with a gate insulating film therebetween.
0122This embodiment mode can be appropriately combined with Embodiment Modes 1 and 2.
0000(Embodiment Mode 4)
0123An embodiment mode of the present invention is described with reference to <figref idref="DRAWINGS">FIGS. 6A to 6F</figref>. This embodiment mode is an example of a semiconductor device according to Embodiment Mode 3 having a channel etch type thin film transistor. Therefore, repeated description of the same portions or the portions having similar functions is omitted.
0124A gate electrode <b>602</b> is formed over a substrate <b>600</b>, and a gate insulating film <b>603</b><i>a </i>and a gate insulating film <b>603</b><i>b </i>are formed covering the gate electrode <b>602</b> (<figref idref="DRAWINGS">FIG. 6A</figref>). An oxide semiconductor film <b>620</b> is formed over the gate insulating film <b>603</b><i>b</i>, and LRTA is performed towards a substrate surface to form an oxide semiconductor film <b>620</b> including a first oxide semiconductor region <b>604</b> with improved crystallinity in a region indicated by a dotted line, and a second oxide semiconductor region <b>605</b> in which crystallization is not as progressed as the first oxide semiconductor region <b>604</b> (see <figref idref="DRAWINGS">FIG. 6B</figref>). A mask <b>608</b> is provided over the oxide semiconductor film (<figref idref="DRAWINGS">FIG. 6C</figref>), and the oxide semiconductor film is processed into a desired shape by a photolithography step to form an oxide semiconductor film <b>609</b> (<figref idref="DRAWINGS">FIG. 6D</figref>).
0125Next, a first conductive film <b>611</b> and a second conductive film <b>612</b> are formed. Then, a mask <b>613</b> made of a resist is formed (see <figref idref="DRAWINGS">FIG. 6E</figref>). In this embodiment mode, conductive films containing titanium and aluminum are formed by a sputtering method as each of the first conductive film <b>611</b> and the second conductive film <b>612</b>.
0126Subsequently, the first conductive film <b>611</b> and the second conductive film <b>612</b> are processed into a desired shape using the mask <b>613</b> by a photolithography step, and first conductive films <b>615</b><i>a </i>and <b>615</b><i>b</i>, and second conductive films <b>616</b><i>a </i>and <b>616</b><i>b </i>each functioning as a source electrode or a drain electrode are formed (<figref idref="DRAWINGS">FIG. 6F</figref>).
0127By the above steps, a thin film transistor in which a semiconductor layer of a part of a channel portion is etched can be manufactured.
0128Note that in this embodiment mode, one more layer of a conductive film made of for example zinc oxide added with aluminum (AlZnO) or zinc oxide added with gallium (GaZnO) may be provided as an n-type oxide semiconductor, between the oxide semiconductor film and the first conductive film <b>611</b>. Alternatively, for example, a stacked layer structure of forming Ti over GaZnO, or forming GaZnO over Ti may be provided. By forming an n-type oxide semiconductor film, connection between the first conductive film <b>611</b> that becomes a source electrode or a drain electrode and the oxide semiconductor film can be made to be favorable, and a contact resistance can be reduced.
0129This embodiment mode can be appropriately combined with Embodiment Modes 1 to 3.
0000(Embodiment Mode 5)
0130In this embodiment mode, a light emitting device which a bottom gate type thin film transistor formed in Embodiment Mode 3 or Embodiment Mode 4 is connected to a pixel electrode is described with reference to <figref idref="DRAWINGS">FIG. 7</figref>. Note that a thin film transistor of this embodiment mode is a channel-etched type.
0131<figref idref="DRAWINGS">FIG. 7</figref> shows a cross-sectional view of a TFT used in a driver circuit and a cross-sectional view of a TFT used in a pixel portion. A reference numeral <b>701</b> denotes a cross-sectional view of a TFT used in a driver circuit, a reference numeral <b>702</b> denotes a cross-sectional view of a TFT used in a pixel portion, and a reference numeral <b>703</b> denotes a cross-sectional view of a light emitting element provided with a current by the TFT <b>702</b>. The TFTs <b>701</b> and <b>702</b> are bottom gate types.
0132The TFT <b>701</b> of the driver circuit includes a gate electrode <b>710</b> formed over a substrate <b>700</b>; a gate insulating film <b>711</b> covering the gate electrode <b>710</b>; and an oxide semiconductor film <b>712</b> containing zinc oxide which overlaps with the gate electrode <b>710</b> with the gate insulating film <b>711</b> interposed therebetween. Further, the TFT <b>701</b> includes first conductive films <b>713</b> each functioning as a source electrode or a drain electrode, and second conductive films <b>714</b> each functioning as a source electrode or a drain electrode. Note that the first conductive films <b>713</b> and the second conductive films <b>714</b> also function as wiring.
0133In <figref idref="DRAWINGS">FIG. 7</figref>, the gate insulating layer <b>711</b> is formed of two layers of insulating films; however, the present invention is not limited to this structure. The gate insulating film <b>711</b> may be formed with a single layer of an insulating film or three or more layers of insulating films.
0134The second conductive films <b>714</b> are formed with aluminum or an alloy containing aluminum. Also, the second conductive films <b>714</b> that are a pair face each other with a channel forming region of the oxide semiconductor film <b>712</b> in therebetween.
0135Further, the first conductive films <b>713</b> are formed with titanium. The first conductive films <b>713</b> are not required to be provided; however, electrical contact property of the second conductive film <b>711</b> with the oxide semiconductor film <b>712</b> becomes favorable. Also, the first conductive films <b>713</b> have a function as barrier layers for preventing diffusion of oxygen in the oxide semiconductor film <b>712</b> to the second conductive films <b>714</b>. As a result, reliability of a TFT can be improved. Note that an oxide semiconductor film is known to show an n-type without performing anything thereto. Therefore, the first oxide semiconductor film in which a channel is formed may have its conductivity type controlled in advance so as to be close to an i-type (also called as an intrinsic-type that is defined as a conductivity type having an equal number of negative and positive charges) as much as possible, by adding an impurity imparting p-type conductivity.
0136The TFT <b>702</b> of the pixel portion includes a gate electrode <b>720</b> formed over the substrate <b>700</b>, the gate insulating film <b>711</b> covering the gate electrode <b>720</b>, and an oxide semiconductor film <b>722</b> which overlaps with the gate electrode <b>720</b> with the gate insulating film <b>711</b> interposed therebetween. Further, the TFT <b>702</b> includes first conductive films <b>723</b> each functioning as a source electrode or a drain electrode, and second conductive films <b>724</b> each functioning as a source electrode or a drain electrode.
0137The second conductive films <b>724</b> are formed with aluminum or an alloy containing aluminum. Also, the second conductive films <b>724</b> that are a pair face each other with a region in which a channel of the oxide semiconductor film <b>722</b> is formed in between.
0138Further, the first conductive films <b>723</b> are formed with titanium. The first conductive films <b>723</b> are not required to be provided; however, electrical contact property of the second conductive film <b>724</b> with the oxide semiconductor film <b>722</b> becomes favorable. Also, the first conductive films <b>723</b> have a function as barrier layers for preventing diffusion of oxygen in the oxide semiconductor film <b>722</b> to the second conductive films <b>724</b>. As a result, reliability of a TFT can be improved. Note that an oxide semiconductor film is known to show an n-type without performing anything thereto. Therefore, the first oxide semiconductor film in which a channel is formed may have its conductivity type controlled in advance so as to be close to an i-type as much as possible, by adding an impurity imparting p-type conductivity.
0139Also, a first passivation film <b>740</b> and a second passivation film <b>741</b> each formed of an insulating film are formed covering the TFTs <b>701</b> and <b>702</b>. The first passivation film <b>740</b> and the second passivation film <b>741</b> can be formed by a thin film formation method such as a plasma CVD method or a sputtering method, using an insulating material such as silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN), or the like. The passivation films covering the TFTs <b>701</b> and <b>702</b> is not limited to two layers, and a single layer or three or more layers may be provided. For example, the first passivation film <b>740</b> and the second passivation film <b>741</b> can be formed of silicon nitride and silicon oxide, respectively. By forming a passivation film of silicon nitride or silicon nitride oxide, entering of impurities from outside into a semiconductor element can be prevented, and degradation of the TFTs <b>701</b> and <b>702</b> due to an effect of moisture or the like can be prevented. In this embodiment mode, the first passivation film <b>740</b> and the second passivation film <b>741</b> are consecutively formed in the same chamber by performing gas switching.
0140Next, one of the second conductive films <b>724</b> is connected to a pixel electrode of a light emitting element <b>703</b>.
0141Subsequently, an insulating layer <b>729</b> (also called partition, or bank) is selectively formed. The insulating layer <b>729</b> is formed so as to have an opening portion over the pixel electrode <b>730</b> and so as to cover the second passivation film <b>741</b>. In this embodiment mode, the insulating layer <b>729</b> is formed covering an entire surface, and then etched using a mask of a resist or the like to form into a desired shape.
0142The insulating layer <b>729</b> can be formed with an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride; an inorganic siloxane based insulating material having an Si—O—Si bond among compounds made of silicon, oxygen, and hydrogen, using a siloxane based material as a starting material; or an organic siloxane based material in which hydrogen bonded with silicon is substituted with an organic group such as methyl or phenyl. Also, the insulating layer <b>729</b> may be formed using a photosensitive or a non-photosensitive material such as an acrylic resin, or a polyimide resin. The insulating layer <b>729</b> preferably has a form of which a curvature radius changes continuously, so that coatability of an electric field light emitting layer <b>731</b> and an opposing electrode <b>732</b> are improved.
0143Subsequently, the electric field light emitting layer <b>731</b> is formed over the pixel electrode <b>730</b> so as to be in contact therewith. As the electric field light emitting layer <b>731</b>, materials showing light emission of red (R), green (G), and blue (B), respectively, are each selectively formed by an evaporation method or the like using an evaporation mask. The materials showing light emission of red (R), green (G), and blue (B), respectively, are preferable since they can be formed by a droplet discharging method in a similar manner to a color filter (such as a low molecular compound or a high molecular compound), and in this case, RGB can be applied separately without using a mask. Note that other than a three-color combination of RGB, the combination may be with four colors by adding emerald green. Also, vermilion may be added. Further, a pixel including an EL element that emits white light may be combined.
0144The opposing electrode <b>732</b> is formed so as to be in contact with the electric field light emitting layer <b>731</b>. Note that although the light emitting element <b>703</b> includes an anode and a cathode, one is used as a pixel electrode, and the other is used as an opposing electrode. In this way, a light emitting device having a display function using a light emitting element is completed.
0145In the present invention, since a channel forming region of an oxide semiconductor film includes at least a crystallized region, a TFT having higher mobility than that of a TFT using an amorphous silicon film can be obtained. Also, since a crystallization step is performed at a lower temperature than that of a TFT using a crystalline silicon film, it is inexpensive as a process.
0146This embodiment mode can be appropriately combined with Embodiment Modes 1 to 4.
0000(Embodiment Mode 6)
0147In this embodiment mode, a liquid crystal display device in which a semiconductor element made of the bottom gate type thin film transistor to which the present invention is applied and a pixel electrode are connected, is described with reference to <figref idref="DRAWINGS">FIGS. 13A to 18B</figref>. Note that Embodiment Mode 5 can be referred to regarding the formation up to the second passivation film <b>741</b>; therefore, the same reference numerals are used as those of <figref idref="DRAWINGS">FIG. 7</figref>, and descriptions thereof are omitted.
0148As in <figref idref="DRAWINGS">FIG. 13A</figref>, after the second passivation film <b>741</b> is formed, an insulating layer <b>1329</b> is formed so as to cover the second passivation film <b>741</b>.
0149Subsequently, wirings <b>1371</b>, <b>1372</b>, <b>1373</b>, and <b>1374</b> connected to the second conductive films <b>714</b> and <b>724</b>, respectively, are formed via contact holes. Then, the second conductive films <b>724</b> are electrically connected to a pixel electrode <b>1330</b> of a liquid crystal element <b>1303</b> via the wiring <b>1374</b>. For the pixel electrode <b>1330</b>, in a case of manufacturing a transmissive type liquid crystal display panel, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium, tin oxide containing titanium oxide, or the like can be used. Of course, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), or the like can be used. Also, in a case of manufacturing a reflective type display panel, as a metal thin film having a reflective property, a conductive film made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, an alloy thereof, or the like can be used. The pixel electrode <b>1330</b> can be foliated by an evaporation method, a sputtering method, a CVD method, a printing method, a droplet discharging method, or the like.
0150Further, an orientation film <b>1331</b> is formed over the pixel electrode <b>1330</b> so as to be in contact therewith. Under a second substrate <b>1340</b> facing the first substrate <b>700</b> with the pixel electrode <b>1330</b> therebetween, an opposing electrode <b>1341</b> and an orientation film <b>1342</b> are stacked in this order. Also, a liquid crystal <b>1343</b> is provided between the pixel electrode <b>1330</b> and the orientation film <b>1331</b> and between the opposing electrode <b>1341</b> and the orientation film <b>1342</b>, and a portion where the pixel electrode <b>1330</b>, the liquid crystal <b>1343</b>, and the opposing electrode <b>1341</b> overlap each other corresponds to a liquid crystal element <b>1303</b>. Note that the pixel electrode <b>1330</b> may be formed to extend over the TFT <b>702</b>, as shown in <figref idref="DRAWINGS">FIG. 13B</figref>. Since an oxide semiconductor film has a light transmitting property with respect to visible light, when a transparent conductive film including indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc, oxide, titanium nitride, or the like each having a light transmitting property, an aperture ratio of a pixel portion can be improved.
0151Note that a distance (cell gap) between the pixel electrode <b>1330</b> and the opposing electrode <b>1341</b> is controlled by a spacer <b>1361</b>. Although in <figref idref="DRAWINGS">FIG. 13A</figref>, the spacer <b>1361</b> is formed by processing an insulating film provided on a first substrate <b>700</b> side into a desired shape, spacers prepared separately may be dispersed over the orientation film <b>1331</b> to control the cell gap. A reference numeral <b>1362</b> denotes a sealant, and by the sealant <b>1362</b>, the liquid crystal <b>1343</b> is sealed between the first substrate <b>700</b> and the second substrate <b>1340</b>.
0152Further, on a surface of the first substrate <b>700</b> that is not the surface over which the TFT <b>701</b> and the TFT <b>702</b> are formed, a polarizing plate <b>1350</b> is provided. Also, on a surface of the second substrate <b>1340</b> that is not the surface over which the opposing electrode <b>1341</b> is formed, a polarizing plate <b>1351</b> is provided. Note that the number of orientation films and polarizing plates, and positions thereof in a liquid crystal display device of the present invention are not limited to those shown in a structure of <figref idref="DRAWINGS">FIG. 13A</figref>.
0153In the present invention, since at least crystallization of a channel forming region of an oxide semiconductor film is improved, a TFT having higher mobility than that of a TFT using an amorphous silicon film can be obtained. Also, since a crystallization step is performed at a lower temperature than that of a TFT using a crystalline silicon film, it is inexpensive as a process. Further, since crystallinity of the oxide semiconductor film is selectively increased by lamp heating, the time it takes for crystallization can be shortened compared to when the entire oxide semiconductor film is crystallized. Therefore, yield can be increased. Also, since crystallization is performed selectively and in a short amount of time, shrinking of a substrate does not occur easily, and a substrate having a relatively low melting point such as a resin substrate can be used. Consequently, a TFT can be manufactured at low cost.
0154Also, since the channel forming region does not absorb visible light, unnecessary photocarriers are not generated. Therefore, a TFT with excellent light resistance can be formed.
0155Subsequently, a different structure of a pixel included in a liquid crystal display device of the present invention is described. <figref idref="DRAWINGS">FIG. 14A</figref> shows one mode of a circuit diagram of the pixel, and <figref idref="DRAWINGS">FIG. 14B</figref> shows one mode of a cross-sectional structure of the pixel corresponding to <figref idref="DRAWINGS">FIG. 14A</figref>.
0156In <figref idref="DRAWINGS">FIGS. 14A and 14B</figref>, a reference numeral <b>1501</b> denotes a switching TFT for controlling input of video signal to the pixel, and a reference numeral <b>1502</b> denotes a liquid crystal element. Specifically, potential of a video signal that is input to the pixel via the switching TFT <b>1501</b> is supplied to a pixel electrode of the liquid crystal element <b>1502</b>. Note that a reference numeral <b>1503</b> denotes a capacitor element for retaining voltage between the pixel electrode of the liquid crystal element <b>1502</b> and an opposing electrode when the switching TFT <b>1501</b> is turned off.
0157Specifically, gate electrodes of the switching TFT <b>1501</b> are connected to a scanning line G, and one of a source region and a drain region is connected to a signal line S, and the other is connected to a pixel electrode <b>1504</b> of the liquid crystal element <b>1502</b>. One of two electrodes included in the capacitor element <b>1503</b> is connected to the pixel electrode <b>1504</b> of the liquid crystal element <b>1502</b>, and the other is supplied with a constant potential, desirably a potential that is of the same level as that of the opposing electrode.
0158Note that in <figref idref="DRAWINGS">FIGS. 14A and 14B</figref>, a structure is that of a multi-gate structure in which the switching TFT <b>1501</b> is serially connected and a plurality of TFTs to which gate electrodes <b>1510</b> are connected share an oxide semiconductor film <b>1512</b>. By having the multi-gate structure, an off current of the switching TFT <b>1501</b> can be reduced. Specifically, although in <figref idref="DRAWINGS">FIGS. 14A and 14B</figref>, a structure of the switching TFT <b>1501</b> is that of two TFTs being serially connected to each other, it may be a multi-gate structure in which three or more TFTs are serially connected to each other, and in which the gate electrodes are also connected. Further, the switching TFT is not required to have a multi-gate structure, and it may be a TFT of a regular single-gate structure in which one gate electrode and one channel forming region are provided
0159Next, a mode of a TFT included in a liquid crystal display device of the present invention that is different from that of <figref idref="DRAWINGS">FIGS. 13A to 14B</figref> is described. <figref idref="DRAWINGS">FIG. 15</figref> shows a cross-sectional view of a TFT used in a driver circuit, and a cross-sectional view of a TFT used in a pixel portion. A reference numeral <b>2301</b> denotes the cross-sectional view of a TFT used in a driver circuit, a reference numeral <b>2302</b> denotes the cross-sectional view of a TFT used in a pixel portion, and a reference numeral <b>2303</b> denotes a cross-sectional view of a liquid crystal element.
0160The TFT <b>2301</b> of the driver circuit includes a gate electrode <b>2310</b> formed over a substrate <b>2300</b>, a gate insulating film <b>2311</b> covering the gate electrode <b>2310</b>, and an oxide semiconductor film <b>2312</b> including a crystallized region in at least a channel forming region, that overlaps with the gate electrode <b>2310</b> with the gate insulating film <b>2311</b> therebetween. Also, the TFT <b>2302</b> of the pixel portion includes a gate electrode <b>2320</b> formed over the substrate <b>2300</b>, the gate insulating film <b>2311</b> covering the gate electrode <b>2320</b>, and an oxide semiconductor film <b>2322</b> including a crystallized region in at least a channel forming region, that overlaps with the gate electrode <b>2320</b> with the gate insulating film <b>2311</b> therebetween. Further, channel protective films <b>2390</b> and <b>2391</b> formed of insulating films are funned so as to cover the channel forming regions of the oxide semiconductor films <b>2312</b> and <b>2322</b>. The channel protective films <b>2390</b> and <b>2391</b> are provided to prevent the channel forming regions of the oxide semiconductor films <b>2312</b> and <b>2322</b> from getting etched during manufacturing steps of the TFT <b>2301</b> and <b>2302</b>. Furthermore, the TFT <b>2301</b> includes first conductive films <b>2313</b> each functioning as a source electrode or a drain electrode and, second conductive films <b>2314</b> each functioning as a source electrode or a drain electrode; and the TFT <b>2302</b> includes first conductive films <b>2323</b> each functioning as a source electrode or a drain electrode and second conductive films <b>2324</b> each functioning as a source electrode or a drain electrode. Note that the first conductive films <b>2313</b> and <b>2323</b>, and the second conductive films <b>2314</b> and <b>2324</b> function as wirings layers.
0161In <figref idref="DRAWINGS">FIG. 15</figref>, the gate insulating layer <b>2311</b> is formed of two layers of insulating films; however the present invention is not limited to this structure. The gate insulating film <b>2311</b> may be formed with a single layer of an insulating film or three or more layers of insulating films.
0162The second conductive films <b>2314</b> and <b>2324</b> are formed with aluminum or an alloy containing aluminum. Also, the second conductive films <b>2314</b> that are a pair and the second conductive films <b>2324</b> that are a pair face each other with a region in which a channel of the oxide semiconductor film <b>2322</b> is formed in between.
0163Further, the first conductive films <b>2313</b> and <b>2323</b> are formed with titanium. The first conductive films <b>2313</b> and <b>2323</b> are not required to be provided; however, electrical contact property of the second conductive films <b>2314</b> and <b>2324</b> with the oxide semiconductor films <b>2312</b> and <b>2322</b> becomes favorable. Also, the first conductive films <b>2313</b> and <b>2323</b> have a function as barrier layers for preventing diffusion of oxygen in the oxide semiconductor films <b>2312</b> and <b>2322</b> to the second conductive films <b>2314</b> and <b>2324</b>. As a result, reliability of a TFT can be improved. Note that the oxide semiconductor films <b>2312</b> and <b>2322</b> are known to show an n-type without performing anything thereto. Therefore, the first oxide semiconductor films in which channels are formed may have their conductivity type controlled in advance so as to be close to an i-type as much as possible, by adding an impurity imparting p-type conductivity.
0164Also, a first passivation film <b>2380</b> and a second passivation film <b>2381</b> each formed of an insulating film are formed covering the TFTs <b>2301</b> and <b>2302</b>. The first passivation film <b>2380</b> and the second passivation film <b>2381</b> can be formed by a thin film formation method such as a plasma CVD method or a sputtering method, using an insulating material such as silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN), etc. The passivation films covering the TFTs <b>2301</b> and <b>2302</b> are not limited to two layers, and a single layer or three or more layers may be provided. For example, the first passivation film <b>2380</b> and the second passivation film <b>2381</b> can be formed with silicon nitride and silicon oxide, respectively. By forming a passivation film with silicon nitride or silicon nitride oxide, entering of impurities from outside into a semiconductor element can be prevented, and degradation of the TFTs <b>2301</b> and <b>2302</b> due to an effect of moisture or the like can be prevented. In this embodiment mode, the first passivation film <b>2380</b> and the second passivation film <b>2381</b> are consecutively formed in the same chamber by performing gas switching.
0165Subsequently, an insulating layer <b>2329</b> is formed covering the second passivation films <b>2381</b>. Next, wirings <b>2371</b>, <b>2372</b>, <b>2373</b>, and <b>2374</b> connected to the second conductive films <b>2314</b> and <b>2324</b>, respectively, are formed via contact holes. Then, the conductive film <b>2324</b> is electrically connected to a pixel electrode <b>2330</b> of the liquid crystal element <b>2302</b> via the wiring <b>2374</b>.
0166An orientation film <b>2331</b> is formed over the pixel electrode <b>2330</b> so as to be in contact there with. Under a second substrate <b>2340</b> facing the first substrate <b>2300</b> with the pixel electrode <b>2330</b> therebetween, an opposing electrode <b>2341</b> and an orientation film <b>2342</b> are stacked in this order. Also, a liquid crystal <b>2343</b> is provided between the pixel electrode <b>2330</b> and the orientation film <b>2331</b> and between the opposing electrode <b>2341</b> and the orientation film <b>2342</b>, and a portion where the pixel electrode <b>2330</b>, the liquid crystal <b>2343</b>, and the opposing electrode <b>2341</b> overlap each other corresponds to a liquid crystal element <b>2303</b>. Note that the pixel electrode may be formed to extend over the TFT. When a transparent conductive film including indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like each having a light transmitting property is used for the first conductive film and the second conducive film, an aperture ratio of a pixel portion can be improved.
0167Note that a distance (cell gap) between the pixel electrode <b>2330</b> and the opposing electrode <b>2341</b> is controlled by a spacer <b>2361</b>. Although in <figref idref="DRAWINGS">FIG. 15</figref>, the spacer <b>2361</b> is formed by processing an insulating film into a desired shape, spacers prepared separately may be dispersed over the orientation film <b>2331</b> to control the cell gap. A reference numeral <b>2362</b> denotes a sealant, and by the sealant <b>2362</b>, the liquid crystal <b>2343</b> is sealed between the first substrate <b>2300</b> and the second substrate <b>2340</b>.
0168Further, on a surface of the first substrate <b>2300</b> that is not the surface over which the TFT <b>2301</b> and the TFT <b>2302</b> are formed, a polarizing plate is provided (not shown). Also, on a surface of the second substrate <b>2340</b> that is not the surface over which the opposing electrode <b>2341</b> is formed, a polarizing plate is provided (not shown). Note that the number of orientation films and polarizing plates, and positions thereof in a liquid crystal display device of the present invention are not limited to those shown in a structure of <figref idref="DRAWINGS">FIG. 15</figref>.
0169Next, a structure of an element substrate used in a liquid crystal display device of the present invention is shown.
0170<figref idref="DRAWINGS">FIG. 16</figref> shows a mode of an element substrate in which a pixel portion <b>6012</b> formed over a first substrate <b>6011</b> is connected to a separately formed signal line driver circuit <b>6013</b>. The pixel portion <b>6012</b> and the scanning line driver circuit <b>6014</b> are each formed using a TFT including an oxide semiconductor film including a crystallized region in at least a channel forming region. By forming the signal line driver circuit with a transistor by which higher mobility can be obtained compared to that of a TFT using an amorphous silicon film, operation of the signal line driver circuit which demands higher driving frequency than that of the scanning line driver circuit can be stabilized. Note that the signal line driver circuit <b>6013</b> may be a transistor using a monocrystalline silicon semiconductor, a TFT using a polycrystalline semiconductor, or a transistor using SOT. The pixel portion <b>6012</b>, the signal line driver circuit <b>6013</b>, and the scanning line driver circuit <b>6014</b> are each supplied with potential of a power sources, various signals, and the like via an FPC <b>6015</b>.
0171Note that the signal driver circuit and the scanning line driver circuit may both be formed over the same substrate as that of the pixel portion.
0172Also, when the driver circuit is separately formed, a substrate over which the driver circuit is formed is not always required to be stuck over a substrate over which the pixel portion is formed, and may be stuck for example over the FPC. <figref idref="DRAWINGS">FIG. 17A</figref> shows a mode of an element substrate in which a pixel portion <b>6022</b> formed over a first substrate <b>6021</b> is connected to a separately formed signal line driver circuit <b>6023</b>. The pixel portion <b>6022</b> and the scanning line driver circuit <b>6024</b> are each formed with a TFT using an oxide semiconductor film including a crystallized region in at least a channel forming region. The signal line driver circuit <b>6023</b> is connected to the pixel portion <b>6022</b> via an FPC <b>6025</b>. The pixel portion <b>6022</b>, the signal line driver circuit <b>6023</b>, and the scanning line driver circuit <b>6024</b> are each supplied with potential of a power source, a variety of signals, and the like via the FPC <b>6025</b>.
0173Also, just a portion of the signal line driver circuit or just a portion of the scanning line driver circuit may be formed over the same substrate as that of the pixel portion using the TFT including an oxide semiconductor film including a crystallized region in at least a channel forming region, and the rest may be formed separately to be electrically connected to the pixel portion. <figref idref="DRAWINGS">FIG. 17B</figref> shows a mode of an element substrate where an analog switch <b>6033</b><i>a </i>included in the signal driver circuit is formed over a first substrate <b>6031</b>, which is the same substrate as that over which a pixel portion <b>6032</b> and a scanning line driver circuit <b>6034</b> are formed, and forming a shift register <b>6033</b><i>b </i>included in the signal line driver circuit over a different substrate separately and then sticking it over the substrate <b>6031</b>. The pixel portion <b>6032</b> and the scanning line driver circuit <b>6034</b> are each formed using the TFT including an oxide semiconductor film including a crystallized region in at least a channel forming region. The shift register <b>6033</b><i>b </i>included in the signal line driver circuit is connected to the pixel portion <b>6032</b> via an FPC <b>6035</b>. The pixel portion <b>6032</b>, the analog switch <b>6033</b><i>a </i>and shift register <b>6033</b><i>b </i>included in the signal line drive circuit, and the scanning line driver circuit <b>6034</b> are each supplied with potential of a power source, a variety of signals, and the like via the FPC <b>6035</b>.
0174As shown in <figref idref="DRAWINGS">FIG. 16</figref> to <figref idref="DRAWINGS">FIG. 17B</figref>, in a liquid crystal display device of the present invention, an entire driver circuit or a portion thereof can be formed over the same substrate as that of a pixel portion, using the TFT including an oxide semiconductor film including a crystallized region in at least a channel forming region.
0175Note that a connection method of a separately formed substrate is not particularly limited, and a COG (chip on glass) method, a wire bonding method, a TAB (tape automated bonding) method or the like can be used. Further, a connection position is not limited to the position shown in <figref idref="DRAWINGS">FIGS. 18A and 18B</figref>, as long as electrical connection is possible. Also, a controller, a CPU, a memory, or the like may be formed separately and connected.
0176Note that a signal line driver circuit used in the present invention is not limited to a mode including only a shift register and an analog switch. In addition to the shift register and the analog switch, another circuit such as a buffer, a level shifter, or a source follower may be included. Also, the shift register and the analog switch is not always required to be provided, and for example a different circuit such as a decoder circuit by which selection of signal line is possible may be used instead of the shift register, and a latch or the like may be used instead of the analog switch.
0177<figref idref="DRAWINGS">FIG. 18A</figref> shows a block diagram of a liquid crystal display device to which the present invention is applied. The liquid crystal display device shown in <figref idref="DRAWINGS">FIG. 18A</figref> includes a pixel portion <b>801</b> including a plurality of pixels and provided with a liquid crystal element; a scanning line driver circuit <b>802</b> that selects each pixel; and a signal line driver circuit <b>803</b> that controls video signal input to a selected pixel.
0178In <figref idref="DRAWINGS">FIG. 18A</figref>, the signal line driver circuit <b>803</b> includes a shift register <b>804</b> and an analog switch <b>805</b>. To the shift register <b>804</b>, a clock signal (CLK) and a start pulse signal (SP) are input. When the clock signal (CLK) and the start pulse signal (SP) are input, timing signals are generated in the shift register <b>804</b>, and the timing signals are input to the analog switch <b>805</b>.
0179Also, the analog switch <b>805</b> is provided with video signals. The analog switch <b>805</b> samples the video signals according to the timing signals and distributes the video signals to a signal line of a latter stage.
0180Next, a structure of the scanning line driver circuit <b>802</b> is described. The scanning line driver circuit <b>802</b> includes a shift register and a buffer <b>807</b>. Also, a level shifter may be included in some cases. In the scanning line driver circuit <b>802</b>, by inputting the clock signal (CLK) and the start pulse signal (SP), a selection signal is generated. The generated selection signal is buffer amplified in the buffer <b>807</b>, and then supplied to a corresponding scanning line. To the scanning line, gates of transistors in pixels of one line are connected. Further, since the transistors in the pixels of one line have to be turned on at the same time, a buffer to which a large current can be fed is used for the buffer <b>807</b>.
0181In a full color liquid crystal display device, when a video signal corresponding to each of R (red), G (green), and B (blue) are sampled in sequence and each are supplied to a corresponding signal line, the number of terminals for connecting the shift register <b>804</b> and the analog switch <b>805</b> corresponds to about ⅓ of the number of terminals for connecting the analog switch <b>805</b> and the pixel portion <b>801</b>. Consequently, by forming the analog switch <b>805</b> and the pixel portion <b>801</b> over the same substrate, terminals used for connecting separately formed substrates are not required as in a case of thinking the analog switch <b>805</b> and the pixel portion over different substrates, and occurrence probability of poor connection can be suppressed, and yield can be increased.
0182<figref idref="DRAWINGS">FIG. 18B</figref> shows a block diagram of a liquid crystal display device to which the present invention is applied that is different from that of <figref idref="DRAWINGS">FIG. 18A</figref>. In <figref idref="DRAWINGS">FIG. 18B</figref>, a pixel portion <b>811</b> is shown, and a signal line driver circuit <b>813</b> includes a shift register <b>814</b>, a latch A <b>815</b>, a latch B <b>816</b>, and a D/A converter circuit (hereinafter referred to as a DAC <b>817</b>). A scanning line driver circuit <b>812</b> is to have the same structure as that of the scanning line driver circuit <b>802</b> in <figref idref="DRAWINGS">FIG. 18A</figref>.
0183To the shift register <b>814</b>, the clock signal (CLK) and the start pulse signal (SP) are input. When the clock signal (CLK) and the start pulse signal (SP) are input, timing signals are generated in the shift register <b>814</b> to be input in sequence to the latch A <b>815</b> of a first stage. When the timing signals are input to the latch A <b>815</b>, video signals are written to the latch A <b>815</b> in synchronism with the timing signals and retained. Note that in <figref idref="DRAWINGS">FIG. 18B</figref>, although it is assumed that the video signals are written to the latch A <b>815</b> in sequence, the present invention is not limited to this structure. A so called division drive in which a plurality of stages of the latch A <b>815</b> are divided into several groups, and video signals are input in parallel for each group. Note that the number of the groups at this time is called a division number. For example, when the latches are divided into groups in each of four stages, this is called division driving with four divisions.
0184The time it takes for a video signal writing to a latch of the latch A <b>815</b> in all of the stages to complete is called a line period. In practice, a line period sometimes includes the line period to which a horizontal retrace line period is added.
0185When one line period is completed, latch signals are supplied to the latch B <b>816</b> of a second stage, and video signals retained in the latch A <b>815</b> are written all at once in synchronism with the latch signals, and retained. To the latch A <b>815</b> which have sent the video signals to the latch B <b>816</b>, subsequent video signals are written in sequence in synchronism with timings signals from the shift register <b>814</b>. In this second round of the one line period, video signals written and retained in the latch B <b>816</b> are input to DAC <b>817</b>.
0186The DAC <b>817</b> converts input video signals from digital to analog, and supplies the signals to a corresponding signal line.
0187Note that the configurations shown in <figref idref="DRAWINGS">FIGS. 18A and 18B</figref> are modes of a liquid crystal display device relating to this embodiment mode, and configurations of a signal line driver circuit and a scanning line driver circuit are not limited thereto.
0188Note that <figref idref="DRAWINGS">FIGS. 16 to 18B</figref> is not used just for a liquid crystal display device relating to this embodiment mode, and can be used for a light emitting device or other display devices.
0189Note that this embodiment mode can be appropriately combined with Embodiment Modes 1 to 4.
0000[Embodiment 1]
0190This embodiment describes a mode of a light emitting element used in the light emitting device described in Embodiment Mode 5, with reference to <figref idref="DRAWINGS">FIGS. 8A to 8F</figref>.
0191<figref idref="DRAWINGS">FIG. 8A</figref> shows an example of forming a first pixel electrode <b>11</b> by using a conductive film having a light transmitting property and a high work function and forming a second pixel electrode <b>17</b> by using a conductive film having a low work function. The first pixel electrode <b>11</b> is formed of an oxide conductive material having a light transmitting property, typically, an oxide conductive material containing a silicon oxide at a concentration of 1 to 15 atomic %. A layer containing a light emitting substance <b>16</b> composed of a hole injecting or transporting layer <b>41</b>, a light emitting layer <b>42</b>, an electron transporting or injecting layer <b>43</b> is formed over the first pixel electrode <b>11</b>. The second pixel electrode <b>17</b> is composed of a first electrode layer <b>33</b> containing an alkali metal or an alkali earth metal such as LiF or MgAg and a second electrode layer <b>34</b> formed of a metal material such as aluminum. The pixel having such the structure can emit light from the first pixel electrode <b>11</b> side as indicated by arrow in the drawing.
0192<figref idref="DRAWINGS">FIG. 8B</figref> shows an example of forming a first pixel electrode <b>11</b> by using a conductive film having a high work function and forming a second pixel electrode <b>17</b> by using a conductive film having a light transmitting property and a low work function. The first pixel electrode <b>11</b> is composed of a first electrode layer <b>35</b> formed of a metal such as aluminum or titanium, or the metal and a metal material containing nitrogen at a concentration of a stoichiometric composition ratio or less, and a second electrode layer <b>32</b> formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic %. A layer containing a light emitting substance <b>16</b> composed of a hole injecting or transporting layer <b>41</b>, a light emitting layer <b>42</b>, an electron transporting or injecting layer <b>43</b> is formed over the first pixel electrode <b>11</b>. The second pixel electrode <b>17</b> is composed of a third electrode layer <b>33</b> containing an elemental substance of an alkali metal or an alkali earth metal such as LiF or CaF or a compound or an alloy thereof, and a fourth electrode layer <b>34</b> formed of a metal material such as aluminum. By forming each the third electrode layer <b>33</b> and the fourth electrode layer <b>34</b> to have a thickness of 100 nm or less to make it possible to permeate light, light can be emitted from a second pixel electrode <b>17</b> side as indicated by arrow in the drawing.
0193<figref idref="DRAWINGS">FIG. 8E</figref> shows air example of emitting light from both of a first electrode and a second electrode. A first pixel electrode <b>11</b> is formed by a conductive film having a light transmitting property and a high work function and a second pixel electrode <b>17</b> is formed by a conductive film having a light transmitting property and a low work function. Typically, the first pixel electrode <b>11</b> is formed of an oxide conductive material including a silicon oxide at a concentration of 1 to 15 atomic % and the second electrode <b>17</b> is composed of a third electrode layer <b>33</b> containing an elemental substance of an alkali metal or an alkali earth metal such as LiF or CaF or a compound of an alloy thereof, with a thickness of 100 nm or less and a fourth electrode layer <b>34</b> formed of a metal material such as aluminum with a thickness of 100 nm or less. Accordingly, light can be emitted from both of the first pixel electrode <b>11</b> and the second electrode <b>17</b> as indicated by an arrow in the drawing.
0194<figref idref="DRAWINGS">FIG. 8C</figref> shows an example of forming a first pixel electrode <b>11</b> by using a conductive film having a light transmitting property and a low work function and forming a second pixel electrode <b>17</b> by a conductive film having a high work function. A structure of a layer containing, a light emitting substance is illustrated as a stacked layer structure formed by stacking sequentially an electron transporting or injecting layer <b>43</b>, a light emitting layer <b>42</b>, and a hole injecting or transporting layer <b>41</b>. The second pixel electrode <b>17</b> is composed of a second electrode layer <b>32</b> formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic %, and a first electrode layer <b>35</b> formed of a metal such as aluminum or titanium, or a metal and a metal material containing nitrogen at a concentration of a stoichiometric composition ratio or less. The first pixel electrode <b>11</b> is composed of a third electrode layer <b>33</b> containing an elemental substance of an alkali metal or an alkali earth metal such as LiF or MgAg or a compound of an alloy thereof, and a fourth electrode layer <b>34</b> formed of a metal material such as aluminum. By forming each the third electrode layer <b>33</b> and the fourth electrode layer <b>34</b> to have a thickness of 100 nm or less to make it possible to permeate light, light can be emitted from the first electrode <b>11</b> side as indicated by an arrow in the drawing.
0195<figref idref="DRAWINGS">FIG. 8D</figref> shows an example of forming a first pixel electrode <b>11</b> by using a conductive film having a low work function and forming a second pixel electrode <b>17</b> by using a conductive film having a light transmitting property and a high work function. A structure of a layer containing a light emitting substance is illustrated as a stacked layer structure formed by stacking sequentially an electron transporting or injecting layer <b>43</b>, a light emitting layer <b>42</b>, and a hole injecting or transporting layer <b>41</b>. The first pixel electrode <b>11</b> is formed to have a similar structure to that illustrated in <figref idref="DRAWINGS">FIG. 8A</figref> and to have a thickness that enables it to reflect light generated in the layer containing a light emitting substance. The second pixel electrode <b>17</b> is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic %. By forming a hole injecting layer by a metal oxide which is an inorganic material (typically, molybdenum oxide or vanadium oxide), oxygen which is introduced when forming the second electrode layer <b>32</b> is supplied and a hole injecting property is improved, accordingly, drive voltage can be reduced in this structure. By forming the second electrode <b>17</b> by a conductive film having a light transmitting property, light can be emitted from one side of the second electrode <b>17</b> as indicated by an arrow.
0196<figref idref="DRAWINGS">FIG. 8F</figref> shows an example of emitting light from both sides, that is, a first pixel electrode and a second pixel electrode. A first pixel electrode <b>11</b> is formed by a conductive film having a light transmitting property and a low work function and a second pixel electrode <b>17</b> is formed by a conductive film having a light transmitting property and a high work function. Typically, the first electrode <b>11</b> is composed of a third electrode layer <b>33</b> containing an elemental substance of an alkali metal or an alkali earth metal such as LiF or CaF or a compound or an alloy thereof, with a thickness of 100 nm or less and a fourth electrode layer <b>34</b> formed of a metal material such as aluminum with a thickness of 100 nm or less. The second pixel electrode <b>17</b> is formed of an oxide conductive material containing a silicon oxide at a concentration of 1 to 15 atomic %.
0197The layer containing a light emitting substance <b>16</b> can be formed by a charge injection transportation material and a light emitting material including an organic compound or an inorganic compound, can include one or a plurality types of layers selected from a low molecular organic compound, an intermolecular organic compound (which does not have a subliming property but have a molecular chain length of 10 μm or less as typified by dendrimer, oligomer, or the like), and a high molecular organic compound, and can be combined with an inorganic compound having an electron injecting transporting property or a hole injecting transporting property.
0198As a particularly high electron transporting material among charge injection transporting materials, for example, metal complexes having a quinoline skeleton or a benzoquinoline skeleton, such as tris(8-quinolinolato)aluminum (abbreviation: Alq<sub>3</sub>), tris(4-methyl-8-quinolinolato)aluminum (abbreviation: Almq<sub>3</sub>), bis(10-hydroxybenzo[h]-quinolinato)beryllium (abbreviation: BeBq<sub>2</sub>), and bis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum (abbreviation: BAlq) can be given.
0199As a high hole transporting material, for example, aromatic amine based compounds (i.e., one having a benzene ring-nitrogen bond), such as 4,4′-bis[N-(1-naphthyl)-N-phenylamino]biphenyl (abbreviation: α-NPD), 4,4′-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (abbreviation: TPD), 4,4′,4″-tris(N,N-diphenylamino)triphenylamine (abbreviation: TDATA); and 4,4′,4″-tris[N-(3-methylphenyl)-N-phenylamino]triphenylamine (abbreviation: MTDATA) can be given.
0200As a particularly high electron injecting material among charge injection transportation materials, compounds of alkali metal or alkaline earth metal such as lithium fluoride (LiF), cesium fluoride (CsF), and calcium fluoride (CaF<sub>2</sub>) can be given. In addition, a mixture of a highly electron transporting material such as Alq<sub>3 </sub>and alkaline earth metal such as magnesium (Mg) may be used.
0201As a highly hole injecting material among charge injection transportation materials, for example, a metal oxide such as molybdenum oxide (MoO<sub>x</sub>), vanadium oxide (VO<sub>x</sub>), ruthenium oxide (RuO<sub>x</sub>), tungsten oxide (WO<sub>x</sub>), or manganese oxide (MnO<sub>x</sub>) can be given. Besides these, phthalocyanine based compounds such as phthalocyanine (H<sub>2</sub>Pc) and copper phthalocyanine (CuPc) can be given.
0202Light emitting layers <b>42</b> having different light emission wavelength bands may be each formed in pixels so as to perform color display. Typically, light emitting layers corresponding to respective luminescent colors of R (red), G (green), and B (blue) are formed. In this case, color purity can be improved and specular reflection (glare) of a pixel portion can be prevented by providing a filter (coloring layer) that transmits light of a certain light emission wavelength band on a light emission side of the pixels. By providing the filter (coloring layer), a circular polarizing plate or the like, which has been conventionally thought to be required, can be omitted, thereby reducing loss of light emitted from the light emitting layers. In addition, a change in hue, which is caused in the case where a pixel portion (a display screen) is seen obliquely, can be reduced.
0203There are various kinds of light emitting materials that can be used for forming the light emitting layers <b>42</b>. With respect to low molecular organic light emitting materials, the following substances can be used: 4-dicyanomethylene-2-methyl-6-[2-(1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]-4H-pyran (abbreviation: DCJT); 2-tert-butyl-4-dicyanomethylene-6-[2-(1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]-4H-pyran (abbreviation: DCJTB); periflanthene; 2,5-dicyano-1,4-bis[2-(10-methoxy-1,1,7,7-tetramethyljulolidine-9-yl)ethenyl]benzene, N,N′-dimethylquinacridone (abbreviation: DMQd); coumarin 6; coumarin 545T; tris(8-quinolinolato)aluminum (abbreviation: Alq<sub>3</sub>); 9,9′-bianthryl; 9,10-diphenylanthracene (abbreviation: DPA); 9,10-bis(2-naphthyl)anthracene (abbreviation: DNA); and the like. Also, another substance may be used.
0204On the other hand, a high molecular organic light emitting material has higher physical strength than that of a low molecular organic light emitting material, and so a light emitting element formed of a high molecular organic material has high durability. Since a high molecular organic light emitting material can be formed into a film by coating, manufacturing an element is relatively easy. A light emitting element structure using the high molecular organic light emitting material is basically the same as that formed by a low molecular organic light emitting material formed by stacking sequentially a cathode, a layer containing a light emitting substance, and an anode. However, a stacked layer structure which is formed in the case of using a low molecular organic light emitting material is difficult to be formed as a stacked layer structure composed of a layer containing a light emitting substance formed of a high molecular organic light emitting material. Most cases, the layer containing a light emitting substance is formed to have two stacked layers. Specifically, a structure is composed sequentially of a substrate, a layer containing a light emitting substance, a hole transporting layer, and an anode.
0205Since emission color is determined by a material for forming the light emitting layer, a desired light emitting element exhibiting desired light emission can be formed by selecting the material. As a high molecular light emitting material which can be used for forming the light emitting layer, polyparaphenylene vinylene based, polyparaphenylene based, polythiophene based, and polyfluorene based materials can be given.
0206As the polyparaphenylene vinylene based material, a derivative of poly(paraphenylenevinylene) (PPV): poly(2,5-dialkoxy-1,4-phenylenevinylene) (RO-PPV); poly(2-(2′-ethyl-hexoxy)-5-methoxy-1,4-phenylenevinylene) (MEH-PPV); poly(2-(dialkoxyphenyl)-1,4-phenylenevinylene) (ROPh-PPV); or the like can be given. As the polyparaphenylene based material, a derivative of polyparaphenylene (PPP): poly(2,5-dialkoxy-1,4-phenylene) (RO-PPP); poly(2,5-dihexoxy-1,4-phenylene); or the like can be given. As the polythiophene based material, a derivative of polythiophene (PT): poly(3-alkylthiophene) (PAT); poly(3-hexylthiophene) (PHT); poly(3-cyclohexylthiophene) (PCHT); poly(3-cyclohexyl-4-methylthiophene) (PCHMT); poly(3,4-dicyclohexylthiophene) (PDCHT); poly[3-(4-octylphenyl)-thiophene] (POPT); poly[3-(4-octylphenyl)-2,2 bithiophene) (PTOPT); or the like can be given. As the polyfluorene based material, a derivative of polyfluorene (PF): poly(9,9-dialkylfluorene) (PDAF); poly(9,9-dioctylfluorene) (PDOF); or the like can be given.
0207In the case that a high molecular organic light emitting material having a hole transporting property is interposed between an anode and a high molecular organic light emitting material having a light emitting property, a hole injecting property of the anode can be improved. Generally, the one which is dissolved with an acceptor material into water is applied by a spin coating method or the like. Since the high molecular organic light emitting material having the hole transporting property is insoluble in an organic solvent, the foregoing material can be stacked over the above mentioned light emitting material having a light emitting property. As the high molecular organic light emitting material having a hole transporting property, a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material; a mixture of polyaniline (PANT) and polystyrenesulfonic acid (PSS) as an acceptor material; or the like can be given.
0208The light emitting layers <b>42</b> can be formed to have a structure exhibiting a single color emission or white emission. In the case of using a white light emitting material, color display can be realized by providing a filter (coloring layer) transmitting light at a specified wavelength at a light emission side of a pixel.
0209In order to form a light emitting layer emitting white emission, Alq<sub>3</sub>, Alq<sub>3 </sub>doped partly with Nile red which is a red emission coloring matter, Alq<sub>3</sub>, p-EtTAZ, and TPD (aromatic diamine) are stacked sequentially by a vapor deposition method. In the case of forming a light emitting layer by a coating method using spin coating, the foregoing material is preferably coated and baked by vacuum heating. For example, an aqueous solution of poly(ethylene dioxythiophene)/poly(styrenesulfonic acid) (PEDOT/PSS), which functions as a hole injecting layer, may be applied over an entire surface of a substrate and baked. Afterwards, a solution of polyvinyl carbazole (PVK) doped with a luminescence center pigment (such as 1,1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6-(p-dimethylamino-styryl)-4H-pyran (DCM1), Nile red, or coumarin 6), which serves as a light emitting layer, may then be applied over the entire surface and baked.
0210The light emitting layer can be formed by a single layer. 1,3,4-oxadiazole derivatives (PBD) having an electron transporting property can be dispersed to polyvinylcarbazole (PVK) having a hole transporting property. Further, white emission can be obtained by dispersing PBD of 30 wt % as an electron transporting agent and dispersing an appropriately amount of four kinds coloring matters (TPB, coumarin 6, DCM1, and Nile red). Besides the light emitting element exhibiting white emission, light emitting elements exhibiting red emission, green emission, or blue emission can be manufactured by appropriately selecting a material of the light emitting layer.
0211In the case that a high molecular organic material having a hole transporting property is interposed between an anode and a high molecular organic material having a light emitting property, a hole injecting property of the anode can be improved. Generally, a high molecular organic material having a hole transporting property dissolved in water together with an acceptor material is coated by a spin coating method. Since the high molecular organic material having a hole transporting property is insoluble in an organic solvent, the foregoing material can be stacked over the above mentioned light emitting material having a light emitting property. As the high molecular organic material having a hole transporting property, a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material; a mixture of polyaniline (PANI) and polystyrenesulfonic acid (PSS) as an acceptor material; or the like can be given.
0212As a material for the light emitting layers <b>42</b>, a triplet excited material including metal complexes can be used besides a singlet excited light emitting material. For example, a red luminescent pixel which has a relatively short half-brightness life is formed by a triplet excited light emitting material among the red luminescent pixel, a green luminescent pixel, and blue luminescent pixel; and the other pixels are formed by a singlet excited light emitting material. Since a triplet excited light emitting material has good emission efficiency, there is an advantage of obtaining luminescence which can be obtained in the case of using a singlet excited light emitting material at low power consumption. That is, reliability can be improved since a light emitting element can be operated at a small amount of current in the case of applying a triplet excited light emitting material for a red emission pixel. In order to reduce power consumption, a red luminescent pixel and a green luminescent pixel are formed by a triplet excited light emitting material, and a blue luminescent pixel can be formed by a singlet excited light emitting material. By forming a green luminescent pixel which is well visible for human by a triplet excited light emitting material, power consumption can be further reduced.
0213As an example of a triplet excited light emitting material, a material using metal complexes as a dopant can be nominated. The following are known as the foregoing metal complexes: metal complexes having platinum which is the third transition series element as a central metal, metal complexes having iridium as a central metal, or the like. These compounds are not limited as a triplet excited light emitting material. A compound having the foregoing structure and a compound having Group 8 to Group 10 elements as a central metal can be used.
0214The following materials for forming the foregoing layer containing a light emitting substance are illustrative only. A light emitting element can be formed by appropriately stacking functional each layer such as a hole injecting transporting layer, a hole transporting layer, an electron injecting transporting layer, an electron transporting layer, a light emitting layer, an electron blocking layer, or a hole blocking layer. Further, a mixed layer or mixed junction can be formed by combining each of the foregoing layers. A layer structure of the light emitting layer is variable. Instead of not providing a specific electron injection region or light emitting region, various changes and modifications such as providing an electrode or a dispersed luminescent material for being used only for the electron injection region or the light emitting region are permissible unless otherwise such changes and modifications depart from the scope of the present invention.
0000[Embodiment 2]
0215In this embodiment, a pixel circuit of a display panel of a light emitting device relating to the present invention and an operational configuration thereof is described with reference to <figref idref="DRAWINGS">FIGS. 9A to 9F</figref>. For the operational configuration of the display panel in a display device in which video signals are digital, there is a configuration in which video signals to be input to a pixel is regulated by voltage, and a configuration in which they are regulated by current. As the configuration in which video signals are regulated by voltage, there is one where voltage applied to a light emitting element is constant (CVCV), and one where current applied to the light emitting element is constant (CVCC). Also, as the configuration in which video signals are regulated by current, there is one where voltage applied to the light emitting element is constant (CCCV), and one where current applied to the light emitting element is constant (CCCC). This embodiment describes a pixel of a CVCV operation with reference to <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>. Further, a pixel of a CVCC operation is described with reference to <figref idref="DRAWINGS">FIGS. 9C to 9F</figref>.
0216In the pixel shown in each of <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, a signal line <b>3710</b> and a power source line <b>3711</b> are arranged in a column direction and a scanning line <b>3714</b> is arranged in a row direction. Also, a switching TFT <b>3701</b>, a driving TFT <b>3703</b>, a capacitor element <b>3702</b>, and a light emitting element <b>3705</b> are included.
0217Note that the switching TFT <b>3701</b> and the driving TFT <b>3703</b> are operated in a linear region when they are turned on. Also, the driving TFT <b>3703</b> has a role of controlling whether voltage is applied to the light emitting element <b>3705</b>. It is favorable in terms of a manufacturing step if both TFTs have the same conductivity type. In this embodiment, the switching TFT <b>3701</b> is formed as an n-channel type TFT, and the driving TFT <b>3703</b> is formed as a p-channel type TFT. Also, as the driving TFT <b>3703</b>, a depletion type TFT may be used in addition to an enhancement type TFT. Further, a ratio (W/L) of a channel width W and a channel length L of the driving TFT <b>3703</b> is preferably 1 to 1000, even though it depends on a mobility of the TFT. As W/L gets larger, an electrical property of the TFT is improved.
0218In the pixel shown in each of <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, the switching TFT <b>3701</b> controls input of video signals to the pixel, and when the switching TFT <b>3701</b> is turned on, video signals are input inside the pixel. Then, voltage of the video signals is retained in the capacitor element <b>3702</b>.
0219In <figref idref="DRAWINGS">FIG. 9A</figref>, in a case where the power source line <b>3711</b> is Vss and an opposing electrode of the light emitting element <b>3705</b> is Vdd, as in <figref idref="DRAWINGS">FIGS. 8C and 8D</figref>, the opposing electrode of the light emitting element is an anode, and an electrode connected to the driving TFT <b>3703</b> is a cathode. In this case, luminance irregularity due to characteristic variation of the driving TFT <b>3703</b> can be suppressed.
0220In <figref idref="DRAWINGS">FIG. 9A</figref>, in a case where the power source line <b>3711</b> is Vdd and the opposing electrode of the light emitting element <b>3705</b> is Vss, as in <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>, the opposing electrode of the light emitting element is a cathode, and the electrode connected to the driving TFT <b>3703</b> is an anode. In this case, by inputting video signals having higher voltage than Vdd to the signal line <b>3710</b>, voltage of the video signals are retained in the capacitor element <b>3702</b> and the driving TFT <b>3703</b> operated in the linear region; consequently, luminance irregularity due to variation of the TFT can be improved.
0221The pixel shown in <figref idref="DRAWINGS">FIG. 9B</figref> has the same pixel configuration as that shown in <figref idref="DRAWINGS">FIG. 9A</figref> except that in <figref idref="DRAWINGS">FIG. 9B</figref>, a TFT <b>3706</b> and a scanning line <b>3715</b> are added.
0222Turning on or off of the TFT <b>3706</b> is controlled by the newly placed scanning line <b>3715</b>. When the TFT <b>3706</b> is turned on, a charge retained in the capacitor element <b>3702</b> is discharged, and the driving TFT <b>3703</b> is turned off. In other words, according to a placement of the TFT <b>3706</b>, a state in which current is not fed to the light emitting element <b>3705</b> can be created forcefully. Therefore, the TFT <b>3706</b> can be called an erasing TFT. Consequently, in the configuration in <figref idref="DRAWINGS">FIG. 9B</figref>, a duty ratio of light emission can be improved since a lighting period can be started at the same time as or right after a start of a writing period, without waiting for signals to be written to all pixels.
0223In a pixel having the foregoing operational configuration, a current value of the light emitting element <b>3705</b> can be determined by the driving TFT <b>3703</b> which operates in the linear region. By the foregoing configuration, characteristic variation of TFTs can be suppressed, luminance irregularity of light emitting elements due to the characteristic variations of the TFTs can be improved, and a display device with improved image quality can be provided.
0224Next, a pixel of a CVCC operation is described with reference to <figref idref="DRAWINGS">FIGS. 9C to 9F</figref>. The pixel shown in <figref idref="DRAWINGS">FIG. 9C</figref> has a pixel configuration shown in <figref idref="DRAWINGS">FIG. 9A</figref> with a power source line <b>3712</b> and a current control TFT <b>3704</b> provided in addition.
0225The pixel shown in <figref idref="DRAWINGS">FIG. 9E</figref> has the same configuration as the pixel shown in <figref idref="DRAWINGS">FIG. 9C</figref>, except that a gate electrode of the driving TFT <b>3703</b> is connected to the power supply line <b>3712</b> arranged in a row direction. In other words, both pixels shown in <figref idref="DRAWINGS">FIGS. 9</figref><i>c </i>and <b>9</b>E show the same equivalent circuit schematic. However, the power supply line <b>3712</b> arranged in a column direction (<figref idref="DRAWINGS">FIG. 9C</figref>) is formed with a conductive film formed in a different layer from that of the power supply line <b>3712</b> arranged in a row direction (<figref idref="DRAWINGS">FIG. 9E</figref>). Here, wirings to which the gate electrode of the driving TFT <b>3703</b> are connected is given focus, and in order to show that layers for manufacturing the wirings are different, they are separately described in <figref idref="DRAWINGS">FIGS. 9C and 9E</figref>.
0226Note that the switching TFT <b>3701</b> operates in the linear region, and the driving TFT <b>3703</b> operates in a saturation region. Also, the driving TFT <b>3703</b> has a role of controlling a current value fed to the light emitting element <b>3705</b>, and the current control TFT <b>3704</b> operates in the saturation region has a role of controlling supply of current to the light emitting element <b>3705</b>.
0227The pixel shown in each of <figref idref="DRAWINGS">FIGS. 9D and 9F</figref> have the same pixel configuration as the pixel shown in each of <figref idref="DRAWINGS">FIGS. 9C and 9E</figref>, respectively, except that they are each provided with an erasing TFT <b>3706</b> and the scanning line <b>3715</b> in addition.
0228Note that in the pixels shown in <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, CVCC operations are also possible. Also, for pixels having the operational configurations shown in <figref idref="DRAWINGS">FIGS. 9C to 9F</figref>, respectively, similarly to <figref idref="DRAWINGS">FIGS. 9A and 9B</figref>, Vdd and Vss can be appropriately changed depending on a direction in which current of a light emitting element flows.
0229In a pixel having the foregoing configuration, since the current control TFT <b>3704</b> operates in the linear region, a small shift in Vgs of the current control TFT <b>3704</b> does not have an effect on the current value of the light emitting element <b>3705</b>. In other words, the current value of the light emitting element <b>3705</b> can be determined by the driving TFT <b>3703</b> which operated in the saturation region. By the foregoing configuration, luminance irregularity of light emitting elements due to characteristic variations of TFTs can be improved, and a display device with improved image quality can be provided
0230Note that although a configuration in which the capacitor element <b>3702</b> is provided is shown, the present invention is not limited thereto, and in a case where a capacity for retaining video signals can be covered by a gate capacitance, the capacitor element <b>3702</b> is not required to be provided.
0231By such an active matrix type display device, in a case where pixel density is increased, low voltage drive is possible since a TFT is provided in each pixel, and this is considered to be advantageous.
0232Further, in a display device relating to the present invention, a driving method of a screen display is not particularly limited, and for example, a dot sequential driving method, a line sequential driving method, an area sequential driving method, or the like may be used. Typically, the line sequential driving method is used, and a time division gray scale driving method or an area gray scale driving method may be appropriately used. Further, image signals input to a source line of the display device may be analog signals, or digital signals, and a driver circuit and the like may be designed appropriately according to the image signals.
0000[Embodiment 3]
0233In this embodiment, mounting of a driver circuit relating to the present invention is described with reference to <figref idref="DRAWINGS">FIGS. 10A to 10C</figref>.
0234As shown in <figref idref="DRAWINGS">FIG. 10A</figref>, a signal line driver circuit <b>1402</b> and scanning line driver circuits <b>1403</b><i>a </i>and <b>1403</b><i>b </i>are mounted on a periphery of a pixel portion <b>1401</b>. In <figref idref="DRAWINGS">FIG. 10A</figref>, as the signal line driver circuit <b>1402</b> and the scanning line driver circuits <b>1403</b><i>a </i>and <b>1403</b><i>b</i>, an IC chip <b>1405</b> is mounted on a substrate <b>1400</b> by a known mounting method such as a method using an anisotropic conductive adhesive or an anisotropic conductive film, a COG method, a wire bonding, a reflow treatment using a solder bump, or the like. Here, the IC chip <b>1405</b> is mounted by a COG method, and connected to an external circuit through an FPC (flexible printed circuit) <b>1406</b>.
0235In a case where a semiconductor element typified by a TFT is formed with an oxide semiconductor as shown in <figref idref="DRAWINGS">FIG. 10B</figref>, the pixel portion <b>1401</b>, the scanning line driver circuits <b>1403</b><i>a </i>and <b>1403</b><i>b</i>, and the like may be integrated over the substrate while the signal line driver circuit <b>1402</b> and the like may be separately mounted as IC chips. In <figref idref="DRAWINGS">FIG. 10B</figref>, the IC chip <b>1405</b> as the signal line driver circuit <b>1402</b> is mounted on the substrate <b>1400</b> by a COG method. The IC chip <b>1405</b> is connected to an external circuit through the FPC <b>1406</b>.
0236Further, as shown in <figref idref="DRAWINGS">FIG. 10C</figref>, there is a case where the signal line driver circuit <b>1402</b> and the like are mounted by a TAB method instead of a COG method. The IC chip is connected to an external circuit through the FPC <b>1406</b>. Although the signal line driver circuit is mounted by a TAB method in <figref idref="DRAWINGS">FIG. 10C</figref>, the scanning line driver circuit may be mounted by a TAB method.
0237When the IC chip is mounted by a TAB method, the pixel portion can occupy a large area in the substrate, leading to a narrower frame.
0238Instead of an IC chip formed over a silicon wafer, an IC (hereinafter referred to as a driver IC) formed over a glass substrate may be provided. Since an IC chip is formed over a circular silicon wafer, the shape of a mother substrate is limited. Meanwhile, a driver IC is formed over a glass substrate whose shape is not limited, which results in increased productivity. Accordingly, the shape and size of a driver IC can be set freely. For example, when forming a driver IC with a long side of 15 to 80 mm, a smaller number of driver ICs are required as compared to the case of mounting IC chips. As a result, the number of connection terminals can be reduced and productive yield can be increased.
0239A driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor may be formed by continuous wave laser light irradiation. A semiconductor film obtained by continuous wave laser light irradiation has few crystal defects and large crystal grains. Accordingly, a transistor having such a semiconductor film is improved in mobility and response speed, capable of high speed driving, and suitable for a driver IC. A driver IC may be formed using an oxide semiconductor film of the present invention in which crystallinity of at least a channel foaming region is improved.
0000[Embodiment 4]
0240In this embodiment, a display module relating to the present invention is described. Here, as one example of the display module, a liquid crystal module is described with reference to <figref idref="DRAWINGS">FIG. 11</figref>.
0241A substrate <b>1601</b> and an opposing substrate <b>1602</b> are stuck together by a sealant <b>1600</b>, and a pixel portion <b>1603</b> and a liquid crystal layer <b>1604</b> are provided therebetween to form a display region.
0242A coloring layer <b>1605</b> is required in a case of performing color display, and in a case of an RGB method, a coloring layer corresponding to each of red, green and blue are provided corresponding to each pixel. On the outsides of the substrate <b>1601</b> and the opposing substrate <b>1602</b>, polarizing plates <b>1606</b> and <b>1607</b> are provided, respectively. Also, on a surface of the polarizing plate <b>1606</b>, a protective film <b>1616</b> is formed, and alleviates impact from the exterior.
0243A wiring substrate <b>1610</b> is connected to a connection terminal <b>1608</b> provided over the substrate <b>1601</b> via an FPC <b>1609</b>. External circuits <b>1612</b> such as a pixel driver circuit (an IC chip, a driver IC, or the like); a control circuit, a power source circuit or the like is incorporated to the wiring substrate <b>1610</b>.
0244A cold cathode tube <b>1613</b>, a reflecting plate <b>1614</b>, and an optical film <b>1615</b> are a backlight unit, and these become a light source to emit light to a liquid crystal display panel. A liquid crystal panel, the light source, the wiring substrate, the FPC, and the like are retained and protected in a bezel <b>1617</b>.
0000[Embodiment 5]
0245In this embodiment mode, as an electronic appliance relating to the present invention, a television device (also simply called a TV, or a television receiving device), a digital camera, a digital video camera, a mobile phone device (also simply called a cellular phone device or a cellular phone), a mobile information terminal such as a PDA, a mobile game machine, a monitor for a computer, a computer, an audio reproducing device such as a car audio component, an image reproducing device such as a home-use game machine provided with a recording medium, or the like, is described with reference to drawings.
0246The mobile information terminal shown in <figref idref="DRAWINGS">FIG. 12A</figref> includes a main body <b>9201</b>, a display portion <b>9202</b>, and the like. By using a display device that is one feature of the present invention, the mobile information terminal can be provided inexpensively.
0247The digital video camera shown in <figref idref="DRAWINGS">FIG. 12B</figref> includes a display portion <b>9701</b>, a display portion <b>9702</b>, and the like. By using the display device that is one feature of the present invention, the digital video camera can be provided inexpensively.
0248The mobile terminal shown in <figref idref="DRAWINGS">FIG. 12C</figref> includes a main body <b>9101</b>, a display portion <b>9102</b>, and the like. Embodiment Modes 1 to 5, and embodiments 1 to 4 can be applied to the display portion <b>9102</b>. By using the display device that is one feature of the present invention, the mobile terminal can be provided inexpensively.
0249The mobile type television device shown in <figref idref="DRAWINGS">FIG. 12D</figref> includes a main body <b>9301</b>, a display portion <b>9302</b>, and the like. By using the display device that is one feature of the present invention, the mobile type television device can be provided inexpensively. The present invention can be widely applied to a small scale television device such as a television device mounted on a mobile terminal such as a cellular phone, a medium scale television device that can be carried around, and a large scale television device (for example, 40-inch or larger).
0250The mobile type computer shown in <figref idref="DRAWINGS">FIG. 12E</figref> includes a main body <b>9401</b>, a display portion <b>9402</b>, and the like. By using the display device that is one feature of the present invention, the mobile type computer can be provided inexpensively.
0251The television device shown in <figref idref="DRAWINGS">FIG. 12F</figref> includes a main body <b>9501</b>, a display portion <b>9502</b>, and the like. By using the display device that is one feature of the present invention, the television device can be provided inexpensively.
0252Among the foregoing electronic appliances, that which uses a secondary battery can have a longer operating time by how much power consumption is reduced, and a need for recharging the secondary battery can be cut out.
0000[Embodiment 6]
0253In this embodiment, a structure of an LRTA device used in the present invention is described with reference to <figref idref="DRAWINGS">FIGS. 19A and 19B</figref>.
0254In <figref idref="DRAWINGS">FIG. 19A</figref>, a gate electrode <b>1922</b>, a gate insulating films <b>1923</b><i>a </i>and <b>1923</b><i>b</i>, and an oxide semiconductor film <b>1902</b> are formed over a glass substrate <b>1901</b>. Also, on a lower surface side of the substrate and on an upper surface side of the substrate, an infrared light lamp <b>1903</b> and an ultraviolet light lamp <b>1904</b> are provided, respectively. And, a first infrared light auxiliary lamp <b>1905</b>, and a second infrared light auxiliary lamp <b>1906</b> are provided in parallel with the ultraviolet light lamp <b>1904</b>. Note that the first infrared light auxiliary lamp <b>1905</b> and the second infrared light auxiliary lamp <b>1906</b> are not required to be provided.
0255Also, this embodiment mode has a structure in which the first infrared light auxiliary lamp <b>1905</b> and the second infrared light auxiliary lamp <b>1906</b> are placed in front and in back (with respect to a moving direction of the substrate) of the ultraviolet light lamp <b>1904</b>, respectively. However, the structure may be that both are placed in the front or in the back.
0256In a structure such as the above, each lamp (the infrared light lamp <b>1903</b>, the ultraviolet light lamp <b>1904</b>, the first infrared light auxiliary lamp <b>1905</b>, and the second infrared light auxiliary lamp <b>1906</b>) moves in a direction of an arrow in <figref idref="DRAWINGS">FIG. 19A</figref>, and scans a linear light. In the structure of this embodiment, a region <b>1908</b> shown by a dotted line in the oxide semiconductor film <b>1902</b> that overlaps with the gate electrode <b>1922</b> with the gate insulating films <b>1923</b><i>a </i>and <b>1923</b><i>b </i>therebetween is irradiated with infrared light from the first infrared light auxiliary lamp <b>1905</b> to be heated. Note that each lamp is moved when lamp irradiation is performed on the substrate; however, the glass substrate may be moved, or both the lamp and the substrate may be moved.
0257After irradiation is performed on the first infrared light auxiliary lamp <b>1905</b>, the upper surface side of the substrate is irradiated with ultraviolet light from the ultraviolet light lamp <b>1904</b>, as well as the lower surface side of the substrate is irradiated with infrared light from the infrared light lamp <b>1903</b>, and the region <b>1908</b> of the oxide semiconductor film <b>1902</b> that overlaps with the gate electrode <b>1922</b> is heated. In this embodiment, crystallization of the oxide semiconductor film <b>1902</b> is performed with this region <b>1908</b> having priority.
0258The region <b>1908</b> heated by irradiation with the ultraviolet light lamp <b>1904</b> and the infrared light lamp <b>1903</b> is heated with infrared light from the second infrared light auxiliary lamp <b>1906</b> that is placed in back of the ultraviolet light lamp <b>1904</b>. Irradiation with infrared light from the second infrared light auxiliary lamp <b>1906</b> is provided to further heat the region <b>1908</b> in which crystallization is promoted.
0259As in the foregoing, the region <b>1908</b> of the oxide semiconductor film <b>1902</b> (the region that becomes a crystalline oxide semiconductor film by a crystallization step) that overlaps with the gate electrode <b>1922</b> appears to move to the front along with a movement of the substrate.
0260<figref idref="DRAWINGS">FIG. 19B</figref> shows a graph showing a relationship between time (Time) and temperature (Temp.) of the region <b>1908</b> of the oxide semiconductor film <b>1902</b>. As shown in <figref idref="DRAWINGS">FIG. 19B</figref>, the region <b>1908</b> comes to a preheating state, then continues on to a main heating state, and a post heating state, with passing of time.
0261As clear from <figref idref="DRAWINGS">FIG. 19B</figref>, in the preheating state, a temperature is raised to a certain degree so that a temperature gradient with the subsequent main heating state is alleviated. This is so that accumulation of warping energy and the like in the oxide semiconductor film due to being heated suddenly in the main heating state, is prevented.
0262Therefore, it is desirable that output energy of the first infrared light auxiliary lamp <b>1905</b> is set to be smaller than output energy of the infrared light lamp <b>1903</b>. At this time, a practitioner may decide how adjustment is to be made to form the appropriate temperature gradient.
0263Next, after the preheating state, infrared light irradiation is performed towards a lower surface side of the substrate, and the oxide semiconductor film <b>1902</b> is brought to the main heating state in which a film surface temperature is raised to 250° C. to 570° C. At this state, crystallinity of the region <b>1908</b> in the oxide semiconductor film <b>1902</b> becomes favorable. Note that ultraviolet light emitted at the same time contributes to electron excitation; therefore, it does not contribute to change in terms of heat.
0264The region <b>1908</b> with improved crystallinity obtained in the main heating state is heated by the second infrared auxiliary lamp <b>1906</b> placed in back of the ultraviolet light lamp <b>1904</b>. This post heating state has a role of preventing a completion of crystallization in a state where thermal equilibrium is deteriorated by sudden cooling in the main heating state. This is a device for obtaining the most stable bond state by providing allowance in a time period required for crystallization.
0265Accordingly, it is desirable that output energy of the second infrared light auxiliary lamp <b>1906</b> is also set to be smaller than that of infrared light lamp <b>1903</b> placed under a substrate surface, and adjusted so that a temperature gradient is formed in which the temperature is gradually lowered.
0266By a structure as in the foregoing, shrinking of a substrate can be suppressed since a portion of an oxide semiconductor film that overlaps with a gate electrode is heated. Also, by performing crystallization by moving each lamp or substrate, throughput can be increased. Also, occurrence of a crystal defect such as stress warping, a dangling bond, or the like that can occur due to sudden heating of an oxide semiconductor film or sudden cooling of a crystalline oxide semiconductor film can be suppressed, and the oxide semiconductor film including the region <b>1908</b> with excellent crystallinity can be obtained.
0267Also, by performing irradiation heating without providing the first infrared light auxiliary lamp <b>1905</b> and the second infrared light auxiliary lamp <b>1906</b>, heating of the substrate may be suppressed.
0268Note that in this embodiment, a structure of an LRTA device using a linear lamp is described; however, a planar lamp may be used to perform the crystallization step.
0000[Embodiment 7]
0269In this embodiment, an example of applying a semiconductor device relating to the present invention to an electrophoresis display device is described with reference to <figref idref="DRAWINGS">FIG. 20</figref>.
0270The electrophoresis display device shown in <figref idref="DRAWINGS">FIG. 20</figref> includes a main body <b>2010</b>, a pixel portion <b>2011</b> displaying an image, a driver IC <b>2012</b>, a receiving device <b>2013</b>, a film battery <b>2014</b>, and the like. Each of the driver IC <b>2012</b>, the receiving device <b>2013</b>, and the like may be mounted with a semiconductor part. The semiconductor device of the present invention can be used for the pixel portion <b>2011</b> and the driver IC <b>2012</b>. Note that the pixel portion <b>2011</b> has a structure where a display layer in which microcapsules, Gyricon beads, and the like are arranged and a driver layer controlling the display layer are stacked. The display layer and the driver layer are interposed between two plastic films.
0271Such an electrophoresis display device is also called an electronic paper, and it is extremely light weight, and since it has a flexible property, it can be rolled up in a tubular form; consequently, it is extremely advantageous in carrying around. Therefore, a display medium of a large screen can be freely carried around. Also, since the semiconductor of the present invention is used for the pixel portion <b>2011</b> and the like, an inexpensive display device can be provided.
0272A variety of modes can be considered as an electrophoresis display device of this embodiment, but the electrophoresis display device of this embodiment is a device in which a plurality of microcapsules each including first particles having a positive charge and second particles having a negative charge are dispersed in a solvent or a solute, and an electrical field is applied to the microcapsules so that the particles in the microcapsules move in opposite directions of each other, and only a color of the particles gathered on one side is displayed. Note that the first particles or the second particles includes a colorant, and does not move in a case where there is not electric field. Also, a color of the first particles is different from a color of the second particles (the particles may also be colorless). That which microcapsules are dispersed in a solvent is called an electronic ink, and this electronic ink can be printed on a surface such as glass, plastic, fabric, paper, and the like.
0273Also, in a semiconductor device of the present invention, in addition to an oxide semiconductor film having a light transmitting property with respect to visible light, a transparent conductive film including indium tin, oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like each having a light transmitting property with respect to visible light for a source electrode, a drain electrode, and the like. If a conventional amorphous silicon or polysilicon is used for a TFT used in a driver layer, to prevent a channel forming region from being irradiated with light, it is necessary that a light shielding film is provided to overlap the channel forming region. However, as in the present invention, by manufacturing the driver layer using the oxide semiconductor film, the source electrode, and the drain electrode each having a light transmitting property with respect to visible light, an electrophoresis display device of a double-sided display can be obtained.
0274Note that the semiconductor device of the present invention can be used as a means for displaying mainly still images for a navigation system, an audio reproducing device (such as a car audio component, or an audio component), a personal computer, a game machine, a mobile information terminal (such as a mobile computer, a cellular phone, a mobile game machine, or an electronic book), and in addition, the semiconductor device can be used for household appliances such as a refrigerator, a washing machine, a rice cooker, a fixed telephone, a vacuum cleaner, and a clinical thermometer, as well as for a hanging poster in a train, and a large-sized information display such as an arrival and departure guide board in a railroad station and an airport.
0000[Embodiment 8]
0275In this embodiment, a digital audio player relating to the present invention is described with reference to <figref idref="DRAWINGS">FIG. 21</figref>.
0276The digital audio player shown in <figref idref="DRAWINGS">FIG. 21</figref> includes a main body <b>2110</b>, a display portion <b>2111</b>, a memory portion <b>2112</b>, an operation portion <b>2113</b>, a pair of earphones <b>2114</b>, and the like. Note that instead of the pair of earphones <b>2114</b>, a pair of headphones, or a wireless pair of earphones can be used. As the display portion <b>2111</b>, liquid crystal, organic EL, or the like can be used. As the memory portion <b>2112</b>, a flash memory with a recording capacity of 200 megabytes (MB) to 200 gigabytes (GB) is used, and by operating the operation portion <b>2113</b>, an image or a sound (music) can be recorded and reproduced.
0277Since a channel forming region of an oxide semiconductor film of a TFT included in a semiconductor device of the present invention includes at least a crystallized region, by providing the semiconductor device of the present invention to the display portion <b>2111</b>, an inexpensive digital audio player with good performance can be provided. Further, since the channel forming region of the oxide semiconductor film is transparent and does not absorb visible light, unnecessary light carriers are not generated. Therefore, since characteristic degradation of the channel forming region due to light irradiation does not occur, a highly reliable digital audio player can be provided.
0278This embodiment can be appropriately combined with Embodiment Modes 1 to 6 and Embodiments 1 to 4.
0279This application is based on Japanese Patent Application serial no. 2005-283782 filed in Japan Patent Office on Sep. 29, 2005, the entire contents of which are hereby incorporated by reference.
Contents4
23 sheets
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Every citation, both ways
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|---|---|---|---|
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| US12272698B2 | Cited by | United States of America | Applicant |
| US12369402B2 | Cited by | United States of America | Applicant |
| US9496138B2 | Cited by | United States of America | Applicant |
| US9660102B2 | Cited by | United States of America | Applicant |
| US10790383B2 | Cited by | United States of America | Applicant |
| US12416838B2 | Cited by | United States of America | Applicant |
| US12193244B2 | Cited by | United States of America | Applicant |
| US10573621B2 | Cited by | United States of America | Applicant |
| US9224838B2 | Cited by | United States of America | Applicant |
| US11107840B2 | Cited by | United States of America | Applicant |
| US9299813B2 | Cited by | United States of America | Applicant |
| US11127858B2 | Cited by | United States of America | Applicant |
| US12067934B2 | Cited by | United States of America | Applicant |
| US11749685B2 | Cited by | United States of America | Applicant |
| US2011101355A1 | Cited by | United States of America | Pre-grant |
| US10559599B2 | Cited by | United States of America | Applicant |
| US9805641B2 | Cited by | United States of America | Applicant |
| US11456320B2 | Cited by | United States of America | Applicant |
| US9269725B2 | Cited by | United States of America | Applicant |
| US11024516B2 | Cited by | United States of America | Applicant |
| US10622485B2 | Cited by | United States of America | Applicant |
| US11954276B2 | Cited by | United States of America | Applicant |
| US11170728B2 | Cited by | United States of America | Applicant |
| US10505049B2 | Cited by | United States of America | Applicant |
| US11538542B2 | Cited by | United States of America | Applicant |
| US9419143B2 | Cited by | United States of America | Applicant |
| US10319723B2 | Cited by | United States of America | Applicant |
| US12183302B2 | Cited by | United States of America | Applicant |
| US9876946B2 | Cited by | United States of America | Applicant |
| US10241373B2 | Cited by | United States of America | Applicant |
| US10256254B2 | Cited by | United States of America | Applicant |
| US10915145B2 | Cited by | United States of America | Applicant |
| US12228971B2 | Cited by | United States of America | Applicant |
| US9721811B2 | Cited by | United States of America | Applicant |
| US11756966B2 | Cited by | United States of America | Applicant |
| US12490518B2 | Cited by | United States of America | Applicant |
| US12396216B2 | Cited by | United States of America | Applicant |
| US10505051B2 | Cited by | United States of America | Applicant |
| US10211231B2 | Cited by | United States of America | Applicant |
| US10249647B2 | Cited by | United States of America | Applicant |
| US10012880B2 | Cited by | United States of America | Applicant |
| US10078243B2 | Cited by | United States of America | Applicant |
| US10680116B2 | Cited by | United States of America | Applicant |
| US10565946B2 | Cited by | United States of America | Applicant |
| US12210257B2 | Cited by | United States of America | Applicant |
| US10714358B2 | Cited by | United States of America | Applicant |
| US9450104B2 | Cited by | United States of America | Applicant |
| US10043424B2 | Cited by | United States of America | Applicant |
| US9647132B2 | Cited by | United States of America | Applicant |
| US9653490B2 | Cited by | United States of America | Applicant |
| US2019012960A1 | Cited by | United States of America | Applicant |
| US10490671B2 | Cited by | United States of America | Applicant |
| US11776483B2 | Cited by | United States of America | Applicant |
| US9972389B2 | Cited by | United States of America | Applicant |
| US10360831B2 | Cited by | United States of America | Applicant |
| US11901485B2 | Cited by | United States of America | Applicant |
| US10141425B2 | Cited by | United States of America | Applicant |
| US12302645B2 | Cited by | United States of America | Applicant |
| US9779679B2 | Cited by | United States of America | Applicant |
| US9245983B2 | Cited by | United States of America | Applicant |
| US12372838B2 | Cited by | United States of America | Applicant |
| US11152397B2 | Cited by | United States of America | Applicant |
| US10304696B2 | Cited by | United States of America | Applicant |
| US9036767B2 | Cited by | United States of America | Applicant |
| US12283634B2 | Cited by | United States of America | Applicant |
| US11749365B2 | Cited by | United States of America | Applicant |
| US9196633B2 | Cited by | United States of America | Applicant |
| US10002970B2 | Cited by | United States of America | Applicant |
| US9722055B2 | Cited by | United States of America | Applicant |
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| US12567351B2 | Cited by | United States of America | Applicant |
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| US11626521B2 | Cited by | United States of America | Applicant |
| US12224376B2 | Cited by | United States of America | Applicant |
| US12541228B2 | Cited by | United States of America | Applicant |
| US11545105B2 | Cited by | United States of America | Applicant |
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| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Examiner's Amendment CommunicationEX.A | EX.A | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail-Record Petition Decision of Granted to Withdraw from IssueMP006 | MP006 | |
| Record Petition Decision of Granted to Withdraw from IssueP006 | P006 | |
| Petition EnteredPET. | PET. | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Printer Rush- No mailingTCPB | TCPB | |
| Mailing Corrected Notice of AllowabilityMCNOA | MCNOA | |
| Reasons for AllowanceEX.R | EX.R | |
| Corrected Notice of AllowabilityCNOA | CNOA | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Reverse Issue FeeVFEE | VFEE | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Mail Response to 312 Amendment (PTO-271)MN271 | MN271 | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Response to Amendment under Rule 312N271 | N271 | |
| Amendment after Notice of Allowance (Rule 312)AllowedA.NA | A.NA | |
| Printer Rush- No mailingTCPB | TCPB | |
| Mailing Corrected Notice of AllowabilityMCNOA | MCNOA | |
| Reasons for AllowanceEX.R | EX.R | |
| Corrected Notice of AllowabilityCNOA | CNOA | |
| Mail PUB other miscellaneous communication to applicantMM327-D | MM327-D | |
| PUB Other miscellaneous communication to applicantM327-D | M327-D | |
| Pubs Case Remand to TCPUBTC | PUBTC | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Reasons for AllowanceEX.R | EX.R | |
| Examiner's Amendment CommunicationEX.A | EX.A | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Response after Non-Final ActionA... | A... | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Workflow - Request for RCE - BeginBRCE | BRCE |
6 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Fee payment procedureMAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| Maintenance fee paymentMAFP | MAFP | |
| Maintenance fee paymentMAFP | MAFP | |
| Certificate of correctionCC | CC | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP |
Numbers
- Publication
- 8790959
- Application
- 13011142
Titles
- English
- Semiconductor device and manufacturing method thereof
Patent term adjustment
- A delay
- +28 daysthe office missed an examination deadline
- Applicant delay
- −302 days
- Net adjustment
- 0 days
Classification
- CPC, 27
- H01L29/7869
- H10D86/423
- H10D30/6755
- H10D30/6757
- G02F1/167
- H01L27/1225
- H10D86/60
- H10D30/031
- H10D30/67
- H10D30/6756
- H10D62/40
- H10D62/405
- H10D99/00
- H10P14/3426
- H10P14/3434
- H10P14/3802
- H10D86/0229
- H10P14/22
- H10P14/6329
- H10P14/69215
- H10P14/69391
- H10P14/69433
- H10P34/42
- H10P50/20
- H10P52/00
- H10P95/70
- H10P95/90
- IPC, 8
- H01L21 00
- H01L29 786
- H01L27 12
- G02F1 1368
- H01L21 20
- H01L21 336
- H01L51 50
- H05B44 00