Semiconductor device, a parallel interface system and methods thereof

PRIORITY STATEMENT

0001This application is a Divisional Application of U.S. patent application Ser. No. 12/929,627 filed on Feb. 4, 2011 now U.S Pat. No. 8,335,291 which is a continuation of application Ser. No. 11/812,438, filed on Jun. 19, 2007, now U.S. Pat. No. 7,907,693, which claims the priority of Korean Patent Application No. 10-2006-0056563, filed on Jun. 22, 2006, in the Korean Intellectual Property Office, the disclosure of each of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003Example embodiments of the present invention relate generally to a semiconductor device, a parallel interface system and methods thereof, and more particularly to a semiconductor device, a parallel interface system and methods of reducing skew.

00042. Description of the Related Art

0005Data transmission rates between semiconductor devices (e.g., between a dynamic random access memory (DRAM) device and a central processing unit (CPU) or a controller) may be limited by a time jitter of a phase locked loop (PLL)/delayed locked loop (DLL), an offset caused by a fabrication error in a transmitter and/or a receiver, interference between transmission signals in a transmission channel, etc.

0006In parallel interface systems, a parallel data signal and a reference clock signal may be transmitted to a receiver in synchronization with a sampling clock signal of a transmitter. However, due to factors limiting the data transmission rate, a difference in channel time between the reference clock signal and the data signal and/or between data signals may occur if a skew occurs (e.g., because the data transmission rate increases between semiconductor devices). The skew may indicate a phase difference between the reference clock signal and the parallel data signal.

0007As the skew increases, a voltage margin and a time margin of a transmission data signal may be reduced. If the time margin is reduced, an “indefinite” portion of data may increase (e.g., a metastable data state of the transmission data signal), and it may be more difficult to secure a sufficient setup/hold time. In order to enable a semiconductor device receiving a parallel data signal to correctly identify the data signal, a sampling clock of the receiving semiconductor device may be set to increase the voltage margin and the time margin.

0008In an example, a synchronous process may be used to set the sampling clock in a parallel interface system. In the conventional synchronizing process, a data signal and a reference clock signal may be separately transmitted to a semiconductor device and the semiconductor device may identify the data signal. However, if a data transmission line is not matched with a reference clock transmission line in the conventional synchronizing process, skew may occur between the data signal and the reference clock signal. Accordingly, it may be difficult to accomplish higher-rate data signal transmission.

0009<figref idref="DRAWINGS">FIG. 1A</figref> is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ<b>1</b> through DQN output from a transmitter within a conventional parallel interface system. <figref idref="DRAWINGS">FIG. 1B</figref> is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ<b>1</b>′ through DQN′ input to a receiver within a conventional parallel interface system.

0010Referring to <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, the transmitter may transmit the reference clock signal TXCLKref and the N parallel data bit signals DQ<b>1</b> through DQN to the receiver in response to a transmitting sampling clock signal TXCLK. The receiver may generate a receiving data sampling clock signal CLKda whose phase may be different from that of the received reference clock signal CLKref by a half period. The receiver may sample the received N parallel data bit signals DQ<b>1</b>′ through DQN′ in response to the receiving data sampling clock signal CLKda. If data transmission lines are not matched with a reference clock transmission line, a timing error (e.g., a phase skew) may occur between the receiving reference clock signal RXCLKref and each signal (e.g., DQ<b>1</b>′) of the N parallel data bit signals DQ<b>1</b>′ through DQN′, as illustrated in <figref idref="DRAWINGS">FIG. 1B</figref>. Accordingly, the receiving data sampling clock signal CLKda may be displaced from a position associated with a theoretical “maximum” time margin. As a result, the time margin and the voltage margin of the N parallel data bit signals DQ<b>1</b>′ through DQN′ may be reduced.

0011Referring to <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, the receiving data sampling clock signal CLKda may be set to provide a higher (e.g., maximum) time margin by performing per-pin deskew process using clock and data recovery (CDR). In the per-pin deskew process CDR, a data signal transmitted per data pin may be oversampled (e.g., two or more times) during a single signal period and a position or phase of the receiving data sampling clock signal CLKda may be extracted based on the values of sampled data signals.

0012<figref idref="DRAWINGS">FIGS. 2A through 2C</figref> are conceptual diagrams illustrating the conventional per-pin deskew process using CDR. Referring to <figref idref="DRAWINGS">FIGS. 2A through 2C</figref>, the phase of an edge sampling clock CLKed may be different from the phase of a data sampling clock signal CLKda by a half period of the phase of a data signal. The edge sampling clock CLKed may be used to detect edge information in the data signal and the data sampling clock signal CLKda may be used to identify the data signal (e.g., as one of a first logic level, such as a higher logic level or logic “1”, and a second logic level, such as a lower logic level or logic “0”).

0013In particular, <figref idref="DRAWINGS">FIG. 2A</figref> illustrates the data sampling clock signal CLKda positioned so as to provide a theoretical maximum time margin, while <figref idref="DRAWINGS">FIGS. 2B and 2C</figref> illustrate conditions where the position of the data sampling clock signal CLKda introduces skew.

0014Referring to <figref idref="DRAWINGS">FIGS. 2B and 2C</figref>, in order to adjust the position of the data sampling clock signal CLKda so as to match the time margin of <figref idref="DRAWINGS">FIG. 2A</figref>, the data sampling clock signal CLKda may be shifted to the “left” in <figref idref="DRAWINGS">FIG. 2B</figref> and to the “right” in <figref idref="DRAWINGS">FIG. 2C</figref>. The per-pin deskew process using CDR may allow a sampling clock signal to track the changes of a data signal so as to maintain a sampling position approximately at the maximum time margin (e.g., see <figref idref="DRAWINGS">FIG. 2A</figref>) even while data is being transmitted. Accordingly, even if a skew occurs between a data signal and a sampling clock signal (e.g., due to the change of temperature or voltage) while data is being transmitted, the per-pin deskew process using CDR may reduce the skew.

0015However, the per-pin deskew process using CDR may require an additional sampling clock signal (e.g., the edge sampling clock CLKed) for detecting edge information in the data signal, a receiving circuit for receiving information relating to a phase skew between the data signal and the data sampling clock signal CLKda, and a phase control circuit for changing the position of the data sampling clock signal CLKda (e.g., so as to maintain the maximum time margin). Thus, an area occupied by a circuit for reducing skew may be increased, as well as manufacturing costs. Accordingly, it may be difficult to employ the per-pin deskew process using CDR in parallel data transmission of conventional semiconductor (e.g., dynamic random access memory (DRAM)) devices.

0016Another conventional process for reducing skew between a data signal and a data sampling clock signal may be a per-pin deskew process using training data. Unlike the conventional per-pin deskew process using CDR, the per-pin deskew process using training data need not include an additional circuit for edge detection in a semiconductor device (e.g., a DRAM device) receiving the data signal.

0017<figref idref="DRAWINGS">FIG. 3</figref> is a conceptual diagram illustrating the conventional per-pin deskew process using training data. Referring to <figref idref="DRAWINGS">FIG. 3</figref>, in a conventional parallel interface system, a transmitting semiconductor device (e.g., a controller) may transmit given pattern data referred to as “training data”. The transmitting semiconductor device may receive the training data back from the receiving semiconductor device in synchronization with receiving sampling clock signals S<b>1</b> through S<b>13</b> having different phases. The transmitting semiconductor device may compare the transmitted training data with the received training data and may determine whether a reception error has occurred based on a result of the comparison.

0018Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a reception error may occur if the training data is received in synchronization with the receiving sampling clock signals S<b>1</b> through S<b>3</b> and S<b>11</b> through S<b>13</b>. An optimum phase (e.g., a phase having a least probability of error) of a receiving sampling clock signal for the transmitting semiconductor device may be determined based on the determination on the reception error. In other words, the phase of the receiving sampling clock signal S<b>7</b> having a least probability of error occurrence may be obtained with phase information of the receiving sampling clock signals S<b>4</b> through S<b>10</b> in which an error does not occur.

0019Referring to <figref idref="DRAWINGS">FIG. 3</figref>, phase information may be obtained per data pin in parallel data transmitted by the transmitting semiconductor device using the above-described process. The phase of a receiving sampling clock signal corresponding to each data pin may be controlled based on the phase information. The phase of a transmitting sampling clock signal of the transmitting semiconductor device may be controlled in the same manner.

0020However, the per-pin deskew process using training data may take a longer period of time to perform as compared to the per-pin deskew process using CDR. Thus, if the per-pin deskew process using training data is performed frequently, system performance may be reduced. Accordingly, in determining whether to use the per-pin deskew process using either training data or CDR data, a system designer may be required to make a trade-off by choosing between the increased occupied chip area allocated to circuitry associated with the per-pin deskew process using CDR data and the decreased performance levels of the per-pin deskew process using training data.

SUMMARY OF THE INVENTION

0021An example embodiment of the present invention is directed to a semiconductor device included within a parallel interface system, including a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of first transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode.

0022Another example embodiment of the present invention is directed to a method of for reducing skew between a reference clock signal and each of a plurality of parallel data bit signals in a parallel interface system including a plurality of transceiver blocks, including first mode adjusting a phase of a transmitting sampling clock signal to generate a phase-controlled transmitting sampling clock signal based on a phase skew between a training data bit signal, among a plurality of training data bit signals, corresponding to a given transceiver block and a reference clock signal in a first operation mode and second mode adjusting the phase of the transmitting sampling clock signal to generate the phase-controlled transmitting sampling clock signal based on phase skew information relating to a phase skew between a given parallel data bit signal, among the plurality of parallel data bit signals, and the reference clock signal in a second operation mode.

0023Another example embodiment of the present invention is directed to a method of reducing skew in a parallel interface system, including reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

0024Another example embodiment of the present invention is directed to a method and semiconductor device for compensating for a skew between a data signal and a clock signal in a parallel interface system by combining per-pin deskew using clock and data recovery (CDR) and per-pin deskew using training data and for decreasing a required circuit area, and a recording medium for recording the method.

BRIEF DESCRIPTION OF THE DRAWINGS

0025The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention.

0026<figref idref="DRAWINGS">FIG. 1A</figref> is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ<b>1</b> through DQN output from a transmitter within a conventional parallel interface system.

0027<figref idref="DRAWINGS">FIG. 1B</figref> is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ<b>1</b>′ through DQN′ input to a receiver within a conventional parallel interface system.

0028<figref idref="DRAWINGS">FIGS. 2A through 2C</figref> are conceptual diagrams illustrating the conventional per-pin deskew process using clock and data recovery (CDR).

0029<figref idref="DRAWINGS">FIG. 3</figref> is a conceptual diagram illustrating a conventional per-pin deskew process using training data.

0030<figref idref="DRAWINGS">FIG. 4</figref> illustrates a parallel interface system according to an example embodiment of the present invention.

0031<figref idref="DRAWINGS">FIG. 5</figref> illustrates a first transceiver block included in a first semiconductor device of <figref idref="DRAWINGS">FIG. 4</figref> according to another example embodiment of the present invention.

0032<figref idref="DRAWINGS">FIG. 6</figref> illustrates a phase detection block included in the parallel interface system of <figref idref="DRAWINGS">FIG. 4</figref> according to another example embodiment of the present invention.

0033<figref idref="DRAWINGS">FIG. 7</figref> illustrates a parallel interface system according to another example embodiment of the present invention.

0034<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart of a process for reducing skew between an N-bit parallel data signal and a reference clock signal in a parallel interface system according to another example embodiment of the present invention.

0035<figref idref="DRAWINGS">FIG. 9</figref> a flowchart expanding upon the reference clock transmission process of <figref idref="DRAWINGS">FIG. 8</figref> during the per-pin deskew process using the training data signal according to another example embodiment of the present invention.

0036<figref idref="DRAWINGS">FIG. 10</figref> is a flowchart illustrating a per-pin deskew process using CDR during the process of <figref idref="DRAWINGS">FIG. 8</figref> according to another example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION

0037Detailed illustrative example embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Example embodiments of the present invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

0038Accordingly, while example embodiments of the invention are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but conversely, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like numbers may refer to like elements throughout the description of the figures.

0039It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

0040It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

0041The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0042Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

0043<figref idref="DRAWINGS">FIG. 4</figref> illustrates a parallel interface system <b>400</b> according to an example embodiment of the present invention. In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the parallel interface system <b>400</b> may include a first semiconductor device <b>410</b>, a second semiconductor device <b>450</b> and a plurality of transmission lines Line<b>0</b> through Line<b>8</b>. In an example, the first semiconductor device <b>410</b> may be a memory controller and the second semiconductor device <b>450</b> may be a dynamic random access memory (DRAM) device.

0044In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the first semiconductor device <b>410</b> may include a reference clock signal transmitting block <b>411</b>, a plurality of first transceiver blocks <b>421</b> through <b>428</b>, a per-pin deskew block <b>430</b>, and a plurality of first selectors (e.g., multiplexers) <b>441</b> through <b>448</b>.

0045In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the reference clock signal transmitting block <b>411</b> may transmit a reference clock signal CLKref to the second semiconductor device <b>450</b> through the transmission line Line<b>0</b>. In an example, the reference clock signal transmitting block <b>411</b> may be implemented by a phase locked loop (PLL) or a delay locked loop (DLL). In addition, the reference clock signal transmitting block <b>411</b> may generate a transmitting sampling clock signal TXCLK. The reference clock signal CLKref may be transmitted to the second semiconductor device <b>450</b> in synchronization with the transmitting sampling clock signal TXCLK.

0046In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the first transceiver blocks <b>421</b> through <b>428</b> may transmit data bits DQ<b>1</b> through DQ<b>8</b>, respectively, to the second semiconductor device <b>450</b> in synchronization with the transmitting sampling clock signal TXCLK.

0047<figref idref="DRAWINGS">FIG. 5</figref> illustrates the first transceiver block <b>425</b> included in the first semiconductor device <b>410</b> of <figref idref="DRAWINGS">FIG. 4</figref> according to another example embodiment of the present invention. In the example embodiment of <figref idref="DRAWINGS">FIGS. 4 and 5</figref>, the first transceiver block <b>425</b> may include a DLL block <b>510</b>, a first transmission driver <b>520</b>, and a clock and data recovery (CDR) reception block <b>530</b>. In an example, each of the first transceiver blocks <b>421</b> through <b>428</b> may include the same structure as the first transceiver block <b>425</b>, with the exception only the first transceiver block <b>425</b> may be configured to receive phase skew information PI.

0048In the example embodiment of <figref idref="DRAWINGS">FIG. 5</figref>, the DLL block <b>510</b> may control the phase of the transmitting sampling clock signal TXCLK based on either a corresponding phase control signal P<b>5</b> among a plurality of phase control signals P<b>1</b> through P<b>8</b> or based on the phase skew information PI, so as to output a phase-controlled transmitting sampling clock signal CLKtx. In addition, the DLL block <b>510</b> may control the phase of the transmitting sampling clock signal TXCLK based on phase information extracted by the CDR reception block <b>530</b> so as to output a phase-controlled receiving sampling clock signal CLKre.

0049In the example embodiment of <figref idref="DRAWINGS">FIG. 5</figref>, the first transmission driver <b>520</b> may transmit a data bit DQ<b>5</b> in synchronization with the phase-controlled transmitting sampling clock signal CLKtx. The CDR reception block <b>530</b> may receive one of the data bit DQ<b>5</b> and the phase skew information PI from a second transceiver block <b>465</b> included in the second semiconductor device <b>450</b>. In an example, the CDR reception block <b>530</b> may receive the data bit DQ<b>5</b> in a normal data transmission/reception mode and may alternatively receive the phase skew information PI in a phase skew information reception mode through the data line Line<b>5</b>. In addition, the CDR reception block <b>530</b> may extract the phase information (e.g., which may be used to control the phase of the transmitting sampling clock signal TXCLK to generate the phase-controlled receiving sampling clock signal CLKre) based on the data bit DQ<b>5</b> received from the second transceiver block <b>465</b>.

0050Returning to the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the per-pin deskew block <b>430</b> may control (e.g., individually control) the phase of the transmitting sampling clock signal TXCLK corresponding to each of the first transceiver blocks <b>421</b> through <b>428</b> based on a phase skew between the reference clock signal CLKref and each of a plurality of bits (e.g., 8 bits) of training data in a first mode. In the first mode, the per-pin deskew block <b>430</b> may output the phase control signals P<b>1</b> through P<b>8</b> for controlling (e.g., individually controlling) the phases of the transmitting sampling clock signal TXCLK for the first transceiver blocks <b>421</b> through <b>428</b>, respectively.

0051In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the first mode may be a power-up mode (e.g., an initial mode) of the parallel interface system <b>400</b>. The per-pin deskew block <b>430</b> may reduce skew (e.g., “static skew”) between each data bit (e.g., DQ<b>5</b>) and the reference clock signal CLKref (e.g., which may occur due to physical or structural dismatching in the parallel interface system <b>400</b>) in the initial mode.

0052In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the per-pin deskew block <b>430</b> may enable the 8-bit training data to be transmitted to the second semiconductor device <b>450</b> in synchronization with the transmitting sampling clock signal TXCLK, which may be controlled so as to have different phase values in the first semiconductor device <b>410</b>, and may receive 8-bit training data fed back from the second semiconductor device <b>450</b>. The per-pin deskew block <b>430</b> may determine whether one or more bits in the received 8-bit training data includes an error and may obtain phase values of the transmitting sampling clock signal TXCLK, at which an error is determined not to occur, with respect to the respective bits of the training data. The per-pin deskew block <b>430</b> may obtain an average of the phase values corresponding to the respective data bits and may output the phase control signals P<b>1</b> through P<b>8</b>. The phase of the transmitting sampling clock signal TXCLK for each data bit may be controlled to have the average phase value by a corresponding phase control signal (e.g., P<b>1</b>).

0053In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the first selectors <b>441</b> through <b>448</b> may receive the corresponding phase control signals P<b>1</b> through P<b>8</b>, respectively, and the phase skew information PI. In addition, each of the first selectors <b>441</b> through <b>448</b> may output either a corresponding phase control signal (e.g., P<b>5</b>) or the phase skew information PI to a corresponding first transceiver block (e.g., first transceiver block <b>425</b>) among the plurality of the first transceiver blocks <b>421</b> through <b>428</b> in response to a mode control signal T<b>1</b>.

0054In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the phases of the phase-controlled transmitting sampling clock signal CLKtx, which may respectively correspond to the first transceiver blocks <b>421</b> through <b>428</b>, may be collectively controlled based on the phase skew information PI received from the second semiconductor device <b>450</b> in a second mode. In an example, the second mode may be an operating mode of the parallel interface system <b>400</b>. In another example, even if the static skew is reduced using the training data, a skew between a data signal and a clock signal may occur due to the change of temperature or voltage during an operation of the parallel interface system <b>400</b>. Skew occurring during an operation of the parallel interface system <b>400</b> may be referred to as “dynamic skew”. Accordingly, dynamic skew may be reduced in the second mode.

0055In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the phase skew information PI may include information relating to a position of the transmitting sampling clock signal TXCLK, which may be extracted from a bit (e.g., DQ<b>5</b>) among the 8 bits DQ<b>1</b> through DQ<b>8</b> transmitted from the first semiconductor device <b>410</b> to the second semiconductor device <b>450</b>.

0056In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the phases of the transmitting sampling clock signal TXCLK may be collectively controlled based on the phase skew information PI extracted from the bit DQ<b>5</b>. However, it is understood that other example embodiments of the present invention need not be limited thereto. For example, the phases of the transmitting sampling clock signal TXCLK may be controlled based on phase skew information extracted from at least two bits (e.g., DQ<b>3</b> and DQ<b>7</b>), among the 8 bits DQ<b>1</b> through DQ<b>8</b>, and/or any other combination of bits. The phases of the transmitting sampling clock signal TXCLK may be controlled for the bits DQ<b>1</b> through DQ<b>5</b>, respectively, based on the phase skew information extracted from the bit DQ<b>3</b> while the phases of the transmitting sampling clock signal TXCLK may be controlled for the bits DQ<b>6</b> through DQ<b>8</b>, respectively, based on the phase skew information extracted from the bit DQ<b>7</b>. The phase skew information extracted from the bit DQ<b>3</b> may be transmitted through the transmission line Line<b>3</b> and the phase skew information extracted from the bit DQ<b>7</b> may be transmitted through the transmission line Line<b>7</b>.

0057In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the second semiconductor device <b>450</b> may include a reference clock signal receiving block <b>451</b>, a plurality of second transceiver blocks <b>461</b> through <b>468</b>, a data storage unit <b>470</b>, a phase detector <b>481</b>, a phase statistics block <b>483</b> and a second selector <b>485</b>. The second transceiver block <b>465</b>, the phase detector <b>481</b>, the phase statistics block <b>483</b> and the second selector <b>485</b> may form a phase detection block <b>480</b> for detecting a phase skew between the data bit DQ<b>5</b> and the reference clock signal CLKref.

0058In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the reference clock signal receiving block <b>451</b> may receive the reference clock signal CLKref from the reference clock signal transmitting block <b>411</b> and may generate a data sampling clock signal CLKda and an edge sampling clock signal CLKed based on the reference clock signal CLKref. The edge sampling clock signal CLKed may be used to detect edge information in a transmitted data signal (e.g., DQ<b>5</b>) and the data sampling clock signal CLKda may be used to identify the transmitted data signal (e.g., DQ<b>5</b>). In an example, the edge sampling clock signal CLKed may have a half-period phase difference with the data sampling clock signal CLKda.

0059In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the second transceiver blocks <b>461</b> through <b>468</b> may transmit and receive the 8 bits DQ<b>1</b> through DQ<b>8</b> of parallel data to and from the first transceiver blocks <b>421</b> through <b>428</b>, respectively. Each of the second transceiver blocks <b>461</b> through <b>468</b> may receive a corresponding bit among the 8 bits DQ<b>1</b> through DQ<b>8</b> of parallel data in synchronization with the data sampling clock signal CLKda. The data storage unit <b>471</b> may store the received bits DQ<b>1</b> through DQ<b>8</b> of parallel data.

0060In the example embodiment of <figref idref="DRAWINGS">FIG. 4</figref>, the phase detection block <b>480</b> may include the second transceiver block <b>465</b>, the phase detector <b>481</b>, the phase statistics block <b>483</b> and the second selector <b>485</b>.

0061<figref idref="DRAWINGS">FIG. 6</figref> illustrates the phase detection block <b>480</b> included in the parallel interface system <b>400</b> of <figref idref="DRAWINGS">FIG. 4</figref> according to another example embodiment of the present invention. In the example embodiment of <figref idref="DRAWINGS">FIG. 6</figref>, the second transceiver block <b>465</b> may include a second transmission driver <b>610</b> and a receiver <b>620</b>. In an example, the other second transceiver blocks <b>461</b> through <b>464</b> and <b>466</b> through <b>468</b> may include the same structure and arrangement as the second transceiver block <b>465</b>.

0062In the example embodiment of <figref idref="DRAWINGS">FIG. 6</figref>, the phase detector <b>481</b> may extract phase skew information for controlling the phase of the transmitting sampling clock signal TXCLK in the first transceiver block <b>425</b> from the data bit DQ<b>5</b> received from the first transceiver block <b>425</b>. The phase statistics block <b>483</b> may calculate a statistical value with respect to the phase skew information detected by the phase detector <b>481</b> during a given data period. For example, the phase statistics block <b>483</b> may calculate an average of the phase skew information detected during the given data period and may output the calculated average.

0063In the example embodiment of <figref idref="DRAWINGS">FIG. 6</figref>, the second selector <b>485</b> may select one of an output of the phase statistics block <b>483</b> and an output of the data storage unit <b>470</b> based on a control command COM received from the first semiconductor device <b>410</b>. The second selector <b>485</b> may output the selected output to the second transceiver block <b>465</b>. In an example, the time at which the second selector <b>485</b> selects the output of the phase statistics block <b>483</b> may be adjusted by the first semiconductor device <b>410</b> to conform to an environment of the parallel interface system <b>400</b>.

0064Accordingly, in the example embodiment of <figref idref="DRAWINGS">FIG. 6</figref>, the second transceiver block <b>465</b> may transmit the data bit DQ<b>5</b> to the first semiconductor device <b>410</b> through the data line Line<b>5</b> during a normal data transmitting/receiving operation and may alternatively transmit the phase skew information output from the phase statistics block <b>483</b> to the first semiconductor device <b>410</b> through the data line Line<b>5</b> during a phase skew information transmitting operation.

0065<figref idref="DRAWINGS">FIG. 7</figref> illustrates a parallel interface system <b>700</b> according to another example embodiment of the present invention. In the example embodiment of <figref idref="DRAWINGS">FIG. 7</figref>, the parallel interface system <b>700</b> may include a first semiconductor device <b>710</b> and a second semiconductor device <b>720</b>. The first semiconductor device <b>710</b> may include the reference clock signal transmitting block <b>411</b>, the first transceiver blocks <b>421</b> through <b>428</b>, the per-pin deskew block <b>430</b>, the first selectors <b>441</b> through <b>448</b> and a phase information receiver <b>611</b>. In an example, the elements <b>411</b>, <b>421</b> through <b>428</b>, <b>430</b>, and <b>441</b> through <b>448</b> may be configured in the same manner as above-described with respect to <figref idref="DRAWINGS">FIG. 4</figref>. Accordingly, a further description thereof has been omitted for the sake of brevity.

0066In the example embodiment of <figref idref="DRAWINGS">FIG. 7</figref>, the phase information receiver <b>611</b> may receive the phase skew information PI from the second semiconductor device <b>720</b> and may outputs the received phase skew information PI to the first selectors <b>441</b> through <b>448</b>. The second semiconductor device <b>720</b> may include the reference clock signal receiving block <b>451</b>, the second transceiver blocks <b>461</b> through <b>468</b>, the data storage unit <b>470</b>, the phase detector <b>481</b>, the phase statistics block <b>483</b>, and a phase information transmitter <b>730</b>. In an example, the reference clock signal receiving block <b>451</b>, the second transceiver blocks <b>461</b> through <b>468</b>, the data storage unit <b>470</b>, the phase detector <b>481</b>, the phase statistics block <b>483</b> may be configured in the same manner as above-described with respect to <figref idref="DRAWINGS">FIG. 4</figref>. Accordingly, a further description thereof has been omitted for the sake of brevity.

0067In the example embodiment of <figref idref="DRAWINGS">FIG. 7</figref>, the phase information transmitter <b>730</b> may receive a statistical value with respect to the phase skew information extracted from the data bit DQ<b>5</b> from the phase statistics block <b>483</b> and may transmit the received statistical value (e.g., the phase skew information PI) to the phase information receiver <b>611</b> (e.g., in real time).

0068In the example embodiment of <figref idref="DRAWINGS">FIG. 7</figref>, unlike the parallel interface system <b>400</b> illustrated in <figref idref="DRAWINGS">FIG. 4</figref>, the parallel interface system <b>700</b> may transmit phase skew information PI from the second semiconductor device <b>720</b> to the first semiconductor device <b>710</b> through an additional phase information transmission line Line<b>9</b>. If the phase skew information PI is transmitted through the separate phase information transmission line Line<b>9</b>, the phase skew information PI may be transmitted to the first semiconductor device <b>710</b> in real time without necessarily affecting the data. As a result, higher-bandwidth CDR may be achieved. The example embodiment of <figref idref="DRAWINGS">FIG. 7</figref> has been illustrated and above-described with respect to an 8-bit parallel interface. However, it is understood that other example embodiments may be directed to a parallel interface having any number of bits, such as, for example, 16 bits, 32 bits, etc. Accordingly, the bits may be grouped by N bits.

0069<figref idref="DRAWINGS">FIG. 8</figref> is a flowchart of a process for reducing skew between an N-bit parallel data signal and a reference clock signal in a parallel interface system according to another example embodiment of the present invention.

0070In the example embodiment of <figref idref="DRAWINGS">FIG. 8</figref>, a reference clock signal may be transmitted to a receiving semiconductor device (at S<b>810</b>). Per-pin deskew may be performed using a training data signal in a first mode (at S<b>820</b>). In the per-pin deskew using the training data signal, if the phase of a transmitting sampling clock signal of a transmitting semiconductor device is changed, the training data signal may be transmitted to the receiving semiconductor device (e.g., during the phase adjustment). The transmitted training data signal may be compared with training data signals received back from the receiving semiconductor device. Based on a result of the comparison, the phase of the transmitting sampling clock signal for each bit of N-bit parallel data may be controlled (e.g., individually controlled).

0071In the example embodiment of <figref idref="DRAWINGS">FIG. 8</figref>, deskew may be performed using CDR in a second mode (at S<b>830</b>). In the deskew using CDR, phase information may be extracted from a given data bit among N bits of parallel data received by the receiving semiconductor device and the extracted phase information may be transmitted to the transmitting semiconductor device. The phases of the transmitting sampling clock signal for each respective bits of parallel data may be collectively controlled based on the extracted phase information.

0072In the example embodiment of <figref idref="DRAWINGS">FIG. 8</figref>, the parallel interface system may be in the first mode if the parallel interface system is being powered up. Accordingly, the first mode may be referred to as an initial mode. If the parallel interface system performs per-pin deskew using training data and operates according to a result of the per-pin deskew, the parallel interface system may be referred to as being in the second mode.

0073<figref idref="DRAWINGS">FIG. 9</figref> a flowchart expanding upon the reference clock transmission process (at S<b>810</b>) of <figref idref="DRAWINGS">FIG. 8</figref> during the per-pin deskew process using the training data signal according to another example embodiment of the present invention. In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, the transmitting semiconductor device may transmit N bits of the training data signal to the receiving semiconductor device in synchronization with the transmitting sampling clock signal having a first phase value (at S<b>910</b>). The receiving semiconductor device may receive the training data signal in synchronization with a given receiving sampling clock signal. The given receiving sampling clock signal may be generated based on the reference clock signal transmitted from the transmitting semiconductor device in synchronization with the transmitting sampling clock signal. For example, the given receiving sampling clock signal may have a half-period phase difference with respect to the reference clock signal.

0074In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, a timing error (e.g., a phase skew) may occur between the reference clock signal received by the receiving semiconductor device and each bit of the received N-bit training data signal.

0075In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, the received training data signal may be stored in the receiving semiconductor device (at S<b>920</b>). The transmitting semiconductor device may determine whether the first phase value of the transmitting sampling clock signal is the same as a reference phase value (at S<b>930</b>). If the transmitting semiconductor device determines that the first phase value of the transmitting sampling clock signal is not the same as the reference phase value (e.g., a phase value of a single period of the training data signal), the first phase value may be increased (e.g., by a fixed value) (at S<b>935</b>) and the process may return to S<b>910</b>. For example, the transmitting semiconductor device may repeatedly increase the phase value of the transmitting sampling clock signal (e.g., by the fixed value) during a single period of the training data signal and may transmit the training data signal to the receiving semiconductor device in synchronization with the transmitting sampling clock signal having a changed phase.

0076In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, the transmitting semiconductor device may receive the training data signal stored in the receiving semiconductor device in synchronization with a given transmitter's receiving sampling clock signal. The given transmitter's receiving sampling clock signal may be positioned so as to provide a maximum time margin (e.g., as shown in <figref idref="DRAWINGS">FIG. 2A</figref>). A per-pin deskew operation on the transmitter's receiving sampling clock signal will be described in greater detail later.

0077In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, if the transmitting semiconductor device determines that the first phase value of the transmitting sampling clock signal is the same as the reference phase value, the process may determine whether an error is present in each bit of the N-bit training data signal with respect to different first phase values of the transmitting sampling clock signal (at S<b>940</b>). First phase values of the transmitting sampling clock signal, which may correspond to each bit of the N-bit training data signal and at which an error does not occur in a given bit, may be obtained and an average phase value may be calculated for the given bit (at S<b>950</b>). Average phase values may be obtained with respect to the N bits, respectively, of the training data signal. A phase of the transmitting sampling clock signal for each bit of data may be set to the average phase value obtained corresponding to the given bit (at S<b>960</b>). Accordingly, a skew between the reference clock signal and a given data bit, which may occur in the receiving semiconductor device, may be reduced by controlling the phase of the transmitting sampling clock signal in the transmitting semiconductor device.

0078In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, the per-pin deskew operation performed on the transmitter's receiving sampling clock signal using the training data signal as will now be described. The training data signal may be transmitted to the receiving semiconductor device in synchronization with a transmitter's transmitting sampling clock signal having a given lower frequency and the receiving semiconductor device may store the received training data signal. It may be assumed that the transmitted training data signal does not include an error.

0079In the example embodiment of <figref idref="DRAWINGS">FIG. 9</figref>, the transmitting semiconductor device may receive the training data signal stored in the receiving semiconductor device in response to the transmitter's receiving sampling clock signal having different phase values. Next, it is determined whether an error occurs in each bit of the training data signal with respect to the different phase values of the transmitter's receiving sampling clock signal. Phase values of the transmitter's receiving sampling clock signal, which correspond to each bit of the N-bit training data signal and at which an error does not occur in a given bit, may be obtained and an average phase value is calculated for the given bit. A phase of the transmitter's receiving sampling clock signal for receiving each bit of data may be set to the average phase value obtained corresponding to the given bit. As described above, the per-pin deskew process using the training data need not include a skew compensation circuit in the receiving semiconductor device, whereby power consumption of the receiving semiconductor device may thereby be reduced.

0080<figref idref="DRAWINGS">FIG. 10</figref> is a flowchart illustrating a per-pin deskew process using CDR at S<b>830</b> of the process of <figref idref="DRAWINGS">FIG. 8</figref> according to another example embodiment of the present invention.

0081In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, the transmitting semiconductor device may transmit the reference clock signal and N parallel data bit signals to the receiving semiconductor device in synchronization with the transmitted sampling clock signal (at S<b>1010</b>). The receiving semiconductor device may generate at least two receiver's receiving sampling clock signals having different phases based on the reference clock signal (at S<b>1020</b>). For example, an edge sampling clock signal, which may be in-phase with the reference clock signal and a data sampling clock signal (e.g., which may have a half-period phase difference with the reference clock signal may be generated.

0082In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, at least one signal among the N parallel data bit signals may be sampled in synchronization with the receiver's receiving sampling clock signals (at S<b>1030</b>). Phase skew information related to the receiver's receiving sampling clock signal may be detected based on sampled data signal values (at S<b>1040</b>). For example, a signal of a single data bit DQ<b>5</b> among the 8 parallel data bits DQ<b>1</b> through DQ<b>8</b> may be sampled using the edge sampling clock signal and the data sampling clock signal in the receiving semiconductor device. In an example, because a delay difference between the bit DQ<b>1</b> and the bit DQ<b>8</b> may be higher (e.g., highest) in the receiving semiconductor device, the bit DQ<b>5</b> may be assumed to have a medium delay value. For this reason, the bit DQ<b>5</b> may be selected from the parallel data bits DQ<b>1</b> through DQ<b>8</b> and phase skew information of the bit DQ<b>5</b> may be detected. The detected phase skew information may be transmitted to the transmitting semiconductor device to control the phase of the transmitting sampling clock signal used to transmit the bit DQ<b>5</b> in the transmitting semiconductor device.

0083In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, if the phase skew information of the bit DQ<b>5</b> detected by the receiving semiconductor device is similar to the skew illustrated in conventional <figref idref="DRAWINGS">FIG. 2B</figref>, a time delay of the data bit signal DQ<b>5</b> may be less than a time delay of the reference clock signal. In an alternative example, if the phase skew information is similar to the skew illustrated in <figref idref="DRAWINGS">FIG. 2C</figref>, the time delay of the data bit signal DQ<b>5</b> may be greater than that of the reference clock signal.

0084In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, the receiving semiconductor device may transmit the detected phase skew information to the transmitting semiconductor device through a data line or a separate phase information transmission line (at S<b>1050</b>). In an example, an interval and/or an instant of time at which the detected phase skew information is transmitted to the transmitting semiconductor device through the data line may be adjusted by the transmitting semiconductor device adaptively, for example, based on an environment of the parallel interface system. If the detected phase skew information is transmitted through the separate phase information transmission line, the detected phase skew information may be transmitted to the transmitting semiconductor device (e.g., in real time) without affecting data, and therefore, higher-bandwidth CDR may be achieved.

0085In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, a phase value of the transmitting sampling clock signal of the transmitting semiconductor device may be determined for each signal of N parallel data bit signals based on the phase skew information (at S<b>1060</b>). If the phase skew information of the bit DQ<b>5</b> detected by the receiving semiconductor device is similar to the skew illustrated in conventional <figref idref="DRAWINGS">FIG. 2B</figref>, the transmitting semiconductor device may transmit the data bit signal DQ<b>5</b> later than the reference clock signal in order to shift the data sampling clock signal CLKda to a position approximating a maximum time margin (e.g., as illustrated in <figref idref="DRAWINGS">FIG. 2A</figref>). Accordingly, the transmitting sampling clock signal used to transmit the data bit signal DQ<b>5</b> may be controlled so as to have a “later” or delayed phase.

0086In the example embodiment of <figref idref="DRAWINGS">FIG. 10</figref>, in an alternative example, if the phase skew information of the bit DQ<b>5</b> is similar to the skew illustrated in conventional <figref idref="DRAWINGS">FIG. 2C</figref>, the transmitting semiconductor device may control the transmitting sampling clock signal used to transmit the data bit signal DQ<b>5</b> so as to have an earlier phase in order to shift the data sampling clock signal CLKda to the position approximating the maximum time margin (e.g., as illustrated in <figref idref="DRAWINGS">FIG. 2A</figref>).

0087While above-described with respect to a hardware implementation, it is understood that other example embodiments of the present invention may be embodied as computer readable codes stored on a computer readable recording medium. The computer readable recording medium may be any data storage device that may store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, optical data storage devices, etc. The computer readable recording medium may also be distributed over network coupled computer systems so that the computer readable code may be stored and executed in a distributed fashion (e.g., over the Internet). Also, functional programs, codes, and code segments for accomplishing the present invention may be easily constructed by programmers skilled in the art to which example embodiments of the present invention are directed.

0088In another example embodiment of the present invention, both static skew and dynamic skew may be reduced without prohibitively increasing either an occupied chip or circuit area and/or power consumption in a receiver. In addition, if phase skew information for reducing dynamic skew is transmitted through a transmission line separated from a data transmission line, the phase skew information may be transmitted to a transmitter in “real time” without affecting data transfers or logic operations. As a result, higher-bandwidth CDR may be accomplished because dynamic skew reduction may be implemented without significantly decreasing performance.

0089Example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. For example, while above-described example embodiments are directed generally to an 8-bit parallel interface system, it is understood that other example embodiments of the present invention may be directed to a parallel interface system including any number of bits.

0090Such variations are not to be regarded as a departure from the spirit and scope of example embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.