Phase locking loop

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to U.S. Provisional Patent Application No. 61/407,967, filed on Oct. 29, 2010; which is hereby incorporated herein by reference in its entirety.

BACKGROUND

Wireless personal area networks (WPANs) are used to convey information over relatively short distances. A WPAN may transfer data at a relatively low rate to minimize power consumption. Unlike wireless local area networks (WLANs), WPANs employ little or no infrastructure. Consequently, WPANS allow small, power-efficient, and inexpensive solutions to be implemented for a wide range of devices.

Smart Utility Networks (SUNs) are one application of WPAN technology. A SUN may operate either over short ranges such as in a mesh network where utility meter information is sent from one utility meter to another, or over longer ranges such as in a star topology where utility meter information is sent to a pole-top collection point. The terms WPAN and SUN are used interchangeably herein.

Devices that communicate via a WPAN, or other type of wireless network, include oscillators that determine the carrier frequencies of the network. The frequencies of the oscillators drift over time. The drift can cause frequency and/or phase errors between the oscillators of communicating wireless devices. Such errors can cause errors in symbol decoding due to rotation of the symbol constellation in the receiving device. Some wireless devices may include a phase-locking loop to lock the receiver frequency to the carrier frequency of a transmission.

SUMMARY

A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received by the wireless receiver. The PLL includes a loop bandwidth controller. The loop bandwidth controller is configured to set a bandwidth of the PLL to a first value for reception of an initial symbol of the packet. The loop bandwidth controller is configured to reduce the bandwidth of the PLL over a number of symbols preceding an initial header of the packet.

In another embodiment, a method includes initializing a PLL of a wireless receiver to operate with a first bandwidth for reception of a wirelessly transmitted orthogonal frequency multiplexed packet. The bandwidth of the PLL is reduced from the first bandwidth to a second bandwidth as symbols preceding an initial header of the packet are received. The first bandwidth provides fast carrier acquisition, and the second bandwidth provides lower phase noise than the first bandwidth.

In a further embodiment, a system includes a first wireless device. The first wireless device is configured to receive a wirelessly transmitted orthogonal frequency multiplexed packet including frequency domain spreading. The first wireless device includes a PLL configured to lock the first wireless device to a carrier frequency of the packet. The PLL includes a despreader and a power loop. The despreader is configured to despread, prior to phase estimation, header and data signals of the packet. The despreading is in accordance with a frequency domain spreading factor applied to the packet at transmission. The power loop is coupled to an output of the despreader. The power loop is configured to extract phase offset from a despread data signal by computing a fraction of the data signal raised to a power. The fraction and the power are determined based on a type of modulation applied to the packet at transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a block diagram of wireless network including a wireless device incorporating a phase-locking loop (PLL) in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 2</figref> shows a block diagram of wireless device including a receiver with a PLL in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 3</figref> shows a block diagram of a PLL in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 4</figref> shows a block diagram of a pilot signal based phase estimator in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIGS. 5A and 5B</figref> show phase error plots respectively corresponding to phase extraction before and after signal mean computation in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 6</figref> shows a block diagram for a pilot and data signal based phase estimator in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 7</figref> shows an illustration of phase offset extraction in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a plot of phase error based on a pilot and data signal based phase estimator in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIGS. 9A and 9B</figref> show plots of bandwidth reduction and mean square error of phase noise resulting from the bandwidth reduction in accordance with various embodiments;

<figref idrefs="DRAWINGS">FIG. 10</figref> shows a plot of phase error produced by a PLL in accordance with various embodiments; and

<figref idrefs="DRAWINGS">FIG. 11</figref> shows a flow diagram for a method for phase locking to a carrier frequency in accordance with various embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The recitation “based on” is intended to mean “based at least in part on.” Therefore, if X is based on Y, X may be based on Y and any number of additional factors.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

A utility network or smart utility network (SUN) is a low-rate (e.g., 40 kbps to 1 Mbps) low-power wireless personal area network (WPAN) that is specifically designed for use in utility metering applications such as transmitting electric, gas, water usage, and other like data from the customer premises to a data collection point operated by the utility. For example, utility meters are installed for each house in a residential neighborhood, and the usage data is sent periodically from each utility meter to a data collection point, which is an element of the SUN. The data collection point is connected by fiber, copper wire, or wireless connection to a central office that collects all the usage data for a region. Usage data is sent either directly from each utility meter to the collection point or from utility meter to utility meter until the collection point is reached in a star or mesh network formation, respectively.

Orthogonal frequency division multiplexing (OFDM) spreads a data stream across a large number of orthogonal sub-carriers. The sub-carriers allow for reduced modulation rates and can enhance signal reliability in multipath environments. OFDM is used in a variety of wireless communication systems, including SUNs. Unfortunately, frequency and/or phase errors between the oscillators of wireless devices communicating via OFDM can disrupt demodulation by perturbing the orthogonality of the sub-carriers.

Embodiments of the present disclosure include a phase-locking loop (PLL) that tracks phase offset existing in symbols of OFDM systems. Note that the term symbol can refer to the OFDM symbol and also to the PSK symbol carried on each subcarrier. The PLL locks the phase rotation of the symbol induced by residual carrier frequency offset in the frequency domain. Embodiments of the PLL use the long training field, scattered pilots, and data symbols of a received packet to generate phase error estimates. Consequently, embodiments of the PLL can operate at a very low signal-to-noise ratio (SNR). For example, embodiments are operable at the low SNR encountered when frequency domain spreading is applied in conjunction with OFDM.

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a block diagram of a wireless system including a wireless device incorporating a PLL in accordance with various embodiments. The system <b>100</b> includes wireless devices <b>102</b> and <b>108</b>. The wireless devices <b>102</b> and <b>108</b> are configured to transmit and/or receive OFDM signals. The wireless devices <b>102</b>, <b>108</b> may apply frequency domain spreading (FDS) to the OFDM signals. Though only two wireless devices <b>102</b>, <b>108</b> are shown, in practice the system <b>100</b> may include any number of wireless devices. In some embodiments, the wireless devices <b>102</b>, <b>108</b> may be SUN devices in accordance with the IEEE 802.15.4 standard.

The wireless device <b>108</b> transmits the signal <b>110</b> for reception by the wireless device <b>102</b>. The wireless device <b>108</b> generates the frequencies of the signal <b>110</b> in accordance with a frequency and phase of an oscillator of the wireless device <b>108</b>. A packet included in the signal <b>110</b> includes a preamble, a header, and a data payload. The preamble may include training fields (e.g., long and/or short training fields). The header may be modulated using binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK). The data payload may be modulated using BPSK, QPSK, or 16-state quadrature amplitude modulation. (16-QAM). Information encoded in the header defines the data rate, modulation, frequency spreading factor, and length of the data payload. Pilots are embedded in the header and data payload to enable the PLL of the wireless device <b>102</b> to track the phase offset of the signal <b>110</b> in the frequency domain. The positions of the pilots in the header and/or data may change from symbol to symbol.

The wireless device <b>102</b> receives the signal <b>110</b>. In order to facilitate proper decoding of the symbols encoded in the signal <b>110</b>, the wireless device <b>102</b> includes the PLL <b>104</b>. The type of modulation and the frequency spreading factor applied to the header of the transmitted packet are known to the receiving wireless device <b>102</b> a priori. The PLL <b>104</b> estimates the phase and/or frequency error between an oscillator of the wireless device <b>102</b> and the oscillator of the wireless device <b>108</b> based on the data, pilot, and training symbols encoded in the signal <b>110</b>. The PLL <b>104</b> adjusts the frequency of the oscillator of the wireless device <b>102</b> based on the estimated phase and/or frequency error.

The PLL <b>104</b> utilizes both the pilot tones and the data tones of the OFDM signal <b>110</b> to track phase offset. Consequently, the PLL <b>104</b> is applicable to embodiments of the OFDM system <b>100</b> that embed pilots in the header and data payload and to embodiments of the OFDM system <b>100</b> that lack pilots in the header and data payload. The PLL <b>104</b> is also capable of tracking phase offset when the pilots shift position with each OFDM symbol to different subcarriers.

<figref idrefs="DRAWINGS">FIG. 2</figref> shows a block diagram of the wireless device <b>102</b> in accordance with various embodiments. The wireless device <b>102</b> includes an OFDM transceiver <b>202</b> for wirelessly transmitting and/or receiving OFDM signals. The OFDM transceiver <b>202</b> includes an OFDM transmitter <b>204</b> and an OFDM receiver <b>206</b>. The OFDM transmitter <b>204</b> includes components for transmitting an OFDM signal, such as amplifiers, D/A converters, filters, a cyclic prefix generator, an inverse Fourier transformer, pilot tone generators, preamble generators, encoders, modulators, etc.

The OFDM receiver <b>206</b> includes components for receiving a wirelessly transmitted OFDM signal, such as amplifiers, filters, digitizers, oscillators, a Fourier transformer, demodulators, decoders, symbol detectors, etc. The receiver <b>206</b> also includes the PLL <b>104</b>. The PLL <b>104</b> adjusts the frequency and/or phase of an oscillator in accordance with the frequency and/or phase of the received signal <b>110</b>.

<figref idrefs="DRAWINGS">FIG. 3</figref> shows a block diagram of the PLL <b>104</b> in accordance with various embodiments. The PLL <b>104</b> includes an equalizer <b>302</b>, a derotator <b>304</b>, a pilot tone extractor <b>306</b>, a data tone extractor <b>308</b>, a phase estimator <b>310</b>, a bandwidth controller <b>312</b>, and a second-order PLL core <b>314</b> including filters for the PLL <b>104</b>. An output of the PLL core <b>314</b> adjusts the frequency and phase of the oscillator <b>316</b>.

The equalizer <b>302</b> applies channel estimates <b>318</b> to equalize a symbol <b>320</b> encoded in the received signal <b>110</b>. The equalizer <b>302</b> may be a minimum mean square error equalizer or other equalizer for use with OFDM symbols known in the art. The derotator <b>304</b> removes rotation from the equalized symbols by multiplying the equalized symbols by the previous phase estimate {circumflex over (θ)}_n|n-1where index n denotes the OFDM symbol index.

The pilot tone extractor <b>306</b> extracts pilot tones from the derotated OFDM symbol. The data tone extractor <b>308</b> extracts data tones from the derotated OFDM symbol <b>322</b>. The extracted pilot tones and/or data tones are provided to the phase estimator <b>310</b>. The phase estimator <b>310</b> estimates the phase difference between the oscillator <b>316</b> and the oscillator of the transmitting device <b>108</b> based on the extracted pilot/data tones. The estimated phase error is denoted {circumflex over (θ)}_n-{circumflex over (θ)}_n|n-1.

The estimated phase error is provided to the second order PLL core <b>314</b>. In the packet based OFDM system <b>100</b>, the packet header contains information used to decode the data payload. Consequently, any phase error in the header symbols must be corrected quickly to allow the header to be decoded without error. To accelerate the convergence of the PLL <b>104</b>, the bandwidth controller <b>312</b> adjusts the bandwidth of the PLL core <b>314</b> from a relatively wide bandwidth value that allows fast convergence to a narrower value providing improved noise rejection. The bandwidth controller <b>312</b> adjusts the bandwidth by changing the gains applied to the PLL core <b>314</b> in the first few symbols of the received packet. The bandwidth controller <b>312</b> adaptively changes the loop filter gain α₁and oscillator gain α₂such that the PLL <b>104</b> enters a stable regime with control of the phase error.

The performance of the phase estimator <b>310</b> impacts the overall performance of the PLL <b>104</b>. <figref idrefs="DRAWINGS">FIG. 4</figref> shows a block diagram of a pilot signal based phase estimator <b>400</b> in accordance with various embodiments. Embodiments of the phase estimator <b>400</b> may be included in the phase estimator <b>310</b>. The pilot symbols <b>402</b> are known to the phase estimator <b>400</b>. The pilot signal based phase estimator <b>400</b> multiplies the equalized and derotated pilot symbols <b>404</b> by the conjugate of the known pilot symbols <b>402</b>. The phase estimator <b>400</b> includes a mean computation block <b>406</b> and a phase detector <b>408</b>.

When the noise level is higher than the signal level, the phase of the original signal is sensitive to large phase noise. The phase estimator <b>400</b> computes the mean of the pilot signals prior to determining the phase. Computing the mean prior to phase detection provides more accurate phase error estimates that computing the mean after phase detection. <figref idrefs="DRAWINGS">FIGS. 5A and 5B</figref> show phase error plots corresponding respectively to phase detection before signal mean computation and after signal mean in accordance with various embodiments. The plots assume SNR=−4 dB with 250 Hz carrier frequency offset (with carrier frequency of 982 MHz). Four pilot tones are used to estimate the phase for each OFDM symbol. <figref idrefs="DRAWINGS">FIGS. 5A and 5B</figref> show that mean computation prior to phase detection, as applied by embodiments of the phase estimators disclosed herein, produces smaller phase errors that computation of mean after phase detection.

<figref idrefs="DRAWINGS">FIG. 6</figref> shows a block diagram for a pilot and data signal based phase estimator <b>600</b> in accordance with various embodiments. Embodiments of the phase estimator <b>600</b> may be included in the phase estimator <b>310</b>. The phase estimator <b>600</b> includes components of the pilot based phase estimator <b>400</b>, a despreader <b>602</b>, a power loop <b>604</b>, and a mean computation block <b>606</b>. The mean computation block <b>606</b> computes the mean of data and/or header signals prior to phase detection by the phase detector <b>408</b> for the reasons explained above.

The wireless network <b>100</b> may employ frequency domain spreading. The phase estimator <b>600</b> provides improved performance by despreading, via the despreader <b>602</b>, as known in the art, packet header and data payload with a frequency domain spreading factor prior to the power loop <b>604</b>.

The header of a received OFDM packet may be modulated using one of BPSK and QPSK, and the modulation type is known to the phase estimator <b>600</b> a priori. For a BPSK constellation and a QPSK constellation, the power loop <b>604</b> implements a 2nd order power-loop and a 4th order power-loop, respectively, to extract the phase offset of the received signal. For example, when there is a phase offset θ in the BPSK constellation, the power loop <b>604</b> applies a 2nd order power-loop to extract the phase offset.

<figref idrefs="DRAWINGS">FIG. 7</figref> shows an illustration of phase offset extraction for a BPSK modulated symbol using a 2nd-order power loop in accordance with various embodiments of the power loop <b>604</b>. The power loop <b>604</b> squares the symbol producing an angle of 2θ corresponding to the squared symbol. The power loop <b>604</b> divides the angle 2θ by 2 to extract the value of the phase θ of the symbol. The power loop <b>604</b> operates similarly for a QPSK modulated symbol. The power loop <b>604</b> raises the QPSK symbol to the fourth power producing an angle of 4θ. The power loop <b>604</b> divides the angle 4θ by 4 to extract the value of the phase θ of the symbol. For a 16-QAM constellation, the power loop <b>604</b> applies a 12th order power-loop (raises to the power 12 and divides by 12) to extract the phase offset of the data payload.

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a plot of phase error based on the pilot and data signal based phase estimator <b>600</b> in accordance with various embodiments. The plot is based on operation with SNR=−4 dB with 250 Hz carrier frequency offset and BPSK modulated header and data with FDS=4 (frequency domain spreading factor of 4). Four tones and 48 tones are used for the pilots and data, respectively. As the plot shows, the phase estimator <b>600</b> significantly decreases phase noise relative to the pilot-based estimator <b>400</b>. A frequency domain spreading factor of 2 (FDS=2) replicates PSK symbols in the positive-numbers data subcarriers and copies them into the negative-numbered data subcarriers with pre-determined phase rotations which reduce the peak-to-average power ratio. A frequency domain spreading factor of 4 (FDS=4) replicates PSK symbols in the lower half of the positive-numbered data tones and copies them to the upper half of the positive-numbered data tones and the lower and upper halves of the negative-numbered data tones, again with pre-determined phase rotations applied to the replicated PSK symbols.

Returning now to <figref idrefs="DRAWINGS">FIG. 3</figref>, for the second order PLL core <b>314</b>, loop filter gain α₁and VCO gain α₂can be expressed as:

<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mrow><mrow><msub><mi>α</mi><mn>1</mn></msub><mo>=</mo><mfrac><mrow><msubsup><mi>ω</mi><mi>n</mi><mn>2</mn></msubsup><mo>⁢</mo><msup><mi>T</mi><mn>2</mn></msup></mrow><mrow><mn>1</mn><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><msub><mi>ζω</mi><mi>n</mi></msub><mo>⁢</mo><mi>T</mi></mrow><mo>+</mo><mrow><msubsup><mi>ω</mi><mi>n</mi><mn>2</mn></msubsup><mo>⁢</mo><msup><mi>T</mi><mn>2</mn></msup></mrow></mrow></mfrac></mrow><mo>,</mo><mi>and</mi></mrow></math></maths><maths id="MATH-US-00001-2" num="00001.2"><math overflow="scroll"><mrow><msub><mi>α</mi><mn>2</mn></msub><mo>=</mo><mfrac><mrow><mrow><mn>2</mn><mo>⁢</mo><msub><mi>ζω</mi><mi>n</mi></msub><mo>⁢</mo><mi>T</mi></mrow><mo>+</mo><mrow><msubsup><mi>ω</mi><mi>n</mi><mn>2</mn></msubsup><mo>⁢</mo><msup><mi>T</mi><mn>2</mn></msup></mrow></mrow><mrow><mn>1</mn><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><msub><mi>ζω</mi><mi>n</mi></msub><mo>⁢</mo><mi>T</mi></mrow><mo>+</mo><mrow><msubsup><mi>ω</mi><mi>n</mi><mn>2</mn></msubsup><mo>⁢</mo><msup><mi>T</mi><mn>2</mn></msup></mrow></mrow></mfrac></mrow></math></maths><br /> where: <ul><li id="ul0001-0001" num="0000"><ul><li id="ul0002-0001" num="0044">T denotes the symbol duration,</li><li id="ul0002-0002" num="0045">ω_ndenotes natural frequency which is related to loop bandwidth f_nas ω_n=2πf_n, and</li><li id="ul0002-0003" num="0046">ζ denotes the damping factor.</li></ul></li></ul>

The bandwidth controller <b>312</b> adaptively changes loop BW f_nsuch that the mean squared error (MSE) of the phase noise is minimized. The bandwidth reduction sequence applied by the bandwidth controller <b>312</b> and the corresponding MSE are shown in <figref idrefs="DRAWINGS">FIGS. 9A and 9B</figref> respectively. <figref idrefs="DRAWINGS">FIG. 9A</figref> shows that the bandwidth controller <b>312</b> sets the PLL <b>104</b> to have a relatively wide bandwidth at the start of the packet, and substantially narrows the bandwidth within the first few symbols of the packet. The wide initial bandwidth allows the PLL <b>104</b> to converge quickly. The narrowed bandwidth reduces phase noise, stabilizing the oscillator <b>316</b>.

<figref idrefs="DRAWINGS">FIG. 10</figref> shows a plot of phase error produced by the PLL <b>104</b> in accordance with various embodiments. The plot illustrates operation of the PLL <b>104</b> in an OFDM system <b>100</b> with 64 subcarriers, 4 pilot tones and 48 data tones, and header and data payload modulated using BPSK with FDS=4. A residual carrier frequency offset of 1 part-per-million (with carrier frequency 928 MHz) at SNR=−4 dB in the AWGN channel is assumed. The plot of <figref idrefs="DRAWINGS">FIG. 10</figref> shows the ability of the PLL <b>104</b> to track residual carrier frequency offset.

Various components of the PLL <b>104</b> including at least some portions of the phase estimator <b>310</b> and the bandwidth controller <b>312</b> can be implemented using a processor in the wireless device <b>102</b> executing software programming that causes the processor to perform the operations described herein. In some embodiments, the phase estimator <b>310</b> includes a processor executing software programming that causes the processor to despread data signals, perform the power loop computations, and/or compute signal mean as disclosed herein.

Suitable processors include, for example, general-purpose microprocessors, digital signal processors, and microcontrollers. Processor architectures generally include execution units (e.g., fixed point, floating point, integer, etc.), storage (e.g., registers, memory, etc.), instruction decoding, peripherals (e.g., interrupt controllers, timers, direct memory access controllers, etc.), input/output systems (e.g., serial ports, parallel ports, etc.) and various other components and sub-systems.

Software programming that causes a processor to perform the operations disclosed herein can be stored in a computer readable storage medium. A computer readable storage medium comprises volatile storage such as random access memory, non-volatile storage (e.g., a hard drive, an optical storage device (e.g., CD or DVD), FLASH storage, read-only-memory), or combinations thereof.

Some embodiments can implement portions of the PLL <b>104</b>, including portions of the phase estimator <b>310</b> and the bandwidth controller <b>312</b> using dedicated circuitry (e.g., dedicated circuitry implemented in an integrated circuit). Some embodiments may use a combination of dedicated circuitry and a processor executing suitable software. For example, some portions of the phase estimator <b>310</b> may be implemented using a processor or hardware circuitry. Selection of a hardware or processor/software implementation of embodiments is a design choice based on a variety of factors, such as cost, time to implement, and the ability to incorporate changed or additional functionality in the future.

<figref idrefs="DRAWINGS">FIG. 11</figref> shows a flow diagram for a method for phase locking to a carrier frequency in accordance with various embodiments. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown. In some embodiments, at least some of the operations of the method <b>1100</b>, as well as other operations described herein, can be performed by a processor executing instructions stored in a computer readable medium.

In block <b>1102</b>, the PLL bandwidth controller <b>312</b> initializes the bandwidth of the PLL <b>104</b> to be relatively wide. The wide initial bandwidth allows the PLL <b>104</b> to converge quickly based on the initial symbols (e.g., the long/short training field symbols) contained in the packet preamble. Quick convergence allows the PLL <b>104</b> to adjust the frequency and/or phase of the oscillator <b>316</b> prior to reception of the packet header, which defines data payload decoding parameters.

In block <b>1104</b>, the PLL bandwidth controller <b>312</b> reduces the bandwidth of the PLL <b>104</b> as symbols preceding the packet header are received. In some embodiments, the bandwidth of the PLL <b>104</b> is narrowed in a plurality of successively narrowing steps. The PLL bandwidth controller <b>312</b> may narrow the bandwidth by reducing the gain of the loop filter of the PLL and/or reducing the gain of the oscillator <b>316</b>.

In block <b>1106</b>, the PLL <b>104</b> determines the location of the pilot tones in the OFDM symbol. The pilot tones may move to different subcarriers with each successive symbol. The PLL <b>104</b> equalizes and derotates the received OFDM symbol, and extracts the pilot and/or data signals from the derotated symbol.

In block <b>1108</b>, the PLL <b>104</b> computes the mean of the extracted pilot signals prior to phase detection.

In block <b>1110</b>, the PLL <b>104</b> despreads the extracted header and/or data signals. The PLL <b>104</b> despreads the signals in accordance with a frequency domain spreading factor applied at transmission of the packet.

In block <b>1112</b>, the PLL <b>104</b> extracts phase offset from the data and/or header signals. The PLL <b>104</b> raises the data/header signal to a power and computes the phase offset as a fraction of the angle of the signal raised to the power. The power and the fraction are selected based on the type of modulation applied to the signal at the transmitting device. For BPSK, QPSK, and 16-QAM modulation types, the power and fraction applied are (2, ½), (4, ¼), and (12, 1/12) respectively.

In block <b>1114</b>, the PLL <b>104</b> computes the mean of the data signal. The PLL <b>104</b> estimates the phase error in block <b>1116</b>, and adjusts the frequency and/or phase of the oscillator <b>316</b> to conform to the frequency and/or phase of the carrier frequency of the received packet based on the estimated phase error in block <b>1118</b>. This can be done by directly controlling the oscillator or by multiplying the incoming samples by frequency correction factors using a complex multiplier.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.