Thin film transistor with increased doping regions

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application No. 61/658,869, filed Jun. 12, 2012 and entitled “Thin Film Transistor With Increased Doping Regions,” the disclosure of which is hereby incorporated herein in its entirety.

TECHNICAL FIELD

The present invention relates generally to transistors, and more specifically, to structures for thin film transistors.

BACKGROUND

Thin film transistors (TFTs) are generally field-effect transistors that have a substrate supporting one or more layers of a semiconductor active layer, a dielectric layer, and metallic contacts. TFTs may be used in a number of electronic devices, such as in liquid crystal displays (LCD), organic light emitting diode displays such as active matrix organic diode (AMOLED) displays, and so on. In these instances, the TFTs may be incorporated into the panel of the display to essentially activate and deactivate select pixels. For example, with LCD displays, each pixel may include a TFT may be communicatively coupled to a red, a blue, and a green pixel, the TFT may selectively activate each pixel cell depending on the desired output. In this way the TFT may act as a switch for each pixel, and thus control the output of the pixel. There are many other uses for TFTs and the above examples are just a couple of conventional uses for TFTs.

SUMMARY

One example of the present disclosure may take the form of a transistor including a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer including an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer.

Other examples of the present disclosure may take the form of an electronic display. The electronic display may include at least one pixel and a transistor including a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer including an extension portion that extends a distance past the metal layer, and at least three doped regions positioned in the silicon layer. The transistor is configured to selectively activate the at least one pixel.

An electronic display including at least one pixel and a transistor communicatively coupled to the at least one pixel and configured to selectively activate the pixel. The transistor includes a metal layer, a silicon layer deposited on at least a portion of the metal layer, the silicon layer including an extension portion that extends a distance past the metal layer, and at least three lightly doped regions positioned in the silicon layer.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1</figref> is a top plan view of conventional TFT with an insulating layer is removed for clarity.

<figref idrefs="DRAWINGS">FIG. 2</figref> is a cross-section view of the TFT of <figref idrefs="DRAWINGS">FIG. 1</figref> viewed along line <b>2</b>-<b>2</b> in <figref idrefs="DRAWINGS">FIG. 1</figref> and including the insulating layer.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a top plan view of a TFT including an extension portion with additional doped regions, with an insulating layer remove for clarity.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a cross-section view of the TFT of <figref idrefs="DRAWINGS">FIG. 3</figref> taken along line <b>4</b>-<b>4</b> in <figref idrefs="DRAWINGS">FIG. 3</figref>, and including an insulating layer.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a top plan view of a second example of a TFT including the extension portion and having an intra-gate doped region.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a top plan view of a third example of a TFT including the extension portion with the doped regions having a variable length.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a top plan view of the TFT of <figref idrefs="DRAWINGS">FIG. 6</figref> but including an intra-gate doped region.

<figref idrefs="DRAWINGS">FIG. 8</figref> is a top plan view of a single gate TFT including additional doped regions on both sides of a channel, with one side of the channel having an extended doped region.

<figref idrefs="DRAWINGS">FIG. 9</figref> is a top plan view of the single gate TFT of <figref idrefs="DRAWINGS">FIG. 8</figref> having additional doped regions of varying lengths, with one side of the channel having an extended doped region.

<figref idrefs="DRAWINGS">FIG. 10</figref> is a top plan view of a single gate TFT including multiple additional doped regions with variable lengths on both sides of the channel.

<figref idrefs="DRAWINGS">FIG. 11</figref> is a top plan view of a single gate TFT including multiple additional doped regions with the same length on both sides of the channel.

<figref idrefs="DRAWINGS">FIG. 12</figref> is a top plan view of a single gate TFT including multiple additional doped regions, where one side of the channel the additional doped regions have the same length and one side of the channel the additional doped regions have varying lengths.

SPECIFICATION

Overview

In some embodiments herein, a thin film transistor (TFT) having an extended poly-silicon structure is disclosed. The extension of the poly-silicon structure also includes multiple lightly doped drain (LDD) regions or slots, which introduce one or more doping agents into the poly-silicon structure. The LDD regions may form source/drain pairs acting as junctions for the TFT. As an example, the TFT may include one or more gates defined by creating a channel between two sections of LDD deposited into the poly-silicon structure. The channel may be defined as a portion of the poly-silicon layer that may be in communication with a conductor, such as a metal electrode. The metal electrode may be flanked on either side by two LDD doped regions. When the TFT is activated, a voltage signal is applied to the electrode and electrons act as charge carriers and move between one doped region (a source) to another doped region (drain).

The TFT of the present disclosure may further include an extension member. The extension member may be formed of a poly-silicon layer, or other non-conductive material that may be doped with one or more doping agents to create a semiconductor. In some embodiments, the extension member may include two or more slots of a LDD. The additional LDD regions or slots may act to divide and reduce a lateral electric field, which may in turn reduce current leakage across the junctions of the TFT. Additionally, in some embodiments, the extension may include spacing regions of the non-conductive material that may be positioned between the additional LDD regions to break up the length of the LDD regions. The spacing regions may reduce the series resistance of the LDD regions, and thus increase the conductivity of the TFT, while still acting to reduce the lateral electric field.

The LDD or doped regions of the extension may have the same length or varying lengths. For example, in some instances, the additional LDD region closest to a gate of the TFT may have the largest length and the other LDD regions may have lengths that are smaller than the first LDD region. In this example, the smaller LDD regions may act to divide the lateral electric field, and the largest LDD at the junction may substantially reduce the lateral electric field to zero or near-zero. These embodiments may help to prevent a high electric field at an edge of the channel approaching the gate. Further, because the additional LDD regions may be relatively small, the electric field may be reduced without substantially reducing the conductivity of the TFT. In some embodiments, the LDD regions may gradually increase in length from a first end of the extension towards the gate. However, in other embodiments, the LDDs may be differently dimensioned. For example, each LDD region may have the same length, some of the LDD regions may have the same length, or each LDD region may have a different length.

In some embodiments, the TFT of the present disclosure may be implemented to control one or more pixels or color cells. In these embodiments, the extension of the poly-silicon material including the additional LDD regions may increase the optical performance of a display incorporating the pixels controlled by the TFT. This is because the LDD reduces the lateral electric field to reduce pixel TFT leakage current which may reduce flicker and/or crosstalk in a display, discussed in more detail below.

DETAILED DESCRIPTION

Turning now to the figures, <figref idrefs="DRAWINGS">FIG. 1</figref> is a simplified top plan view of a conventional double gate TFT <b>100</b> including two gates <b>102</b>, <b>104</b>. In <figref idrefs="DRAWINGS">FIG. 1</figref> an insulating layer is removed for clarity. <figref idrefs="DRAWINGS">FIG. 2</figref> is a cross-section view of the TFT <b>100</b> viewed along line <b>2</b>-<b>2</b> in <figref idrefs="DRAWINGS">FIG. 1</figref>, but including the insulating layer. The TFT <b>100</b> includes a conductor, such as a metal layer <b>116</b> having a first branch <b>118</b> and a second branch <b>120</b>, which form two gates of the TFT <b>100</b>. The two metal layer branches <b>118</b>, <b>120</b> are structured to intersect between two doped regions of a silicon layer <b>106</b>, discussed in more detail below. The metal or conductive layer <b>116</b> may be formed of various types of electrical conductors, such as metallic materials (e.g., copper, aluminum, metal alloys), or materials laced with metallic particles.

The silicon layer <b>106</b> is often placed on a substrate (not shown), such as mica, silicon nitride, silicon dioxide, metal-coated silicon, quartz, glass or another base material. The silicon layer <b>106</b> may be poly-silicon, crystalline silicon, or amorphous silicon, depending on the desired use. In a double gate TFT, such as the TFT <b>100</b> illustrated in <figref idrefs="DRAWINGS">FIGS. 1 and 2</figref>, the silicon layer <b>106</b> may have two legs <b>128</b>, <b>130</b> that are interconnected to form a corner portion <b>126</b>. In this embodiment, the first leg <b>128</b> extends across the first metal branch <b>118</b> and the second leg <b>130</b> extends across the second metal branch <b>120</b>. The two legs <b>128</b>, <b>130</b> may be doped with one or more dopants (such as, but not limited to, arsenic, boron, antimony, arsenic, aluminum, selenium, germanium, or the like, depending on the particular semiconductor) to define a source and a drain. For example, the first leg <b>128</b> may define a first lightly doped region <b>108</b> and a second lightly doped region <b>110</b>. The combination of the poly-silicon of the leg <b>128</b> and the lightly doped region <b>108</b> may form a source <b>101</b>, and the combination of the poly-silicon of the leg <b>126</b> and the second lightly doped region <b>110</b> may form the drain <b>103</b>, such that the two regions <b>108</b>, <b>110</b> may from portions of the drain and the source for the TFT <b>100</b>. Accordingly, the source <b>101</b> and the drain <b>103</b> for the TFT may be formed by a combination of the poly-silicon layer <b>106</b> and one or more lightly doped regions <b>108</b>, <b>110</b>. Similarly, the second leg <b>130</b> may define a source <b>105</b> and a drain <b>106</b> that may include one or more portions of poly-silicon and lightly doped regions <b>112</b>, <b>114</b>. It should be noted that the source and drain for each leg may be interchanged. For example, the silicon leg <b>126</b> and doped region <b>110</b> may function as a source and the silicon region <b>128</b> and lightly doped region <b>108</b> may function as a drain.

The doped regions <b>108</b>, <b>110</b>, <b>112</b>, <b>114</b> may be doped with the same dopant or different dopants; however, generally, the doped portions may be doped with the same dopant. The doped portions <b>108</b>, <b>110</b>, <b>112</b>, and <b>114</b> may be a lightly doped drain (LDD) structure, where the implant density of the dopant may be relatively low, e.g., between 10¹⁸-10²³cm⁻³of impurity atoms. In some embodiments, the silicon layer <b>106</b>, and specifically the legs and corner portions <b>126</b>, <b>128</b>, <b>130</b> may be heavily doped regions that include the same dopant or doping type as the lightly doped regions <b>108</b>, <b>110</b>, <b>112</b>, <b>114</b>. In these embodiments, the lightly doped regions <b>108</b>, <b>110</b>, <b>112</b>, <b>114</b> may have a lower density of impurity atoms as compared to the surrounding heavily doped silicon portions <b>126</b>, <b>128</b>, <b>130</b>.

With reference to <figref idrefs="DRAWINGS">FIG. 2</figref>, the first branch <b>118</b> of the metal layer <b>116</b> may be positioned above and between a first lightly doped region <b>108</b> and a second lightly doped region <b>110</b>. Similarly, the second branch <b>120</b> may be positioned above and between a third lightly doped region <b>112</b> and a fourth lightly doped region <b>114</b>. It should be noted that a gate insulator <b>122</b> may physically separate the lightly doped regions <b>108</b>, <b>110</b> from the metal layer <b>116</b>. A channel <b>124</b> may be defined on the silicon layer <b>106</b> between the two lightly doped regions <b>108</b>, <b>110</b>, and <b>112</b>, <b>114</b>, and the channel <b>124</b> may be substantially parallel to the branches <b>118</b>, <b>120</b> of the metal layer <b>116</b>. In this manner, the lightly doped regions <b>108</b>, <b>110</b> and <b>112</b>, <b>114</b> may be separated from each other to define the regions at source <b>101</b> and drain <b>103</b> and create channel <b>124</b> where electrons may flow between when a voltage is applied to the metal layer <b>116</b>. In some embodiments, the channel <b>124</b> may be the only portion of the silicon layer that may not be doped with impurity atoms.

Additionally, as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, the silicon layer <b>106</b> and the lightly doped regions <b>108</b>, <b>110</b>, <b>112</b>, <b>114</b> may be at least partially covered by the gate insulator <b>122</b>. The insulator <b>122</b>, which is a dielectric layer, prevents the lightly doped regions <b>108</b>, <b>110</b>, <b>112</b>, and <b>114</b> as well as the poly-silicon layer <b>106</b> from directly contacting the metal layer <b>116</b>. The insulator <b>122</b> may be substantially any suitable insulator as conventionally known in the art.

With reference to <figref idrefs="DRAWINGS">FIG. 2</figref>, in operation, a signal or voltage is applied to the metal layer <b>116</b> to activate the TFT <b>100</b>. With a N-type TFT, the activation signal may be positive voltage.

The insulator <b>122</b> may act as a dielectric layer in a capacitor and induce a charge in the channel <b>124</b> between the two lightly doped regions <b>108</b>, <b>110</b> and <b>112</b>, <b>114</b> and the heavily doped regions <b>126</b>, <b>128</b>, <b>130</b> (e.g., between the source <b>101</b> and drain <b>103</b> of each leg of the silicon layer <b>106</b>). The charge induces an electron flow from the source <b>101</b> (defined as the first lightly doped region <b>108</b> and the heavily doped silicon portion <b>128</b>) to the drain <b>103</b> (defined as the second lightly doped region <b>110</b> and the second heavily doped silicon portion <b>126</b>), making the channel <b>124</b> conductive. The second gate <b>104</b> may activate in a similar manner. When the voltage is removed from the metal layer <b>116</b> (e.g., gate), the electrons are substantially depleted from the channel <b>124</b>, so that substantially no current is present in the channel <b>124</b>.

The TFT <b>100</b> of <figref idrefs="DRAWINGS">FIGS. 1 and 2</figref> may be used in numerous applications, such as in displays for electronic devices (e.g., LCD) displays. However, in some instances, conventional TFTs, such as the TFT <b>100</b> illustrated in <figref idrefs="DRAWINGS">FIGS. 1 and 2</figref>, may have a relatively large leakage current. In other words, in an “off” state when the turn-off voltage (negative voltage for N-type, positive voltage for p-type) is applied to the metal layer <b>116</b>, these conventional TFTs may have some current transmitted through the channel <b>124</b>. In instances where the TFT <b>100</b> is used to control one or more pixel elements in a display, current leakage may cause flicker in the display as certain colors of the pixels controlled by one or more TFTs <b>100</b> may change brightness due to current leakage, although the TFT <b>100</b> may actually be turned off. Similarly, current leakage in the TFT <b>100</b> may create crosstalk or another image distortion characteristics as certain pixels may not be turned off completely and there is leakage current in some of the pixels elements controlled by the TFTs <b>100</b>. For example, thinner transistors devices, such as conventional TFTs, may experience higher electric lateral fields due to two-dimensional effects arising from the reduced junction depth compared to thicker film devices.

Embodiments of the present disclosure may reduce or substantially eliminate current leakage, and thus may reduce display artifacts such as flicker and crosstalk when TFTs of the present disclosure are incorporated into a display such as a LCD display. <figref idrefs="DRAWINGS">FIG. 3</figref> is a simplified top plan view of a first embodiment of a thin film transistor <b>200</b> including an extended silicon layer <b>106</b> having two or more additional doped portions or slots. <figref idrefs="DRAWINGS">FIG. 4</figref> is a cross-sectional view of the TFT <b>200</b> viewed along line <b>4</b>-<b>4</b> in <figref idrefs="DRAWINGS">FIG. 3</figref>. In some embodiments, the TFT <b>200</b> may be a low temperature poly-silicon (LTPS) transistor and may include a poly-silicon base processed at low temperatures. However, it should be noted that the techniques and ideas disclosed herein may be used for other types of transistors. For example, other types of poly-silicon transistors, other silicon based transistors (e.g., amphorous or crystalline silicon), and so on may incorporate the teachings and embodiments disclosed herein.

The TFT <b>200</b> may be somewhat similar to the TFT <b>100</b> illustrated in <figref idrefs="DRAWINGS">FIG. 1</figref>, in that the TFT <b>200</b> may include a metal layer <b>216</b> and a silicon layer <b>206</b> each having two branches or legs to form a multi-junction transistor. However, as shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, the TFT <b>200</b> may further include an elongated or extension portion of the silicon layer <b>250</b>. In some embodiments, the extension and the silicon layer may be a poly-silicon material and may include one more lightly doped regions, such as a LDD slots, discussed in more detail below, as well as one or more heavily doped regions that have an increased amount of dopant compared to the LDD regions. The extension <b>250</b> will be discussed in more detail below, but generally may act to decrease current leakage between two doped portions forming a source and a drain for the TFT <b>200</b>.

The TFT <b>200</b> may include a metal or other conductive layer <b>206</b>. The metal layer <b>206</b> may be a metal or metal alloy, such as, but not limited to, aluminum, gold, copper, or alloys thereof. Depending on the desired structure for the TFT <b>200</b>, the metal layer <b>206</b> may have one or more branches <b>218</b>, <b>220</b> to form two or more terminals, gates, or junctions. For example, the TFT <b>200</b> illustrated in <figref idrefs="DRAWINGS">FIG. 3</figref> may have two gates as each branch <b>218</b>, <b>220</b> may form an electrode for a source and drain pair of the semiconductor layer (doped portions of the silicon layer). However, it should be noted that in other embodiments, the number of terminals may be varied based on the desired design and/or application for the TFT <b>200</b>. For example, the TFT <b>200</b> may include a single gate or more than two gates. As will be discussed in more detail below, the metal layer <b>216</b> may be communicatively coupled to one or more signal lines (e.g., data or gate lines)(not shown) which may provide signals to control the TFT <b>200</b>. As shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, the TFT <b>200</b> may include two gates or junctions <b>260</b>, <b>262</b>, where each gate <b>260</b>, <b>262</b> may be defined as a source/drain pair and an electrode.

The TFT <b>200</b> may also include a silicon layer <b>206</b> that may have one more lightly doped portions <b>208</b>, <b>210</b>, <b>212</b>, <b>214</b>, where the lightly doped portions may form a portion of a source/drain pair along with one or more highly doped regions of the silicon layer. For example, a drain <b>203</b> for gate <b>201</b> is the combination of the lightly doped region <b>210</b> and the highly doped region <b>226</b> forming the intra-gate silicon layer between the two gates <b>260</b>, <b>262</b>. A source <b>201</b> for the gate <b>260</b> is the combination of lightly doped regions <b>208</b>, <b>252</b>, <b>254</b> and heavily doped regions <b>256</b>, <b>258</b>, <b>260</b> forming the extension. Similarly, the source <b>205</b> for gate <b>262</b> is the combination of the lightly doped region <b>212</b> and the heavily doped region <b>230</b>, and the gate <b>207</b> for the gate <b>262</b> is the combination of the lightly doped region <b>214</b> adjacent the channel and the heavily doped region <b>226</b>. Additionally, the silicon layer <b>206</b> may include the extension <b>250</b> which may include additional lightly doped regions or portions <b>252</b>, <b>254</b>. The silicon layer <b>206</b> may include two legs <b>228</b>, <b>230</b>, with the first leg <b>228</b> including the extension portion <b>250</b>. The silicon layer <b>206</b> may include an elbow <b>226</b> or corner portion forming a transition between the two legs <b>228</b>, <b>230</b>. In some embodiments, the elbow <b>226</b> may also include a lightly doped portion (see <figref idrefs="DRAWINGS">FIG. 6</figref>) to form an intra-gate doped region, discussed in more detail below.

The silicon layer <b>206</b>, including the extension <b>250</b>, may include portions that have been doped with one or more dopants or doping agents (such as but not limited to, phosphor, arsenic, or the like). It should be noted that the silicon region <b>206</b> may include one or more areas that may be heavily doped with a dopant. For example, the elbow <b>226</b> and/or both legs <b>228</b>, <b>230</b> may be doped an increased density of impurity atoms as compared to the lightly doped regions. It should be noted that in many instances, TFTs used for pixels in displays may be N-type, and so may be doped with phosphor or arsenic or other similar donor type materials. The doping agents may be elements that are inserted into the silicon layer <b>206</b> to alter select characteristics, such as the electrical properties, of the silicon layer <b>206</b>. In some instances, the doped portions may have free electrons that allow an electric current to flow through the doped portion of the silicon layer <b>206</b>. In such instances, the TFT <b>200</b> may form an N-type transistor.

Additionally, the doped portions of the silicon layer <b>206</b> may form a LDD or other similarly lightly or low doped structure. That is, the lightly doped portions of the silicon layer <b>206</b> may have a relatively low concentration of a doping agent. In some embodiments, the implant density of the doping agent for the doped portions may range between 10¹⁸-10²⁰of impurity atoms per cubic centimeter. The LDD regions may have a lower dopant density as compared to other portions of the silicon layer <b>106</b>, except for the channel forming the gates, which may not be doped with any doping agents.

The first two lightly doped portions along with the heavily doped regions of the first leg <b>228</b> may form a source <b>201</b> and a drain <b>203</b>. Although, it should be noted that the source <b>201</b> and drain <b>203</b> may be alternatively arranged. That is, the first lightly doped regions <b>208</b>, <b>252</b>, <b>254</b> and the heavily doped regions <b>256</b>, <b>258</b><b>260</b> of the extension <b>250</b> may form the drain, and the second lightly doped region <b>210</b> and the corner portion <b>226</b> of the layer <b>206</b> may form the source, depending on the desired structure for the TFT <b>200</b>. The first leg <b>228</b> of the silicon layer <b>206</b> may thus include a first source/drain pair <b>201</b>, <b>203</b> that extend across either side of the first branch <b>218</b> of the metal layer <b>216</b>. As shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, the source <b>201</b> and the drain <b>203</b> may be spaced from each other to from a channel <b>224</b>. In some instances, two lightly doped regions <b>208</b>, <b>210</b> may be formed adjacent to the channel <b>224</b>. The channel <b>224</b>, similar to the channel <b>124</b>, may conduct current when a voltage is applied to the branch <b>218</b> as electrons move from the source <b>208</b> to the drain <b>210</b>. For example, the metal branch <b>218</b> may be positioned parallel to and above the channel <b>224</b>. The channel <b>224</b> may be formed of a portion of non-doped silicon of the silicon layer <b>206</b>.

Unlike conventional transistors, the TFT <b>200</b> may include the extension portion <b>250</b> which may include additional lightly doped portions <b>252</b>, <b>254</b>. The additional lightly doped portions <b>252</b>, <b>254</b>, along with the first lightly doped region <b>208</b>, may reduce electrical field interference that may affect the current transfer through the channel <b>224</b>. For example, generally when the TFT <b>200</b> is activated, a lateral electric field may be induced due a non-zero potential between the source <b>201</b> and drain <b>203</b> as a voltage is applied to the metal layer <b>216</b>. The lateral electric field causes electrons to move between the source <b>201</b> and drain <b>203</b>, activating the TFT <b>200</b>. However, in some instances the lateral electric field may cause current to leak (e.g., some conductivity across the channel <b>224</b>) at zero and negative gate bias. That is, the lateral electric field may be strong enough to cause the TFT <b>200</b> to be slightly activated although little or no voltage may be applied to the metal layer <b>216</b>. In some instances, the current leakage may be exponentially dependent on the lateral electric field, and thus reducing the lateral electric field may substantially reduce current leakage.

With reference again to <figref idrefs="DRAWINGS">FIGS. 3 and 4</figref>, the lateral electric field of the TFT <b>200</b> may be divided by the two additional lightly doped regions <b>252</b>, <b>254</b> prior to reaching the junction <b>260</b>. The additional lightly doped regions <b>208</b>, <b>252</b>, <b>254</b>, which may be slots of LDD, may create multiple junctions to divide the lateral electric field along each of the junctions, and thus reduce the electric field as it travels from a first end of the extension <b>250</b> towards the junction <b>260</b>. This is because the mobility of electrons (or other carriers) within the TFT <b>200</b> is related to the lateral electric field, and by increasing the lightly doped portions (LDD) within the silicon layer <b>206</b>, the lightly doped regions <b>252</b>, <b>254</b> decrease the mobility of carriers within the silicon layer <b>206</b>, especially as many portions of the silicon layer may be heavily doped. Specifically, a depletion region may be formed at junctions between the lightly doped regions <b>208</b>, <b>252</b>, <b>254</b> and the heavily doped regions of the silicon layer <b>206</b> (which may be heavily doped N-Type poly-silicon). In the depletion region, the resistance may be very high as there may be no free carriers or electrons within that region. Accordingly, in some instances, the only way for the electrons to travel across the depletion region is to increase the electrical field in that area and sweep the electrons from an first edge of the junction to a second edge. In other words, most of the applied voltage will drop at the depletion region between the lightly doped regions and the heavily doped regions of the silicon layer <b>206</b> Therefore, by increasing the doped regions of LDD, the division of the lateral field is increased, and the electrical field at top or upper lightly doped region <b>208</b> near the channel <b>124</b> is reduced in that fewer carriers (electrons) may be able to move out from the channel <b>224</b> to form a leakage current.

In some embodiments, the extension <b>250</b> may include a single lightly doped region that extends the entire length LT of the extension. In these embodiments, the electric field may be reduced; however, the resistance of the TFT <b>200</b> may be substantially increased, reducing the conductivity. This is because the LDD regions may have an increased resistance as compared to the more heavily doped regions of the layer <b>206</b>. Accordingly, in many embodiments, the extension <b>250</b> may include the lightly doped regions <b>252</b>, <b>254</b> spaced apart from one another by one or more heavily doped or spacing regions <b>256</b>, <b>258</b> formed of the silicon layer <b>206</b>. In these embodiments, the TFT <b>200</b> may maintain a required level of conductivity and act to reduce the lateral electric field and thus current leakage.

In some embodiments, the first lightly doped region <b>252</b> may have a length L and the second lightly doped region <b>254</b> may have a length L<b>0</b>. The lengths L and L<b>0</b> may range from 1 to 4 microns, depending on the desired application for the TFT <b>200</b>. For example, if the TFT <b>200</b> is used in a display screen, the total length LT of the extension <b>250</b>, and thus the lightly doped regions L and L<b>0</b>, may depend on the desired resolution of the screen. The better the resolution, the shorter the extension length LT. However, even with relatively high resolutions, the extension <b>250</b> may still be a sufficient length to provide a sufficient reduction in the lateral electric field to reduce current leakage. In some embodiments, this length may range between 3 μm to 30 μm. Additionally, as will be discussed in more detail below, the lengths the various lightly doped regions may vary as compared to each other.

It should be noted that the lightly doped regions, which may be LDD slots, may be formed in the same mask as the n-type doping. Accordingly, the manufacturing process for the TFT <b>200</b> may be similar to conventional manufacturing processes, except that the length of the silicon layer may be extended to include the extension, and additional portions of LDD or other doping regions may be applied.

With reference again to <figref idrefs="DRAWINGS">FIG. 3</figref>, the second leg <b>230</b> of the silicon layer <b>206</b> may be substantially similar to the second leg <b>130</b> of the TFT <b>100</b>. For example, the second leg <b>230</b> may include a source <b>205</b> (defined as the heavily doped end <b>230</b> and the lightly doped region <b>212</b> adjacent the metal branch) and a drain <b>207</b> (defined as the heavily doped region <b>226</b> and the lightly doped region <b>214</b>) that may be separated by a channel (not shown). The metal branch <b>218</b> may induce electrons to travel between the source <b>205</b> and drain <b>207</b> across the channel to create current flow. However, because the silicon layer <b>206</b> is formed with the extension member <b>250</b>, the reduction in the lateral electric field may also reduce current leakage across this gate <b>262</b> as well as the first gate junction <b>260</b>.

In some embodiments, the TFT <b>200</b> may include a lightly doped region that extends between the two gates <b>260</b>, <b>262</b>. <figref idrefs="DRAWINGS">FIG. 5</figref> is a simplified top view of an example of the TFT with a doped region extending between the first gate and the second gate. In this embodiment, a lightly doped region <b>270</b> may extend between the first electrode or branch <b>218</b> and the second electrode or branch <b>220</b> to form an intra-gate doped region. In this embodiment, the two drains <b>210</b>, <b>214</b> may be formed of a single lightly doped region, the lightly doped region <b>270</b>. This may provide an additional junction for the TFT <b>200</b> to further reduce the lateral electric field.

It should be noted that, in embodiments where the lightly doped region <b>270</b> extends between the two gates <b>260</b>, <b>262</b>, the TFT <b>200</b> may have an increased resistance through the silicon layer <b>206</b> and doping regions. Accordingly, in instances where a higher conductivity may be desired, embodiments such as the TFT illustrated in <figref idrefs="DRAWINGS">FIGS. 3 and 4</figref> may be preferred, as the series resistance of the two doped regions <b>208</b>, <b>210</b>, rather than the single resistive region of the lightly doped region <b>270</b>, may have a better conductivity.

In some instances, the number of the additional lightly doped regions may be increased and/or the length of the various lightly doped regions may be varied from one another. <figref idrefs="DRAWINGS">FIG. 6</figref> is a top simplified view of another example of a TFT <b>300</b>. In this example, an extension region <b>350</b> may include four lightly doped regions. A first lightly doped region <b>308</b> may form a portion of a source drain pair <b>308</b>, <b>310</b> communicatively coupled to the first metal branch <b>218</b>. The first lightly doped region <b>308</b> may have a length of L<b>1</b>. A second lightly doped region <b>352</b> may be spaced from the first lightly doped region <b>308</b> by a spacer <b>356</b> of heavily doped silicon, the second lightly doped region <b>352</b> may have a length of L<b>2</b>. A third lightly doped region <b>354</b> may be spaced from the second lightly doped region <b>352</b> by a spacer <b>358</b> and may have a length of L<b>3</b>. A fourth lightly doped region <b>355</b> may be spaced from the third doped region <b>354</b> by a spacer <b>361</b> and may have a length L<b>4</b>. Each of the spacers may be heavily doped regions of silicon, which may have an increased density of dopant agents compared to the lightly doped regions.

With reference to <figref idrefs="DRAWINGS">FIG. 6</figref>, in some embodiments, each of the lengths L<b>1</b>, L<b>2</b>, L<b>3</b>, and L<b>4</b> may be different from one another. As a first example, L<b>1</b> may be greater than L<b>2</b>, L<b>2</b> may be greater than L<b>3</b>, and L<b>3</b> may be greater than L<b>4</b>. In this manner, the length of the lightly doped regions on the silicon layer <b>206</b> may increase in length closer towards the channel <b>224</b>. As a non-limiting example, the first length L<b>1</b> may be approximately 4 microns, the second length L<b>2</b> may be approximately 3 microns, the third length L<b>3</b> may be approximately 2 microns and the fourth length L<b>4</b> may be 1 micron. However, it should be noted that the lengths L<b>1</b>, L<b>2</b>, L<b>3</b>, and L<b>4</b> may be selected based on the desired applications and characteristics of the TFT <b>300</b>, and the above listed examples are meant as illustrative only.

In some embodiments, one or more of the lengths L<b>1</b>, L<b>2</b>, L<b>3</b>, and L<b>4</b> may be the same as one another. In other embodiments, the lengths L<b>2</b>, L<b>3</b>, and/or L<b>4</b> may be varied from one another, but may not gradually increase in length. In some instances, the first lightly doped region <b>308</b> may provide the greatest reduction in the lateral electric field as compared to the other doped regions <b>352</b>, <b>354</b>, <b>355</b>. This is because the first lightly doped region <b>308</b> is adjacent to the channel <b>224</b> and may better reduce the electric field at the edge of the channel <b>224</b>. In these instances, the remaining lightly doped regions <b>352</b>, <b>354</b>, <b>355</b> may function to divide the lateral electric field, which then may allow the first region <b>308</b> to more easily reduce the electric field. Accordingly, the lengths L<b>2</b>, L<b>3</b>, and L<b>4</b> of the second through fourth lightly doped regions may be relatively small as compared to the first lightly doped region <b>308</b>, which may still reduce the overall electric field in the TFT <b>300</b>. The division of the electric field may be a relatively linear division, accordingly in some instances three lightly doped regions on the extension <b>250</b> may be sufficient to substantially reduce the electric field; however, additional lightly doped regions may also further reduce the electric field.

The spacers <b>356</b>, <b>358</b>, <b>361</b> are heavily doped portions of the poly-silicon or other silicon layer and may separate the lightly doped regions. The length of the spacers <b>356</b>, <b>358</b>, <b>361</b> may be modified to match the lengths of the lightly doped regions, may be different from the lightly doped regions, and/or may be constant or varied across the length of the extension <b>350</b>. For example, as shown in <figref idrefs="DRAWINGS">FIG. 6</figref>, the spacers may have relatively the same length, whereas the length of the lightly doped regions may vary. However other variations are also envisioned.

The TFT <b>300</b> of <figref idrefs="DRAWINGS">FIG. 6</figref> may further include a lightly doped region <b>370</b> that may extend between the two gates <b>360</b>, <b>362</b>. <figref idrefs="DRAWINGS">FIG. 7</figref> is a top plan view of the TFT <b>300</b> of <figref idrefs="DRAWINGS">FIG. 6</figref>, with a lightly doped region <b>370</b> extending between the first gate <b>360</b> and the second gate <b>362</b>. As with <figref idrefs="DRAWINGS">FIG. 5</figref>, in this embodiment, the TFT <b>300</b> may include an additional junction, which may further reduce the electric field but may increase the resistance of the TFT.

Single Gate TFT

In some embodiments, the TFT may have only a single gate, e.g., only one metal or conductive branch. <figref idrefs="DRAWINGS">FIG. 8</figref> is a top plan view of a single gate TFT including additionally doped regions. The TFT <b>400</b> may include a metal branch <b>418</b> that may divide a silicon layer <b>406</b> into a source portion <b>401</b> and a drain portion <b>403</b>. It should be noted that although the different portions <b>401</b>, <b>403</b> are discussed herein as being either the source or drain, the actual source and drain may be positioned on either side of the branch or otherwise oriented. Further, the different examples discussed below may be implemented on either the source or drain side of the TFT. Accordingly, the discussion of a particular structure being on the drain or source side of the branch is illustrative only and not meant to be limiting.

With reference to <figref idrefs="DRAWINGS">FIG. 8</figref>, the source portion <b>401</b> may include an extension <b>450</b> which may include additionally lightly doped regions <b>452</b>, <b>454</b> that may be separated by one or more spacers <b>456</b>, <b>458</b> (which may be heavily doped regions). The first or upper lightly doped region <b>408</b> may form partial portion of the source <b>401</b> for the TFT <b>400</b>, and one or more electrons may travel across the channel (not shown) to the drain <b>403</b>. The additionally lightly doped regions <b>452</b>, <b>454</b> and may be formed as LDD structures, and the spacers <b>456</b>, <b>458</b> may be heavily doped regions of the silicon layer <b>406</b>. The second lightly doped region <b>454</b> may be located adjacent to an end <b>432</b> of the silicon layer <b>406</b>. As will be discussed below, the lightly doped region <b>408</b> adjacent the channel <b>408</b> and/or the additional lightly doped regions <b>452</b>, <b>454</b> may have the same lengths or varying lengths from each other. However, as shown in <figref idrefs="DRAWINGS">FIG. 8</figref>, in this embodiment, each of the lightly doped regions <b>408</b>, <b>452</b>, <b>454</b> may have approximately the same length as each other.

With continued reference to <figref idrefs="DRAWINGS">FIG. 8</figref>, the drain portion <b>403</b>, may include a lightly doped region <b>470</b> and heavily doped region <b>430</b> forming the drain. The lightly doped region <b>470</b> in this example may form a “L” shape as it transitions from a location adjacent to the channel (not shown) to the end <b>430</b> of the silicon layer <b>406</b>. The lightly doped region <b>470</b>, however, may terminate prior to the end <b>430</b> of the layer <b>406</b>. In other words, the doped region <b>470</b> may form a substantially continuously lightly doped region along the drain side of the silicon layer <b>406</b>.

In another example, the TFT <b>400</b> may include additional lightly doped layers that gradually increase in length from the end <b>430</b> towards the branch <b>418</b>. <figref idrefs="DRAWINGS">FIG. 9</figref> is a top plan view of a single gate TFT having additionally lightly doped regions with varying lengths. With reference to <figref idrefs="DRAWINGS">FIG. 9</figref>, the TFT <b>400</b> may include the first lightly doped region <b>408</b>, a second lightly doped region <b>452</b>, a third lightly doped region <b>454</b>, and a fourth lightly doped region <b>455</b>. Each of the lightly doped regions <b>408</b>, <b>452</b>, <b>455</b>, <b>455</b> may have a length that may be different than the adjacent lightly doped region. In one instance, the length of the lightly doped regions may increase from the end <b>432</b> towards the branch <b>418</b>, such that the first lightly doped region <b>408</b> may have the longest length, the second lightly doped region <b>452</b> may have the next longest length, the third lightly doped region <b>454</b> may have the third largest length, and the fourth lightly doped region <b>455</b> may have the shortest length. However, the lengths of the lightly doped regions may be otherwise varied, e.g., they may decrease in length from the end <b>432</b> towards the branch <b>410</b>, or may have random lengths along a length of the extension <b>450</b>.

With continued reference to <figref idrefs="DRAWINGS">FIG. 9</figref>, similar to <figref idrefs="DRAWINGS">FIG. 8</figref>, in the TFT <b>400</b> the drain side of the silicon layer <b>406</b> may include the lightly doped region <b>470</b> that may extend along a substantial length of the drain portion <b>403</b>.

In yet other embodiments, the drain side <b>403</b> of the TFT <b>400</b> may include varying portions of lightly doped regions. <figref idrefs="DRAWINGS">FIG. 10</figref> is a top plan view of a single gate TFT including multiple lightly doped regions on either side of the branch. In this example, the extension <b>450</b> portion of the TFT <b>400</b> may be substantially similar to the extension portion <b>450</b> of the TFT illustrated in <figref idrefs="DRAWINGS">FIG. 9</figref>. In other words, the TFT <b>400</b> may include multiple lightly doped regions on the source side of the silicon layer <b>406</b> that vary in length from the end <b>432</b> towards the branch <b>418</b>. However, in this example, the TFT <b>400</b> may further include a drain lightly doped region <b>410</b> as well as a first additional lightly doped region <b>440</b> and a second lightly doped region <b>442</b>. The two lightly doped regions <b>440</b>, <b>442</b> may have the same length or varying lengths (see <figref idrefs="DRAWINGS">FIG. 11</figref>). In these embodiments, the additional doped regions <b>440</b>, <b>442</b> may also be LDD structures and may help to reduce the lateral field, while not significantly reducing the conductivity of the silicon layer <b>406</b>. For example, the drain region <b>403</b> illustrated in <figref idrefs="DRAWINGS">FIG. 8</figref> includes a single lightly doped region that has a long length, and may therefore have an increased resistance as compared to the TFT <b>400</b> of <figref idrefs="DRAWINGS">FIG. 10</figref> where the lightly doped regions are separated by heavily doped regions of the silicon <b>406</b>.

In some embodiments, the <b>410</b> may have a first length, the first additional lightly doped region <b>440</b> may have a second length, and the third lightly doped region <b>442</b> may have a third length, where the first length, the second length, and the third length may be different from each other. As one example, the lengths of the lightly doped regions <b>410</b>, <b>440</b>, <b>442</b> may decrease the farther they are from the branch <b>418</b>. As discussed above, this is because in many instances the lightly doped region closest to the channel may have the largest effect on the reduction of the electric field, and so keeping the other regions smaller may reduce the resistance of the silicon layer <b>406</b>, while still dividing the electric field.

With continued reference to <figref idrefs="DRAWINGS">FIG. 10</figref>, the drain <b>410</b> may be separated from the first additional lightly doped region <b>440</b> by a spacer <b>439</b>. Depending on the desired shape of the TFT <b>400</b>, the spacer <b>439</b> as shown in <figref idrefs="DRAWINGS">FIG. 10</figref> may form a corner or elbow so that the drain portion <b>403</b> of the TFT <b>400</b> may have a “L” shape as it transitions away from the branch <b>418</b> towards the end portion. In this example, both sides of the channel (not shown) may have regions that may act to reduce the lateral electric field of the silicon layer <b>406</b>, without substantially increasing the resistance of the TFT, as the spacer may be formed of a heavily doped silicon material.

In yet other examples, the TFT may include additional lightly doped regions on either side of the channel, where each lightly doped region has approximately the same length. <figref idrefs="DRAWINGS">FIG. 11</figref> is a top plan view of a single gate TFT including lightly doped regions having approximately the same length. In this example, the source portion <b>401</b> may include the three lightly doped regions <b>408</b>, <b>452</b>, <b>454</b> that may each have approximately the same length and be separated by a first spacer <b>456</b> and a second spacer <b>458</b>, each having approximately the same length. The drain portion <b>403</b> may include three lightly doped regions <b>410</b>, <b>440</b>, <b>442</b> each having approximately the same length, and being separated by a first spacer <b>439</b> and a second spacer <b>437</b>. In these instances, the second doped region <b>440</b> on the drain portion <b>403</b> may form the elbow for the silicon layer <b>406</b>, whereas the spacer <b>439</b> or heavily portion between the drain <b>410</b> and the other doped region <b>440</b> may have a reduced length. However, in other embodiments, the lengths of the spacer and/or doped regions may be differently configured.

In some embodiments, a first side of the metal branch <b>418</b> may have lightly doped regions with different lengths and a second side of the branch <b>418</b> may have lightly doped regions with the same length. <figref idrefs="DRAWINGS">FIG. 12</figref> is a top plan view of a single gate TFT including a first side <b>401</b> having lightly doped regions with varying lengths and a second side <b>403</b> having lightly doped regions with the same length. In this example, the first side <b>401</b>, which may be the source side or the drain side, may include an additional lightly doped region compared to the second side <b>403</b>. However, in other embodiments, the second side <b>403</b> may include more lightly doped regions than the first side.

It should be noted that the above examples for the single gate TFTs may be combined with each other or otherwise varied. Additionally, although the examples may be discussed with respect to a “source” side and a “drain” side, the two sides and/or structures may be reversed depending on the implementation of the TFT. Moreover, although the above examples are discussed with respect to single gate TFTs, depending on the space available in a particular structure or device incorporating the TFT, the examples may also be incorporated into double gate TFTs.

CONCLUSION

The foregoing description has broad application. For example, while examples disclosed herein may focus on thin film transistors, it should be appreciated that the concepts disclosed herein may equally apply to substantially any other type of transistor or semiconductor device. Similarly, although the input device and TFTs may be discussed with respect to display screens and devices, the devices and techniques disclosed herein are equally applicable to other types of applications including transistors, such as TFTs. Accordingly, the discussion of any embodiment is meant only to be exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples.