Systems and methods for handling data rate changes within a packet or frame

BACKGROUND

1. Field of the Invention

This disclosure relates to telecommunications, and, more particularly, to systems and methods for handling data rate changes within a packet or frame.

2. Description of the Related Art

A wireless network is a type of telecommunications network whose interconnections are implemented using radio-frequency (RF) signals. In these systems, transfer of information is typically accomplished through a modulation process. At a transmitter, a modulator combines a data signal with a carrier wave and the resulting modulated signal is transmitted. Then, at a receiver, an RF stage detects the modulated signal and a demodulator extracts the data signal from the carrier wave.

The modulation process works by modifying the amplitude, frequency, and/or phase of the carrier wave as a function of the data signal. Certain modulation schemes (M-ary modulation) may use orthogonal waveforms to communicate two or more bits at once (i.e., as a single “symbol”), which effectively results in higher data rates. For example, a 4-FSK modulation scheme (i.e., a 4-level scheme) is capable of communicating two bits at once (i.e., a two-bit symbol). Meanwhile, an 8-FSK scheme (i.e., an 8-level scheme) is capable of communicating three bits at once (i.e., a three-bit symbol). Therefore, under similar conditions, a signal transmitted with an 8-FSK scheme has a higher data rate than a signal transmitted with a 4-FSK scheme. However, changing the modulation scheme during the course of a transmission typically requires an expensive resynchronization process.

SUMMARY

Systems and methods for handling data rate changes within a packet or frame are described. In an embodiment, a system may include a radio frequency (RF) circuit operable to receive a message having a plurality of segments, including a first segment that is modulated according to a first modulation data rate. The system may also include a demodulator circuit coupled to the RF circuit and operable to demodulate the first segment into a first demodulated segment having a demodulation data rate, wherein the demodulation data rate is greater than the first modulation data rate. The system may further include a de-mapper circuit coupled to the demodulator circuit and operable to convert the first demodulated segment into a first converted segment having the first modulation data rate.

According to an embodiment, an apparatus may include a demodulator operable to receive a message modulated at least in part with a first modulation data rate and to output a demodulated message having a demodulation data rate, wherein the first modulation data rate is different from the demodulation data rate. The apparatus may also include a de-mapper operable to receive the demodulated message and convert a first portion of the demodulated message into a first converted portion having the first modulation data rate.

According to an embodiment, a method may include the actions of receiving a first message having a first portion modulated with N levels, demodulating the first portion into a first demodulated portion having M levels, where M and N are integers and M is an even multiple of N, and converting the first demodulated portion into a first converted portion having N levels.

BRIEF DESCRIPTION OF THE DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1A</figref> is a simplified block diagram illustrating an example embodiment of a communications device.

<figref idrefs="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating an example embodiment of an RF receiver.

<figref idrefs="DRAWINGS">FIGS. 2A and 2B</figref> are diagrams illustrating example embodiments of messages.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a diagram illustrating an example of a sequence of messages.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a flowchart of an example embodiment of a method for handling data rate changes within a packet or frame.

<figref idrefs="DRAWINGS">FIG. 5</figref> is an example of a de-mapper conversion table.

While being susceptible to various modifications and alternative forms, specific embodiments discussed in this specification are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the disclosure to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

DETAILED DESCRIPTION

In the paragraphs that follow, various systems and methods for handling data rate changes within a message (e.g., a packet, frame, or the like) are described. One aspect of the specification relates to a communications device configured to handle data rate changes within a message. This particular communications device is described as a mobile phone for illustration purposes; however, it should be understood the principles described below are equally applicable to any other device with wireless communications capabilities, including, for example, computers, tablets, modems, routers, repeaters, bridges, media players, portable devices, televisions, etc. Another aspect of specification relates to an RF receiver configured to implement methods for handling data rate changes within a message. Although the RF receiver is indicated as a component of a mobile phone, it may be used in any other suitable wireless device. Another aspect of the specification relates to various modes of operation of a demodulator and a de-mapper that enable certain methods for handling data rate changes within a message.

<figref idrefs="DRAWINGS">FIG. 1A</figref> is a simplified block diagram of communications device <b>100</b> according to certain embodiments. As illustrated here, communications device <b>100</b> may be a mobile phone or the like. Microcontroller (MCU) <b>105</b> interfaces with display <b>110</b>, memory <b>115</b>, audio processor <b>120</b>, and radio-frequency (RF) transceiver <b>125</b>. RF antenna <b>130</b> is coupled to RF transceiver <b>125</b>. In some embodiments, an inter-integrated (“I²C”) bus may be employed to connect two or more of these components, although any other suitable bus may be used. When inter-component interfaces are implemented as a I²C bus, for example, the bus may use two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock (SCL). A separate line may be used for synchronization purposes, for example, to prevent interference and/or share resources within device <b>100</b>.

Typically, MCU <b>105</b> may receive system power (“V_BAT”) through a voltage regulator or the like (not shown). And in some embodiments, MCU <b>105</b> may be configured to manage power provided to other system components. When powered off, components <b>110</b>, <b>115</b>, <b>120</b>, and/or <b>125</b> may not load the shared bus, thus allowing MCU <b>105</b> and/or other components to use the bus.

In some cases, MCU <b>105</b> may be a low-power programmable controller, microcontroller, processor, microprocessor, field-programmable gate array (“FPGA”), or any other suitable control circuit. For example, MCU <b>105</b> may include one or more of integrated random-access memory (“RAM”), read-only memory (“ROM”), flash memory (or other non-volatile memory generally), one-time programmable (“OTP”) circuitry, analog-to-digital converters (“ADCs”), digital-to-analog-converters (“DACs”), counters, timers, input/output (“I/O”) circuitry and controllers, reference circuitry, clock and timing circuitry (including distribution circuitry), arithmetic circuitry (e.g., adders, subtractors, multipliers, dividers), general and programmable logic circuitry, power regulators, or the like.

Instructions stored by memory <b>115</b>, may be executable by MCU <b>105</b> to perform the various operations specified by the instructions. For example MCU <b>105</b> may include any processor capable of executing instructions. For example, the processor may be a general-purpose processor, an embedded processor, a digital signal processor (DSP), or any other suitable type of processor that implements any suitable instruction set architecture (ISA), such as, for example, one or more of the x86, ARM™, PowerPC™, SPARC™, or MIPS™ ISAs. In some embodiments, the processor may be integrated with a dedicated storage medium and/or other elements as part of an ASIC, microcontroller, or other integrated circuit structure.

Memory <b>115</b> represents an embodiment of a computer-accessible or computer-readable storage medium configured to store program instructions and data. Program instructions and/or data may be stored upon different types of computer-accessible media. In general, a computer-accessible medium or storage medium may include any type of mass storage media or memory media such as magnetic or optical media. A computer-accessible medium or storage medium may also include any volatile or non-volatile media such as RAM (e.g., SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, or the like, whether included in MCU <b>105</b> as system memory <b>155</b> or another type of memory. Program instructions and data stored via a computer-accessible medium may be transmitted by transmission media or signals such as electrical, electromagnetic, or digital signals, which may be conveyed via a communication medium such as a network and/or a wireless link, such as may be implemented via any suitable interface.

In some embodiments, display <b>110</b> may include a liquid crystal display (LCD) or an organic light emitting diode (OLED) display; although any other display device may be used. Display <b>110</b> may also include a controller that receives commands from MCU <b>105</b> and display images to a user on an LCD or other type of screen. These images may contain graphics or other information that allow a user to interact with device <b>100</b>. In some embodiments, display <b>110</b> may further include a touch screen controller that allows a user to enter commands directly through display <b>110</b>.

Audio processor <b>120</b> may include a digital signal processor (DSP) or the like with ADCs and DACs that are configured to receive and provide audio content to a user. Moreover, audio processor <b>120</b> may be connected to one or more speakers and/or a microphone (not shown) to allow the user to participate in a phone call, listen to an audio file, record an audio message, etc.

In some embodiments, RF transceiver <b>125</b> may include an RF transmitter, an RF receiver, and an RF switch to allow full-duplex communications. In operation, the transmitter portion of RF transceiver <b>125</b> transmits voice and/or data to another wireless device (e.g., a modem, base station, etc.) using RF antenna <b>130</b>. In some cases, RF antenna <b>130</b> may be implemented as an antenna array comprising two or more antenna elements or the like. Meanwhile, an RF switch allows the RF receiver portion of RF transceiver <b>125</b> to receive voice and/or data from other wireless devices through RF antenna <b>130</b>. The receiver portion of RF transceiver <b>125</b> is described in more detail in the following section.

In the illustrated embodiment, components <b>105</b>, <b>110</b>, <b>115</b>, <b>120</b>, and <b>125</b> are shown as separate components of device <b>100</b>. In alternative embodiments, however, two or more of components <b>105</b>, <b>110</b>, <b>115</b>, <b>120</b>, and <b>125</b> may be integrated, for example, in a single chip or microchip. In some cases, integrating components may improve the overall performance of device <b>100</b> in one or more ways such as, for example, flexibility, responsiveness, die area, cost, materials used, efficiency, accuracy, power consumption, reliability, robustness, etc. In other cases, any of components <b>105</b>, <b>110</b>, <b>115</b>, <b>120</b>, and <b>125</b> may be split into two or more discrete circuits to achieve other goals. For example, RF transceiver <b>125</b> may be split into separate transmitter and receiver circuits to reduce interference. Additionally, MCU <b>105</b> may be split into two or more individual processors to more effectively perform certain functions.

<figref idrefs="DRAWINGS">FIG. 1B</figref> is a block diagram illustrating RF receiver <b>135</b> configured to implement methods for handling data rate changes within a message. In some embodiments, RF receiver <b>135</b> may be employed as part of RF transceiver <b>125</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>. As illustrated here, RF antenna <b>130</b> is connected to RF stage <b>145</b>, and RF stage <b>145</b> is connected to demodulator <b>155</b>. De-mapper <b>165</b> is connected to demodulator <b>155</b> and to MCU <b>105</b> (not shown).

Antenna <b>130</b> may be any RF antenna suitable for picking up RF signal <b>140</b>. Meanwhile, RF circuit or stage <b>145</b> may be any circuit configured to convert RF signal <b>140</b> into intermediate frequency (IF) signal <b>150</b>. To that end, RF stage <b>145</b> may include one or more amplifiers, oscillators, mixers, filters, and the like. Demodulator <b>155</b> is a circuit configured to extract data or symbols from one or more carrier waves in IF signal <b>150</b> and produce demodulated signal <b>160</b>.

In some embodiments, demodulator <b>155</b> may be an analog or digital device including filters, comparators, dividers, timers, etc. In other embodiments, demodulator <b>155</b> may be programmable. For example, demodulator <b>155</b> may include one or more circuits (e.g., a DSP or the like) that may implement a demodulation algorithm in software. Software instructions may be stored within demodulator <b>155</b> and/or external memory such as memory <b>115</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>.

De-mapper <b>165</b> is a circuit configured to process symbols of demodulated signal <b>160</b> and produce de-mapped signal <b>170</b>. For example, de-mapper <b>165</b> may be a logic circuit, controller, processor, or a programmable circuit suitable for applying conversion instructions to demodulated signal <b>160</b>. In some embodiments, de-mapper may have its own memory <b>175</b> configured to store software instructions, mathematical formulas, and/or look-up tables. In other embodiments, however, these instructions, formulas, and/or look-up tables may be stored in external memory such as, for example, memory <b>115</b> of <figref idrefs="DRAWINGS">FIG. 1</figref>.

De-mapped signal <b>170</b> may include de-mapped symbols that may then be output, for example, to MCU <b>105</b> for further processing. Although as illustrated de-mapper circuit <b>165</b> is shown as part of RF receiver <b>135</b>, in alternative embodiments de-mapper <b>165</b> may be a part of MCU <b>105</b>, or other circuit arrangements may be used.

Typically, at a transmitter end, digital data to be communicated to RF receiver <b>135</b> may be formatted into one or more messages (e.g., “packets” or “frames”). Generally speaking, a “packet” includes a header and a payload. The header portion of the packet includes control information that allows a communications network to properly deliver the packet to a particular device (e.g., device <b>100</b> of <figref idrefs="DRAWINGS">FIG. 1A</figref>), whereas the payload includes actual user data desired to be transmitted. A popular example of a packet is the IP packet used across the Internet and other networks. Meanwhile, a “frame” contains one or more packets as well as some additional synchronization information. This formatting process may follow any appropriate protocol or procedure, such as Internet Protocol version 4 (IPv4) or the like.

Once formatted, a digital signal containing these messages may be modulated with one or more carrier waves. Examples of modulation schemes include M-ary frequency-shift keying (FSK), Gaussian frequency-shift keying (GFSK), amplitude shift-keying (ASK), etc. In some embodiments, the digital signal may be modulated with orthogonal waveforms that communicate two or more bits as a single symbol. For example, a 4-FSK modulation scheme communicates a two-bit symbol, whereas an 8-FSK scheme conveys a three-bit symbol.

Moreover, some communication methods may allow signals to be transmitted with different modulation levels or data rates. For instance, a single protocol may allow RF signal <b>140</b> to be modulated with two levels (e.g., 2-FSK), four levels (e.g., 4-FSK), and/or eight levels (e.g., 8-FSK). These modulation schemes may be allowed to change over time. For example, a particular communication or connection may be initiated using 2-FSK modulation. If the connection is determined to be of high quality—e.g., because a signal strength measure or signal-to-noise ratio meets a threshold value—then the transmitter may increase the modulation to a higher level (e.g., 4-FSK or 8-FSK). Conversely, if an ongoing connection is determined to be of low quality—e.g., noise increases during a call, etc.—then a communication being performed using 4-FSK modulation may be downgraded to 2-FSK modulation.

Referring back to <figref idrefs="DRAWINGS">FIG. 1B</figref>, the resulting modulated signal may be transmitted to RF receiver <b>135</b> (e.g., over the air), detected as RF signal <b>140</b> by antenna <b>130</b>, and converted into IF signal <b>150</b> by RF stage <b>145</b>. Demodulator <b>155</b> then demodulates the binary signal or messages encoded in IF signal <b>150</b> and outputs demodulated signal <b>160</b>.

In some applications, demodulation may be performed in “real time.” Therefore, the adoption of various modulation data rates in the course of a communication may require the use of various demodulators working in parallel; where each demodulator may be configured to operate at a different modulation data rate. This approach, however, causes the number of demodulation circuit components and the associated power requirements to increase. In addition, if the data rate change occurs within a single packet or frame, the system may require a complex resynchronization procedure and/or time-critical circuitry dedicated to avoiding such resynchronization. As described herein, however, some embodiments of the systems and methods described are capable of handling such data rate changes with a fewer number of demodulators, or even with a single demodulator.

To this end, in some embodiments, demodulator <b>155</b> may demodulate IF signal <b>150</b> using the highest modulation scheme available under a given protocol. For instance, using the same example discussed above, if a hypothetical protocol allows RF signal <b>140</b> to be modulated with 2-FSK, 4-FSK, and 8-FSK, then demodulator <b>155</b> may demodulate the entire signal <b>150</b> using an 8-FSK demodulation scheme. In some embodiments, this demodulation operation may take place regardless of the actual data rate with which RF signal <b>140</b> (or a portion thereof) was originally modulated.

In some embodiments, a deviation ratio (in the case of multi-level FSK/GFSK) and/or a modulation depth ratio (in case of multi-level ASK) of a signal or message may be 2—e.g., it may include 4 and 2 level data rates. In other embodiments, the deviation and/or modulation depth ratios may be 4—e.g., it may include 8, 4, and 2 level data rates. In yet other embodiments, the symbol rate may be constant across some or all data rates within a message (e.g., packet or frame). For example, the number of symbols transmitted per unit of time may remain constant in some cases, although the number of bits encoded per symbol may vary.

For example, consider a situation employing the same hypothetical protocol where RF signal <b>140</b> can be modulated with 2-FSK, 4-FSK, or 8-FSK. Suppose that RF signal <b>140</b> encodes two packets, a first packet modulated with 2-FSK and a second packet modulated with 4-FSK. Instead of attempting to demodulate the first packet with a 2-FSK scheme and the second packet with a 4-FSK scheme, demodulator <b>155</b> may demodulate the entire IF signal <b>150</b> using 8-FSK. As another example, consider a case where RF signal <b>140</b> encodes a single packet, and the packet includes two segments (e.g., header and payload). Assume that a first segment (e.g., header) is modulated with 4-FSK and the second segment (e.g., payload) of the same packet is modulated with 8-FSK. Because the maximum available data rate under the hypothetical protocol is 8-FSK, demodulator <b>155</b> may still demodulate the entire packet using 8-FSK.

Once RF signal <b>140</b> is demodulated into demodulated signal <b>160</b>, de-mapper circuit <b>165</b> may process the symbols within demodulated signal <b>160</b> to produce de-mapped signal <b>170</b>. These additional operations are discussed below.

De-mapper <b>165</b> may receive demodulated signal <b>160</b> and produce de-mapped signal <b>170</b>. As described above, demodulated signal <b>160</b> may be demodulated with a data rate higher than the data rate at which RF signal <b>140</b> was modulated. Accordingly, in some embodiments, de-mapper <b>165</b> may convert or map a high-data rate symbol (i.e., a symbol demodulated with a higher demodulation data rate) into a low-data rate symbol (i.e., a symbol with a lower original modulation data rate).

In some embodiments, demodulated signal <b>160</b> may include one or more messages. For sake of illustration, <figref idrefs="DRAWINGS">FIG. 2A</figref> shows message <b>200</b> according to some embodiments. As illustrated, message <b>200</b> may be a packet or the like. Particularly, packet <b>200</b> may have two segments—header <b>205</b> and payload <b>210</b>. Data rate indicator <b>215</b> may be within header <b>205</b>. In other configurations, however, data rate indicator may be located elsewhere (e.g., immediately before header <b>205</b>, within payload <b>210</b>, etc.). In some embodiments, date rate indicator <b>215</b> may be one or more bits, codes, or symbols that contain information about the modulation data rate of payload <b>210</b> (or any subsequent message portion or segment). For example, header <b>205</b> may be modulated with a first modulation data rate, payload <b>210</b> may be modulated with a second modulation data rate, and the first modulation data rate may be different from the second modulation data rate. In this case, data rate indicator <b>215</b> may contain information regarding the second modulation data rate.

Message <b>220</b> of <figref idrefs="DRAWINGS">FIG. 2B</figref> may be one or more packets, one or more frames, or any other message. As illustrated, message <b>220</b> includes two data rate indicators <b>225</b> and <b>230</b>. Accordingly, in this particular embodiment, message <b>220</b> may have three modulation data rates—i.e., an initial modulation data rate corresponding to the segment to the left of data rate indicator <b>225</b>, a second modulation data rate corresponding to the segment between data rate indicators <b>225</b> and <b>230</b>, and a third modulation data rate corresponding to the segment to the right of data rate indicator <b>230</b>. It should be understood, however, that any number of data rate indicators may be used in any message, and these indicators may be located anywhere within the message.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a diagram illustrating a sequence of messages <b>300</b> according to certain embodiments. For example, this sequence of messages may be a data stream <b>300</b> within demodulated signal <b>160</b>. As illustrated, data stream <b>300</b> includes at least three messages <b>305</b>, <b>310</b>, and <b>315</b>. First message <b>305</b> may be a packet or frame having a header modulated with a first modulation level. Data rate indicator <b>320</b> may contain information indicating that subsequent data within the same message is modulated with a second modulation level. Second message <b>310</b> does not include a data rate indicator, so it may be understood that it is modulated with the same data rate indicated in the preceding indicator—i.e., data rate indicator <b>320</b>. The header of third message <b>315</b> is also modulated with that same data rate; however, data rate indicator <b>325</b> indicates that the remainder of message <b>315</b> is modulated with a third modulation data rate.

Data stream <b>300</b> may be explained, for example, by any number of hypothetical scenarios. For example, assume that message <b>305</b> is the first message received in the communication. Under a given communication protocol, at least a portion of that first message may be encoded using a pre-determined modulation data rate (e.g., 2-FSK). After that, however, a second portion of the message may be modulated using a higher modulation data rate (e.g., 16-FSK). Accordingly, data rate indicator <b>320</b> may provide information that allows a receiver to determine that, from that point forward, data is modulated using the higher rate. In some embodiments, a data rate indicator indicates that the very next symbol was modulated with a different data rate. In other embodiments, a data rate indicator may inform that the actual data rate change will take place a number of symbols down the stream.

Now assume that, after second message <b>310</b> is received, the system detects that the 16-FSK modulation data rate is not fully supported or yields unsatisfactory signal quality. Upon this determination, data rate indicator <b>325</b> may inform, for example, that the remainder of message <b>315</b> is modulated using a lower modulation data rate (e.g., 8 or 4-FSK). In other words, as the communications system adapts to new conditions and modifies the rate of modulation or transmission of the signal or message, a corresponding data rate indicator may be provided within a signal or message. It should be emphasized that this example is provide as an illustration only, and that that many variations are possible.

With reference to <figref idrefs="DRAWINGS">FIG. 4</figref> a flowchart of a method for handling data rate changes within a packet or frame is depicted according to certain embodiments. At <b>405</b>, demodulator <b>155</b> receives a data stream within IF signal <b>150</b>. At <b>410</b>, demodulator <b>155</b> demodulates the data stream using a demodulation scheme based on M levels. In some embodiments, M is a power of 2 (e.g., 2, 4, 8, 16, 32, 64, etc.), such that each symbol contains log₂M bits. When M is different from the number of levels N of the message being processed, de-mapper <b>165</b> may convert M-level symbols to N-level symbols at <b>415</b>. In some embodiments, M may be an even multiple (i.e., an even number that is a multiple) of N. Accordingly, the conversion process may involve mapping an element having log₂M bits into a converted element having log₂N bits.

At <b>420</b>, de-mapper <b>165</b> may determine whether the message being processed contains a data rate indicator. If not, then de-mapper <b>165</b> may continue the same operation on subsequent symbols received in the data stream. On the other hand, if de-mapper <b>165</b> detects data rate indicator showing that a subsequent message segment is modulated with P levels, then de-mapper <b>165</b> may modify the conversion operation to output P-level symbols. Although in this example the data rate indicator is detected by de-mapper <b>165</b>, this functionality may be provided by any other system component that is, for example, capable of performing packet inspection.

Turning now to <figref idrefs="DRAWINGS">FIG. 5</figref>, illustrative de-mapper conversion table <b>500</b> is shown according to certain embodiments. The conversion operation is illustrated in a table format ease of understanding; however, it should be understood that similar operations may be implemented using mathematical formulas, programming instructions or rules, etc. Furthermore, this specific table is applicable for a system where 2 level, 4 level, and 8 level modulation schemes are used. However, it should be understood that, in other situations, other tables having more or less levels may be similarly built.

As illustrated, the left column of table <b>500</b> shows the output of demodulator <b>155</b> as three-bit symbols (e.g., 000, 001, 011, etc.). This indicates that, in this example (i.e., a system with 2 level, 4 level, and 8 level possible modulation schemes), demodulator <b>155</b> normally operates at its maximum data rate of three bits per symbol—i.e., an eight-level modulation scheme such as 8-FSK, or the like. Meanwhile, the top row of table <b>500</b> shows a de-mapping conversion of the demodulated three-bit symbols (e.g., 8-FSK) into one-bit symbols (e.g., 2-FSK) and two-bit symbols (e.g., 4-FSK). Although depicted here for clarity purposes, in other implementations, the last column of table <b>500</b> (showing a 1:1 conversion of three-bit symbols into the same three-bit symbols) may be omitted.

It should be noted that the values on the far left column of table <b>500</b> (output of demodulator <b>155</b>) are ordered following a Gray code, such that two successive values differ by one bit. In some embodiments, it has been determined that the use of Gray coding may make the de-mapping process less susceptible to noise and/or spurious output. However, in other embodiments, alternatives to Gray coding may be used.

As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, a message or segment thereof may include a symbol demodulated with M=8. If a data rate indicator indicates that the message or segment was in fact modulated with N=2, for example, then de-mapper <b>165</b> may transform the symbol from a 3-bit representation to a 1-bit representation. For example, a 010 symbol may be converted to a 1, and a 111 symbol may be converted to a 0. On the other hand, if another data rate indicator indicates that another message or segment was modulated with N=4, then de-mapper <b>165</b> may transform the symbol from a 3-bit representation to a 2-bit representation. For example, the 010 symbol may be converted to a 01, and the 111 symbol may be converted to a 11. Finally, if the data rate indicator indicates that the message or segment was modulated with N=8, then de-mapper <b>165</b> may output the incoming symbol in demodulated signal <b>160</b> as signal <b>170</b> without further processing (or it may perform a 1:1 conversion).

As described above, some embodiments of the systems and methods described herein allow a de-mapping process to be executed the time-critical demodulation process. In some instances, these systems and methods enable handling of data rate changes within a packet or frame while avoiding the need for resynchronization and without the use of complex and time-critical circuitry. Further, these embodiments reduce the number of gates and power consumption of RF transceivers and communications devices.

Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to a person of ordinary skill in the art once the specification is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.