Method for programming a floating gate

PRIORITY ENTITLEMENT

0001This application is a continuation application of application Ser. No. 13/327,364 filed Dec. 15, 2011, which is a divisional application of application Ser. No. 12/363,232 filed Jan. 30, 2009, now U.S. Pat. No. 7,859,911, which claims priority to Provisional Patent Application Ser. No. 61/082,403 filed on Jul. 21, 2008, all of which are incorporated herein by reference in their entireties. This application and the parent applications have at least one common inventor.

TECHNICAL FIELD

0002The invention relates to low-current analog integrated circuitry. More particularly, the invention relates to microelectronic floating gate circuit architectures, systems, and methods for their programming and operation.

BACKGROUND OF THE INVENTION

0003Programmable analog circuits are often required in applications where voltage accuracy and low power use are desirable traits.

0004Band gap reference voltage circuits are frequently used in applications that require a high degree of voltage accuracy. Band gap voltage reference circuits are known for their capabilities for providing excellent accuracy and stability over time and a range of operating temperatures. Unfortunately, however, band gap references are limited to a fixed voltage level, typically about 1.2V. The additional circuitry required for providing other voltage levels, such as fixed gain amplifiers for example, can be seriously detrimental to accuracy. Additionally, band gap voltage reference circuits generally draw a significant amount of power, presenting an additional problem in applications in which low power consumption is desirable.

0005Floating gate voltage reference circuits are often chosen for their low power requirements, but can be problematic in applications requiring a high degree of accuracy in providing a selected programmed voltage level, particularly over time and changes in temperature. A floating gate may be conceptualized as a charge oasis of conductive material electrically isolated from the outside world by a semiconductor substrate desert. The floating gate is capacitively coupled to the substrate or to other conductive layers. The floating gate is usually used to provide bias to the gate of a transistor and is readable without causing a significant leakage of charge. In theory, a floating gate programmed at a particular charge level remains at that level permanently, since the floating gate is insulated by the surrounding material. The floating gate is commonly charged using Fowler-Nordheim tunneling, or Channel Hot Carrier (CHC) tunneling, practices generally known to practitioners of the microelectronic arts. The accuracy of common floating gate circuits is limited for at least two primary reasons. Firstly, the potential on a floating gate decreases after it is programmed due to the capacitance inherent in the tunneling device. This voltage offset is well-defined and predictable, but is unavoidable in prior art floating gate voltage reference circuits because the capacitance of the tunneling device cannot be completely eliminated. Secondly, the accuracy of prior art floating gate voltage reference circuits is also hampered by the decay of the theoretically permanent charge on the floating gate over time. The decay of the charge over time occurs due to various factors, including the gradual escape of electrons from the tunneling device, and dielectric relaxation of the floating gate capacitors. The decay of charge is not entirely predictable since it can be influenced by environmental factors such as mechanical and thermal stress effects or other variables.

0006Due to these and other problems and potential problems, improved floating gate reference and feedback circuits would be useful and advantageous in the arts. Floating gate circuit architecture and associated methods adapted to rapid and accurate offset compensation would be particularly beneficial contributions to the art.

SUMMARY OF THE INVENTION

0007In carrying out the principles of the present invention, in accordance with preferred embodiments, the invention provides advances in the arts with novel methods directed to providing low-current floating gate architectures with offset mitigation capabilities and improved accuracy.

0008According to aspects of the invention, preferred embodiments of floating gate circuit methods use an iterative floating gate device and floating reference node programming technique for improved accuracy and stability.

0009According to one aspect of the invention, a preferred embodiment includes method steps for programming a floating gate circuit using a tunneling device and a floating reference node for iteratively programming an output with an offset-mitigating feedback loop.

0010According to another aspect of the invention, a preferred embodiment thereof includes the step of operating a suitably equipped circuit in a tunneling mode whereby charge is added to a tunneling device and conducted to a first op amp input such that the first op amp input voltage becomes equal with a second op amp input reference voltage. In a further step the op amp inputs are reversed for operating the op amp in a unity gain mode such that the output of the circuit is substantially equal to the reference voltage.

0011According to another aspect of the invention, a preferred embodiment thereof includes using the steps for programming a plurality of floating gates.

0012According to yet another aspect of the invention, a preferred embodiment includes the steps of monitoring the output of the circuit, and based on a comparison of the circuit output with a preselected tolerance threshold, selectably reiterating the tunneling mode step and the unity gain mode step using an incrementally changed reference voltage.

0013The invention has advantages including but not limited to providing one or more of the following features; improved accuracy, rapid programming, improved stability over a range of operating conditions, and efficient, ultra-low power requirements. These and other advantageous features and benefits of the present invention can be understood by one of ordinary skill in the arts upon careful consideration of the detailed description of representative embodiments of the invention in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0014The present invention will be more clearly understood from consideration of the following detailed description and drawings in which:

0015<figref idref="DRAWINGS">FIG. 1</figref> is a simplified schematic diagram depicting an example of a circuit useful for implementing the methods of the invention;

0016<figref idref="DRAWINGS">FIG. 2</figref> is schematic diagram of a preferred alternative embodiment of a circuit useful for implementing the invention;

0017<figref idref="DRAWINGS">FIG. 3</figref> depicts wave form examples illustrating the operation of the embodiments of the invention introduced with reference to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>; and

0018<figref idref="DRAWINGS">FIG. 4</figref> is a process flow diagram showing an alternative view of an example of steps in preferred methods of the invention;

0019<figref idref="DRAWINGS">FIG. 5</figref> is schematic diagram of a preferred alternative embodiment of a multiple floating gate programming circuit useful for implementing the invention; and

0020<figref idref="DRAWINGS">FIG. 6</figref> is schematic diagram of an example of an alternative embodiment of a floating gate programming circuit useful for implementing the invention.

0021References in the detailed description correspond to like references in the various drawings unless otherwise noted. Descriptive and directional terms used in the written description such as front, back, top, bottom, upper, side, et cetera, refer to the drawings themselves as laid out on the paper and not to physical limitations of the invention unless specifically noted. The drawings are not to scale, and some features of embodiments shown and discussed are simplified or amplified for illustrating principles and features, as well as anticipated and unanticipated advantages of the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

0022While the making and using of various exemplary embodiments of the invention are discussed herein, it should be appreciated that the present invention provides inventive concepts which can be embodied in a wide variety of specific contexts. It should be understood that the invention may be practiced with various electronic circuits, microelectronic circuit components, systems, system components, and subsystems without altering the principles of the invention. For purposes of clarity, detailed descriptions of functions, components, and systems familiar to those skilled in the applicable arts are not included. In general, the invention provides programmable analog voltage reference circuits for rapidly and accurately setting an output to a given selected voltage.

0023Now referring primarily to <figref idref="DRAWINGS">FIG. 1</figref>, the structure of an example of an embodiment of a programmable floating gate circuit <b>10</b> is shown in a simplified schematic, and its operation is described. An op amp <b>12</b> and a voltage level shifting device <b>15</b> are interconnected in a configuration in which a first switch SW<b>1</b> controls the output of the voltage level shifting device <b>15</b> to a tunneling device T<b>1</b>. A second switch SW<b>2</b> selectably connects the tunneling device T<b>1</b> to ground. A third switch SW<b>3</b> selectably completes a feedback loop <b>13</b> from the op amp output AMPOUTPUT to a second op amp input <b>12</b>B. A fourth switch SW<b>4</b> selectably connects a reference voltage VREF to the second op amp input <b>12</b>B as well. Note that the op amp output AMPOUTPUT is also preferably coupled to the input of the voltage level shifting device <b>15</b>. The first op amp input <b>12</b>A is connected at a junction referred to herein as a floating reference node <b>20</b>, denoting the connection among the op amp <b>12</b>, the tunneling device T<b>1</b>, and ground. The capacitance of the configuration is represented by C<b>0</b> between the reference node <b>20</b> and ground. A reverse input <b>12</b>C to the op amp <b>12</b> is provided for selectably reversing the polarity of the op amp, <b>12</b>.

0024The circuit arrangement shown in <figref idref="DRAWINGS">FIG. 1</figref>, and its functional equivalents, facilitates operation in two modes, tunneling mode, and unity gain mode, in the following manner. Assume for the sake of illustration that the potential of the floating reference node <b>20</b> is initially at zero volts. Further assume for the sake of illustration that the switches shown in <figref idref="DRAWINGS">FIG. 1</figref> are in the following initial states: SW<b>1</b> closed; SW<b>2</b> open; SW<b>3</b> open; SW<b>4</b> closed. It can be seen that a path is provided from the voltage level shifting device <b>15</b>, through SW<b>1</b>, to a floating gate at tunneling device T<b>1</b>. Accordingly, during programming the voltage at the tunneling device T<b>1</b> is raised to a level sufficient for Fowler-Nordheim tunneling to occur. As a result, voltage increases at the floating reference node <b>20</b>, initially causing the voltage at the first op amp input <b>12</b>A to rise. The closed state of SW<b>4</b> also applies reference voltage VREF to the second input <b>12</b>B of the op amp <b>12</b>. Gradually, the voltage at the floating reference node <b>20</b> becomes equal to VREF, the equal voltage at the op amp inputs <b>12</b>A and <b>12</b>B causes the op amp output AMPOUTPUT to decrease, in turn diminishing the input to the voltage level shifting device <b>15</b>, which causes a corresponding drop in the voltage at the tunneling device T<b>1</b>, halting the Fowler-Nordheim tunneling. The first and fourth switches SW<b>1</b>, SW<b>4</b>, then open, and switches two and three, SW<b>2</b>, SW<b>3</b>, close, placing feedback <b>13</b> on the second op amp input <b>12</b>B, while the selectable application of voltage at the reverse op amp input <b>12</b>C is preferably used to reverse the first <b>12</b>A and second <b>12</b>B inputs in order to cause the op amp <b>12</b> to operate as a unity gain voltage buffer. Thus, it can be seen that the circuit <b>10</b> has two operating states. A tunneling mode is used for adding charge to the tunneling device in order to bring the floating gate to a voltage level equal to, or nearly equal to, the floating reference voltage. A buffer mode is used to operate the op amp as a unity gain buffer maintaining the selected voltage level.

0025The AMPOUTPUT voltage is preferably monitored using suitable techniques known in the arts, and in the event a selected voltage level is not present within in acceptable tolerances, e.g., the AMPOUTPUT voltage is too low due to non-ideal behavior of the circuit, the process described above may be reiterated with the modification that the reference voltage VREF may be increased, which in turn results in an increased voltage at the floating reference node <b>20</b>, and ultimately increased voltage at AMPOUTPUT. Using the circuits and techniques of the invention, the AMPOUTPUT voltage can be rapidly adjusted to approach a selected value within precise tolerances by using successive iterations of the steps shown and described. The programmed floating gate may be erased to reset the circuit by raising the voltage at C<b>0</b>, energizing the trapped electrons in the floating gate to an energy level sufficient to enable them to escape.

0026Various implementations of the invention are possible, and all variations of potential embodiments cannot, and need not, be shown herein. Although specific exemplary embodiments using representative component parts are shown for the purposes of illustration, some elements of the circuit may be substituted without undue experimentation by those skilled in the arts. For instance, analog comparison devices such as analog to digital converter (ADC) devices or comparators may be used in place of op amps, level shifter topology may be implemented in various ways, and suitable modifications may be made to adapt the circuit for current, power, transconductance, or other inputs and/or outputs. The invention may be used, for example, in power systems, energy systems, portable electronics, battery and power supply management systems, and the like. An example of a preferred embodiment is shown in <figref idref="DRAWINGS">FIG. 2</figref>, providing a more detailed view of an implementation of the conceptual circuit <b>10</b> introduced in <figref idref="DRAWINGS">FIG. 1</figref>. A control signal P<b>1</b> is generated by a suitable voltage source (not shown) for controlling transistors M<b>0</b> and M<b>2</b>. Control signal P<b>2</b> is generated by a voltage source VOLTAGE<b>1</b> for controlling transistor M<b>1</b>. A voltage level shifting circuit <b>15</b> is implemented by the charge pump configuration formed by transistors M<b>0</b>, M<b>1</b> and M<b>2</b>. The voltage level shifting circuit <b>15</b> produces sufficient voltage to induce Fowler-Nordheim tunneling at tunneling device T<b>1</b>, placing a charge on the floating gate of the tunneling device T<b>1</b>. The tunneling device T<b>1</b> is connected to the first input <b>12</b>A of the op amp <b>12</b>. The second op amp input <b>12</b>B is connected directly to a reference voltage source VREF through transistor M<b>7</b>, controlled by a reference voltage control. A “DONE” signal may be asserted following the completion of a programming iteration using a suitable voltage source. Upon triggering by the DONE signal, the transistor M<b>3</b> selectably couples the tunneling device T<b>1</b> to ground, a signal at reverse input <b>12</b>C reverses op amp <b>12</b> polarity, and the feedback transistor M<b>3</b> places the op amp <b>12</b> in negative feedback mode, operating as a unity gain voltage buffer. The accompanying timing diagram at the bottom of <figref idref="DRAWINGS">FIG. 2</figref> illustrates the operation of the example of the embodiment of the circuit <b>10</b>. As shown, when P<b>1</b> is on, and tunneling at the tunneling device T<b>1</b> is caused to occur, P<b>2</b> is off, and vice versa, when p<b>1</b> is switched off, P<b>2</b> is switched on with the result that the DONE signal is activated, causing the op amp <b>12</b> to operate in unity gain mode.

0027The steps described may be reiterated one or more times as needed in order to approach the desired voltage level within a selected degree of accuracy, although it is believed that in general few iterations are required for most applications. It should be understood by those skilled in the arts that the circuit and components shown are representative of one example of an embodiment of the circuitry and methods of the invention for illustrative purposes and are not exclusive, restrictive, or limiting, as to the potential implementations and uses of the invention. For example, those skilled in the arts will appreciate that the floating gate circuit architecture and offset cancellation methods may be used in a wide variety of contexts for managing offsets of electronic signals such as voltage, current, impedance, and the like.

0028<figref idref="DRAWINGS">FIG. 3</figref> illustrates an example of the use of preferred embodiments of the apparatus and method of the invention as shown in and described with respect to <figref idref="DRAWINGS">FIG. 1</figref> and <figref idref="DRAWINGS">FIG. 2</figref>. Voltage waveforms are shown for voltages measured at AMPOUTPUT, FLOATINGREF (from floating node <b>20</b>), and VREF, plotted during the course of operation of the circuit <b>10</b>. The time span shown is divided into five segments for reference purposes. Referring to segment numeral <b>1</b>, it can be seen that VREF is initially 1.4V, a representative preselected value arbitrarily chosen for illustration purposes. It should be appreciated by those skilled in the arts that voltage levels shown and described are not restrictive, but are illustrative of typical voltages levels with which the invention may be used within the context of the microelectronics arts. The FLOATINGREF voltage can be seen to increase during segment <b>1</b> from an initial value near zero Volts to 1.4V at segment <b>2</b>. The output voltage AMPOUTPUT drops (segment <b>1</b>) from an initial value of about 5V, to about 4V when the floating reference voltage FLOATINGREF reaches a level equal to the reference voltage VREF, shown at reference numeral <b>2</b>. As shown where segment <b>2</b> meets segment <b>3</b>, when tunneling is stopped, the output AMPOUTPUT operates in unity gain mode, but due to non-ideal operation of the circuitry, e.g., capacitive coupling C<b>0</b> at the tunneling device T<b>1</b> (<figref idref="DRAWINGS">FIGS. 1 and 2</figref>), and possibly also due to switching inefficiencies, outputs 1.3V instead of the selected target voltage of 1.4V. Referring again to the trace for VREF, at segment <b>4</b>, the reference voltage is increased by 100 mV to compensate for the non-idealities of the circuit, and the steps are reiterated, in turn increasing FLOATINGREF to 1.5V, resulting in the output AMPOUTPUT shown at segment <b>5</b>, of 1.4V, and the circuit <b>10</b> is permitted to remain in unity gain mode. It should be understood that the values shown in this example are provided as an illustration of the operation of a preferred embodiment of the invention and are not exclusive or limiting. The invention may be practiced using a wide range of values as appropriate in a broad range of applications and contexts.

0029An alternative depiction of steps in methods of programming circuits using floating gate devices according to the invention is shown in <figref idref="DRAWINGS">FIG. 4</figref>. Shown in box <b>40</b>, in an initial state, the tunneling device is disconnected from ground, and the amplifier feedback is disconnected <b>42</b>. Applying voltage from the amplifier output and voltage shifting device to the tunneling device <b>44</b>, and a reference voltage to the amplifier reference input <b>46</b>, tunneling is induced <b>48</b>. Tunneling permits the voltage at the floating reference input terminal of the op amp to increase to the point where the output voltage of the op amp decreases until tunneling stops <b>48</b>. The polarity of the op amp is then reversed, placing the op amp in unity gain mode <b>50</b>. As shown at decision diamond <b>54</b>, a determination is made of whether the output level is within acceptable tolerances. If the op amp output voltage is acceptable, the tunneling device is left tied to ground and the op amp remains in unity gain mode <b>56</b>. If an acceptable voltage level has not been reached, the process is reiterated, returning to step <b>40</b> after an adjustment is made to the reference voltage <b>52</b>.

0030<figref idref="DRAWINGS">FIG. 5</figref> is schematic diagram of an alternative embodiment of a multiple floating gate programming circuit. It can be seen that the exemplary circuit <b>10</b> of <figref idref="DRAWINGS">FIG. 5</figref> resembles that of <figref idref="DRAWINGS">FIG. 2</figref> in that in a similar arrangement, a level shifter <b>15</b> is used to place charge on the floating gate of tunneling device T<b>1</b>. Tunneling device T<b>1</b> is coupled to the first input <b>12</b>A of the op amp <b>12</b>. In this example, a second tunneling device T<b>2</b> is also shown connected between the reference voltage VREF, the second op amp input <b>12</b>B, and ground. As the first voltage at the first input <b>12</b>A rises due to the tunneling occurring at the first tunneling device T<b>1</b>, the voltage reference VREF applied at the second input <b>12</b>B is also applied to the gate of the second tunneling device T<b>2</b>. As the voltages at the floating reference node <b>20</b> and the reference VREF equalize, the tunneling ceases. The application of a signal “DONE” at the reverse op amp input <b>12</b>C is used to reverse the op amp polarity, placing it in a unity gain mode of operation.

0031An alternative approach to programming a floating gate for practicing the invention is shown in <figref idref="DRAWINGS">FIG. 6</figref>. In this schematic diagram of an example of an alternative embodiment of a floating gate programming circuit, Channel-Hot-Carrier (CHC) programming is used to program the floating gate <b>62</b> at transistor device M<b>66</b>. Initially, with switches SW<b>6</b> and SW<b>7</b> closed and SW<b>8</b> tied to VSUPPLY, the amplifier/comparator <b>64</b> is functioning in comparator mode. The floating reference node <b>62</b> is at a high voltage and the amp <b>64</b> comparator output is high, causing device M<b>68</b> to turn on. The conduction through device M<b>66</b> causes channel-hot-carrier transfer of charge to occur, placing a charge on the floating gate at node <b>62</b>. When the voltage at node <b>62</b> goes lower than the reference voltage VREF, the comparator <b>64</b> output goes low, causing device M<b>68</b> to turn off, in turn causing the CHC transfer of charge to node <b>62</b> to cease. At this point, switch SW<b>9</b> is closed, ensuring that M<b>68</b> remains off preventing further CHC at M<b>66</b>. Closing switch SW<b>10</b> causes the amplifier/comparator <b>64</b> to operate in unity gain amplifier mode. The value at the floating node <b>62</b> is preferably monitored, whereby the reference voltage VREF may be incremented and the steps reiterated in order to compensate for any errors introduced by non-deal circuitry, such as for example errors introduced by capacitive coupling due to switching. In order to erase the charge stored on the floating gate <b>62</b>, switches SW<b>6</b>, SW<b>9</b>, and SW<b>11</b> are closed, and SW<b>8</b> is tied to the drain of device M<b>66</b>. The floating node <b>62</b> begins from low voltage, causing the output of the comparator to be low. The ERASE VOLTAGE coupled to M<b>66</b> through switches SW<b>8</b> and SW<b>11</b> is high, causing Fowler Nordheim tunneling to occur at the floating gate device M<b>66</b>. As the voltage at the floating node <b>62</b> rises above the reference voltage VREF, the comparator output is high. At this point SW<b>11</b> is preferably opened, causing tunneling in the floating gate device M<b>66</b> to come to a stop.

0032The methods and apparatus of the invention provide one or more advantages including but not limited to, speed, accuracy, offset compensation, and efficiency in programmable analog circuits. While the invention has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps or materials in the embodiments shown and described may be used in particular cases without departure from the invention. Various modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons skilled in the arts upon reference to the drawings, description, and claims.