Computers including an undiced semiconductor wafer with Faraday Cages and internal flexibility sipes

0001This application is a continuation of U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, which is a continuation-in-part of U.S. patent application Ser. No. 12/292,553, filed Nov. 20, 2008, which is a non-provisional of U.S. Provisional Application No. 60/996,530, filed on Nov. 21, 2007, and U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. U.S. patent application Ser. No. 12/292,769, filed Nov. 25, 2008, is also a non-provisional of U.S. Provisional Application No. 60/996,553, filed on Nov. 26, 2007. The contents of all of the above-mentioned applications are hereby incorporated herein by reference.

BACKGROUND

00021. Field of the Disclosure

0003The disclosure relates to a Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices combined with the applicant's prior internal sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit. More specifically, a Faraday Cage coincides with an outer compartment, which forms one surface of a sipe surrounding an inner compartment including a personal computer microchip and/or a photovoltaic cell and/or a fuel cell and/or a battery.

0004The disclosure also relates to a semiconductor wafer, such as silicon, containing a multitude of microchips, such as with one or more core microprocessors. Instead of separating the microchips into separate dies in the conventional process, the entire semiconductor wafer is used essentially intact as a computer. More specifically, interconnects can be added to the printed circuit architecture of the wafer to connect the wafer microchips to other wafer microchips and/or other components on the wafer or external to it. Still more specifically, each microchip can be a complete system on a chip (SoC). Even more specifically, the semiconductor wafer can be used with other conventional interface devices for power and data, including wireless such as radio and/or optic, and/or wired such as fiber optic and/or electric, including for each SoC microchip on the wafer. In another specific embodiment, two or more semiconductor wafers can be stacked in vertical layers; for example, with a first wafer including microprocessors or cores; a second wafer including random access memory or RAM; and a third wafer including other components; each SoC microchip, in this example, can have one or more components on each of the three wafers.

0005The disclosure also relates to the semiconductor wafer including one or more of the applicant's prior internal sipe inventions, with an outer compartment having an internal sipe.

0006The disclosure also relates to the semiconductor wafer being surrounded by one or more Faraday Cages integrated into the internal sipe invention.

00072. Brief Description of the Prior Art

0008Faraday Cage surrounding semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices, are described by the applicant in his U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004, and published as Pub. No. US 2004/0215931 A1 on Oct. 28, 2004.

0009The applicant's prior internal footwear sipe inventions, including at least one compartment surrounded by at least one internal sipe, such as a slit, are described by the applicant in his U.S. patent application Ser. No. 11/802,930, filed May 25, 2007 and published as Pub. No. US 2008/0086916 A1 on Apr. 17, 2008, as well as in several earlier U.S. applications filed by the applicant.

0010Existing semiconductor wafers, currently up to 300 mm in diameter, are always cut into a large number of separate dies, with one microchip formed into a package from each flaw-free die cut from the semiconductor wafer; some dies are inherently defective and are discarded. A typical semiconductor wafer is shown in the applicant's U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003.

0011As described in Wikipedia, “wafer scale integration” (WSI) is a yet-unused system of building very-large integrated circuit networks that use an entire silicon wafer to produce a single “super-chip.” Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers.

0012Many companies including TI and ITT attempted to develop “wafer scale integration” (WSI) production systems in the 1970's and '80's, but all failed and no products were released. Further attempts at WSI appear to be largely abandoned for decades.

0013One critical problem that has not been overcome is that of inherent flaws in semiconductor wafers. It has been an ongoing goal to develop methods to handle faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally, this approach uses a grid pattern of sub-circuits and “rewires” around the damaged areas using appropriate logic.

0014The overwhelming difficulty of this approach is illustrated by the history of famous computer pioneer Gene Amdahl, who attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments from Groupe Bull, Sperry Rand, and Digital Equipment Corporation, who (along with others) provided as estimated $230 million in financing. The design called for a 2.5″ square chip with 1200 pins on the bottom. After burning through about one third of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which would not happen for 100 years. There were several subsequent efforts in the 1980's, but none successful.

0015Another well-known problem is the field of wafer-scale integration technology is the impact of thermal expansion on external connectivity. More specifically, when a WSI microelectronic complex is connected to a circuit board by thousands of, for example, connectors positioned between the microelectronic complex and the circuit board, these connectors can be damaged due to the different rates of thermal expansion experience by the surfaces of the microelectronic comples and circuit board.

0016Taking for example a finished silicon wafer, packaged in a material such as ceramic, the wafer typically expands at a rate of 3 ppm/C. In contrast, the material of the circuit board typically expands at a rate of 20-40 ppm/C. Thus, as the two materials heat up, the two surfaces will expand at different rates, potentially damaging many of the connectors distributed between the wafer and the circuit board. See Norman, et al., U.S. Pat. No. 7,279,787.

0017The present disclosure solves these longstanding problems with existing technology.

SUMMARY

0018In the applicant's disclosure regarding Faraday Cages and siped compartments, two entirely different technologies (siped cushioning compartments and Faraday Cages) from two entirely different and unrelated fields of technology (“macro” athletic footwear and microelectronics), each with their own completely different art, have been integrated into a surprising new combination wherein the integrated structural components have simultaneous dual functions that are completely separate and unrelated.

0019Moreover, the integrated use of a sipe media both as a lubricant between the siped compartments and as a cooling media for a microchip (or other electronic component) to deal with the critical microprocessor heat dissipation problem is an additional surprising combination of two entirely separate technical functions that are completely different into a single new structural and material component with dual functions, again from entirely different and unrelated fields of art.

0020The applicant's semiconductor wafer computer disclosure solves the two longstanding problems that have heretofore made all such wafer-scale integration efforts fail.

0021First, the applicant's disclosure solves the longstanding inherent flaw intolerance problem discussed above by using microchips on the wafer that are personal computer systems on the chip (SoC), so that each wafer microchip can operate independently, including communicating with other wafer microchips, such as wirelessly in free space and/or waveguides by radio or optical device. In the applicant's approach, the wafer microchips that inherently are flawed during manufacture or fail in operation require no elaborate special handling like that described above. Generally, if they fail fatally, the remaining wafer microchips inherently ignore them since they do not communicate with other microchips; also, partial failure can be detected remotely and the microchip can be turned off, if necessary.

0022Second, the applicant's disclosure solves the longstanding unequal thermal expansion problem discussed above by reducing, even almost eliminating the need for pins, since both on wafer and off wafer communication by the independently functioning microchips (personal computer SoC's) on the wafer can be accomplished by radio or optics connections that do not require pins or require far fewer structural connections. In addition, the applicant's use of stacked semiconductor wafers, which can have very similar or identical materials and expansion rates, can obviate the need for conventional motherboards or reduce their role.

0023Moreover, since the personal computer microchips on the semiconductor wafer can operate independently, such as in conventional clusters of several or many or all of the personal computers on the wafer (or including personal computers off the wafer as well), the operations occurring on the wafer can be asynchronous. The applicant's disclosure thereby also solves the longstanding problem of synchronizing such wafer scale operations by obviating the need for synchronizing them, as would be necessary without the applicant's disclosure.

0024These and other features of the disclosure will become apparent from the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

0025<figref idref="DRAWINGS">FIGS. 1-9</figref> of this application are FIGS. 1-6, 52, 61, 67, 74, and 79 of both the applicant's U.S. application Ser. No. 11/802,033 filed May 18, 2007 and published on Apr. 10, 2008 as Pub. No. US 2008/0083140 A1 and PCT Application PCT/US2007/011976 filed 18 May 2007 and published on 31 Jan. 2008 as Int. Pub. No. WO 2008/013594 A2, as well as U.S. application Ser. No. 11/802,930 filed May 25, 2007 and published on Apr. 17, 2008 as Pub. No. US 2008/0086916 A1; all three applications are incorporated herein by reference. In addition, <figref idref="DRAWINGS">FIGS. 1-6</figref> (except <b>6</b>D-<b>6</b>F) of this application are FIGS. 83-88 of both the applicant's U.S. application Ser. No. 11/282,665 filed Nov. 21, 2005 and published on Nov. 9, 2006 as Pub. No. US 2006/0248749 A1 and PCT Application PCT/US2005/042341 filed 21 Nov. 2005 and published on 1 Jun. 2006 as Int. Pub. No. WO 2006/058013 A2, both of which are incorporated herein by reference.

0026<figref idref="DRAWINGS">FIG. 1A-4A</figref> show a frontal or sagittal plane cross section view of an example of a device <b>510</b> such as a flexible insert with a siped compartment or chamber or bladder.

0027<figref idref="DRAWINGS">FIGS. 1B-6B</figref> shows a horizontal plane view of a device <b>510</b> example.

0028<figref idref="DRAWINGS">FIG. 1C</figref> is an exploded perspective view showing the relationship of an insert device <b>510</b>, which has a siped compartment or chamber or bladder, with a midsole, bottom sole, and upper of a shoe or other footwear.

0029<figref idref="DRAWINGS">FIGS. 1D-1F</figref> show an example of the <b>510</b> invention using typical commercial air bladder embodiments as compartment <b>501</b> modified with outer compartment <b>500</b>.

0030<figref idref="DRAWINGS">FIGS. 5A-6A</figref> show a frontal or sagittal plane cross section view of an example of a device <b>510</b> such as a flexible insert with two siped compartments or chambers or bladders or combination.

0031<figref idref="DRAWINGS">FIG. 7A</figref> shows a computer laptop with the <b>510</b>/<b>511</b>/<b>513</b> inventions and <figref idref="DRAWINGS">FIG. 7B</figref> shows a semiconductor microchip with the <b>510</b>/<b>511</b>/<b>513</b> inventions.

0032<figref idref="DRAWINGS">FIGS. 7C-7D</figref> show additional examples of the <b>510</b>/<b>511</b>/<b>513</b> inventions applied to electronic game controllers and cell phone.

0033<figref idref="DRAWINGS">FIG. 8</figref> is a chart showing approximate comparison of hardness scales.

0034<figref idref="DRAWINGS">FIGS. 9A-9C</figref> show a large urban telephone book lying flat, solid wooden block, and an upright very thick book to illustrate basic concepts of sipe flexibility and stability.

0035<figref idref="DRAWINGS">FIGS. 10-22</figref> of this application are FIGS. 10A-10I, 16A-16Z, 16AA, and 16AB, 17A-17D, 21B, 22A, 23A-23E, 25A-25D, 26A-26C, 27A-27H, 28, 29A, 30A-30C, and 31 of both the applicant's U.S. application Ser. No. 10/802,049 filed May 17, 2004 and published on Oct. 28, 2004 as Pub. No. US 2004/0215931 A1.

0036<figref idref="DRAWINGS">FIGS. 10A-10I</figref> are simplified diagrams of a section of a computer network, such as the Internet, showing an embodiment of a system architecture utilizing an internal firewall to separate that part of a networked PC (including a system reduced in size to a microchip) that is accessible to the network for shared processing from a part that is kept accessible only to the PC user; also showing the alternating role that each PC in the network may play as either a master or slave in a shared processing operation involving one or more slave PC's in the network; and showing a home or business network system which can be configured as an Intranet; in addition, showing PC and PC microchips controlled by a controller (including remote) with limited or no processing capability; and showing PC and PC microchips in which an internal firewall <b>50</b> can be reconfigured by a PC user.

0037<figref idref="DRAWINGS">FIGS. 11A-11K</figref> show a new hierarchical network architecture for personal computers and/or microprocessors based on subdivision of parallel processing or multi-tasking operations through a number of levels down to a processing level.

0038<figref idref="DRAWINGS">FIGS. 12A-12D</figref> show an internal firewall <b>50</b> with a dual function, including that of protecting Internet users (and/or other network users sharing use) of one or more slave personal computers PC <b>1</b> or microprocessors <b>40</b> from unauthorized surveillance or intervention by an owner/operator of those slave processors.

0039<figref idref="DRAWINGS">FIG. 13</figref> shows that all microprocessors of a personal computer or personal computer on a microchip can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component.

0040<figref idref="DRAWINGS">FIG. 14</figref> shows a PC microprocessor on a microchip similar to that of <figref idref="DRAWINGS">FIG. 13</figref>, except that Figure shows microprocessors <b>93</b> and <b>94</b> each connecting to an optical wired connection <b>99</b>′ such as thin mirrored hollow wire or optical omniguide or optical fiber.

0041<figref idref="DRAWINGS">FIG. 15</figref> show multiple firewalls <b>50</b> within a personal computer <b>1</b> or PC microchip <b>90</b>.

0042<figref idref="DRAWINGS">FIG. 16</figref> show the use for security of power interruption or data overwrite of volatile memory like DRAM and non-volatile memory like Flash or MRAM (or ovonics), respectively, of the network portion of a personal computer PC<b>1</b> or system on a microchip PC<b>90</b>.

0043<figref idref="DRAWINGS">FIG. 17</figref> show exemplary microchip and photovoltaic cell embodiments.

0044<figref idref="DRAWINGS">FIG. 18</figref> show exemplary microchip and Faraday Cage embodiments.

0045<figref idref="DRAWINGS">FIG. 19</figref> shows a silicon wafer <b>500</b> used to make microchips.

0046<figref idref="DRAWINGS">FIG. 20A</figref> shows a top view of a microchip <b>501</b> surrounded by adjoining portions of adjoining microchips <b>501</b> in a section of the silicon wafer <b>500</b>. <figref idref="DRAWINGS">FIG. 20B</figref> shows a top view of the microchip <b>501</b> embodiment of <figref idref="DRAWINGS">FIG. 20A</figref> after the die has been separated from the silicon wafer <b>500</b> and positioned in a microchip package <b>503</b>.

0047<figref idref="DRAWINGS">FIG. 21</figref> show alternative embodiments that unite separate fabrication processes on the same microchip <b>501</b>.

0048<figref idref="DRAWINGS">FIG. 22</figref> shows a combination of the embodiments shown in <figref idref="DRAWINGS">FIGS. 20 and 21</figref>.

0049<figref idref="DRAWINGS">FIGS. 23A-23H</figref> are modifications of <figref idref="DRAWINGS">FIGS. 18A-27H</figref> of this application, which are FIGS. 27A-27H of U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004 and published on Oct. 28, 2004, as Pub. No. US 2004/0215931 A1 and U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, both of which applications are hereby incorporated by reference herein for completeness of disclosure.

0050<figref idref="DRAWINGS">FIGS. 23A-23H</figref> are more specific example embodiments of the <figref idref="DRAWINGS">FIG. 7B</figref> example; they show examples of the applicant's inventions involving one or more Faraday Cages surrounding various combinations of semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices with the applicant's internal sipe inventions <b>510</b>/<b>511</b>/<b>513</b>.

0051FIGS. <b>24</b>A and <b>25</b>A-<b>25</b>B are modifications of FIGS. 28 and 29A-29B of U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, which was above incorporated by reference herein for completeness of disclosure.

0052<figref idref="DRAWINGS">FIG. 24A</figref> is a top view of a semiconductor wafer <b>1500</b>, the entire semiconductor wafer <b>1500</b> being used essentially intact as a computer, which can also include a Faraday Cage and a siped compartment. <figref idref="DRAWINGS">FIG. 24B</figref> is a side cross section of three stacked wafers <b>1500</b>. <figref idref="DRAWINGS">FIG. 24C</figref> is another top view of a wafer <b>1500</b>, but subdivided into smaller components, such as half sections and quarter sections.

0053<figref idref="DRAWINGS">FIGS. 25A-25B</figref> are modifications of FIGS. 29A-29B of the '657 application incorporated by reference herein above. <figref idref="DRAWINGS">FIG. 25B</figref> shows a microchip <b>1501</b> as a separated die in a package <b>1503</b> including the applicant's internal sipe inventions <b>510</b>/<b>511</b>/<b>513</b> and the Faraday Cage <b>300</b>.

0054<figref idref="DRAWINGS">FIGS. 26A-26B</figref> is <figref idref="DRAWINGS">FIGS. 7A-7B</figref> with the addition of Faraday Cages, as well as stacked dies in <figref idref="DRAWINGS">FIG. 7B</figref>.

0055<figref idref="DRAWINGS">FIGS. 27A-27B</figref> are like FIGS. 28A-28B of the '033 and '930 Applications incorporated above shows in cross-section an example of a tire <b>535</b>, such as for a wheel <b>533</b> of a transportation vehicle, with a device <b>510</b>.

0056It is understood that the reference numbers identified in this application and in U.S. Patent Applications '665, '033, and '930 incorporated by reference herein, are used consistently throughout the application such that like reference numbers are used to describe the same or like elements.

DETAILED DESCRIPTION

0057<figref idref="DRAWINGS">FIGS. 1-9</figref> of this application are FIGS. 1-6, 52, 61, 67, 74, and 79 of both the applicant's U.S. application Ser. No. 11/802,033 filed May 18, 2007 and published on Apr. 10, 2008 as Pub. No. US 2008/0083140 A1 and PCT Application PCT/US2007/011976 filed 18 May 2007 and published on 31 Jan. 2008 as Int. Pub. No. WO 2008/013594 A2, as well as U.S. application Ser. No. 11/802,930 filed May 25, 2007 and published on Apr. 17, 2008 as Pub. No. US 2008/0086916 A1; all three applications are incorporated herein by reference. In addition, <figref idref="DRAWINGS">FIGS. 1-6</figref> (except <b>6</b>D-<b>6</b>F) of this application are FIGS. 83-88 of both the applicant's U.S. application Ser. No. 11/282,665 filed Nov. 21, 2005 and published on Nov. 9, 2006 as Pub. No. US 2006/0248749 A1 and PCT Application PCT/US2005/042341 filed 21 Nov. 2005 and published on 1 Jun. 2006 as Int. Pub. No. WO 2006/058013 A2, both of which are incorporated herein by reference.

0058<figref idref="DRAWINGS">FIGS. 1-9</figref> show the applicant's prior inventions incorporating forms of insertable devices with one or more internal (or mostly internal) sipes, including slits (or channels or grooves and other shape, including geometrically regular or non-regular shapes, such as anthropomorphic shapes), into a large variety of products, including footwear and orthotics, athletic, occupational and medical equipment and apparel, padding for equipment and furniture, balls, tires and any other structural or support elements in a mechanical, architectural or any other device.

0059New reference numerals used in the <figref idref="DRAWINGS">FIGS. 1-79</figref> are further defined as follows: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0060">Ref. No <b>500</b>: An outer compartment, such as an outer compartment <b>161</b> or chamber <b>188</b> or bladder, at least partially or mostly or entirely enclosing a space within the outer compartment/chamber/bladder <b>500</b>, which can be located anywhere in a footwear sole or upper or both or other article described in this application. Construction and materials can be, as one embodiment example, simpler in shape but otherwise similar to those used in any commercial samples of Nike Air™.</li><li id="ul0001-0002" num="0061">Ref. No <b>501</b>: An inner compartment, such as an inner compartment <b>161</b> or chamber <b>188</b> or bladder, is located inside the enclosed space of the outer compartment/chamber/bladder <b>500</b>. Construction and materials of the inner compartment/chamber/bladder <b>501</b> can be, as one embodiment example, like those used in any commercial samples of gas bladders in Nike Air™.</li><li id="ul0001-0003" num="0062">Ref. No. <b>502</b>: Structural element that is optional anywhere within either outer compartment/chamber/bladder <b>500</b> or inner compartment/chamber/bladder <b>501</b>, of which a <b>501</b> embodiment is shown; any flexible, resilient material can be used, including structures molded into the shape of (and using the material of) the compartment/chamber/bladder <b>500</b> or <b>501</b>, as is very common in the art, such as many commercial samples of gas bladders used in Nike Air™, as well as foamed plastic or plastic composite or other materials, like Nike Shox™ or Impax™ or Reebok DMX™ or New Balance N-ergy™. In addition, other materials can be used directly within a <b>501</b>/<b>500</b> compartment or can connected to or through a <b>501</b>/<b>500</b> compartment, as in the cushioning components of the shoe sole heel of commercial samples of Adidas 1™, including electromechanical, electronic, and other components. Some devices may benefit from the use of rigid or semi-rigid materials for part or all of a media within a compartment.</li><li id="ul0001-0004" num="0063">Ref. No. <b>503</b>: Attachment of two compartment/chambers/bladders <b>500</b>/<b>501</b>, including particularly attachment of outer <b>500</b> to inner <b>501</b>; any practical number of attachments of any form using any materials can be used, including glue.</li><li id="ul0001-0005" num="0064">Ref. No. <b>504</b>: Media contained within all or part of compartment/chamber/bladder <b>500</b> or <b>501</b>, particularly <b>501</b>, can be any useful material, such as gas (including, as an example, gas used in Nike Air™ or ambient air, liquid or fluid, gel, or foam (such as a plastic like PU or EVA or equivalent or rubber (natural or synthetic) or combination of two or more; encapsulation of foam is optional); material particles or coatings, such as dry coatings like Teflon™ can also be used. An optional element in an outer compartment/chamber <b>500</b> (or an inner compartment/chamber <b>501</b> that itself contains an inner compartment/chamber, as in <figref idref="DRAWINGS">FIG. 87</figref>).</li><li id="ul0001-0006" num="0065">Ref. No. <b>505</b>: Internal sipe or slit or channel or groove for flexibility, such as between inner and outer compartment/chamber <b>500</b>/<b>501</b> (or bladder) surfaces, as one embodiment example; such surfaces can be substantially parallel and directly contact in one useful embodiment example, but are not attached so that at least parts of the two surfaces can move relative to each other, such as to facilitate a sliding motion between surfaces; the surfaces can be in other useful forms that allow portions of the surfaces to be proximate to each other but not contacting in an unloaded condition or in a partially loaded condition or in a maximally loaded condition.</li><li id="ul0001-0007" num="0066">Ref. No. <b>506</b>: Media of internal sipe <b>505</b>; media <b>506</b> can be any useful material like those used in media <b>504</b>; media <b>506</b> can be located in part or all of <b>505</b> to decrease (or increase) sliding resistance between <b>500</b>/<b>501</b> or <b>505</b> surfaces, for example, to lubricate the surfaces with any suitable material; silicone or Teflon™ can be used, for example; an optional element.</li><li id="ul0001-0008" num="0067">Ref. No. <b>507</b>: Metal particles.</li><li id="ul0001-0009" num="0068">Ref. No. <b>508</b>: Shock absorbing fluid containing <b>507</b>; a magnetorheological fluid.</li><li id="ul0001-0010" num="0069">Ref. No. <b>509</b>: Electromagnetic field-creating circuit.</li><li id="ul0001-0011" num="0070">Ref. No. <b>510</b>: A flexible insert or component including siped compartments <b>161</b> or chambers <b>188</b> or bladders used for example as outer and inner compartments/chambers/bladders <b>500</b>/<b>501</b> for footwear soles or orthotics or uppers or other uses; a useful embodiment being two or more compartment or chambers (or bladders) <b>161</b>/<b>188</b> (or mix) that are separated at least in part by an internal sipe <b>505</b>, including the example of at least one <b>501</b> (either <b>161</b>/<b>188</b> or bladder) inside at least one <b>500</b> (either <b>161</b>/<b>188</b> or bladder) and being separated by an internal sipe <b>505</b>.</li><li id="ul0001-0012" num="0071">Ref. No. <b>580</b>: Computer or computer component.</li><li id="ul0001-0013" num="0072">Ref. No. <b>581</b>: Micro-technology and nanotechnology devices, including a semiconductor microchip device (a part of a die or an entire die or multiple dies assembled together) microelectromechanical systems (MEMS), field-programmable gate arrays (FPGA's) and faraday cages, photovoltaic cells, fuel cells, batteries, and including devices assembled at the molecular or atomic scale.</li></ul>

0073<figref idref="DRAWINGS">FIGS. 1-7</figref> show, as numeral <b>510</b>, examples of a device or flexible insert including siped compartments <b>161</b> or chambers <b>188</b> or bladders (another term used in the art) for use in any footwear soles, including conventional soles <b>22</b> or the applicant's prior inventions, including footwear/shoe soles <b>28</b> and midsole inserts <b>145</b> as described in applicant's published '087 Application and Ser. No. 11/282,665 U.S. application published Nov. 9, 2006, as Pub. No. US 2006/0248749 A1 incorporated by reference, or for orthotics <b>145</b> as described in the applicant's published '034 U.S. Application, '869 Patent, and WO 02/09547 WIPO publication, as well as to be published by WIPO PCT Application Number PCT/US2005/042341, all incorporated by reference herein, including for uppers for footwear or orthotics (or including uppers), or for other flexibility uses in athletic equipment like helmets and apparel including protective padding and guards, as well as medical protective equipment and apparel, and other uses, such as protective flooring, improved furniture cushioning, balls and tires for wheels, and other uses.

0074The device or flexible insert with siped compartments or chambers <b>510</b> include embodiments like two or more of either compartments <b>161</b> or chambers <b>188</b> or bladders (or a any mix including two or more of a compartment, a chamber, and a bladder) that are separated at least in part or in several parts or mostly or fully by an internal sipe <b>505</b>. The flexible insert <b>510</b> can be inserted during assembly of an article by a maker or manufacturer or is insertable by a user or wearer (into an article like a shoe, for example, as part of a removable midsole insert <b>145</b> described above), or integrated into the construction of a device as one or more components.

0075Siped compartments or chambers <b>510</b> include example embodiments such as <figref idref="DRAWINGS">FIGS. 1-7</figref>, which generally show at least one inner compartment <b>161</b> or chamber <b>188</b> inside at least one other outer compartment <b>161</b> or chamber <b>161</b>; and the two compartments/chambers <b>161</b>/<b>188</b> being separated by an internal sipe <b>505</b>.

0076One practical example embodiment of the invention is any prior commercial embodiment of Nike Air™ gas bladder or compartment (like typical examples in FIGS. 12-16 of U.S. Pat. No. 6,846,534, which is hereby incorporated by reference) that is installed unattached, as is, located within the space enclosed partially or fully by a new, slightly larger outer compartment of one additional layer of the same or similar material, with the same or a simpler or the simplest geometric shape; that is, not necessarily following indentations or reverse curves, but rather incorporating straighter or the straightest lines, as seen in cross-section: for example, following the outermost side curvature seen in <figref idref="DRAWINGS">FIGS. 12-16</figref>, but with upper and lower surfaces that are substantially flat and parallel (or curved and parallel), to facilitate ease of movement between the two surfaces of the sipe <b>505</b> formed, increasing the resulting flexibility.

0077The new additional, outer compartment thus thereby has created by its presence an internal sipe <b>505</b> between the two unconnected compartments. The new internal sipe <b>505</b> provides much greater flexibility to any footwear sole <b>22</b> or <b>28</b>, since it allows an inner, otherwise relatively rigid Nike Air™ compartment structure to become an inner compartment <b>501</b> (instead of typically being fixed into the other materials such as EVA of the footwear sole) to move freely inside the new outer compartment <b>500</b>, which becomes a new compartment that is fixed to the footwear sole, rather that the conventional Nike Air™ bladder. The flexibility improvement allows the shoe sole to deform under a body weight load like a wearer's bare foot sole, so that stability is improved also, especially lateral stability.

0078The result is that the conventional, inner Nike Air™ compartment—now contained by a new outer compartment—can move easily within the overall footwear sole, allowing the sole to bend or flex more easily in parallel with the wearer's bare foot sole to deform to flatten under a body weight load, including during locomotion or standing, so that footwear sole stability is improved also, especially lateral stability. The extent to which the inner Nike Air™ compartment is “free-floating” within the new outer compartment can be controlled or tuned, for example, by one or more attachments (permanent or adjustable) to the outer compartment or by the media in the internal sipe.

0079The internal sipe <b>505</b> includes at least two surfaces that can move relative to each other to provide a flexibility increase for a footwear sole so that the shape of the footwear sole can deform under a body weight load to better parallel to the shape of the barefoot sole of a wearer under a same body weight load. The relative motion between the two internal sipe <b>505</b> surfaces increases the capability of the footwear sole to bend during locomotion under a wearer's body weight load to better parallel the shape of said wearer's bare foot sole.

0080Also, the sliding motion between internal support surfaces within the shoe sole <b>28</b> allowed by internal sipe <b>505</b> in response to torsional or shear forces between a wearer's foot and the ground assists in controlling and absorbing the impact of those forces, whether sudden and excessive or chronically repetitive, thereby helping to protect the wearer's joints from acute or chronic injury, especially to the ankles, knees, hips, lower back, and spine.

0081A benefit of the siped compartments/chambers <b>510</b> is that, as a single unitary component, it can be used in any conventional manner in constructing the footwear sole <b>28</b>, generally like that used with a conventional single layer compartment such as used in Nike Air™; i.e. the outer surface of <b>510</b> can, as a useful embodiment, adhere to the adjacent materials like plastic such as PU (polyurethane) or EVA (ethyl vinyl acetate) or other plastic or rubber of the footwear sole that contact the <b>510</b> component, just as would be the case with the outer surface of existing single compartment <b>161</b> or chamber <b>188</b> of commercial examples of Nike Air™. However, the internal sipe <b>505</b> formed by the use of an inner compartment/chamber <b>501</b> in the siped compartment/chamber <b>510</b> provides flexibility in a footwear sole <b>28</b> that is absent in the relatively rigid footwear sole <b>28</b> formed with a conventional, single layer compartment <b>161</b> or chamber <b>188</b> of the many Nike Air™ commercial examples.

0082The sipe surfaces can in one useful example embodiment be formed by the inner surface (or part or parts of it) of the outer compartment <b>500</b> and the outer surface (or part or parts of it) of the inner compartment <b>501</b>. Such sipe surfaces can be substantially parallel and directly contact each other in one useful embodiment example, but the two surfaces are generally not attached to each other, so that the sipe surfaces can move relative to each other to facilitate a sliding motion between the two surfaces.

0083The sipe surfaces can be in other useful forms that allow portions of the surfaces to be proximate to each other in an unloaded condition, rather than contacting; such surfaces can make partial or full direct contact under a wearer's body weight load (which can vary from a fraction of a “g” to multiple “g” forces during locomotion) or remain somewhat separated; the amount of sipe surface area making direct contact can also vary with a wearer's body weight load. The sipes surfaces also may not be parallel or only partially parallel, such as the areas of direct surface contact or proximal surface contact.

0084To preclude the surfaces of the internal sipe <b>505</b> from directly contacting each other (whether loaded or unloaded), the sipe surfaces can include an internal sipe media <b>506</b> located between the surfaces to reduce friction by lubrication and increase relative motion and therefore flexibility. Useful example embodiments of the internal sipe media <b>506</b> include any useful material known in the art (or equivalent), such as a liquid like silicone as one example, a dry material like Teflon™ as another example, or a gas like that used in Nike Air™ as a further example. The media <b>506</b> can be located in all of the sipe <b>505</b> or only part or parts, as shown in <figref idref="DRAWINGS">FIGS. 1-6</figref>.

0085The media <b>506</b> can be used to decrease (or increase) sliding resistance between the inner surfaces of the sipe; for example, to lubricate with any suitable material known in the art. The internal sipe media <b>506</b> is an optional feature.

0086The attachments <b>503</b> can be simply passive (i.e. static) or actively controlled by electronic, mechanical, electromagnetic, or other useful means. The attachments <b>503</b> can, for example, be designed to break away as a failsafe feature to compensate for a predetermined extreme torsional load, for example, to reduce extreme stress on critical joints (in lieu of a wearer's cartilage, tendons, muscle, bone, or other body parts being damaged); the attachments <b>503</b> can then be reset or replaced (or, alternatively, return automatically upon relief of extreme stress to a normal position).

0087Example embodiments of the compartments and chambers <b>500</b>/<b>501</b> can include a media <b>504</b> such as a gas (like that used in Nike Air™ or ambient atmospheric air), a liquid or fluid, a gel, a foam (made of a plastic like PU or EVA, both of which are common in the footwear art, or equivalent, or of a rubber (natural or synthetic) or blown rubber or a rubber compound or equivalent or of another useful material or of a combination of two or more of the preceding foam plastic/rubber/etc.) or a useful combination of one or more gas, liquid, gel, foam, or other useful material.

0088<figref idref="DRAWINGS">FIGS. 2A</figref>, <b>3</b>A, and <b>4</b>A show examples of embodiments of siped compartment/chamber/bladders <b>510</b> wherein either the inner compartment/chamber/bladder <b>501</b> or the outer compartment <b>500</b> can have one or more openings, for pressure equalization, assembly facilitation, or other purposes.

0089<figref idref="DRAWINGS">FIG. 5A</figref> shows an example embodiment with an inner compartment/chamber/bladder <b>501</b>¹having a smaller inner compartment/chamber/bladder <b>501</b>²; additional smaller inner compartments <b>501</b> are possible in a similar progression, either enclosed within the previous larger inner compartment <b>501</b> or within the same <b>501</b> or <b>500</b>.

0090<figref idref="DRAWINGS">FIG. 6A</figref> shows an example embodiment with two inner compartment/chamber/bladders <b>501</b>¹and <b>501</b>²which are layered within outer compartment/chamber/bladder <b>500</b>; additional compartment/chamber <b>501</b> layers can be useful also.

0091<figref idref="DRAWINGS">FIG. 1B</figref> shows an example embodiment of the device <b>510</b> in a horizontal plane view of <figref idref="DRAWINGS">FIGS. 1A</figref>, <b>2</b>A, <b>3</b>A, <b>4</b>A, <b>5</b>A, and <b>6</b>A.

0092<figref idref="DRAWINGS">FIG. 1C</figref> is an exploded perspective view showing the relationship of an insert device <b>510</b>, which has a siped compartment or chamber or bladder, with a midsole <b>148</b>, bottom sole <b>149</b>, and upper <b>21</b> of a shoe or any other footwear. The midsole <b>148</b> and bottom sole <b>149</b> (and any additional layers not shown) together form a shoe sole which can be any footwear sole, including any conventional sole <b>22</b> or any sole <b>28</b> according to one of the applicant's patents or applications. In the simple example shown, the device <b>510</b> can be inserted during a conventional manufacturing or assembly process or by a footwear wearer and can be located anywhere in the footwear sole and/or upper.

0093<figref idref="DRAWINGS">FIG. 1E</figref> shows a detailed frontal plane cross section of an example conventional commercial gas bladder/compartment/chamber shown as inner bladder or compartment or chamber <b>501</b> in schematic perspective in <figref idref="DRAWINGS">FIG. 1D</figref>. <figref idref="DRAWINGS">FIG. 2F</figref> shows the same detailed cross sectional view of the same inner bladder or compartment or chamber <b>501</b> enveloped by an outer bladder or compartment or chamber <b>500</b> forming an insertable siped compartment <b>510</b>, including wherein all or part of the sipe <b>505</b> is a slit.

0094<figref idref="DRAWINGS">FIG. 7A</figref> shows a perspective view of a laptop personal computer <b>580</b> or any other electronic device with one of a potential multitude of potential example embodiments of the applicant's <b>510</b> or <b>511</b> or <b>513</b> inventions described above are used in two areas, but other useful embodiments with any of the previously described variations can be employed beneficially. For example, as shown, the <b>510</b>/<b>511</b>/<b>513</b> inventions can be used for cushioning selected corners of the laptop or can be integrated in the laptop frame in the same or other areas; and/or individual components of the laptop computer such as a harddrive can be protected by being mounted in a protected <b>510</b>/<b>511</b>/<b>513</b>, such as the housing of the hard-drive forming an inner compartment <b>501</b> of the <b>510</b> siped compartment invention.

0095<figref idref="DRAWINGS">FIG. 7B</figref> shows a semiconductor microchip device <b>581</b> example including a part of a die or an entire die or multiple dies assembled together using the applicant's <b>510</b>/<b>511</b>/<b>513</b> invention; other devices <b>581</b> can include other micro-technology and nanotechnology devices, including microelectromechanical systems (MEMS), field-programmable gate arrays (FPGA's) and faraday cages, photovoltaic cells, fuel cells, batteries, and including devices assembled at the molecular or atomic scale. The <figref idref="DRAWINGS">FIG. 7B</figref> example embodiment can include a single layer of die or dies or can include a stacked arrangement of two or more layers of separate dies. <figref idref="DRAWINGS">FIG. 7C</figref> shows a cross section of the semiconductor microchip device <b>581</b> example of <figref idref="DRAWINGS">FIG. 7B</figref>, showing a stacked arrangement of three layers of separate dies <b>581</b>#<b>1</b>, <b>581</b>#<b>2</b>, and <b>581</b>#<b>3</b>.

0096<figref idref="DRAWINGS">FIGS. 7C and 7D</figref> show other examples such as electronic game controllers or any other remote controllers <b>580</b> and cell phones <b>580</b> that can beneficially incorporates any of the applicant's <b>510</b>/<b>511</b>/<b>513</b>.

0097<figref idref="DRAWINGS">FIG. 8</figref> shows a chart displaying “Approximate Comparison of Hardness Scales”. Products using the <b>510</b> or <b>511</b> or <b>513</b> inventions can be made of any material and any material hardness shown in chart, including Rockwell C and B Scales and Brinell Hardness Scale, including metallic and ceramic, generally for non-cushioning, relatively rigid structural elements into which a degree of flexibility is to be introduced using the applicant's <b>510</b>/<b>511</b>/<b>513</b> inventions, specific examples of which are shown in <figref idref="DRAWINGS">FIGS. 7A-7B</figref>.

0098<figref idref="DRAWINGS">FIG. 9A</figref> shows that, in an analogous way, especially to the thicker heel portion of a typical shoe sole, a thick urban area telephone book has in effect hundreds of mostly “internal sipes”, each page being in effect separated by a horizontal internal slit from each adjacent page, each of which thereby is able to move freely relative to each other, resulting in a flexible telephone book that bends quite easily as is well known by all, while at the same time relatively stable when a vertical force like body weight is applied. <figref idref="DRAWINGS">FIG. 9B</figref> shows, in contrast, if the same wood fiber material with the same dimensions as a thick telephone book were formed instead into a single piece of wood with no pages, like a solid particle board, it would be quite rigid with little flexibility, although it will support a body weight stably. <figref idref="DRAWINGS">FIG. 9C</figref> shows if, instead, the sipes were rotated 90 degrees into vertical slits and open to the bottom, so that the spine of a much wider telephone book with shorter pages is on top (in the form of a shoe sole with deep open external sipes, those external sipes would also provide a substantial amount of flexibility like that of the human foot sole, but at the cost of excessive instability when a vertical force like body weight is applied, as is obvious from common experience, since the pages will splay out uncontrollably.

0099<figref idref="DRAWINGS">FIGS. 10-22</figref> of this application are FIGS. 10A-10I, 16A-16Z, 16AA, and 16AB, 17A-17D, 21B, 22A, 23A-23E, 25A-25D, 26A-26C, 27A-27H, 28, 29A, 30A-30C, and 31 of both the applicant's U.S. application Ser. No. 10/802,049 filed May 17, 2004 and published on Oct. 28, 2004 as Pub. No. US 2004/0215931 A1.

0100As shown in <figref idref="DRAWINGS">FIGS. 10A-10F</figref>, to deal with operational and security issues, it may be beneficial for individual users to have one microprocessor or equivalent device that is designated, permanently or temporarily, to be a master <b>30</b> controlling device (comprising hardware and/or software and/of firmware and/or other component) that remains inaccessible (using, for example, a hardware and/or software and/or firmware and/or other component firewall <b>50</b>) directly by the network but which controls the functions of the other slave microprocessors <b>40</b> when the network is not utilizing them.

0101For example, as shown in <figref idref="DRAWINGS">FIG. 10A</figref>, a typical PC <b>1</b> may have four or five microprocessors (even on a single microprocessor chip), with one master <b>30</b> and three or four slaves <b>40</b>, depending on whether the master <b>30</b> is a controller exclusively (through different design of any component part), requiring four slave microprocessors <b>40</b>; or the master microprocessor <b>30</b> has the same or equivalent microprocessing capability as a slave <b>40</b> and multiprocesses in parallel with the slave microprocessors <b>40</b>, thereby requiring only three slave microprocessors <b>40</b>. The number of PC slave microprocessors <b>40</b> can be increased to virtually any other number, such as at least about eight, about 16, about 32, about 64, about 128, about 256, about 512, about 1024, and so on. These multiples are not required, and the number of PC master microprocessors <b>30</b> may be increased. Also included is an internal firewall <b>50</b> between master <b>30</b> and slave <b>40</b> microprocessors. As shown in preceding <figref idref="DRAWINGS">FIGS. 1-9</figref>, the PC <b>1</b> in <figref idref="DRAWINGS">FIG. 10A</figref> may be connected to a network computer <b>2</b> and to the Internet or WWW or present or future equivalent or successor <b>3</b>, like the Grid (or MetaInternet).

0102Other typical PC hardware components such as hard drive <b>61</b>, floppy diskette drive <b>62</b>, compact disk-read only memory (CD-ROM) <b>63</b>, digital video disk (DVD) <b>64</b>, Flash memory <b>65</b>, random access memory (RAM) <b>66</b>, video or other display <b>67</b>, graphics card <b>68</b>, and sound card <b>69</b>, as well as digital signal processor or processors, together with the software and/or firmware stored on or for them, can be located on either side of internal firewall <b>50</b>, but such devices as the display <b>67</b>, graphics card <b>68</b> and sound card <b>69</b> and those devices that both read and write and have non-volatile memory (retain data without power and generally have to be written over to erase), such as hard drive <b>61</b>, Flash memory <b>65</b>, floppy diskette drive <b>62</b>, read/write CD-ROM <b>63</b> or DVD <b>64</b> may be located on the PC user side of the internal firewall <b>50</b>, where the master microprocessor is also located, as shown in <figref idref="DRAWINGS">FIG. 10A</figref>, for security reasons; their location can be flexible, with that capability controlled such as by password-authorized access.

0103Alternately, any of these devices that are duplicative (or for other exceptional needs) like a second hard drive <b>61</b>′, can be located on the network side of the internal firewall <b>50</b>. RAM <b>66</b> or equivalent or successor memory, which typically is volatile (data is lost when power is interrupted), should generally be located on the network side of the internal firewall <b>50</b>, but some can be located with the master microprocessor to facilitate its independent use.

0104However, read-only memory (ROM) devices including most current CD drives (CD-ROM's) <b>63</b>′ or DVD's (DVD-ROM) drives <b>64</b>′ can be safely located on the network side of the internal firewall <b>50</b>, since the data on those drives cannot be altered by network users; preemptive control of use may remain with the PC user.

0105However, at least a portion of RAM can be kept on the Master <b>30</b> microprocessor side of the internal firewall <b>50</b>, so that the PC user can retain the ability to use a core of user PC <b>1</b> processing capability entirely separate from any network processing. If this capability is not desired, then the master <b>30</b> microprocessor can be moved to the network side of the internal firewall <b>50</b> and replaced with a simpler controller on the PC <b>1</b> user side, like the master remote controller <b>31</b> discussed below and shown in <figref idref="DRAWINGS">FIG. 10I</figref>.

0106The master microprocessor <b>30</b> may also control the use of several or all other processors <b>60</b> owned or leased by the PC user, such as home entertainment digital signal processors <b>70</b>, especially if the design standards of such microprocessors in the future conform to the requirements of network parallel processing as described above. In this general approach, the PC master processor uses the slave microprocessors or, if idle (or working on low priority, deferrable processing), makes them available to the network provider or others to use. Wireless connections <b>100</b>, including optical wireless, are expected to be extensively used in home or business network systems, including use of a master remote controller <b>31</b> without (or with) microprocessing capability, with broad bandwidth connections such as fiber optic cable connecting directly to at least one component such as a PC <b>1</b>, shown in a slave configuration, of the home or business personal network system; that connection links the home system to the network <b>2</b> such as the Internet <b>3</b>, as shown in <figref idref="DRAWINGS">FIG. 10I</figref>. A business system may include broadband such as fiber optic or optical wireless links to most or all personal computers PC <b>1</b> and other devices with microprocessors, such as printers, copiers, scanners, fax machines, telephone and video conferencing equipment; other wired or wireless links also can be used.

0107A PC <b>1</b> user can remotely access his networked PC <b>1</b> by using another networked master microprocessor <b>30</b> on another PC <b>1</b> and using a password or other access control means for entry to his own PC <b>1</b> master microprocessor <b>30</b> and files, as is common now in Internet and other access. Alternately, a remote user can simply carry his own digitally stored files and his own master microprocessor or use another networked master microprocessor temporarily has his own.

0108In the simplest configuration, as shown in <figref idref="DRAWINGS">FIG. 10B</figref>, the PC <b>1</b> may have a single master microprocessor <b>30</b> and a single slave microprocessor <b>40</b>, separated by an internal firewall <b>50</b>, with both processors used in parallel or multitasking processing or with only the slave <b>40</b> so used, and connected with broad bandwidth such as optical fiber wire <b>99</b> to a network computer <b>2</b> and Internet <b>3</b> and successors like the Grid (or MetaInternet). Virtually any number of slave microprocessors <b>40</b> is possible. The other non-microprocessor components shown in <figref idref="DRAWINGS">FIG. 10A</figref> above may also be included in this simple <figref idref="DRAWINGS">FIG. 10B</figref> configuration.

0109As shown in <figref idref="DRAWINGS">FIG. 10C</figref>, microchips <b>90</b> are expected to integrate most or all of the other necessary computer components (or their present or future equivalents or successors), like a PC's volatile memory like RAM <b>66</b> (such as DRAM), graphics <b>82</b>, sound <b>83</b>, power management <b>84</b>, network communications <b>85</b>, and video processing <b>86</b>, possibly including modem <b>87</b>, non-volatile memory like flash (or magnetic like MRAM or ovonic unified memory) <b>88</b>, system BIOS <b>88</b>′, digital signal processor (DSP) or processors <b>89</b>, and other components or present or future equivalents or successors) and internal bus, on a single chip <b>90</b> (silicon, plastic, or other), known in the industry as “system on a chip”. Such a PC microchip <b>90</b> can have the same architecture as that of the PC <b>1</b> shown above in <figref idref="DRAWINGS">FIG. 10A</figref>: namely, a master control and/or processing unit <b>93</b> and one or more slave processing units <b>94</b> (for parallel or multitasking processing by either the PC <b>1</b> or the Network <b>2</b>), separated by an internal firewall <b>50</b> and connected by broad bandwidth wire <b>99</b> such as optical fiber cable to a network computer <b>3</b> and the Internet <b>3</b> and successors like the Grid (or MetaInternet). Alternatively, microchip <b>90</b> can be an “appliance” system on a chip.

0110Existing PC components with mechanical components like hard drive <b>61</b>, floppy or other removable diskette <b>62</b>, CD-ROM <b>63</b>, and DVD <b>64</b>, which are mass storage devices with mechanical features that will likely not become an integral part of a PC “system of a chip” may still be capable of connection to a single PC microchip <b>90</b> and control by a single PC master unit <b>93</b>.

0111In the simplest multi-processor case, as shown in <figref idref="DRAWINGS">FIG. 10D</figref>, the chip <b>90</b> has a single master unit <b>93</b> and at least one slave unit <b>94</b> (with the master having a controlling function only or a processing function also), separated by an internal firewall <b>50</b> and connected by broad bandwidth wire <b>99</b> such as fiber optic cable to a network computer <b>3</b> and the Internet <b>3</b> (and successors like the Grid or MetaInternet). The other non-microprocessor components shown in <figref idref="DRAWINGS">FIG. 10A</figref> above may also be included in this simple <figref idref="DRAWINGS">FIG. 10D</figref> configuration.

0112As noted above, any computer may be both a user and provider, alternatively—a dual mode operating capability. Consequently, any PC <b>1</b> within the network <b>2</b>, connected to the Internet <b>3</b> and successors like the Grid (or MetaInternet), can be temporarily a master PC <b>30</b> at one time initiating a parallel or multitasking processing request to the network <b>2</b> for execution by at least one slave PC <b>40</b>, as shown in <figref idref="DRAWINGS">FIG. 10E</figref>. At another time the same PC <b>1</b> can become a slave PC <b>40</b> that executes a parallel or multitasking processing request by another PC <b>1</b>′ that has temporarily assumed the function of master <b>30</b>, as shown in <figref idref="DRAWINGS">FIG. 10F</figref>. The simplest approach to achieving this alternation is for both master and slave versions of the parallel processing software to be loaded in each or every PC <b>1</b> that is to share in the parallel processing, so each PC <b>1</b> has the necessary software means, together with minor operational modifications, such as adding a switching means by which a signaled request for parallel processing initiated by one PC <b>1</b> user using master software is transmitted to at least a second PC <b>1</b>, triggering its slave software to respond by initiating parallel processing.

0113As shown in <figref idref="DRAWINGS">FIGS. 10G and 10H</figref>, which are parallel to <figref idref="DRAWINGS">FIGS. 10E and 10F</figref>, the number of PC slave processors <b>40</b> can be increased to any virtually other number, such as at least about 4; as shown, the processing system is completely scalar, so that further increases can occur to, for example, about eight, about 16, about 32, about 64, about 128, about 256, about 512, about 1024, and so on; the PC master microprocessors <b>30</b> can also be increased.

0114In summary, as noted above relative to <figref idref="DRAWINGS">FIG. 10I</figref>, a PC <b>1</b> can function as a slave PC <b>40</b> and be controlled by a master controller <b>31</b>, which can be remote and which can have limited or no microprocessing capability, but can as well have similar or greater capability. Such a master controller <b>31</b> can be located on the PC user side of the internal firewall <b>50</b>, under the control of the PC user, while the microprocessors <b>40</b> reside on the network side of the internal firewall <b>50</b>. The master controller <b>31</b> may receive input from the PC user by local means such as keyboard, microphone, videocam or future hardware and/or software and/or firmware or other equivalent or successor interface means (as does a master processor <b>40</b>) that provides input to a PC <b>1</b> or microprocessor <b>30</b> originating from a user's hand, voice, eye, nerve or nerves, or other body part; in addition, remote access by telephone, cable, wireless or other connection may also be enabled by a hardware and/or software and/or firmware and/or other means with suitable security such as password controlled access. Similarly, relative to a PC “system on a chip”, a master controller unit (which could be capable of being accessed by the PC user through a remote controller <b>31</b>) with only a controlling capability can be located on the PC user side of the internal firewall <b>50</b>, under the control of the PC user, while the slave processor units <b>94</b> would reside on the network side of the internal firewall <b>50</b>.

0115<figref idref="DRAWINGS">FIGS. 10A-10C</figref> show PC <b>1</b> with an internal firewall <b>50</b> that is configurable through either hardware and/or software and/or firmware and/or other means; software configuration is easiest and most typical, but active motherboard hardware configuration is possible and may present some security advantages, including a use of manual or electromechanical or other switches or locks. <figref idref="DRAWINGS">FIG. 10A</figref> shows a CD-ROM <b>63</b>′ that has been placed by a PC user on the network side of an internal firewall <b>50</b> from a previous position on the PC user side of an internal firewall <b>50</b>, which was shown in <figref idref="DRAWINGS">FIG. 10A</figref>. The settings of an internal firewall <b>50</b> may default to those that safely protect the PC <b>1</b> from uncontrolled access by network users, but with capability for the relatively sophisticated PC user to override such default settings and yet with proper safeguards to protect the unsophisticated user from inadvertently doing so; configuration of an internal firewall <b>50</b> may also be actively controlled by a network administrator in a local network like that of a business, where a PC user may not be the owner or leaser of the PC being used, either by remote access on the network or with a remote controller <b>31</b>.

0116Similarly, <figref idref="DRAWINGS">FIGS. 10C and 10D</figref> show a PC “system on a chip” <b>90</b> with an internal firewall <b>50</b> that is configurable through either hardware and/or software and/or firmware and/or other means; software configuration is easiest and most typical. Active configuration of the integrated circuits of the PC microchip <b>90</b> is also possible and may present some speed and security advantages. Such direct configuration of the circuits of the microchip <b>90</b> to establish or change its internal firewall <b>50</b> could be provided by the use of field-programmable gate arrays (or FPGA's) or their future equivalents or successors; microcircuit electromechanical or other switches or locks can also be used potentially. For example, slave processing unit <b>94</b> can be moved to the PC user side of an internal firewall <b>50</b> from a network side position. The same active configuration of the chip circuit can use FPGA's for the simplest form of multiprocessing microchip <b>90</b> with a single slave unit <b>94</b>, transferring its position to the PC user's side of an internal firewall <b>50</b> from a network side as shown by slave processing units <b>94</b> in <figref idref="DRAWINGS">FIGS. 10C and 10D</figref>.

0117<figref idref="DRAWINGS">FIGS. 11G-11I</figref> show the applicant's new hierarchical network structure and function applied to the design of a personal computer PC <b>1</b>, as discussed previously in FIGS. 10A and 10B of the '049 Application. <figref idref="DRAWINGS">FIG. 11G</figref> shows the simplest general design, with a master M₁microprocessor <b>30</b> and two slave S₂₁and S₂₂microprocessors <b>40</b>. <figref idref="DRAWINGS">FIG. 11H</figref> shows the same network structure with an additional level of slave microprocessors <b>40</b>, S₃₁through S₃₄, while <figref idref="DRAWINGS">FIG. 11I</figref> shows the same network structure as <figref idref="DRAWINGS">FIG. 11H</figref> with an additional level of slave microprocessors <b>40</b>, S₄₁through S₄₈. As shown in these examples, this network structure is completely scalar, including any practical number of slave microprocessors <b>40</b> on any practical number of processing levels.

0118<figref idref="DRAWINGS">FIG. 11J</figref> shows a useful embodiment in which each microprocessor <b>30</b> and <b>40</b> has, in addition to internal cache memory, its own random access memory (RAM) <b>66</b> or equivalent memory (volatile like DRAM or non-volatile like Flash memory, magnetic such as MRAM memory, or ovonic unified memory), integrated on-microchip <b>90</b> or separate off-microchip. A significant amount of such microchip RAM (volatile like DRAM or non-volatile like Flash memory, magnetic such as MRAM memory, or ovonic unified memory), significantly greater than cache memory (SRAM) and other on-chip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but an on-microprocessor chip location for DRAM or Flash (or MRAM or ovonic memory), like cache (SRAM) memory, offers the best potential for improving microprocessor speed and efficiency. The design can also incorporate (or substitute) conventional shared memory or RAM <b>66</b>′ (i.e. memory used by all, or some, of the microprocessors <b>30</b> or <b>40</b> (or <b>90</b>) of the personal computer PC <b>1</b>).

0119<figref idref="DRAWINGS">FIGS. 11A-11C</figref> are parallel to <figref idref="DRAWINGS">FIGS. 11G-11I</figref> above, but show PC microprocessor <b>90</b> architecture rather than macro PC <b>1</b> architecture; a PC microprocessor <b>90</b> is as earlier described in <figref idref="DRAWINGS">FIG. 10C</figref>, a personal computer on a microchip.

0120<figref idref="DRAWINGS">FIG. 11D</figref> is like <figref idref="DRAWINGS">FIG. 11J</figref>, also except for showing PC microprocessor <b>90</b> architecture instead of PC <b>1</b> architecture. <figref idref="DRAWINGS">FIG. 11D</figref> shows a useful embodiment in which each PC microprocessor <b>93</b> or <b>94</b> has its own integrated on-microchip (or separate off microchip) random access memory (RAM) <b>66</b> or equivalent memory (volatile like DRAM or non-volatile, like Flash memory, magnetic such as MRAM memory, or ovonic unified memory). A significant amount of such RAM or other memory, significantly greater than cache (SRAM) memory or other on-microchip memory used on microprocessor chips today, can be beneficial in improving the efficient operation of the microprocessor; if located off-microprocessor chip, the size of such memory can substantially exceed the size of the associated microprocessor, but an on-microprocessor chip <b>90</b> location for DRAM or Flash (or MRAM or ovonic memory), like cache (SRAM) memory, offers the best potential for improving microprocessor speed and efficiency. The microchip design can also incorporate (or substitute) conventional shared memory or RAM <b>66</b>′ (i.e. memory used by all, or some, of the PC microprocessors <b>93</b> or <b>94</b> of the personal computer PC microprocessor <b>90</b>).

0121<figref idref="DRAWINGS">FIGS. 11A-11D</figref> show a different and improved basic microchip architecture which can exclude or reduce the currently used superscalar approach in microprocessors to execute multiple instructions during each clock cycle. The <figref idref="DRAWINGS">FIGS. 11A-11D</figref> architecture is much simpler and, by integrating memory with microprocessor, reduces memory bottlenecks. The simplicity of the <figref idref="DRAWINGS">FIGS. 11A-11D</figref> microchip design, which may have little or no superscalar components, compared to conventional superscalar designs (the inherent extreme complexity of which creates a very substantial memory overhead), can result in the use of a much greater proportion of independent, non-superscalar processors per microchip, exclusive of integrating memory or RAM <b>66</b> onto the microprocessor chip <b>90</b>, as discussed in <figref idref="DRAWINGS">FIG. 11D</figref>.

0122<figref idref="DRAWINGS">FIGS. 11G-11J</figref>, by using the same architecture for PC <b>1</b> networks as <figref idref="DRAWINGS">FIGS. 11A-11D</figref>, import the same advantage of microchip parallel processing performance to parallel processing in PC <b>1</b> networks.

0123<figref idref="DRAWINGS">FIG. 11K</figref> shows a direct connection of optical fiber <b>99</b> from Internet <b>3</b> (or another network) to random access memory (RAM) microchip <b>66</b>′. The connection may be at a central portion <b>140</b> of RAM chip <b>66</b>′ to provide equal access to stored data on RAM chip <b>66</b>′. The direct connection can be anywhere on RAM chip <b>66</b>′. Digital signal processor (DSP) <b>89</b> is on RAM chip <b>66</b>′ for connection with optical fiber <b>99</b>. RAM chip <b>66</b>′ is for shared memory use among PC's <b>1</b> and for broadcast use. RAM chip <b>66</b>′ can include volatile or non-volatile (flash-type) memory. RAM chip <b>66</b>′ can have more than one DSP <b>89</b>, such as shown in <figref idref="DRAWINGS">FIG. 20B</figref>.

0124All <figref idref="DRAWINGS">FIGS. 11A-11K</figref>, like the preceding figures of this application, show sections of a network of personal computers PC <b>1</b> (or PC microprocessors <b>90</b>) or microprocessors <b>30</b> or <b>40</b> which can be parts of the WWW or Internet or Internet II or the Next Generation Internet (meaning connected to it) or Intranets or Extranets or other networks.

0125Also, except for <figref idref="DRAWINGS">FIGS. 11A-11C</figref> and <b>11</b>G-<b>11</b>I, all of the <figref idref="DRAWINGS">FIG. 11</figref> series show personal computers PC <b>1</b> and microprocessors <b>30</b> or <b>40</b> as occupying the same location. This dual representation was done for economy of presentation and to show the parallel functionality and interchangeability in conceptual terms of personal computer PC <b>1</b> and microprocessors <b>30</b> or <b>40</b> in the structure of the new network. So, taking <figref idref="DRAWINGS">FIG. 16A</figref> as an example, M₁, S₂₁and S₂₂show three personal computers PC <b>1</b> or, alternatively, one microprocessor <b>30</b> and two microprocessors <b>40</b>.

0126As noted initially in <figref idref="DRAWINGS">FIG. 10C</figref>, a personal computer PC <b>1</b> can be reduced in size to a PC microprocessor chip <b>90</b>, so preceding Figures showing personal computer PC <b>1</b> also generally represent PC microprocessor chip <b>90</b>.

0127Finally, <figref idref="DRAWINGS">FIGS. 11A-11K</figref> show a mix of electrical and optical connections, including wired <b>99</b>, especially connections such as optical glass fiber or omniguides, and wireless <b>100</b>, especially wireless optical (and mixtures of both in a single figure), and dense wave division multiplexing (DWDM). Generally, either <b>99</b> or <b>100</b> or a mix can be used relatively interchangeably in the network inventions shown (as well as in prior figures), though in some embodiments either highest transmission speed (i.e. broadest bandwidth) or mobility (or some other factor) may dictate a use of wired or wireless. Generally, fiber optic wire <b>99</b> and dense wave division multiplexing (DWDM) may provide the most advantageous transmission means because it has the greatest bandwidth or data transmission speed, so it may be used for connections between personal computers and microchips, including direct connections, although optical wireless <b>100</b> also offers very high bandwidth, especially with dense wave division multiplexing (DWDM). Other wireless <b>100</b> (but also including optical wireless), including with DWDM, can be used where mobility is a paramount design criteria.

0128The <figref idref="DRAWINGS">FIG. 11</figref> embodiments can be combined with, or modified by incorporating, any other network system architectures (including client/server or peer to peer) or any other topologies (including ring, bus, and star) either well known now in the art or their future equivalents or successors.

0129Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 11A-11K</figref> can be combined with any one or more of the preceding or subsequent figures of this application to provide a useful improvement over the art.

0130The parallel processing network architecture shown in the preceding <figref idref="DRAWINGS">FIGS. 11A-11K</figref> and in earlier figures has several features unique to its basic design that provide for the security of personal computers PC <b>1</b> (or PC microprocessor <b>90</b>) or microprocessor <b>40</b> that share other computers for parallel and multi-tasking processing. First, the slave personal computers PC <b>1</b> (or microprocessors <b>40</b>) each have only part of the operation (for large operations, only a very small part) and therefore unauthorized surveillance of a single PC <b>1</b> can provide only very limited knowledge of the entire operation, especially in only a relatively local area in which switching or routing was employed. Second, the addresses of the slave personal computers PC <b>1</b> (or microprocessors <b>40</b>) are known or traceable, and therefore are not protected by anonymity (like hackers usually are) in case of unauthorized intervention. In addition, cryptography can be employed, with on microprocessor chip <b>30</b>, <b>40</b>, or <b>90</b> hardware <b>55</b> being used in some embodiments due to efficiency, although software and firmware can also be used, or a separate PC <b>1</b> hardware-based component <b>56</b> like an encryption microchip can be used; with either encryption component <b>55</b> or <b>56</b>, micro electromechanical locks can be used to prevent access other than by the direct physical user; other MicroElectroMechanical System (MEMS) devices located on microchips like PC<b>90</b> can be used for access prevention or other functions. Nonetheless, these inherent strengths can be substantially reinforced, as indicated in <figref idref="DRAWINGS">FIGS. 12B-12D</figref>.

0131<figref idref="DRAWINGS">FIG. 12A</figref> shows at least one internal firewall <b>50</b> performing its conventional function of keeping out intruders such as hackers from the Internet <b>3</b> from unauthorized access for either surveillance of, or intervention in, a user's personal computer PC <b>1</b> (or PC microprocessor <b>90</b>) or master microprocessor <b>30</b>.

0132<figref idref="DRAWINGS">FIG. 12B</figref> shows that, since Internet users can, as enabled by the applicant's network structure invention, use one or more of the slave microprocessors <b>40</b> of another's personal computer PC <b>1</b> (or PC microprocessor <b>90</b>) for parallel (or multi-tasking) processing, the at least one internal firewall <b>50</b> has a dual function in also protecting Internet <b>3</b> use (or other shared use on a network) from unauthorized surveillance or intervention by a PC <b>1</b> owner/user who is providing the shared resources. To maintain the privacy necessary to operate such a cooperatively shared network arrangement, unauthorized surveillance or intervention must be carefully prevented by hardware/software/firmware or other means.

0133<figref idref="DRAWINGS">FIG. 12C</figref> therefore shows master M personal computer PC <b>1</b> (or PC microprocessor <b>90</b>) using the slave S₂microprocessor <b>40</b> of a different personal computer, PC <b>1</b>′, which is available for Internet <b>3</b> (or other net) shared use, while internal firewall <b>50</b>′ blocks unauthorized access into PC <b>1</b>′ by PC <b>1</b> (although PC <b>1</b>′ owner/user can always interrupt a shared operation and take back control and use of slave S′ microprocessor <b>40</b>, which then triggers off-loading action to compensate, as discussed above in FIGS. 16I-16J of the '049 Application).

0134<figref idref="DRAWINGS">FIG. 12D</figref> is similar to <figref idref="DRAWINGS">FIG. 12C</figref>, but shows a PC microprocessor <b>90</b> with a slave microprocessor <b>94</b> being used by Internet <b>3</b> users (or other net), so that at least one firewall <b>50</b> serves both to deny access such as surveillance by master M microprocessor <b>93</b> to an Internet <b>3</b> parallel processing (or multi-tasking) operation on slave S microprocessor <b>94</b> and to deny access to master M microprocessor <b>93</b> by Internet <b>3</b> (or other net) users of slave S microprocessor <b>94</b>. At least one internal firewall <b>50</b> may be implemented by non-configurable hardware at the microchip level to provide protection against tampering with the internal firewall <b>50</b> by a PC <b>1</b> user, who has easier access to software or macro hardware such as PC motherboards to alter. PC <b>90</b> microchips may employ tamper-resistant construction or tamper-proof construction. As such, PC <b>90</b> microchips may be permanently locked by out-of-specification conditions or permanently destroyed by attempts at physical access.

0135Also, non-configurable hardware denying access from the network is the most immune to hacking from any outside source, including the Internet, and can therefore be used either for general protection or to protect an innermost kernel of the most confidential of personal files (such as passwords or financial data) and the most critical of operating system components, such as the system bios or access to file alternation.

0136At the same time, the <figref idref="DRAWINGS">FIG. 12</figref> and earlier embodiments provide a solution to digital rights management by providing a highly safe environment for the owners of digital versions of audio, video, and software copyrighted material. Such copyrighted material as movies, television, music, and application or operating system software may be decrypted and controlled on the network user side of the PC <b>1</b> or PC <b>90</b>, while the PC <b>1</b> user is denied access to the decrypted digital version of the copyrighted material. However, the network user can make the material viewable to the PC <b>1</b> user, but not copyable, via the PC <b>1</b> and PC <b>90</b> microchip architecture shown in <figref idref="DRAWINGS">FIGS. 10A and 10C</figref>.

0137Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 12A and 12B</figref> can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0138<figref idref="DRAWINGS">FIG. 13</figref> is like FIG. 20B of the '049 Application (and therefore also can be combined with <figref idref="DRAWINGS">FIGS. 11J and 11D</figref>, respectively), but show additionally that all microprocessors <b>30</b>, <b>40</b>, <b>93</b>, and <b>94</b> of PC <b>1</b> or PC <b>90</b>₁can have a separate input/output communication link to a digital signal processor (DSP) or other transmission/reception connection component. The additional communications linkages are shown as <b>141</b>, <b>142</b>, <b>143</b>, and <b>144</b>, which connect to M₁, S₁, S₂₁, and S₂₂, respectively, and connect to the network, including the Internet <b>3</b>, the WWW, the Grid, and equivalents or successors Like all preceding and subsequent figures, <figref idref="DRAWINGS">FIG. 13</figref> is a schematic architectural plan of the new and unique components of the parallel processing system invention disclosed in this application and can represent either physical connections or virtual relationships independent of hardware. <figref idref="DRAWINGS">FIG. 13</figref> shows an embodiment in which the additional linkages lead through the Internet <b>3</b> to microprocessors PC <b>90</b>₂₅-<b>90</b>₂₈.

0139The additional communications linkages <b>141</b>, <b>142</b>, <b>143</b>, and <b>144</b>, as well as the original linkages <b>111</b>, <b>112</b>, <b>113</b>, and <b>114</b> of <figref idref="DRAWINGS">FIGS. 20A and 20B</figref>, may have a bandwidth sufficiently broad to at least avoid constraining the processing speed of microprocessors <b>30</b>, <b>40</b>, <b>93</b>, and <b>94</b> connected to the linkages. The ultra high bandwidth of optical connections like optical fiber or omniguides or optical wireless may provide external connections between PC <b>1</b> and PC <b>90</b>₁microprocessors that are far greater than the internal electrical connections or buses of those microprocessors, for example, by a factor of 10, or 100, or 1000, which are already possible with optical fiber, or 1,000,000, which is possible with optical omniguides, which are not limited to a relatively smaller band of wavelengths using DWDM like optical fiber; future increases will be substantial since the well established rate of increase for optical bandwidth is much greater than that for microprocessor speed and electrical connections. Wireless optical antennas that are positioned on the exterior of houses, buildings, or mobile reception sites, instead of inside of glass or other windows, should significantly increase the number of optical wavelengths that can be sent or received by each of the wireless optical antennas; the entire connection is freespace optical wireless, which allows for greater dense wave division multiplexing (DWDM) and thereby greater bandwidth.

0140A major benefit of the embodiment shown in <figref idref="DRAWINGS">FIG. 13</figref> is that PC <b>1</b> and PC <b>90</b>₁can function like the <figref idref="DRAWINGS">FIG. 9</figref> embodiment to efficiently perform operations that are uncoupled, so that each microprocessor M₁, S₁-S₃₄can operate independently without microprocessors M₁, S₁, and S₂₁-S₂₂being idled, as they may be in <figref idref="DRAWINGS">FIG. 13</figref>. Another benefit is that for tightly coupled parallel operations, microprocessors M₁, S₁, and S₂₁-S₂₂can have broad bandwidth connections with microprocessors <b>30</b>, <b>40</b>, <b>93</b>, or <b>94</b> that are not located on PC <b>1</b> or PC <b>90</b>₁. Thus the embodiments shown in <figref idref="DRAWINGS">FIG. 13</figref> provide an architecture that allows PC <b>1</b> or PC <b>90</b>₁the flexibility to function in parallel operations either like <figref idref="DRAWINGS">FIG. 13</figref> embodiments or like the FIG. 9 embodiment of the '049 Application, depending on the type of parallel operation being performed. Studies indicate that single chip multiprocessors like PC <b>90</b>₁can also perform uniprocessor operations with a speed like that of uniprocessor architectures like wide-issue superscalar or simultaneous multithreading.

0141Like FIG. 20B of the '049 application, the embodiment of <figref idref="DRAWINGS">FIG. 13</figref> includes broad bandwidth connection to the Internet <b>3</b> by wired means such as optical connection by fiber optic cable or omniguide or optical wireless, although other wired or non-wired means can be used with benefit, and the use of DWDM or wideband CDMA is clearly advantageous. It should be noted that the architecture of the <figref idref="DRAWINGS">FIGS. 20 and 21</figref> embodiments may be particularly advantageous with ultrawideband communication connections.

0142Another advantage of the embodiments shown in <figref idref="DRAWINGS">FIGS. 14A and 14B</figref> when functioning in the FIG. 9 (of the '049 Application) form of loosely coupled or uncoupled parallel processing or multitasking is that if PC <b>1</b> or PC <b>90</b>₁is functioning as a web server and typically uses only one microprocessor to do so, it can quickly add mirror web sites using one or more additional microprocessors to meet increasing volume of visits or other use of the web site. This replication of web sites on additional microprocessors in response to increasing load can also be done using the <figref idref="DRAWINGS">FIG. 11</figref> form of tightly coupled parallel processing. PC <b>1</b> and PC <b>90</b>₁or any of their microprocessors <b>30</b>, <b>40</b>, <b>93</b>, and <b>94</b> or other components can also serve as a switch or a router, including other associated hardware/software/firmware network components.

0143Any of the embodiments shown in <figref idref="DRAWINGS">FIG. 13</figref> can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0144Binary tree configurations of microprocessors shown in <figref idref="DRAWINGS">FIGS. 11</figref>, and <b>13</b> can be laid out in 2D using an H-tree configuration, as shown in FIG. 21C of the '049 Application, and can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0145<figref idref="DRAWINGS">FIG. 14A</figref> shows a microprocessor PC <b>90</b>₁like that of <figref idref="DRAWINGS">FIG. 13</figref>, except that <figref idref="DRAWINGS">FIG. 14A</figref> shows the microprocessors <b>93</b> and <b>94</b> each connecting to an optical wired interconnection <b>99</b>′ such as thin mirrored hollow wire or omniguide or optical fiber (and other very broad bandwidth connections can be used); the interconnect can include a digital signal processor <b>89</b>′ employed with a microlaser <b>150</b>, which can be tunable, and other components to transmit and receive digital data for microprocessors <b>93</b> and <b>94</b> into the optical wired interconnects <b>99</b>′ such as an omniguide using, for example, a specific wavelength of light for each separate channel of each separate microprocessor <b>93</b> and <b>94</b> utilizing dense wave division multiplexing (DWDM).

0146<figref idref="DRAWINGS">FIG. 14B</figref> shows an enlargement of the digital signal processor <b>89</b>′ with microlaser <b>150</b> with other transmission and reception components.

0147<figref idref="DRAWINGS">FIG. 14A</figref> shows a simple bus network connection architecture between the interconnect <b>99</b>′ and the microprocessors <b>93</b> and <b>94</b>. However, since the interconnection <b>99</b>′ is optical and the bandwidth available is very broad, the optical connection <b>99</b>′ allows connections between microprocessors <b>93</b> and <b>94</b> in PC <b>90</b>₁that are functionally equivalent to those shown in FIG. 13 of the '049 Application, which includes a representation of physical connections. The interconnects between microprocessors <b>93</b> and <b>94</b> like <figref idref="DRAWINGS">FIG. 13</figref> are shown within the omniguide <b>99</b>′ shown in <figref idref="DRAWINGS">FIG. 14A</figref>. In fact, the potential bandwidth of the optical interconnect <b>99</b>′ is so great that complete interconnection between all microprocessors <b>93</b> and <b>94</b> with PC <b>90</b>₁is possible, even for a much greater number of microprocessors either in a larger PC <b>90</b>₁, like <figref idref="DRAWINGS">FIG. 11C</figref> for example, or in other PC <b>90</b>s, such as PC <b>90</b>₂₁-<b>90</b>₂₄and <b>90</b>₃₁-<b>90</b>₃₁₆in <figref idref="DRAWINGS">FIG. 13</figref> connected to PC <b>90</b>₁through a network such as the Internet <b>3</b>, the WWW, or the Grid; consequently, any conventional network structure can be implemented. Consequently, the embodiment shown in <figref idref="DRAWINGS">FIG. 14A</figref> has the flexibility of those of <figref idref="DRAWINGS">FIG. 13</figref> to function in parallel operations like either the FIGS. 20A-20B embodiments or like the FIG. 9 embodiment (both of the 0.049 Application), depending on the type of parallel operation to be performed, or the <figref idref="DRAWINGS">FIG. 11</figref> embodiments.

0148It should be noted that the optical interconnect <b>99</b>′ shown in <figref idref="DRAWINGS">FIG. 14A</figref> can beneficially have a shape other than a thin wire or tube, such as an omniguide with any form or shape located above and connection to microlasers <b>150</b> at a suitable location such as on or near the upper surface of the microchip PC <b>90</b>₁located at least at each microprocessor <b>93</b> and <b>94</b> or connected thereto, for example; the optical interconnect <b>99</b>′ and microlasers <b>150</b> and associated transmission and reception components can be located elsewhere on the microchip PC <b>90</b>₁with benefit. An omniguide can take a waveform shape or rely exclusively on a mirrored (or semi-mirrored) surface or surfaces (or combination of both shape and mirrored surface) to guide lightwave signals such as propagated by a microlaser <b>150</b> substantially directly and/or by reflection. A relatively large optical interconnect <b>99</b>′ can enable freespace or wireless-like connections between microlasers <b>150</b>; such an optical interconnect <b>99</b>′ can cover substantially the entire PC<b>90</b> microchip or can connect multiple PC<b>90</b> microchips and can connect one or more PC<b>90</b> microchips to other PC components.

0149As shown in <figref idref="DRAWINGS">FIG. 14A</figref>, random access memory (RAM) <b>66</b> can be located on microchip PC <b>90</b>₁like in <figref idref="DRAWINGS">FIG. 11D</figref> and also can be connected directly or indirectly to the optical interconnect <b>99</b>′ (or use non-optical connections not shown), so that the microprocessors <b>93</b> and <b>94</b> and RAM <b>66</b> can communicate with a very broad bandwidth connection, including with RAM <b>66</b> and microprocessors <b>93</b> and <b>94</b> located off microchip PC <b>90</b>₁on the network including the Internet <b>3</b> and WWW. Any other components of the PC <b>90</b> microchip can be connected with the optical interconnect <b>99</b>′ and more than one such interconnect <b>99</b>′ can be used on the same PC <b>90</b> or other microchip. Microlasers <b>150</b> can include, for example, 5-to-20-micron-high (or other height) vertical cavity-surface-emitting lasers (VCSELs), which can beam down waveguides built into the PC<b>90</b> microchip; alternatively, freespace optics can be employed; and lenses can be employed. Radio-frequency (RF) signals can also be used for similar interconnects <b>99</b>′. Micro light emitting diodes (LEDs) can substitute for one or some or all of the microlasers <b>150</b> and either can be a transceiver (transmit and receive light signals).

0150<figref idref="DRAWINGS">FIG. 14C</figref> is a side cross section of the microchip PC <b>90</b>₁shown in <figref idref="DRAWINGS">FIG. 14A</figref> taken at hatched line <b>22</b>C (which is abbreviated). <figref idref="DRAWINGS">FIG. 14C</figref> shows the location of the omniguide above the surface of the microprocessors <b>93</b> and <b>94</b> and RAM <b>66</b> and connecting them while also containing two or more microlasers <b>150</b> (associated DSP and other components not shown) proximate to each to contain the optical signal generated by the microlasers <b>150</b> so that the signal can be transmitted between microprocessors <b>93</b> and <b>94</b> and RAM <b>66</b> either directly or by being reflected off the mirrored (or semi-mirrored) surface of the omniguide <b>99</b>′, for example. Each of the microprocessors <b>93</b> and <b>94</b> (or <b>30</b> or <b>40</b>) and RAM <b>66</b> (or any other memory component such as L1 cache or L2 cache, for example, or other microchip component) can have one or more microlasers <b>150</b> and each such microlaser <b>150</b> can distinguish itself from other microlasers <b>150</b> on the microchip (or off it) that also generate wavelength signals by using, for example, a distinct wavelength of light for data transmission and/or utilizing wave or dense wave division multiplexing. <figref idref="DRAWINGS">FIG. 14A</figref> is a top view of the microchip PC <b>90</b>₁, which is a PC system on a microchip, any of which disclosed in this application can be also more generally any microchip with multiple processors. The microlasers <b>150</b> (and associated transmission and reception components such as DSP) that are associated with RAM (or parts of it) or other memory components can either provide data in response to direct inquiries or fetches made by a microprocessor <b>93</b> or <b>94</b> or can broadcast a continual stream of current data (continually updated and repeated in continuous cycle, for example) which is used by the microprocessor as needed.

0151Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 14A</figref>, <b>14</b>B and <b>14</b>C can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0152<figref idref="DRAWINGS">FIG. 15A</figref> shows multiple firewalls <b>50</b>, a concept indicated earlier by the at least one firewall <b>50</b> discussed in <figref idref="DRAWINGS">FIG. 12D</figref>. <figref idref="DRAWINGS">FIG. 15A</figref> shows a PC<b>1</b> or microchip <b>90</b> with a primary firewall <b>50</b> and additional interior firewalls <b>50</b>¹, <b>50</b>², and <b>50</b>³, that are within primary firewall <b>50</b>. As shown, interior firewall <b>50</b>³is in the most protected position, since it is inside all the other firewalls, while the other interior firewalls <b>50</b>², and <b>50</b>¹are progressively less protected, since, for example, interior firewall <b>50</b>¹is protected from the outside network only by the primary firewall <b>50</b>. As shown, progressively more protected positions can be created within the PC<b>1</b> or microchip <b>90</b>. The interior firewalls can also be arranged in any other way within the primary firewall <b>50</b>. The interior firewalls can be used to separate user files from system files, for example, or to separate various hardware components from each other. In this manner, a number of compartments can be created within the PC<b>1</b> or microchip <b>90</b> to more safely protect the software, hardware, and firmware of the PC<b>1</b> or microchip <b>90</b>, just as ships have a number of separate watertight compartments to protect against flooding and avoid sinking. Any of the primary or interior (or other inner firewalls discussed below) can be hardware, software, or firmware, or a combination, and can coexist in layers, so that a firewall <b>50</b>, for example, may have a hardware firewall, a software firewall, and a firmware firewall, either as independent units or as integrated components. W³in <figref idref="DRAWINGS">FIG. 15A</figref> and subsequent Figures denotes the World Wide Web.

0153<figref idref="DRAWINGS">FIG. 15B</figref> shows another embodiment of compartments created by inner firewalls within a PC<b>1</b> or microchip <b>90</b>. Primary firewall <b>50</b> and interior firewall <b>50</b>¹are like <figref idref="DRAWINGS">FIG. 15A</figref>, but interior firewalls <b>50</b>², <b>50</b>³, and <b>50</b>⁴are shown perpendicular to firewalls <b>50</b> and <b>50</b>¹(just to illustrate in a simplified schematic way, which may be different in an actual embodiment). In this way, an upper row of compartments U¹and U²can be used, for example, to bring from the network files which are first authenticated and then enter into the U¹compartment, are decrypted, and undergo a security evaluation, such as by virus scan, before transfer to the most secure compartment U². Any operations could potentially occur in any compartment, depending on the level of security desired by the user (by over-ride) for example, but an advantageous default system would allow for files with the highest levels of authentication, encryption, and other security evaluations to be allowed into the most secure compartments.

0154Similarly, operating system files can also be authenticated and brought from the network side of the PC<b>1</b> or microchip <b>90</b> into compartment O¹for decryption and security evaluation or other use, and then finally transferred into the most secure compartment O². Again, similarly, a row of compartments can be used for separating hardware, such as a master microprocessor <b>30</b> or <b>93</b> being located in compartment M¹and a remote controller <b>31</b>, for example, located in compartment M².

0155Also, additional inner firewalls <b>50</b>²², <b>50</b>³³, and <b>50</b>⁴⁴can be located outside the primary firewall <b>50</b>, but within the network portion of the PC<b>1</b> or microchip <b>90</b>, to separate user files in compartment U from operating system files in compartment O from hardware such a slave microprocessor in compartment S on the network side. In the example shown, an additional row is shown for hardware, including a hard drive in a compartment HD on the network side, a hard drive in compartment HD¹on the PC<b>1</b> or microchip <b>90</b> user's side, and flash memory (such as system bios <b>88</b>) in compartment F². Each microprocessor <b>30</b>, <b>40</b>, <b>93</b>, or <b>94</b> can have its own compartment in a manner like that shown in <figref idref="DRAWINGS">FIG. 15B</figref>, as can associated memory or any other hardware component.

0156<figref idref="DRAWINGS">FIG. 15C</figref> shows an inner firewall <b>50</b> embodiment similar to <figref idref="DRAWINGS">FIG. 15B</figref>, but <figref idref="DRAWINGS">FIG. 15C</figref> shows that any file or set of files, such as operating files O or user data files U or application files A, can have its own inner firewall <b>50</b>^Oor <b>50</b>^Uor <b>50</b>^A. Similarly, any hardware component, such as hard drive HD, also can have its own inner firewall <b>50</b>^HD. Additionally, more than one file or set of files or hardware components can be grouped together within an inner firewall, such as <b>50</b>^Sshown in <figref idref="DRAWINGS">FIG. 15C</figref>.

0157<figref idref="DRAWINGS">FIGS. 15D and 15E</figref> show operating system files O or application files A like those shown in <figref idref="DRAWINGS">FIG. 15C</figref>, but organized differently in discrete layers, each separate grouping of the operating or application files having a separate firewall <b>50</b> (and optionally with as well as a PC<b>1</b> or PC<b>90</b> firewall shown in earlier Figures), so that the firewall structure is like that of an onion. The operating system files O or application files A can have a parallel structure, with an innermost kernel operating system or application file located in the center, with additional features in other files in subsequent layers, from the simplest to the most complex and from the most secure and trusted to the least secure and trusted.

0158Using this structure, as shown in <figref idref="DRAWINGS">FIG. 15D</figref>, an innermost operating system core O¹may be firmware stored in a read-only memory (ROM), located in a microchip for quick access, so that a simplest version operating system with all core features can be protected absolutely from alteration and can be available almost immediately, without lengthy boot up procedures required by loading the operating system from a hard drive, for example. The core operating system O¹can include a core of the system BIOS or of the operating system kernel, for example; it would be advantageous for this core to be capable of independent operation, not dependent on components in other levels to operate at the basic core level (similarly, other levels can advantageously be independent of higher levels).

0159A secondary operating system O²can be software located advantageously on flash or other microchip non-volatile memory such as magnetic (or less advantageously, a hard drive or other mechanical storage media) and can consist of additional features that are more optional, such as those not always used in every session, or features that require updating, changing, or improving, such features coming from trusted sources located on a network, such as the Internet or the Web; additional portions of or upgrades to the system BIOS and the operating system kernel can be located in O², for example.

0160A third level operating system O³located, for example, on a hard drive, can consist of additional software features that are used only occasionally and are more optional, and can be loaded as needed by a user into DRAM or magnetic memory microchip for execution, for example. Operating systems O²and O³can include, for example, the most recent upgrades from a known and trusted source, such as a commercial software vendor or open source software developer, that are downloaded from a network, including the Internet and the Web, or loaded from conventional memory media like CD or floppy diskette. All three levels of such operating systems O¹, O², and O³together can constitute, for example, roughly the equivalent of a conventional PC operating system typical in the year 2000.

0161A fourth level operating system O⁴, for example, can consist of special use or single use operating system add-ons, especially software coming from untrusted or unauthenticated sources on a network, such as the Internet or the Web.

0162For example, the graphical interface of the operating system can be in 2D only at the O¹level, in 3D at the O²level, rendering at the O³level, and animation in the O⁴level; additionally, a standard format can be maintained in the O¹and O²levels, with user or vender customization at the O³level.

0163As shown in <figref idref="DRAWINGS">FIG. 15E</figref>, application files such as A¹, A², A³, and A⁴can be structured the same way as operating system files O in <figref idref="DRAWINGS">FIG. 15D</figref> and with the same layered approach to firewalls <b>50</b> as in <figref idref="DRAWINGS">FIG. 15D</figref>. Typical application software of the year 2000 can be restructured in this manner.

0164The kernel operating system files O¹and O², as well as kernel application files A¹and A²can be located in any personal computer PC<b>1</b> or PC<b>90</b>, including at the level of an appliance including the simplest device, advantageously in ROM and in non-volatile read/write memory such as Flash (or magnetic such as MRAM, or ovonic memory) microchips, for example, as described in <figref idref="DRAWINGS">FIGS. 15D and 15E</figref> above. Inclusion of wireless connection capability is advantageous, as is the use of DWDM.

0165An advantage of the file and firewall structures shown in <figref idref="DRAWINGS">FIGS. 15D and 15E</figref> is that a system crash or file corruption should never occur at the simple and unalterable level O¹or A¹and any level above O¹or A¹can be recovered at a lower level, specifically the highest level at which there is a stable system or uncorrupted data. For example, a word processing application program can have the most basic functions of a typewriter (i.e. storing alphanumeric, punctuation, spacing, and paragraph structure data) stored on a ROM microchip in A¹and related user files (i.e. such as a word document) on U². Insertion of a digital video file into a word document can be handled at the A³level and insertion of a downloaded special effect at the A⁴level. In this example, a crash caused by the insertion at the least secure and most complex A⁴level would not disturb the word document located at the U²or U³level. Rebooting and/or recovery can be automatic when detected by the operating system or at the option of the user.

0166Thus, <figref idref="DRAWINGS">FIGS. 15A-15E</figref> illustrate embodiments wherein a PC<b>1</b> or microchip <b>90</b> includes a hierarchy of firewalls. In the context of the present invention, firewalls may be structured to allow varying degrees of access from the network side of PC<b>1</b> or microchip <b>90</b>. As discussed above, ROM may totally deny access from the network side, effectively creating an innermost firewall. Hardware, software, firmware, or combinations thereof may be structured to deny or allow a predetermined maximum level of access from the network side, effectively creating outer firewalls. Similarly, intermediate firewalls effectively may be created.

0167The embodiments of <figref idref="DRAWINGS">FIGS. 15A-15E</figref>, as well as earlier <figref idref="DRAWINGS">FIGS. 12A-12D</figref> and earlier embodiments, provide a solution to digital rights management by providing a highly safe environment for the owners of digital versions of audio, video, and software copyrighted material. Such copyrighted material as movies, television, music, and application or operating system software may be decrypted and controlled on the network user side of the PC <b>1</b> or PC <b>90</b>, while the PC <b>1</b> user is denied access to the decrypted digital version of the copyrighted material. However, the network user can make the material viewable to the PC <b>1</b> user, but not copyable, via the PC <b>1</b> and PC <b>90</b> microchip architecture shown in <figref idref="DRAWINGS">FIGS. 10A and 10C</figref>. For example, a copyrighted movie or music album may be a file that is associated with control and other software; all files located on one or more specific hardware components may be grouped together within an inner firewall, such as <b>50</b>^Sshown in <figref idref="DRAWINGS">FIG. 15C</figref>.

0168Additional security for copyright owners may be provided by using a digital signal processor (DSP), and/or analog and/or other components grouped within the inner firewall <b>50</b>^Sto convert network user selected decrypted digital files into analog files before they are transmitted off the PC <b>90</b> microchip, so that only an analog signal exits the PC <b>90</b> microchip for viewing or listening by the PC <b>1</b> user. As such, direct digital copying by the PC <b>1</b> user of copyrighted digital files provided over the Internet is prevented.

0169Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 15A-15E</figref> can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0170Additionally, an inner firewall can divide any hardware component into a separate network side compartment and a separate firewall protected side compartment. For example, a hard drive <b>61</b> can have a controller <b>61</b>′ that is divided into two compartments, HD and HD¹, as above. As shown in FIG. 24 of the '049 Application, the user side HD¹compartment of the controller <b>61</b>′ can have a read capability controller r and a write capability controller w, while the network side HD compartment can be limited to a read capability controller r only. The user side HD¹compartment controller can be, for example, used to control only the upper surface of the hard drive <b>61</b> platters, while the network side HD compartment controller can be used to control only the lower surface of the hard drive <b>61</b> platters, so that a single hard drive can effectively serve a dual role as both a network-accessible hard drive and a user-accessible hard drive, while maintaining a firewall <b>50</b> between them. Additionally, the network side HD controller can optionally have a write capability also, which can be preemptively turned on or off by the PC<b>1</b> or microchip <b>90</b> user. Other relative allocations between network and user of the HD <b>61</b> platters can be made and can be configurable by the user or system administrator or not configurable.

0171Similarly, CD drives <b>63</b> or DVD drives <b>64</b> (read only or read/write) can have a controller <b>63</b>′ or <b>64</b>′ like that of the HD controller <b>61</b>′ above that is divided by a firewall <b>50</b>, so that some laser beams are under network control and other laser beams are under user control, like the above hard drives. Floppy disk drives, “Zip” drives, and other removable disk or diskette drives can similarly be divided by a firewall <b>50</b> so that there is a physical user portion of the disk or diskette and a physical network portion of the disk or diskette, both either fixed or configurable by a user or system administrator or other authorized source. Memory microchips such as RAM or Flash or other can also be divided into network and user sides in a similar manner.

0172The use of volatile memory on the network side of the PC<b>1</b> or microchip <b>90</b> is particularly useful in eliminating viruses and other security problems originating from the network side, such as malicious hackers on the Internet. When the network side of the firewall <b>50</b> of the PC<b>1</b> or microchip <b>90</b> is returned to its user (preemptively or otherwise), volatile memory like random access memory (RAM) such as DRAM on the network side can first be erased. For example, volatile memory can be purged by momentarily interrupting power to the network side of the PC<b>1</b> or microchip <b>90</b>, thereby erasing all network data so that no network data is retained when the user regains control of the network side of the PC<b>1</b> or microchip <b>90</b> for the user's use, except at the user's option; other conventional means may be employed. Of course, when the user is specifically using the network side, for example, for Web browsing, the operating system or the user can selectively save network side files or transfer them to the user side.

0173On the network side, non-volatile memory like Flash, MRAM, and ovonic memory with network data must be overwritten to obtain the same erasure-type protection, which can be a disadvantage if it takes much more time. Moreover, for relatively large storage media, such as CD-RW or DVD-RW with write-once capability, network data writing must be tracked to be effectively erased. Any new network file on non-volatile memory with only a write-once capability can be erased by overwriting all “0's” to “1's”, so that, for example, the network data written on a CD-RW or DVD-RW would be converted to all “1's” or “pits” (no unpitted writing surface within the network data sector, permanently overwriting the file); optionally, the operating system or the user can selectively save network side files or transfer them to the user side, or vice versa. There is a disadvantage to using Flash memory, since repeated overwriting will eventually degrade it.

0174<figref idref="DRAWINGS">FIGS. 16A-16D</figref> show the use for security of power interruption or data overwrite of volatile memory like DRAM and non-volatile memory like Flash or MRAM (or ovonics), respectively, of the network portion (N) of a personal computer PC<b>1</b> or system on a microchip PC<b>90</b>; the network (N) portion being created within a PC<b>1</b> or PC<b>90</b> by a firewall <b>50</b> (as described above in previous figures) and including resources that, when idled by a user, can be used by the network, including the Internet (I) or the World Wide Web. Such use is to prevent the unplanned or approved mixture of user and network files by either files being retained in the “swing space” (N) during the transition from use by a network user to use by the PC<b>1</b>/PC<b>90</b> user or vice versa.

0175As shown in <figref idref="DRAWINGS">FIG. 16A</figref> and <figref idref="DRAWINGS">FIG. 16C</figref>, when the network portion (N) of the PC<b>1</b> personal computer or PC<b>90</b> microchip is idled by a user, for example, power is interrupted to volatile memory like DRAM and/or data is overwritten to files in non-volatile memory like Flash or MRAM (or ovonics), so that no files exist in the network portion (N) after such interruption or overwriting.

0176After the step shown in <figref idref="DRAWINGS">FIGS. 16A and 16</figref> C, the network portion (N) can be used safely from a security viewpoint by a user from the network, including the Internet and the World Wide Web (and potentially including other network resources), as shown in <figref idref="DRAWINGS">FIG. 16B</figref>, or by the PC<b>1</b>/PC<b>90</b> user, as shown in <figref idref="DRAWINGS">FIG. 16D</figref>, potentially including other resources from the user portion (U) of the PC<b>1</b> or PC<b>90</b>. As noted earlier, the <figref idref="DRAWINGS">FIG. 16</figref> approach can advantageously be used as an additional feature to other conventional security measures.

0177Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 16A-16D</figref> can be combined with one or more of any of the preceding figures of this application to provide a useful improvement over the art.

0178The PC <b>90</b> microchip as previously described, or a personal computer PC <b>1</b> (or any microchip, including a special or general purpose microprocessor on a microchip, alone or including one or more other system components as previously described) may include one or more photovoltaic cells <b>201</b>, as are well known in the art. The photovoltaic cells <b>201</b> may be located on the PC <b>90</b> microchip or located near the PC <b>90</b> microchip, such as adjoining it or adjacent to it, or located less near, such as in the PC <b>90</b> microchip user's home, office, or vehicle, either inside or outside, or may be located more remotely.

0179<figref idref="DRAWINGS">FIG. 17A</figref> shows one or more photovoltaic cells <b>201</b> located on a PC <b>90</b> microchip. The photovoltaic cells <b>201</b> may use electromagnetic radiation, such as visible light, as a power source that is directed to the cells <b>201</b> by an optical waveguide <b>202</b>, which may include a size that is sufficient to allow the cells <b>201</b> to generate electrical power at maximum output level or at a most efficient level. In addition, visible light in freespace (without a waveguide <b>202</b>) may also serve as a power source and can be directed by the use of one or more lenses <b>204</b>.

0180<figref idref="DRAWINGS">FIG. 17B</figref> shows a single microchip <b>200</b> including both a PC <b>90</b> and one or more photovoltaic cells <b>201</b>. <figref idref="DRAWINGS">FIG. 17B</figref> shows a top view of a multi-layer microchip having one or more photovoltaic cells <b>201</b> on one side of a microchip <b>200</b>, with a PC <b>90</b> on the other side of the microchip <b>200</b>, as shown in <figref idref="DRAWINGS">FIG. 17C</figref> in a bottom view of the same microchip as <figref idref="DRAWINGS">FIG. 17B</figref>. Besides being integrated on the same microchip <b>200</b>, the photovoltaic cells <b>201</b> may be located separately from the PC <b>90</b> microchip, and the two separate elements may be joined or adjoining.

0181A light source for the photovoltaic cells <b>201</b> can be direct or indirect and can be sunlight or artificial light, including light from a laser, or a combination, and can be optionally focused by a lens <b>204</b>. The light may be coherent with one or more discrete frequencies, such as from a laser, or incoherent with many frequencies. The artificial light may be generated by well known conventional means that are conventionally powered by electricity distributed by the existing electrical power grid, as is well known in the art.

0182A single photovoltaic cell or a number of cells <b>201</b> may power each component on the PC <b>90</b> microchip, such as the master microprocessor <b>93</b> or slave microprocessors <b>94</b>, DRAM or MRAM, Flash memory, DSP, or laser <b>150</b>, or any of the other components previously described. The photovoltaic cells <b>201</b> may be connected to one or more batteries. The photovoltaic cells <b>201</b> can be located remotely as a separate unit, such as on the PC <b>90</b> microchip user's roof at home, car, or office, so that the cells <b>201</b> provide general local power or power dedicated to the PC <b>90</b> microchip and/or associated components. The PC <b>90</b> microchip may be a network server, router, or switch, so that any network component can be powered by photovoltaic cells <b>201</b>, including the Internet, an Intranet, or the World Wide Web.

0183The <figref idref="DRAWINGS">FIG. 17A-17C</figref> embodiments advantageously eliminate the need for a microchip, such as the PC <b>90</b> microchip, to have a wired connection <b>99</b> that typically provides power or data or both, but which also provides a connection means for the entry of electromagnetic flux, which can impair or destroy the functioning of the PC <b>90</b> microchip. The embodiments shown rely on light, which does not transmit electromagnetic flux, for power and data.

0184<figref idref="DRAWINGS">FIG. 18A</figref> shows a single microchip <b>200</b>, combining a PC <b>90</b> microchip (or any microchip, including a special or general purpose microprocessor on a microchip, alone or including one or more other system components as previously described) and one or more photovoltaic cells <b>201</b>, that is substantially surrounded by a Faraday Cage <b>300</b>, such as is well known in the art, that is optimized to shield against magnetic flux, including high frequency flux (and may include shielding against electric flux). Faraday Cage <b>300</b> may be constructed of a mesh structure, or may also be a continuous structure without holes, which has an advantage of preventing entry by very high frequency electromagnetic flux, and may incorporate other microchip structures, such as a heat sink <b>301</b>.

0185<figref idref="DRAWINGS">FIG. 18B</figref> shows separate PC <b>90</b> microchip and one or more photovoltaic cells <b>201</b>; the two separate components are connected by a wire <b>99</b>, and all three components are substantially surrounded by a Faraday Cage <b>300</b>, also known as a Faraday Shield or Screen.

0186<figref idref="DRAWINGS">FIG. 18C</figref> shows the same components as <figref idref="DRAWINGS">FIG. 18B</figref>, but shows each component substantially surrounded by a separate Faraday Cage <b>300</b>, all of which may be connected. For portable handheld wireless devices, the ground for the Faraday Cage <b>300</b> may be the user's body.

0187As shown in <figref idref="DRAWINGS">FIG. 18D</figref>, the PC <b>90</b> microchip may be located in a housing for any of the PC's described previously, such as a case of a laptop personal computer <b>401</b> or a PC cell phone <b>402</b>, which may also have a separate Faraday Cage <b>300</b>, so that the PC <b>90</b> microchip is substantially surrounded by more than one Faraday Cage <b>300</b>. The inner Faraday Cage <b>300</b> surrounding the PC <b>90</b> microchip may be optimized to shield against specific frequencies of magnetic flux, such as high frequency flux in the microwave range, which may be assisted by the relatively smaller size of the PC <b>90</b> microchip (compared to its housing). <figref idref="DRAWINGS">FIG. 18D</figref> shows an inner Faraday Cage <b>300</b> surrounding only a portion, the PC <b>90</b>, of a microchip such as the combined microchip <b>200</b>.

0188As shown in <figref idref="DRAWINGS">FIGS. 18E and 18F</figref>, the PC <b>90</b> microchip can be separate from the photovoltaic cell or cells <b>201</b> and can be joined by a wired connection <b>99</b>.

0189As shown in <figref idref="DRAWINGS">FIG. 18E</figref>, an inner Faraday Cage <b>300</b> may surround only a portion of a PC <b>90</b> microchip, such as a Magnetic Random Access Memory (MRAM) component.

0190<figref idref="DRAWINGS">FIG. 18F</figref> shows Faraday Cage <b>300</b> that surrounds only a portion of one or more photovoltaic cells <b>201</b>, such as a part conducting an electrical current flow directly to the PC <b>90</b> microchip.

0191The PC <b>90</b> microchip may also be powered by one or more fuel cells <b>211</b> or one or more batteries (each with one or more cells) <b>221</b> or any combination of such batteries <b>221</b>, fuel cells <b>211</b>, or photovoltaic cells <b>201</b>. As shown in <figref idref="DRAWINGS">FIGS. 18E and 18F</figref>, the PC <b>90</b> microchip is typically separate from a fuel cell or cells <b>211</b> or batteries <b>221</b> and can be joined by a wired connection <b>99</b>, as shown, as is the case with a photovoltaic cell or cells <b>201</b>. A wired connection <b>99</b> can be configured to protect the PC <b>90</b> microchip from electromagnetic flux through the use of RF traps or Ferrite grommets or beads <b>212</b> on the wire or cable connection <b>99</b>.

0192By providing power without an external wired connection <b>99</b>, both fuel cells <b>211</b> and batteries <b>221</b> isolate the PC <b>90</b> microchip from a power grid that can transmit electromagnetic flux, but to do so a battery or batteries <b>221</b> can be configured to provide connection to the power grid only intermittently when charging is required.

0193<figref idref="DRAWINGS">FIG. 18G</figref> shows a microchip, such as a PC <b>90</b> microchip, surrounded by a Faraday Cage <b>300</b> but without including a photovoltaic cell <b>201</b> shown in <figref idref="DRAWINGS">FIGS. 18A-18F</figref>.

0194<figref idref="DRAWINGS">FIG. 18H</figref> shows a PC housing such as a laptop PC <b>401</b> or PC cell phone <b>402</b> including a PC <b>90</b> microchip and separate Faraday Cages <b>300</b> surrounding both the microchip and housing. Also shown is an antenna <b>499</b> (or antennas) for wireless communication that can be separated from the Faraday Cage <b>300</b> to protect the electrical components of the PC by an RF trap or Ferrite grommets or beads <b>212</b>. The antenna <b>499</b> can project externally from the PC housing or be located internally in the PC housing, such as in the screen housing of a laptop PC <b>401</b>. In an exemplary implementation, the antenna <b>499</b> is located outside of at least one Faraday Cage <b>300</b>.

0195Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 17A-17C</figref> and <b>18</b>A-<b>18</b>H may be combined with one or more other embodiments shown in those figures or in preceding <figref idref="DRAWINGS">FIGS. 1-16</figref> and described herein.

0196<figref idref="DRAWINGS">FIG. 19</figref> shows a silicon wafer <b>500</b> used to make microchips. The largest wafers <b>500</b> in current use are 300 mm (12 inches) in diameter and can contain as many as 13 billion transistors. Current state of the art in microchip fabrication is 0.13 micron process technology and the next process will be measured in nanometers (90 nm). As shown in <figref idref="DRAWINGS">FIG. 19</figref>, microchips <b>501</b> are separated by an edge portion <b>502</b>. A microchip <b>501</b> can be a PC <b>90</b> microchip.

0197<figref idref="DRAWINGS">FIG. 20A</figref> shows a top view of a microchip <b>501</b> surrounded by adjoining portions of adjoining microchips <b>501</b> in a section of the silicon wafer <b>500</b>. The microchip <b>501</b> is bounded by edge portions <b>502</b>. Although the current state of the art in microchip fabrication on a silicon wafer is to use only one process on a wafer, embodiments of the invention use two or more fabrication processes on a single wafer <b>500</b>.

0198As shown in the example of <figref idref="DRAWINGS">FIG. 20A</figref>, one process can be located on one section <b>511</b> on the microchip <b>501</b>, while a second process can be located on a second section <b>521</b> of the microchip <b>501</b>. A third process can be located on a third section <b>531</b> of the microchip <b>501</b>; additional processes can also be located on other sections of the microchip <b>501</b>.

0199The processes can be completely separate while at least sharing the common silicon wafer <b>500</b> base, and the processes can occur at different fabrication facilities, including those owned by different manufacturers. Alternatively, two or more separate processes may have common sub-processes that can be integrated, i.e., performed at the same time. Sections of the microchip <b>501</b> that are not undergoing a process can be protected from that process by a protective coating that is unaffected by that process and removed after that process. There can be one or more temporary protective coatings, which can remain on for more than one process.

0200The separate sections of the separate fabrication processes of the microchip <b>501</b> can be in any shape or pattern of the microchip. As shown in the <figref idref="DRAWINGS">FIG. 20A</figref> example, one or more separate processes can be located on adjoining portions of adjoining microchips. For example, as shown in <figref idref="DRAWINGS">FIG. 20A</figref>, section <b>521</b> is located on the lower portion of one row of microchips <b>501</b> and on the upper portion of the adjoining row of microchips <b>501</b>, which would be positioned upside down of the wafer <b>500</b>, so that the contiguous area of the section <b>521</b> process is maximized. Similarly, section <b>531</b> is shown in the example located on the lower portion of the adjoining row of microchips <b>501</b> and on the upper portion of the middle row of microchips <b>501</b>. Alternatively, all of the microchips <b>501</b> of the wafer <b>500</b> can be positioned upright on the wafer.

0201Embodiments of the invention include any fabrication process of a silicon wafer <b>500</b> and can include wafers made of other materials suitable for microelectronic devices, such as gallium arsenide. The fabrication processes in current widespread use are generally CMOS (complementary metal-oxide semiconductor), but can be bipolar or other. The separate processes (and separate sections <b>511</b>, <b>521</b>, and <b>531</b> shown in <figref idref="DRAWINGS">FIG. 29A</figref>) can be for general purpose microprocessor (including one or more cores), memory (DRAM or non-volatile such as Flash or MRAM or ovonic), analog (including radio and/or laser), digital signal processing (DSP), micro-electromechanical system (MEMS), field programmable gate arrays (FPGA), graphic processing unit (GPU), microprocessor chipset, and others.

0202Embodiments of the invention facilitate a “system on a chip” (SoC), such as the earlier described PC <b>90</b> microchip, by allowing most or all of the micro components of a PC to be located on a single microchip. Even the consolidation of only two microchips into a single microchip provides a significant increase in processing speed and reduced power consumption. The silicon die becomes the motherboard for all the micro components of the PC, leaving only the macro components like battery, power supply, and input/output (I/O) connections to be located on the printed circuit motherboard. The result is ultra-large-scale-integration.

0203<figref idref="DRAWINGS">FIG. 20B</figref> shows a top view of the microchip <b>501</b> embodiment of <figref idref="DRAWINGS">FIG. 20A</figref> after the die has been separated from the silicon wafer <b>500</b> and positioned in a microchip package <b>503</b>.

0204The fabrication processes illustrated in <figref idref="DRAWINGS">FIGS. 20A-20B</figref> can include material such as silicon germanium, gallium arsenide, indium phosphide and others used, for example, as deposits on silicon. Besides using different materials in different sections of the microchip, different size processes can be used in different microchip sections, such as a 0.13 micron process on section <b>511</b> and a 0.18 micron process on section <b>521</b> in the <figref idref="DRAWINGS">FIG. 29A</figref> example. All or parts of the microchip <b>501</b> can be synchronous or asynchronous. Both different size and different material processes can be combined on different sections of the microchip <b>501</b>.

0205Although the maximum increase in speed and decrease in power consumption can be achieved by putting all micro or nano components on a single “system on a chip,” such as for a PC, even a minimal combination of just two different micro or nano components of a single microchip <b>501</b> can yield a very significant increase in speed and decrease in power consumption. To take a very simple example, a silicon wafer <b>500</b> can have 256 MB of DRAM manufactured onto a section <b>531</b> of the microchips <b>502</b> located on the wafer by one factory; when that DRAM process is completed, a second factory can add a general purpose CPU like a Pentium 4 to a second section <b>511</b> of the microchips <b>501</b> on the silicon wafer <b>500</b>. Such an approach allows direct communication between microprocessor and DRAM on the microchip <b>501</b> for much greater speed and reduced power. Since 256 MB DRAM is an inexpensive commodity product currently, especially if purchased as wafers <b>500</b>, there would be little or no increase in the production time of the microprocessor.

0206<figref idref="DRAWINGS">FIG. 21A</figref> illustrates an embodiment of the invention, which is an alternative method of uniting separate fabrication processes on the same microchip <b>501</b>. Sections <b>501</b>¹, <b>501</b>², and <b>501</b>³of <figref idref="DRAWINGS">FIG. 21A</figref> correspond to sections <b>511</b>, <b>521</b>, and <b>531</b> of <figref idref="DRAWINGS">FIGS. 20A &amp; 20B</figref> in that both sets of sections represent three separate processes, but in <figref idref="DRAWINGS">FIG. 21A</figref> each section is a separate die cut from a wafer <b>500</b> and all three sections are united in a single package <b>503</b>. The section dies <b>501</b>¹, <b>501</b>², and <b>501</b>³can be held together by the chip package <b>503</b> or can be glued together, or a combination of the two in parts or the whole. In addition, the section dies can be assembled into a chip package <b>503</b> or the package can be assembled around the dies or a combination of both partially or completely.

0207The separate process dies illustrated in the <figref idref="DRAWINGS">FIG. 21A</figref> example may be assembled with the surface that the process is on in each die being substantially level with each other, so that both process surfaces of the dies form a plane that is substantially flat. The edges of the dies are configured so adjoining dies fit together as closely as possible, as shown in <figref idref="DRAWINGS">FIG. 21A</figref> at <b>502</b>²and <b>502</b>³.

0208The circuits of dies <b>501</b>¹, <b>501</b>², and <b>501</b>³are connected at their edges <b>502</b>³and <b>502</b>²by interconnect lines <b>580</b> that can be widened as shown in <b>581</b> of <figref idref="DRAWINGS">FIG. 21B</figref>, which shows a portion of die edge <b>502</b>³and <b>502</b>²in an enlarged view. A process can be added in the area <b>591</b> overlapping the edges of the dies at <b>502</b>³and <b>502</b>²bounded by lines <b>590</b>; in that process interconnect lines <b>580</b> of the two separate dies can be connected by laying down connections at <b>582</b> that connect to the enlarged portions <b>581</b> of the interconnect lines <b>580</b>, as illustrated in <figref idref="DRAWINGS">FIG. 21B</figref>.

0209<figref idref="DRAWINGS">FIG. 21C</figref> shows that the die edges <b>502</b>³and <b>502</b>²can have any shape or pattern, not just a straight line shown above in <figref idref="DRAWINGS">FIGS. 21A &amp; 21B</figref>.

0210<figref idref="DRAWINGS">FIG. 22</figref> shows a combination of the embodiments shown in <figref idref="DRAWINGS">FIGS. 20 and 21</figref>. Microchip <b>501</b> as shown in <figref idref="DRAWINGS">FIG. 20</figref> is shown assembled with separate dies <b>501</b>¹, <b>501</b>², and <b>501</b>³into a microchip package <b>503</b>, with edges between dies at <b>502</b>¹, <b>502</b>², <b>502</b>³, and <b>502</b>²³, which could include a connection process such as the example shown in <figref idref="DRAWINGS">FIG. 21B</figref>.

0211The microchip <b>501</b> dies shown in <figref idref="DRAWINGS">FIGS. 20-22</figref> can be packaged using FCPGA (flip-chip pin grid array), FCBGA (flip-chip ball grid array), BBUL (bumpless build-up layer) or other technology.

0212Any of the embodiments shown in <figref idref="DRAWINGS">FIGS. 19</figref>, <b>20</b>A-<b>20</b>B, <b>21</b>A-<b>21</b>C, and <b>22</b> can be combined with one or more other embodiments shown in those figures or in the preceding <figref idref="DRAWINGS">FIGS. 1-18</figref> and described herein.

0213<figref idref="DRAWINGS">FIGS. 23A-23H</figref> are new inventions based on <figref idref="DRAWINGS">FIGS. 18A-27H</figref> of this application, which are FIGS. 27A-27H of U.S. application Ser. No. 10/802,049 filed Mar. 17, 2004 and published on Oct. 28, 2004, as Pub. No. US 2004/0215931 A1 and U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, both of which applications are hereby incorporated by reference herein for completeness of disclosure.

0214<figref idref="DRAWINGS">FIGS. 23A-23H</figref> are example new embodiments based on the <figref idref="DRAWINGS">FIG. 7B</figref> example; they show examples of the applicant's inventions involving one or more Faraday Cages surrounding various combinations of semiconductor microchips, photovoltaic cells, and/or other micro and/or nano devices with the applicant's internal sipe inventions <b>510</b>/<b>511</b>/<b>513</b>. In the exemplary embodiments shown, the Faraday Cages <b>300</b> coincide with the outer compartment <b>500</b>, which forms a surface of the sipe <b>505</b> (as previously defined) which can partially or completely surround the PC <b>90</b> microchip and/or photovoltaic cell <b>201</b> and/or fuel cell <b>211</b> and/or battery <b>221</b>; any one or more of which (<b>90</b>/<b>201</b>/<b>211</b>/<b>221</b>) can be connected by wire <b>99</b>, which can also be protected by Faraday Cage <b>300</b> so that all components are protected; and one or more Faraday Cages <b>300</b> and or internal sipes <b>505</b> can be inside a Faraday Cage <b>300</b> and/or internal sipe <b>505</b> so as to provide additional protection, including of one or more individual components, as shown in several useful examples in the <figref idref="DRAWINGS">FIGS. 23A-23H</figref>.

0215Heat sink <b>301</b> or other microchip cooling device can be augmented or replaced by a cooling media <b>506</b>, which can for example circulate by convection alone within the sipe <b>505</b> as shown in <figref idref="DRAWINGS">FIG. 23G</figref> for example or can be allowed to circulate away from the microchip or other micro or nano device to a heat sink in another location, for example, including by circulation powered by a pump, for example, or other powered means. One or more attachments <b>503</b> can provide external connection from the microchip/cell <b>200</b> or other component like fuel cell <b>211</b> or battery <b>221</b> to the outer compartment <b>500</b> and/or Faraday Cage <b>300</b> and then to other external connections, such as a wire <b>99</b> as shown in <figref idref="DRAWINGS">FIG. 23C</figref> or an antenna <b>499</b> as shown in <figref idref="DRAWINGS">FIG. 23H</figref>; as shown in the <figref idref="DRAWINGS">FIG. 23D</figref> example, one or more attachments <b>503</b>, which can be one or more conventional pins, can connect a microchip PC <b>90</b> and/or other component with an internal Faraday Cage <b>300</b>. Advantageous combinations of the <figref idref="DRAWINGS">FIGS. 23A-23H</figref> embodiments can be made with embodiments shown in <figref idref="DRAWINGS">FIGS. 24A-24C</figref>, <b>25</b>A-<b>25</b>B and <b>26</b>A-<b>26</b>B, as well as with previous <figref idref="DRAWINGS">FIGS. 1-22</figref>.

0216FIGS. <b>24</b>A and <b>25</b>A-<b>25</b>B are based on FIGS. 28 and 29A-29B of U.S. application Ser. No. 10/684,657 filed Oct. 15, 2003 and published on Aug. 18, 2005, as Pub. No. US 2005/0180095 A1, which was above incorporated by reference herein for completeness of disclosure.

0217<figref idref="DRAWINGS">FIG. 24A</figref> is a top view of a semiconductor wafer <b>1500</b>, of which 300 mm. is a current example using a 90 nanometer process, made of silicon, gallium arsenide, or any other suitable semiconductor materials in current use or future equivalents. The wafer <b>1500</b> contains a multitude of microchips <b>1501</b> with each microchip <b>1501</b> including, for example, 1 or more core microprocessors <b>93</b> or <b>94</b>, including at least 2 or 4 or 8 or 16 or 32 or 64 or 128 or 256 or 512 or 1028 or more cores. But instead of separating the microchips <b>1501</b> into separate dies in the conventional process along lines <b>1502</b>, the entire semiconductor wafer <b>1500</b> of any size (including smaller that 300 mm) is used essentially intact (that is, undiced into dies) as a computer (or in one example embodiment, the wafer <b>1500</b> can be virtually entire and intact, excluding deactivated or disconnected incomplete microchips <b>1501</b> located around the periphery of a circular wafer and microchips <b>1501</b> with manufacturing defects or other damage, such as failure during use, which can remain inactively on the wafer); instead of separating along lines <b>1502</b>, interconnects <b>1505</b> of any length or configuration can be added to the printed circuit architecture to connect the microchips <b>1501</b> to other microchips <b>1501</b> and/or other components on the wafer <b>1500</b> or external to it, using any interconnection means or architecture known in the art.

0218The microchips <b>1501</b> on the wafer <b>1500</b> can for example each be a complete personal computer (PC <b>90</b>) system on a chip (SoC), including for example microprocessors, random access memory, radio and/or optical communication components, and other operational components necessary for each microchip <b>1501</b> to be capable of functioning as a fully independent PC <b>90</b> unit on the semiconductor wafer <b>1500</b>. Each PC <b>90</b> microchip <b>1501</b> on the wafer <b>1500</b> is in effect a stand-alone unit capable of operating independent of any other PC <b>90</b> microchip <b>1501</b> on the wafer; this means that operations of PC <b>90</b> microchips <b>1501</b> occurring on the wafer <b>1500</b> can occur asynchronously, such as some or all of the PC <b>90</b> microchips <b>1501</b> on a wafer can operate together as a cluster of personal computers, as is conventional in the art, and can also include other personal computers in the cluster that are not on the wafer <b>1500</b>. The semiconductor wafer <b>1500</b> can be used with other conventional interface devices for power and data communication, including wireless such as radio and/or optic (See <figref idref="DRAWINGS">FIG. 14</figref>, for example), and/or wired such as fiber optic and/or electric; such connections can reduce or eliminate the need for interconnections between the PC <b>90</b> microchips <b>1501</b> or pins connecting a wafer <b>1500</b>, for example, to a motherboard (not shown). One or more PC <b>90</b> microchips <b>1501</b> can also include these connections, and all can include wireless communication capability such a radio or optic device, so that even cluster operations between PC microchips <b>1501</b> on a wafer <b>1500</b> can occur completely on wafer <b>1500</b>, obviating the need for pins and interconnects.

0219Alternatively, more than one semiconductor wafer <b>1500</b> can be stacked in vertical layers, for example, with wafer <b>1500</b> #<b>1</b> including microprocessors or cores; wafer <b>1500</b> #<b>2</b> including random access memory or RAM such as DRAM; and wafer <b>1500</b> #<b>3</b> including other components, as shown in the <figref idref="DRAWINGS">FIG. 24B</figref> example, which is similar to <figref idref="DRAWINGS">FIG. 7B</figref> of this application. The wafers stacked can be entire wafers as shown, or portions of wafers (such as <figref idref="DRAWINGS">FIG. 24C</figref> below), or one or more entire wafers with one or more portions of wafers or dies or other components.

0220By reducing or eliminating the need to go “off microchip” or off wafer in this case to complete computation operations, the applicant's invention provides huge savings in terms of speed and energy efficiency.

0221<figref idref="DRAWINGS">FIG. 24A</figref> also shows an example of the semiconductor wafer <b>1500</b> including one or more of the applicant's <b>510</b> or <b>511</b> or <b>513</b> internal sipe invention, with an outer compartment <b>500</b> with a sipe <b>505</b>. In addition, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example of the semiconductor wafer <b>1500</b> including one (or potentially more) Faraday Cage <b>300</b> surrounding the semiconductor wafer <b>1500</b>. Moreover, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example embodiment wherein both one or more of the internal siped inventions <b>510</b>/<b>511</b>/<b>513</b> and one or more of the Faraday Cages <b>300</b> can be used with the same semiconductor wafer <b>1500</b>. Finally, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example wherein one or more of the outer compartment <b>500</b> of the internal siped invention coincide with one or more of the Faraday Cages <b>300</b>. Each of the four example embodiments described above in this paragraph can be used independently from each other or in any combination, including all four together as shown in <figref idref="DRAWINGS">FIG. 24A</figref>.

0222<figref idref="DRAWINGS">FIG. 24B</figref> shows a side cross section of vertically stacked semiconductor wafers <b>1500</b>, which have interconnects or vias <b>1504</b> between facing proximate surfaces of the wafers. <figref idref="DRAWINGS">FIG. 24B</figref> shows a three wafer example embodiment; two or more wafers can be stacked in any manner, including with each directly aligned on top of one another, as shown, or partially overlapping in any manner. Two or more of the wafers <b>1500</b> can contact directly as shown or a non-wafer layer can be between them.

0223As with the example embodiments shown in <figref idref="DRAWINGS">FIG. 24A</figref>, <figref idref="DRAWINGS">FIG. 24B</figref> shows those stacked wafers <b>1500</b> including one or more of the applicant's <b>510</b> or <b>511</b> or <b>513</b> internal sipe invention, with an outer compartment <b>500</b> with a sipe <b>505</b>. In addition, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example of the stacked semiconductor wafers <b>1500</b> including one or more Faraday Cage <b>300</b> surrounding the semiconductor wafer <b>1500</b>. Moreover, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example embodiment wherein both one or more of the internal siped inventions <b>510</b>/<b>511</b>/<b>513</b> and one or more of the Faraday Cages <b>300</b> can be used with the same stacked semiconductor wafers <b>1500</b>. Finally, <figref idref="DRAWINGS">FIG. 24A</figref> shows an example wherein one or more of the outer compartment <b>500</b> of the internal siped invention coincide with one or more of the Faraday Cages <b>300</b> surrounding the stacked wafers <b>1500</b>. Each of the four example embodiments described above in this paragraph can be used independently from each other or in any combination, including all four together as shown in <figref idref="DRAWINGS">FIG. 24B</figref>.

0224<figref idref="DRAWINGS">FIG. 24C</figref> is another top view of a circular wafer <b>1500</b>, but subdivided into smaller components, such as half sections at the upper example and quarter sections in the lower sections. Other smaller component embodiments, including other non-rectangular embodiments can be used beneficially. Advantageous combinations of the <figref idref="DRAWINGS">FIGS. 24A-24C</figref> embodiments with embodiments shown in <figref idref="DRAWINGS">FIGS. 23A-23H</figref> can also be made, as well as with <figref idref="DRAWINGS">FIGS. 25A-25B</figref> and <b>26</b>A-<b>26</b>B, as well as with previous <figref idref="DRAWINGS">FIGS. 1-22</figref>.

0225The invention examples shown in <figref idref="DRAWINGS">FIGS. 24A-24B</figref> can be used as stand-alone computers or as networked computers or as components of a computer. As noted above, sipe media <b>506</b> can also be a coolant, which can circulate to a location outside the outer compartment <b>500</b> (not shown) or be enclosed within the <b>300</b>/<b>500</b> structure (shown in <figref idref="DRAWINGS">FIG. 24B</figref> partially filling sipe <b>505</b> as one example and completely filling sipe <b>505</b> as another example (not shown).

0226<figref idref="DRAWINGS">FIGS. 25A-25B</figref> are modifications of <figref idref="DRAWINGS">FIGS. 20A and 20B</figref> of this application (which are FIGS. 29A-29B of the '657 application incorporated by reference herein above). <figref idref="DRAWINGS">FIG. 25A</figref> shows a top view of PC <b>90</b> microchips <b>1501</b> on a portion of the semiconductor wafer <b>1500</b>, including interconnects <b>1505</b> between the microchips <b>1501</b>, and the microchips <b>1501</b> being bounded by edge portions <b>1502</b>.

0227<figref idref="DRAWINGS">FIG. 25B</figref> shows a microchip <b>1501</b> as a separated die in a package <b>1503</b> including the applicant's internal sipe inventions <b>510</b>/<b>511</b>/<b>513</b> and the Faraday Cage <b>300</b>. Advantageous combinations of the <figref idref="DRAWINGS">FIGS. 25A-25B</figref> embodiments can be made with embodiments shown in <figref idref="DRAWINGS">FIGS. 23A-23H</figref>, <b>24</b>A-<b>24</b>C, and <b>26</b>A-<b>26</b>B, as well as with previous <figref idref="DRAWINGS">FIGS. 1-22</figref>.

0228<figref idref="DRAWINGS">FIGS. 26A-26B</figref> are like <figref idref="DRAWINGS">FIG. 7A-7B</figref> with the addition of Faraday Cages, as well as the addition of stacked dies in a side view in <figref idref="DRAWINGS">FIG. 26B</figref>. Advantageous combinations of the <figref idref="DRAWINGS">FIGS. 26A-26B</figref> embodiments can be made with embodiments shown in <figref idref="DRAWINGS">FIGS. 23A-23H</figref>, <b>24</b>A-<b>24</b>C, and <b>25</b>A-<b>25</b>B, as well as with previous <figref idref="DRAWINGS">FIGS. 1-22</figref>.

0229By way of background, FIG. 28A of the '033 and '930 Applications incorporated by reference herein above shows in cross-section an example of a tire <b>535</b>, such as for a wheel <b>533</b> of a transportation vehicle, with a device <b>510</b>; the internal sipe <b>505</b> and/or inner compartment/chamber/bladder <b>501</b> can be pressured or not (valve not shown). As shown in the example, inner compartment/chamber/bladder <b>501</b> can have one or more direct attachments <b>503</b> to the wheel and the structural elements shown can be made of any useful material as is conventional in the art, including plastic and/or plastic composite and/or carbon fiber. The outer compartment/chamber/bladder <b>500</b> can be abbreviated to cover only part of inner compartment/chamber/bladder <b>501</b>, as shown in <figref idref="DRAWINGS">FIG. 28A</figref>, (possibly pressure-sealed to the wheel like a conventional automobile tire and wheel); the outer compartment/chamber/bladder <b>500</b> can also be abbreviated further to cover only a lesser portion, including at least a tread portion, which can include rubber (natural or synthetic, as can other or all parts of the outer compartment <b>500</b>. FIG. 28B of the '033 and '930 applications shows in a side view cross-section an example of shape of structural elements <b>502</b> of the inner compartment <b>501</b> (not shown for simplicity).

0230<figref idref="DRAWINGS">FIG. 27A</figref> is new in this application and shows another tire <b>535</b> example embodiment similar to that of <figref idref="DRAWINGS">FIG. 28A</figref> discussed in the previous paragraph, but maximizing lateral stability by locating the structural elements <b>502</b> at the sides of the tire <b>535</b>, while maximizing soft ride by locating the media such as gas in the central portion of the tire <b>535</b>. New <figref idref="DRAWINGS">FIG. 27B</figref> is a side view of <figref idref="DRAWINGS">FIG. 27A</figref> and is the same as <figref idref="DRAWINGS">FIG. 28B</figref> discussed above.

0231<figref idref="DRAWINGS">FIGS. 23A-27</figref> can be combined in any manner with each other and with any or all of <figref idref="DRAWINGS">FIGS. 1-22</figref> of this applications, as well as with the Figures of the applicant's patents and applications incorporated by reference herein this application.

0232Broadly, the flexible inserts or components <b>510</b>, <b>511</b>, and <b>513</b> can be usefully employed anywhere that cushioning already is being used, or could be with beneficial effect, such as protective padding or cases for equipment of any sort, including portable devices like PC laptops or video players and/or games, cell phones, personal digital assistants (PDA's), and personal digital music players like Apple Ipods™ and MP3 players, as examples, such as the mounting of delicate electronic (or other) components like hard-drives or for vibration dampening, such as in automobile structural and body components and connections.

0233The applicant's two earlier applications, U.S. application Ser. No. 11/190,087 published as Publication No. US 2005/0268487 A1 on Dec. 8, 2005 describing footwear and U.S. application Ser. No. 11/108,034 published as Publication No. US 2005/0217142 A1 on Oct. 6, 2005 describing orthotics, as well as U.S. Pat. No. 7,010,869, issued Mar. 14, 2006 (of which the '034 application is a continuation), are hereby expressly incorporated by reference in its entirety for completeness of disclosure. The applicant's earlier application Ser. No. 11/179,887 published as Publication No. US 2005/0241183 A1 on Nov. 3, 2005 describing footwear is hereby expressly incorporated by reference in its entirety for completeness of disclosure.

0234The applicant's other footwear U.S. Pat. Nos. 4,989,349; 5,317,819; 5,544,429; 5,909,948; 6,115,941; 6,115,945; 6,163,982; 6,308,439; 6,314,662; 6,295,744; 6,360,453; 6,487,795; 6,584,706; 6,591,519; 6,609,312; 6,629,376; 6,662,470; 6,675,498; 6,675,499; 6,708,424; 6,729,046; 6,748,674; 6,763,616; 6,789,331; 6,810,606; 6,877,254; 6,918,197; 7,010,869; 7,082,697; 7,093,379; 7,127,834; 7,168,185; 7,174,658; 7,234,249; 7,287,341; 7,334,350; and 7,334,356 are all hereby incorporated by reference herein in their entirety into this application for completeness of disclosure of the applicant's novel and useful combination of one or more of any of the features or components of any of the figures of this application with one or more of any of the features of any one or more of the preceding applicant's patents listed above in this paragraph.

0235The applicant's other footwear U.S. Applications with Publication Numbers US 20020000051; 20020007571; 20020007572; 20020014020; 20020014021; 20020023373; 20020073578; 20020116841; 20030046830; 20030070320; 20030079375; 20030131497; 20030208926; 20030217482; 20040134096; 20040250447; 20050016020; 20050086837; 20050217143; 20060032086; 20060248749; 20070240332; 20070271817; 20080000108; 20080005931; 20080022556; 20080083140; and 20080086916 are hereby incorporated by reference herein in their entirety into this application for completeness of disclosure of the applicant's novel and useful combination of one or more of any of the features or components of any of the figures of this application with one or more of any of the features of any one or more of the preceding applicant's published U.S. Applications listed above in this paragraph.

0236The applicant's non-footwear patents on global network computers, U.S. Pat. Nos. 6,167,428; 6,732,141; 6,725,250; 7,024,449; 7,035,906, and 7,047,275 are all hereby incorporated by reference herein in their entirety into this application for completeness of disclosure of the applicant's novel and useful combination of one or more of any of the features or components of any of the figures of this application with one or more of any of the features of any one or more of the preceding applicant's patents listed above in this paragraph.

0237The applicant's non-footwear applications on global network computers are U.S. application Ser. Nos. 09/085,755; 09/884,041; 09/935,779; 10/663,911; 11/196,527; 11/329,423; and 11/338,887, as well as U.S. application Ser. No. 10/802,049 with U.S. Publication Number US 2004/0215931 published Oct. 28, 2004; U.S. application Ser. No. 10/684,657 with U.S. Publication Number US 2005/0180095 published Aug. 18, 2005; U.S. application Ser. No. 11/196,527 filed Aug. 4, 2005 with U.S. Publication Number US 2006/0095497 published May 4, 2006; U.S. application Ser. No. 11/329,423 filed Jan. 11, 2006 with U.S. Publication Number US 2006/0177226 published Aug. 10, 2006; U.S. application Ser. No. 11/338,887 filed Jan. 25, 2006 with U.S. Publication Number US 2006/0190565 published Aug. 24, 2006; all of these applications are hereby incorporated by reference herein in their entirety into this application for completeness of disclosure of the applicant's novel and useful combination of one or more of any of the features or components of any of the figures of this application with one or more of any of the features of any one or more of the preceding applicant's applications, including published applications, listed above in this paragraph.

0238To avoid confusion, any numeral in the above listed non-footwear patents or applications relating to computers that is the same as a numeral in the above listed footwear patents or applications should have (or be presumed to have) a prefix numeral of “1” added to the numeral (the equivalent of adding “1000” to the numeral, so that all the numerals of both sets of applications and patents remain unique).

0239In the following claims, the term “chamber” means a compartment <b>161</b> or a chamber <b>188</b> or a bladder and the term “sipe” means a sipe <b>505</b> or a slit or a channel or a groove as described in the textual specification above and associated figures of this application.

0240The foregoing shoe designs meet the objectives of this invention as stated above. However, it will clearly be understood by those skilled in the art that the foregoing description has been made in terms of the preferred embodiments and various changes and modifications may be made without departing from the scope of the present invention which is to be defined by the appended claims.