Flat panel display device and method of manufacturing the same

BACKGROUND

00011. Field of the Invention

0002Embodiments relate to a flat panel display device and method of manufacturing the same.

00032. Description of the Related Art

0004Flat panel display devices, e.g., liquid crystal display devices (LCDs), which use electrical-optical properties of a liquid crystal, and organic light emitting display devices (OLEDs), which use self-emission features of an organic light emitting diodes, may include a passive matrix type and an active matrix type. The active matrix type may be desirable because it has excellent resolution and is suitable for displaying videos, as compared with the passive matrix type.

0005Active matrix flat panel display devices may include a thin film transistor and a capacitor. Accordingly, multiple masks and processes for manufacturing the thin film transistor and the capacitor may be required. For example, a mask for forming an active layer of the thin film transistor and a lower electrode of the capacitor, a mask for forming a gate electrode of the thin film transistor and an upper electrode of the capacitor, a mask for exposing source and drain regions, and a mask for forming a source electrode and a drain electrode may be required.

SUMMARY

0006Embodiments are directed to a flat panel display device and method of manufacturing the same, which represent advances over the related art.

0007It is a feature of an embodiment to provide a flat panel display device that can be manufactured using a small number of masks, thus reducing manufacturing costs.

0008At least one of the above and other features and advantages may be realized by providing a flat panel display device including a substrate, the substrate including a first region and a second region; an active layer on the first region of the substrate, the active layer including a semiconductor material; a lower electrode on the second region of the substrate, the lower electrode including the semiconductor material; a first insulating layer on the substrate including the active layer and the lower electrode thereon; a gate electrode on the first insulating layer, the gate electrode overlying the active layer and including a first conductive layer pattern and a second conductive layer pattern; an upper electrode on the first insulating layer, the upper electrode overlying the lower electrode and including the first conductive layer pattern and the second conductive layer pattern; a second insulating layer on the gate electrode and the upper electrode, the second insulating layer exposing portions of the active layer and portions of the upper electrode; and a source electrode and a drain electrode connected to the exposed portions of the active layer.

0009The semiconductor material may include amorphous silicon or a polysilicon.

0010The lower electrode may include dopant ions implanted therein.

0011The first conductive layer pattern may include at least one of amorphous ITO, ITO, poly-ITO, and IZO.

0012The second conductive layer pattern may include at least one of tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and alloys thereof.

0013The second conductive layer pattern corresponding to the upper electrode may be interposed between edges of the corresponding first conductive layer pattern and the second insulating layer thereon.

0014At least one of the above and other features and advantages may also be realized by providing a flat panel display device including a substrate, the substrate including a first region, a second region, and a third region; an active layer on the first region of the substrate, the active layer including a semiconductor material; a lower electrode on the second region of the substrate, the lower electrode including the semiconductor material; a first insulating layer on the substrate including the active layer and the lower electrode thereon; a gate electrode on the first insulating layer, the gate electrode overlying the active layer and including a first conductive layer pattern and a second conductive layer pattern; an upper electrode on the first insulating layer, the upper electrode overlying the lower electrode and including the first conductive layer pattern and the second conductive layer pattern; an anode electrode on the first insulating layer in the third region, the anode electrode including the first conductive layer pattern and the second conductive layer pattern; a second insulating layer on the gate electrode, the upper electrode, and the anode electrode, the second insulating layer exposing portions of the active layer, the anode electrode, and the upper electrode; a source electrode connecting exposed portions of the active layer and the anode electrode; a drain electrode connected to exposed portions of the active layer; a pixel defining layer on the substrate including the source electrode and drain electrode thereon, the pixel defining layer exposing portions of the anode electrode in the light emitting region; an organic light emitting layer on the anode electrode in the light emitting region; and a cathode electrode on the organic light emitting layer.

0015The semiconductor material may include amorphous silicon or polysilicon.

0016The lower electrode may include dopant ions implanted therein.

0017The first conductive layer pattern may include at least one of amorphous ITO, ITO, poly-ITO, and IZO.

0018The second conductive layer pattern may include at least one of tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and alloys thereof.

0019The second conductive layer pattern corresponding to the upper electrode may be interposed between edges of the corresponding first conductive layer pattern and the second insulating layer thereon.

0020The substrate may include transparent glass or plastic.

0021At least one of the above and other features and advantages may also be realized by providing a flat panel display device including a substrate, the substrate including a first region, a second region, and a third region; an active layer on the first region of the substrate, the active layer including a semiconductor material; a lower electrode on the second region of the substrate, the lower electrode including the semiconductor material; a first insulating layer on the substrate including the active layer and the lower electrode thereon; a gate electrode on the first insulating layer, the gate electrode overlying the active layer and including a first conductive layer pattern and a second conductive layer pattern; an upper electrode on the first insulating layer, the upper electrode overlying the lower electrode and including the first conductive layer pattern and the second conductive layer pattern; a second insulating layer on the gate electrode and the upper electrode, the second insulating layer exposing portions of the active layer and portions of the upper electrode; a source electrode and a drain electrode connected to the exposed portions of the active layer; a third insulating layer on the substrate including the source electrode and drain electrode thereon, the third insulating layer exposing portions of the source electrode or the drain electrode; an anode electrode connected to the exposed portion of the source electrode or drain electrode; a pixel defining layer on the anode electrode, the pixel defining layer exposing portions of the anode electrode; an organic light emitting layer on the anode electrode in the light emitting region; and a cathode electrode on the organic light emitting layer.

0022The semiconductor material may include amorphous silicon or polysilicon.

0023The lower electrode may include dopant ions implanted therein.

0024The first conductive layer pattern may include at least one of amorphous ITO, ITO, poly-ITO, and IZO.

0025The second conductive layer pattern may include at least one of tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and alloys thereof.

0026The second conductive layer pattern corresponding to the upper electrode may be interposed between edges of the corresponding first conductive layer pattern and the second insulating layer thereon.

0027The substrate may include transparent glass or plastic.

0028At least one of the above and other features and advantages may also be realized by providing a method of manufacturing a flat panel display device, the method including providing a substrate such that the substrate includes a first region and a second region; forming and patterning a semiconductor material layer on the substrate to form an active layer in the first region and a lower electrode in the second region; forming a first insulating layer on the substrate including the active layer and the lower electrode thereon; forming a first conductive layer and a second conductive layer on the first insulating layer; patterning the first conductive layer and the second conductive layer to form a gate electrode on the first insulating layer such that the gate electrode overlies the active layer and includes a first conductive layer pattern and a second conductive layer pattern, and an upper electrode on the first insulating layer such that the upper electrode overlies the lower electrode and includes the first conductive layer pattern and the second conductive layer pattern; forming a second insulating layer on the first insulating layer including the gate electrode and the upper electrode thereon; patterning the second insulating layer to form an aperture pattern such that the aperture pattern exposes portions of the active layer and portions of the upper electrode; forming a third conductive layer on the second insulating layer such that the third conductive layer fills the aperture pattern; patterning the third conductive layer to form a source electrode and a drain electrode such that the source and drain electrodes are connected to exposed portions of the active layer; removing portions of the second conductive layer pattern of the upper electrode in the second region exposed by the aperture pattern; and implanting ions into the lower electrode through the aperture pattern, the first conductive layer pattern, and the first insulating layer corresponding to the aperture pattern.

0029The semiconductor layer may include amorphous silicon or polysilicon.

0030The first conductive layer may include one of amorphous ITO, ITO, poly-ITO, and IZO.

0031The second conductive layer may include at least one of tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and alloys thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

0032The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

0033<figref idref="DRAWINGS">FIG. 1</figref> illustrates a cross-sectional view of a flat panel display device according to an embodiment;

0034<figref idref="DRAWINGS">FIG. 2</figref> illustrates a cross-sectional view of a flat panel display device according to another embodiment;

0035<figref idref="DRAWINGS">FIGS. 3A to 3I</figref> illustrates cross-sectional views of stages in a method of manufacturing a flat panel display device according to an;

0036<figref idref="DRAWINGS">FIG. 4</figref> illustrates a cross-sectional view of a flat panel display device according to yet another embodiment; and

0037<figref idref="DRAWINGS">FIGS. 5A to 5H</figref> illustrates cross-sectional views of stages in a method of manufacturing a flat panel display device according to another embodiment.

DETAILED DESCRIPTION

0038Korean Patent Application No. 10-2009-0122492, filed on Dec. 10, 2009, in the Korean Intellectual Property Office, and entitled: “Flat Panel Display Device and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety.

0039Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

0040In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

0041When an element is referred to as being “connected to” another element, it can be directly connected to the another element or be indirectly connected to the another element with one or more intervening elements interposed therebetween.

0042<figref idref="DRAWINGS">FIG. 1</figref> illustrates a cross-sectional view of a flat panel display device according to an embodiment. In <figref idref="DRAWINGS">FIG. 1</figref>, regions where a thin film transistor and a capacitor are formed are schematically shown.

0043A substrate <b>10</b> made of, e.g., an insulating material, may include a thin film transistor forming region T and a capacitor forming region C. A buffer layer <b>12</b> may be disposed on the transistor forming region T and the capacitor forming region C of the substrate <b>10</b>. An active layer <b>14</b><i>a </i>including a channel region and source and drain regions may be disposed on the buffer layer <b>12</b> in the transistor forming region T. A lower electrode <b>14</b><i>b </i>may be disposed on the buffer layer <b>12</b> in the capacitor forming region C. The active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>may include a semiconductor material made of, e.g., amorphous silicon or polysilicon. Dopant ions may be implanted in the lower electrode <b>14</b><i>d </i>for conductivity. In an implementation, the lower electrode <b>14</b><i>b </i>and the active layer <b>14</b><i>a </i>may be disposed in the same plane on the buffer layer <b>12</b>.

0044A first insulating layer <b>16</b> may be disposed on the buffer layer <b>12</b> including the active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>thereon. The first insulating layer <b>16</b> may serve as a gate insulating layer of the thin film transistor and a dielectric of the capacitor.

0045A gate electrode <b>20</b><i>a </i>including a first conductive layer pattern <b>18</b> and a second conductive layer pattern <b>20</b> may be disposed on the first insulating layer <b>16</b> over, i.e., may overlie, the active layer <b>14</b><i>a</i>. An upper electrode <b>20</b><i>b </i>including the first conductive layer pattern <b>18</b> and the second conductive layer pattern <b>20</b> may be disposed on the first insulating layer <b>16</b> over, i.e., may overlie, the lower electrode <b>14</b><i>b</i>. In an implementation, the first conductive layer patterns <b>18</b> and the second conductive layer patterns <b>20</b> of the gate electrode <b>20</b><i>a </i>and upper electrode <b>20</b><i>b </i>may be disposed in the same plane, respectively, on the first insulating layer <b>16</b>.

0046A second insulating layer <b>22</b> may be disposed on the first insulating layer <b>16</b> including the gate electrode <b>20</b><i>a </i>and the upper electrode <b>20</b><i>b </i>thereon. An aperture pattern, i.e., a plurality of openings, may be formed in the second insulating layer <b>22</b> to expose portions of the source and drain regions of the active layer <b>14</b><i>a </i>as well as portions of the upper electrode <b>20</b><i>b</i>. The second conductive layer pattern <b>20</b> of the upper electrode <b>20</b><i>b </i>may be interposed between edges of the corresponding first conductive layer pattern <b>18</b> and the second insulating layer <b>22</b> thereon. The first conductive layer pattern <b>18</b> may include, e.g., a transparent conductive material; and the second conductive layer pattern <b>20</b> may include, e.g., metal or an alloy.

0047A source electrode <b>24</b><i>a </i>may be disposed on the second insulating layer <b>22</b> and may be connected to the source region of the active layer <b>14</b><i>a </i>through the aperture pattern. A drain electrode <b>24</b><i>b </i>may be disposed on the second insulating layer <b>22</b> and may be connected to the drain region of the active layer <b>14</b><i>a </i>through the aperture pattern.

0048<figref idref="DRAWINGS">FIG. 2</figref> illustrates a cross-sectional view of a flat panel display device according to another embodiment. In particular, the flat panel device illustrated in <figref idref="DRAWINGS">FIG. 2</figref> may a bottom emission type of organic light emitting display device.

0049A substrate <b>10</b> made of an insulating material, e.g., transparent glass and/or plastic, may include a thin film transistor forming region T, a capacitor forming region C, and a pixel forming region P. A buffer layer <b>12</b> may be disposed on the thin film transistor forming region T, the capacitor forming region C, and the pixel forming region P of the substrate <b>10</b>. An active layer <b>14</b><i>a </i>including a channel region, a source region, and a drain region may be disposed on the buffer layer <b>12</b> in the thin film transistor forming region T. A lower electrode <b>14</b><i>b </i>may be disposed on the buffer layer <b>12</b> in the capacitor forming region C. The active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>may include a semiconductor material, e.g., amorphous silicon or polysilicon. Dopant ions may be implanted in the lower electrode <b>14</b><i>d </i>for conductivity. In an implementation, the lower electrode <b>14</b><i>b </i>and the active layer <b>14</b><i>a </i>may be disposed in the same plane on the buffer layer <b>12</b>.

0050A first insulating layer <b>16</b> may be disposed on the buffer layer <b>12</b> including the active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>thereon. The first insulating layer <b>16</b> may serve as a gate insulating layer of the thin film transistor and a dielectric of the capacitor.

0051A gate electrode <b>20</b><i>a </i>including a first conductive layer pattern <b>18</b> and a second conductive layer pattern <b>20</b> may be disposed on the first insulating layer <b>16</b> over, i.e., may overlie, the active layer <b>14</b><i>a</i>. An upper electrode <b>20</b><i>b </i>including the first conductive layer pattern <b>18</b> and the second conductive layer pattern <b>20</b> may be disposed on the first insulating layer <b>16</b> over, i.e., may overlie, the lower electrode <b>14</b><i>b</i>. An anode electrode <b>20</b><i>c </i>including the first conductive layer pattern <b>18</b> and the second conductive layer pattern <b>20</b> may be disposed on the first insulating layer <b>16</b> in the pixel forming region P. In an implementation, the first conductive layer patterns <b>18</b> and the second conductive layer patterns <b>20</b> of the gate electrode <b>20</b><i>a </i>and upper electrode <b>20</b><i>b </i>may be disposed in the same plane, respectively, on the first insulating layer <b>16</b>.

0052A second insulating layer <b>22</b> may be disposed on the first insulating layer <b>16</b> including the gate electrode <b>20</b><i>a</i>, the upper electrode <b>20</b><i>b</i>, and the anode electrode <b>20</b><i>c </i>thereon. An aperture pattern, i.e., a plurality of openings, may be formed in the second insulating layer <b>22</b> to expose portions of the source and drain regions of the active layer <b>14</b><i>a</i>, portions of the upper electrode <b>20</b><i>b</i>, and portions of the anode electrode <b>20</b><i>c </i>in the light emitting region. The second conductive layer pattern <b>20</b> of the upper electrode <b>20</b><i>b </i>may be interposed between edges of the corresponding first conductive layer pattern <b>18</b> and the second insulating layer <b>22</b> thereon. In addition, the second conductive layer pattern <b>20</b> of the anode electrode <b>20</b><i>c </i>may be interposed between edges of the corresponding first conductive layer pattern <b>18</b> and the second insulation layer <b>22</b> thereon. The first conductive layer <b>18</b> may include, e.g., a transparent conductive material; and the second conductive layer <b>20</b> may include, e.g., a metal or an alloy.

0053A source electrode <b>24</b><i>a </i>may be formed on the second insulating layer <b>22</b> and may be connected to both the source region of the active layer <b>14</b><i>a </i>and the anode electrode <b>20</b><i>c </i>in the light emitting region through the aperture pattern. A drain electrode <b>24</b><i>b </i>may be disposed on the second insulation layer <b>22</b> and may be connected to the drain region of the active layer <b>14</b><i>a </i>through the aperture pattern.

0054A pixel defining layer <b>26</b> may be disposed on the second insulating layer <b>22</b> including the source electrode <b>24</b><i>a </i>and the drain electrode <b>24</b><i>b </i>thereon. An aperture pattern may be formed in the pixel defining layer <b>26</b> to expose portions of the anode electrode <b>20</b><i>c </i>in the light emitting region. An organic light emitting layer <b>28</b> may be disposed on exposed portions of the anode electrode <b>20</b><i>c </i>in the light emitting region. A cathode electrode <b>30</b> may be disposed on the pixel defining layer <b>26</b> including the organic light emitting layer <b>28</b> thereon.

0055In the flat panel display device according to the present embodiment, signals provided from outside may be stored in the capacitor. Further, signals may be provided to the anode electrode <b>20</b><i>c </i>by the thin film transistor. Thus, when a predetermined voltage is applied to the anode electrode <b>20</b><i>c </i>and the cathode electrode <b>30</b>, holes injected from the anode electrode <b>20</b><i>c </i>and electrons injected from the cathode electrode <b>30</b> may be recombined in the organic light emitting layer <b>28</b>. Accordingly, characters and/or images may be displayed by light emitted from the organic light emitting layer <b>28</b> to the outside through the substrate <b>10</b>.

0056The embodiments will now be described in more detail through a manufacturing process of a flat panel display device having the above configuration.

0057<figref idref="DRAWINGS">FIGS. 3A to 3I</figref> illustrate cross-sectional views of stages in a method of manufacturing a flat panel display device according to an embodiment. In particular, a method of manufacturing the structure of the flat panel display device of <figref idref="DRAWINGS">FIG. 2</figref> is exemplified in the following description.

0058Referring to <figref idref="DRAWINGS">FIG. 3A</figref>, a substrate <b>10</b> including a thin film transistor forming region T, a capacitor forming region C, and a pixel forming region P may be provided. A buffer layer <b>12</b> and a semiconductor layer (not illustrated) may be sequentially formed on the substrate <b>10</b> including the thin film transistor forming region T, the capacitor forming region C, and the pixel forming region P. The semiconductor layer may be patterned to form an active layer <b>14</b><i>a </i>including a channel region, a source region, and a drain region on the buffer layer <b>12</b> in the thin film transistor forming region T and a lower electrode <b>14</b><i>b </i>on the buffer layer <b>12</b> in the capacitor forming region C. Thus, the active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>may be formed at the same time. The patterning may be carried out by, e.g., photolithography and etching, using a first mask. The semiconductor layer may include, e.g., amorphous silicon or polysilicon, and, if desired, may be subjected to crystallization.

0059Referring to <figref idref="DRAWINGS">FIG. 3B</figref>, a first insulating layer <b>16</b>, a first conductive layer <b>18</b>′, and a second conductive layer <b>20</b>′ may be sequentially formed on the buffer layer <b>12</b> including the active layer <b>14</b><i>a </i>and the lower electrode <b>14</b><i>b </i>thereon. The first insulating layer <b>16</b> may include, e.g., a silicon oxide film SiO₂. The first conductive layer <b>18</b>′ may include, e.g., a transparent conductive material having conductivity sufficient to be used an electrode. In an implementation, the transparent conductive material may include e.g., amorphous ITO (Indium Tin Oxide), ITO, poly-ITO, and/or IZO (Indium Zinc Oxide). The second conductive layer <b>20</b>′ may include, e.g., metal. In an implementation, the metal may include, e.g., tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and/or alloys thereof.

0060Referring to <figref idref="DRAWINGS">FIG. 3C</figref>, a gate electrode <b>20</b><i>a</i>, an upper electrode <b>20</b><i>b</i>, and an anode electrode <b>20</b><i>c </i>may be formed by patterning the first conductive layer <b>18</b>′ and the second conductive layer <b>20</b>′ on the active layer <b>14</b><i>a</i>, the lower electrode <b>14</b><i>b</i>, and the pixel forming region P, respectively. Thus, the gate electrode <b>20</b><i>a</i>, the upper electrode <b>20</b><i>b</i>, and the anode electrode <b>20</b><i>c </i>may each include a first conductive layer pattern <b>18</b> and a second conductive layer pattern <b>20</b> and may be formed at the same time. The patterning may be carried out by, e.g., photolithography and etching, using a second mask. In an implementation, high-density dopant ions may be implanted into the source region and the drain region of the active layer <b>14</b><i>a </i>in, using the gate electrode <b>20</b><i>a </i>as a mask.

0061Then, a second insulating layer <b>22</b> may be formed on the first insulating layer <b>16</b> including the gate electrode <b>20</b><i>a</i>, the upper electrode <b>20</b><i>b</i>, and the anode electrode <b>20</b><i>c </i>thereon.

0062Referring to <figref idref="DRAWINGS">FIG. 3D</figref>, an aperture pattern, i.e., a plurality of openings, including apertures <b>22</b><i>a</i>, <b>22</b><i>b</i>, and <b>22</b><i>c </i>may be formed by patterning the second insulating layer <b>22</b> and the first insulating layer <b>16</b> by, e.g., photolithography and etching, using a third mask. The apertures <b>22</b><i>a</i>, <b>22</b><i>b</i>, and <b>22</b><i>c </i>may expose portions of the source and drain regions of the active layer <b>14</b><i>a</i>, portions of the upper electrode <b>20</b><i>b</i>, and portions of the anode electrode <b>20</b><i>c </i>in the light emitting region.

0063Referring to <figref idref="DRAWINGS">FIG. 3E</figref>, a conductive layer <b>24</b> may be formed on the insulating layer <b>22</b> to fill the apertures <b>22</b><i>a</i>, <b>22</b><i>b</i>, and <b>22</b><i>c. </i>

0064Referring to <figref idref="DRAWINGS">FIG. 3F</figref>, the conductive layer <b>24</b> may be patterned to form a source electrode <b>24</b><i>a </i>connected to both the source region of the active layer <b>14</b><i>a </i>and the anode electrode <b>20</b><i>c </i>in the light emitting region as well as a drain electrode <b>24</b><i>b </i>connected to the drain region of the active layer <b>14</b><i>a </i>through the aperture <b>22</b><i>a</i>. The patterning may be carried out by, e.g., photolithography and etching, using a fourth mask. During the patterning process, portions of the second conductive layer pattern <b>20</b> exposed by the aperture <b>22</b><i>b </i>in the capacitor forming region C, i.e., in the upper electrode <b>20</b><i>b</i>, and the aperture <b>22</b><i>c </i>in the pixel forming region P, i.e., in the anode electrode, may be removed using the fourth mask.

0065Referring to <figref idref="DRAWINGS">FIG. 3G</figref>, dopant ions may be implanted into the lower electrode <b>14</b><i>b </i>through the aperture <b>22</b><i>b </i>in the capacitor forming region C. In the implanting process, since the dopant ions may be implanted into the lower electrode <b>14</b><i>b </i>through exposed portions of the first conductive layer pattern <b>18</b> and the first insulating layer <b>16</b>, an ion implantation energy may be adjusted such that the lower electrode <b>14</b><i>b </i>including the semiconductor layer has sufficient conductivity.

0066Referring to <figref idref="DRAWINGS">FIG. 3H</figref>, a pixel defining layer <b>26</b> may be formed on the second insulating layer <b>22</b> including the source electrode <b>24</b><i>a </i>and the drain electrode <b>24</b><i>b </i>thereon. Portions of the anode electrode <b>20</b><i>c </i>in the light emitting region may be exposed by patterning the pixel defining layer <b>26</b> by, e.g., photolithography and etching, using a fifth mask.

0067Referring to <figref idref="DRAWINGS">FIG. 3I</figref>, an organic light emitting layer <b>28</b> may be formed on exposed portions of the anode electrode <b>20</b><i>c </i>of the light emitting region <b>26</b><i>a</i>. Then, a cathode electrode <b>30</b> may be formed on the pixel defining layer <b>26</b> including the organic light emitting layer <b>28</b> thereon.

0068The method according to the present embodiment may help ensure ideal ion implantation conditions by removing portions of the second conductive layer pattern <b>20</b> exposed by the aperture <b>22</b><i>b </i>in the capacitor forming region C. The portions of the second conductive layer pattern <b>20</b> exposed by the aperture <b>22</b><i>b </i>may be removed using the fourth mask, i.e., the same mask for forming the source electrode <b>24</b><i>a </i>and the drain electrode <b>24</b><i>b</i>. Accordingly, the implantation may provide the lower electrode <b>14</b><i>b </i>with sufficient conductivity without using a separate mask (see <figref idref="DRAWINGS">FIGS. 3F and 3G</figref>). Thus, it is possible to manufacture a flat panel display device using only five masks (first to fifth masks), thereby reducing manufacturing costs by decreasing a number of masks and processes.

0069Further, since a capacitor having a MOS (Metal-Oxide-Semiconductor) structure including the lower electrode <b>14</b><i>b</i>-insulating layer <b>16</b>-upper electrode <b>20</b><i>b </i>is implemented by a manufacturing process of a thin film transistor, it is possible to achieve high electrostatic capacity by using the relatively thin insulating layer (SiO₂) <b>16</b> as a dielectric. In addition, as high electrostatic capacity may be achieved from a relatively small area, it is possible to relatively increase a size (aperture ratio) of the light emitting region.

0070<figref idref="DRAWINGS">FIG. 4</figref> illustrates a cross-sectional view of a flat panel display device according to another embodiment. In particular, <figref idref="DRAWINGS">FIG. 4</figref> illustrates a top emission type organic light emitting display device.

0071A substrate <b>40</b> including an insulating material, e.g., transparent glass and/or plastic, may include a thin film transistor forming region T, a capacitor forming region C, and a pixel forming region P. A buffer layer <b>42</b> may be disposed on the substrate <b>40</b> in the thin film transistor forming region T, the capacitor forming region C, and the pixel forming region P. An active layer <b>44</b><i>a </i>including a channel region, a source region, and a drain region may be disposed on the buffer layer <b>12</b> in the thin film transistor forming region T. A lower electrode <b>44</b><i>b </i>may be disposed on the buffer layer <b>42</b> in the capacitor forming region C. The active layer <b>44</b><i>a </i>and the lower electrode <b>44</b><i>b </i>may include a semiconductor material, e.g., amorphous silicon or polysilicon. Dopant ions may be implanted in the lower electrode <b>44</b><i>d </i>for conductivity. In an implementation, the lower electrode <b>44</b><i>b </i>and the active layer <b>44</b><i>a </i>may be disposed in the same plane on the buffer layer <b>42</b>.

0072A first insulating layer <b>46</b> may be disposed on the buffer layer <b>12</b> including the active layer <b>44</b><i>a </i>and the lower electrode <b>44</b><i>b </i>thereon. The first insulating layer <b>46</b> may serve as a gate insulating layer of the thin film transistor and a dielectric of the capacitor.

0073A gate electrode <b>50</b><i>a </i>including a first conductive layer pattern <b>48</b> and a second conductive layer pattern <b>50</b> may be disposed on the first insulating layer <b>46</b> over, i.e., may overlie, the active layer <b>44</b><i>a</i>. An upper electrode <b>50</b><i>b </i>including the first conductive layer pattern <b>48</b> and the second conductive layer pattern <b>50</b> may be disposed on the first insulating layer <b>46</b> over, i.e., may overlie, the lower electrode <b>44</b><i>b</i>. In an implementation, the first conductive layer patterns <b>48</b> and the second conductive layer patterns <b>50</b> of the gate electrode <b>50</b><i>a </i>and upper electrode <b>50</b><i>b </i>may be disposed in the same plane, respectively, on the first insulating layer <b>46</b>.

0074A second insulating layer <b>52</b> may be disposed on the first insulating layer <b>46</b> including the gate electrode <b>50</b><i>a </i>and the upper electrode <b>50</b><i>b </i>thereon. An aperture pattern, i.e., a plurality of openings, may be formed in the second insulating layer <b>52</b> to expose portions of the source and drain regions of the active layer <b>44</b><i>a </i>as well as portions of the upper electrode <b>50</b><i>b</i>. The second conductive layer pattern <b>50</b> of the upper electrode <b>50</b><i>b </i>may be interposed between edges of the corresponding first conductive layer pattern <b>48</b> and the second insulating layer <b>52</b> thereon. The first conductive layer pattern <b>48</b> may include, e.g., a transparent conductive material; and the second conductive layer pattern <b>50</b> may include, e.g., a metal and/or an alloy.

0075A source electrode <b>54</b><i>a </i>and drain electrode <b>54</b><i>b </i>may be disposed on the second insulating layer <b>52</b> and may be connected to source and drain regions, respectively, of the active layer <b>44</b><i>a </i>through the aperture pattern. A third insulating layer <b>56</b> may be disposed on the second insulating layer <b>52</b> including the source electrode <b>54</b><i>a </i>and the drain electrode <b>54</b><i>b </i>thereon. A via-hole may be formed in the third insulating layer <b>56</b> to expose portions of the source electrode <b>54</b><i>a </i>or the drain electrode <b>54</b><i>b. </i>

0076An anode electrode <b>58</b> may be disposed on the third insulating layer <b>56</b> and may be connected to exposed portions of the source electrode <b>54</b><i>a </i>or the drain electrode <b>54</b><i>b </i>through the via-hole. A pixel defining layer <b>60</b> may be disposed on the third insulating layer <b>56</b> including the anode electrode <b>58</b> thereon. An aperture may be formed in the pixel defining layer <b>60</b> to expose portions of the anode electrode <b>58</b> in the light emitting region. An organic light emitting layer <b>62</b> may be disposed on the exposed portion of the anode electrode <b>58</b> in the light emitting region. A cathode electrode <b>64</b> may be disposed on the pixel defining layer <b>60</b> including the organic light emitting layer <b>62</b> thereon.

0077In the flat panel display device of the present embodiment, signals provided from outside may be stored in the capacitor. In addition, signals may be provided to the anode electrode <b>58</b> by the thin film transistor. Therefore, when a predetermined voltage is applied to the anode electrode <b>58</b> and the cathode electrode <b>64</b>, holes injected from the anode electrode <b>58</b> and electrons injected from the cathode electrode <b>64</b> may be recombined in the organic light emitting layer <b>62</b>. Thus, characters and/or images may be displayed by light emitted from the organic light emitting layer <b>62</b> to the outside.

0078<figref idref="DRAWINGS">FIGS. 5A to 5H</figref> illustrate cross-sectional views of stages in a method of manufacturing a flat panel display device according to another embodiment. In particular, the method of the present embodiment may form a flat panel display device having the structure of <figref idref="DRAWINGS">FIG. 4</figref>.

0079Referring to <figref idref="DRAWINGS">FIG. 5A</figref>, a substrate <b>40</b> including a thin film transistor forming region T, a capacitor forming region C, and a pixel forming region P may be provided. A buffer layer <b>42</b> and a semiconductor layer (not illustrated) may be sequentially formed on the substrate <b>40</b> including the thin film transistor forming region T, the capacitor forming region C, and the pixel forming region P. The semiconductor layer may be patterned to form an active layer <b>44</b><i>a </i>including a channel region, a source region, and a drain region on the buffer layer <b>42</b> in the thin film transistor forming region T as well as a lower electrode <b>44</b><i>b </i>on the buffer layer <b>42</b> in the capacitor forming region C. Thus, the active layer <b>44</b><i>a </i>and the lower electrode <b>44</b><i>b </i>may be formed at the same time. The patterning may be carried out by, e.g., photolithography and etching, using a first mask. The semiconductor layer may include, e.g., amorphous silicon or polysilicon, and, if desired, may be subjected to crystallization.

0080Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, a first insulating layer <b>46</b>, a first conductive layer <b>48</b>′, and a second conductive layer <b>50</b>′ may be sequentially formed on the buffer layer <b>42</b> including the active layer <b>44</b><i>a </i>and the lower electrode <b>44</b><i>b </i>thereon. The first insulating layer <b>46</b> may include, e.g., a silicon oxide film SiO₂. The first conductive layer <b>48</b>′ may include, e.g., a transparent conductive material having conductivity sufficient to be used an electrode. In an implementation, the transparent conductive material may include, e.g., amorphous ITO, ITO, poly-ITO, and/or IZO. The second conductive layer <b>50</b>′ may include, e.g., a metal. In an implementation, the metal may include, e.g., tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), chromium (Cr), niobium (Nb), and/or alloys thereof.

0081Referring to <figref idref="DRAWINGS">FIG. 5C</figref>, a gate electrode <b>50</b><i>a </i>and an upper electrode <b>50</b><i>b </i>may be formed on the active layer <b>44</b><i>a </i>and the lower electrode <b>44</b><i>b </i>by patterning the second conductive layer <b>50</b>′ and the first conductive layer <b>48</b>′ by, e.g., photolithography and etching, using a second mask. Thus, the gate electrode <b>50</b><i>a </i>and the upper electrode <b>50</b><i>b </i>may each include a first conductive layer pattern <b>48</b> and a second conductive layer pattern <b>50</b> and may be formed at the same time. In an implementation, high-density dopant ions may be implanted into the source and drain regions of the active layer <b>44</b><i>a </i>using the gate electrode <b>50</b><i>a </i>as a mask.

0082Then, a second insulating layer <b>52</b> may be formed on the first insulating layer <b>46</b> including the gate electrode <b>50</b><i>a </i>and the upper electrode <b>50</b><i>b </i>thereon.

0083Referring to <figref idref="DRAWINGS">FIG. 5D</figref>, an aperture pattern, i.e., a plurality of openings, including apertures <b>52</b><i>a </i>and <b>52</b><i>b </i>may be formed by patterning the second insulating layer <b>52</b> and the first insulating layer <b>46</b> by, e.g., photolithography and etching, using a third mask. The apertures <b>52</b><i>a </i>and <b>52</b><i>b </i>may expose portions of the source and drain regions of the active layer <b>44</b><i>a </i>as well as portions of the upper electrode <b>50</b><i>b</i>, respectively.

0084Referring to <figref idref="DRAWINGS">FIG. 5E</figref>, a conductive layer <b>54</b> may be formed on the second insulating layer <b>52</b> to fill the apertures <b>22</b><i>a </i>and <b>52</b><i>b. </i>

0085Referring to <figref idref="DRAWINGS">FIG. 5F</figref>, the conductive layer <b>54</b> may be patterned to form a source electrode <b>54</b><i>a </i>connected to the source region of the active layer <b>44</b><i>a </i>and a drain electrode <b>54</b><i>b </i>connected to the drain region of the active layer <b>44</b><i>a </i>through the aperture <b>52</b><i>a</i>. The patterning may be carried out by, e.g., photolithography and etching, using a fourth mask. During the patterning process, portions of the second conductive layer pattern <b>50</b> exposed by the aperture <b>52</b><i>b </i>in the capacitor forming region C may be removed using the fourth mask.

0086Referring to <figref idref="DRAWINGS">FIG. 5G</figref>, dopant ions may be implanted into the lower electrode <b>44</b><i>b </i>through the aperture <b>52</b><i>b </i>in the capacitor forming region C. In the implantation process, since the dopant ions may be implanted into the lower electrode <b>44</b><i>b </i>through the exposed portions of the first conductive layer pattern <b>48</b> and first insulating layer <b>46</b>, ion implantation energy may be adjusted such that the lower electrode <b>44</b><i>b </i>including the semiconductor material has sufficient conductivity.

0087Referring to <figref idref="DRAWINGS">FIG. 5H</figref>, a third insulating layer <b>56</b> may be formed on the second insulating layer <b>52</b> including the source electrode <b>54</b><i>a </i>and the drain electrode <b>54</b><i>b </i>thereon. A via-hole may be formed to expose portions of the source electrode <b>54</b><i>a </i>or the drain electrode <b>54</b><i>b </i>by patterning the third insulating layer <b>56</b> by, e.g., photolithography and etching, using a fifth mask.

0088A conductive layer (not illustrated) may be formed on the third insulating layer <b>56</b> to fill the via-hole. An anode electrode <b>58</b> connected to exposed portions of the source electrode <b>54</b><i>a </i>or drain electrode <b>54</b><i>b </i>through the via-hole may be formed by patterning the conductive layer by, e.g., photolithography and etching, using a sixth mask.

0089A pixel defining layer <b>60</b> may be formed on the third insulating layer <b>56</b> including the anode electrode <b>58</b> thereon. An aperture may be formed to expose portions of the anode electrode <b>58</b> in the light emitting region by patterning the pixel defining layer <b>60</b> by, e.g., photolithography and etching, using a seventh mask. Further, an organic light emitting layer <b>62</b> may be formed on exposed portions of the anode electrode <b>58</b> in the light emitting region. A cathode electrode <b>64</b> may be formed on the pixel defining layer <b>60</b> including the organic light emitting layer <b>62</b> thereon.

0090The method according to the present embodiment may help ensure suitable ion implantation conditions by removing portions of the second conductive layer pattern <b>50</b> exposed by the aperture <b>52</b><i>b </i>in the capacitor forming region C. the portions of the second conductive layer pattern <b>50</b> exposed by the aperture <b>52</b><i>b </i>may be removed using the fourth mask, i.e., the same mask for forming the source electrode <b>54</b><i>a </i>and drain electrode <b>54</b><i>b</i>. Accordingly, the implantation may provide the lower electrode <b>44</b><i>b </i>with sufficient conductivity without using a separate mask (see <figref idref="DRAWINGS">FIGS. 5F and 5G</figref>). Thus, it is possible to manufacture a flat panel display device using fewer masks, thereby reducing manufacturing costs by decreasing a number of masks and processes.

0091Further, since a capacitor having a MOS (Metal-Oxide-Semiconductor) structure including the lower electrode <b>44</b><i>b</i>-insulating layer <b>46</b>-upper electrode <b>50</b><i>b </i>may be formed by the manufacturing process of an embodiment, it is possible to achieve high electrostatic capacity by using a relatively thin insulating layer (SiO₂) <b>46</b> as a dielectric. As high electrostatic capacity may be achieved from a relatively small area, it is possible to relatively increase a size (aperture ratio) of the light emitting region.

0092Since dopant ions may be implanted in the lower electrode formed of a semiconductor material without using a separate mask to provide conductivity, it is possible to manufacture a flat panel display device, using, e.g., five masks (first to fifth masks). Therefore, it is possible to reduce manufacturing cost by decreasing the number of masks and processes, as compared with the related art. Thus, it may not cost a great deal to manufacture the devices due to a limited number of masks; and yield may be increased due to the reduction in process steps, such that overall manufacturing cost may decrease.

0093Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.