Method of manufacturing semiconductor memory device

0001The present application is a Continuation Application of U.S. patent application Ser. No. 12/149,439, filed on May 1, 2008, now U.S. Pat. No. 8,017,457 which is based on Japanese patent application No. 2007-124554, filed on May 9, 2007, the entire contents of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a method of manufacturing a semiconductor memory device. The present invention particularly relates to a method of manufacturing a non-volatile semiconductor memory element having a limit on the number of times of rewriting information and a volatile semiconductor memory element such as DRAM having no upper limit on the number of times of rewriting information with high integration on the same semiconductor substrate and at low cost.

00042. Description of Related Art

0005In recent years, resistance RAM (RRAM) having a variable resistance memory element as memory that is used in information equipment such as computers and mobile telephones and the like has been receiving attention. A variable resistance memory element is a memory element that is basically constituted by a thin film resistor such as a binary metal oxide, a transition metal oxide, an aluminum oxide, a silicon oxide or germanium oxide being sandwiched between two electrodes, and makes use of the phenomenon in which the resistance of the thin film resistor changes by impressing an electrical field or flowing an electrical current across the electrodes.

0006Since the resistance value of the thin-film resistor is stored even when the impression of the electrical field or current is removed, it is possible to realize non-volatile memory. The information that is stored in the variable resistance memory element can be read out by comparing the resistance value with a reference value. This kind of memory element is generally called RRAM as mentioned above. It is possible to constitute a variable resistance memory element in an array such as DRAM (Dynamic Random Access Memory) by combining with a selection transistor.

0007For example, <figref idref="DRAWINGS">FIG. 25</figref> shows a non-volatile semiconductor memory element disclosed in Japanese Unexamined Patent Application, First Publication, No. 2004-342843 as an example of a variable resistance memory element that can readily store and read out information, and can be readily manufactured with a comparatively easy manufacturing method. <figref idref="DRAWINGS">FIG. 26</figref> shows a non-volatile semiconductor memory element disclosed in Japanese Unexamined Patent Application, First Publication, No. 2006-173267 as an example of another example of a variable resistance memory element that can stably perform operations such as recording information with a constitution that is stable even with respect to heat.

0008The non-volatile semiconductor memory element shown in <figref idref="DRAWINGS">FIG. 25</figref> has a substrate <b>401</b>, a lower electrode <b>402</b>, an insulation film <b>403</b>, an amorphous thin film <b>404</b>, an upper electrode <b>405</b>, an electrode layer <b>406</b>, and a conduction layer <b>407</b>. Also, non-volatile semiconductor memory element shown in <figref idref="DRAWINGS">FIG. 26</figref> has a substrate <b>501</b>, a lower electrode <b>502</b>, an ion source layer <b>503</b>, a memory layer <b>504</b>, an insulating layer <b>505</b> denoted by reference numeral <b>505</b>, and an upper electrode <b>506</b>.

0009The conventional memory elements shown above utilize the oxidation-reduction action of metal, such as silver, copper, or zinc. Specifically, when an electrical field is impressed on a thin-film resistor (the amorphous thin film <b>404</b> and the memory layer <b>504</b>) consisting of a transition metal oxide, an aluminum oxide, a silicon oxide or germanium oxide sandwiched between two electrodes (the upper electrodes <b>405</b> and <b>506</b> and the lower electrodes <b>402</b> and <b>502</b>), the aforementioned metal that exists in one electrode is oxidized (ionized), moves through the thin-film electrode to be reduced and deposited at the other electrode, whereby the resistance value of the thin-film electrode falls. Also, when an electrical field is impressed in the reverse direction, the deposited metal is once again ionized and returns to the original electrode, and so the resistance value of the thin-film electrode rises. Thereafter, even if the electrical field between the electrodes is removed, the resistance value of the thin-film resistor is maintained, and information is stored in a non-volatile manner using this phenomenon. In addition, these memory elements are capable of reading and writing at high speeds on par with DRAM, and so their use as non-volatile RAM has been expected.

0010However, it is has been reported that the abovementioned memory elements have a limit to the number of changes of the resistance value of the thin-film resistor, that is, the number of times of rewriting information. Accordingly, the abovementioned memory element is not suitable for uses in which information is frequently rewritten as work memory, such as DRAM (Dynamic Random Access Memory) Therefore, there is a problem that it cannot be used as non-volatile RAM for realizing computer systems, mobile phones, information appliance products, etc. with an instant-on function.

0011On the other hand, while DRAM is suited to uses such as information being frequently rewritten as work memory, due to its being volatile memory, it has the characteristic of the information being lost when the power is turned off.

0012In this way, since RRAM and DRAM have a relationship of complementing each other, it has been desired for them to be used in combination. Therefore, if it were possible to form these two types of memory elements with the same manufacturing process and on the same chip, it would be possible to provide a memory system that is easy to use at a low cost, and so its realization has been sought.

0013The present invention has been achieved in view of the above circumstances, and has as its object to provide a method of manufacturing a non-volatile semiconductor memory having a limit on the number of times of rewriting information and a volatile semiconductor memory element such as DRAM having no upper limit on the number of times of rewriting information with high integration on the same semiconductor substrate and at low cost.

SUMMARY OF THE INVENTION

0014In order to achieve the abovementioned object, the present invention adopts the following constitution.

0015A method of manufacturing a semiconductor memory device of the present invention comprises the steps of forming a first selection transistor and a second selection transistor; forming a variable resistance element by sequentially laminating a first electrode that is connected to the first selection transistor, a variable resistance layer that contacts the first electrode, and a second electrode that contacts the variable resistance layer; and forming a capacitance element by sequentially laminating a third electrode that is connected to the second selection transistor, a dielectric layer that contacts the third electrode and consists of the same material as the variable resistance layer, and a fourth electrode that contacts the dielectric layer; wherein either one of the first electrode or the second electrode is formed with the same material as the third electrode and the fourth electrode, while the other one of the first electrode or the second electrode is formed with a different material than the third electrode and the fourth electrode, and the semiconductor memory device is formed on a same semiconductor substrate with a non-volatile semiconductor memory element provided with the first selection transistor and the variable resistance element that is connected to the first selection transistor, and a volatile semiconductor memory element provided with the second selection transistor and the capacitance element that is connected to the second selection transistor.

0016Also, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable that, other than forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode, the step of forming the volatile semiconductor memory element and the step of forming the non-volatile semiconductor memory element be essentially the same.

0017Also, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable in the step of forming the variable resistance element and the step of forming the capacitance element to simultaneously form a first electrode dummy electrode and the third electrode with the same material; form the first electrode with a different material than the third electrode after removing the first electrode dummy electrode; simultaneously form the dielectric layer and the variable resistance layer on the first electrode and the third electrode, respectively; and simultaneously form the second electrode and the fourth electrode consisting of the same material as the third electrode on the dielectric layer and the variable resistance layer, respectively.

0018Furthermore, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable in the step of forming the variable resistance element and the step of forming the capacitance element to simultaneously form the first electrode and the third electrode with the same material; simultaneously form the dielectric layer and the variable resistance layer on the first electrode and the third electrode, respectively; simultaneously form a second electrode dummy electrode and the fourth electrode with the same material as the first electrode and the third electrode on the dielectric layer and the variable resistance layer, respectively; and form the second electrode with a different material than the first, third and fourth electrodes after removing the second electrode dummy electrode.

0019Also, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable in the step of forming the variable resistance element and the step of forming the capacitance element to simultaneously form the first electrode and the third electrode with the same material; simultaneously form the dielectric layer and the variable resistance layer on the first electrode and the third electrode, respectively; simultaneously form the second electrode and a fourth electrode dummy electrode with a different material than the first electrode and the third electrode on the dielectric layer and the variable resistance layer, respectively; and form the fourth electrode with the same material as the first and third electrodes after removing the fourth electrode dummy electrode.

0020Moreover, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable to laminate the fourth electrode on the second electrode.

0021Moreover, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable in the step of forming the variable resistance element and the step of forming the capacitance element to simultaneously form a first electrode dummy electrode and the third electrode with the same material; remove a portion of the first electrode dummy electrode and form the first electrode on the remaining first electrode dummy electrode with a different material than the third electrode; simultaneously form the dielectric layer and the variable resistance layer on the first electrode and the third electrode, respectively; and simultaneously form the second electrode and the fourth electrode each consisting of the same material as the third electrode on the dielectric layer and the variable resistance layer, respectively.

0022Moreover, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable that the material that constitutes the dielectric layer and the variable resistance layer includes any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide.

0023Furthermore, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable that the transition metal oxide consists of any one or a mixture of tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide.

0024Furthermore, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable to form the third electrode and the fourth electrode and either one of the first electrode and the second electrode with any of tungsten, titanium, platinum, and gold.

0025Furthermore, in the method of manufacturing a semiconductor memory device of the present invention, it is preferable that the other of the first electrode and the second electrode be formed with any of silver, copper, and zinc.

0026According to the aforementioned method of manufacturing a semiconductor memory device, in the step of forming the variable resistance element and the step of forming the capacitance element, by forming the dielectric layer and the variable resistance layer with a mutually identical material, forming either of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode, and forming the other of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode, it is possible to readily form the non-volatile semiconductor memory element and the volatile semiconductor memory element on the same semiconductor substrate.

0027Also, according to the aforementioned method of manufacturing a semiconductor memory device, other than forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode, the step of forming the volatile semiconductor memory element and the step of forming the non-volatile semiconductor memory element are essentially the same. Therefore, it is possible to manufacture a volatile semiconductor memory element and a non-volatile semiconductor memory element nearly simultaneously.

0028Also, the aforementioned method of manufacturing a semiconductor memory device is a method that forms a first electrode dummy electrode simultaneously with the third electrode and with the same material as the third electrode, forms the first electrode with a different material than the third electrode after removing the first electrode dummy electrode, and sequentially forms the dielectric layer and variable resistance layer and the second electrode and fourth electrode, and just by adding a series of steps of formation and removal of the first electrode dummy electrode and formation of the first electrode, it is possible to readily and with a high integration form a volatile semiconductor memory element and a non-volatile semiconductor memory element.

0029Furthermore, the aforementioned method of manufacturing a semiconductor memory device is a method that forms a second electrode dummy electrode simultaneously with the fourth electrode and with the same material as the fourth electrode and forms the second electrode with a different material than the first, third, and fourth electrodes after removing the second electrode dummy electrode, and so just by adding a series of steps of formation and removal of the second electrode dummy electrode and formation of the second electrode, it is possible to readily and with a high integration form a volatile semiconductor memory element and a non-volatile semiconductor memory element.

0030Furthermore, the aforementioned method of manufacturing a semiconductor memory device is a method that forms a fourth electrode dummy electrode simultaneously with the fourth electrode and with a different material than the first and third electrodes, and forms the fourth electrode with the same material as the first and third electrodes after removing the fourth electrode dummy electrode, and so just by adding a series of steps of formation and removal of the fourth electrode dummy electrode and formation of the fourth electrode, it is possible to readily and with a high integration form a volatile semiconductor memory element and a non-volatile semiconductor memory element.

0031Furthermore, the aforementioned method of manufacturing a semiconductor memory device is a method that forms a first electrode dummy electrode simultaneously with the third electrode and with the same material as the third electrode, and forms the first electrode with a different material than the third electrode after removing a portion of the first electrode dummy electrode, and so just by adding a series of steps of formation of the first electrode dummy electrode, removal of a portion thereof and formation of the first electrode, it is possible to readily and with a high integration form a volatile semiconductor memory element and a non-volatile semiconductor memory element.

0032According to the method of manufacturing a semiconductor memory device of the present invention, it is possible to manufacture a non-volatile semiconductor memory element having a limit on the number of times of rewriting information and a volatile semiconductor memory element such as DRAM having no upper limit on the number of times of rewriting information with high integration on the same semiconductor substrate and at low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

0033<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> are circuit diagrams showing the circuit composition of the semiconductor memory device which is the first embodiment the present invention.

0034<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are partial sectional drawings showing the main portions of the semiconductor memory device which is the first embodiment of the present invention.

0035<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>, specifically being partial sectional drawings that show the formation process of a first electrode dummy electrode and a third electrode.

0036<figref idref="DRAWINGS">FIGS. 4A and 4B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>, specifically being partial sectional drawings that show the process of deleting the first electrode dummy electrode.

0037<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>, specifically being partial sectional drawings that show the formation process of the first electrode.

0038<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>, specifically being partial sectional drawings that show the formation process of the dielectric layer and variable resistance layer and the second and fourth electrodes.

0039<figref idref="DRAWINGS">FIGS. 7A and 7B</figref> are partial sectional drawings that show the main portions of the semiconductor memory device of the second embodiment of the present invention.

0040<figref idref="DRAWINGS">FIGS. 8A and 8B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 7A</figref> and <figref idref="DRAWINGS">FIG. 7B</figref>, specifically being partial sectional drawings that show the formation process of the first electrode and third electrode and the dielectric layer and variable resistance layer.

0041<figref idref="DRAWINGS">FIGS. 9A and 9B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 7A</figref> and <figref idref="DRAWINGS">FIG. 7B</figref>, specifically being partial sectional drawings that show the formation process of the second electrode dummy electrode and the fourth electrode.

0042<figref idref="DRAWINGS">FIGS. 10A and 10B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 7A</figref> and <figref idref="DRAWINGS">FIG. 7B</figref>, specifically being partial sectional drawings that show the process for eliminating the second electrode dummy electrode.

0043<figref idref="DRAWINGS">FIGS. 11A and 11B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 7A</figref> and <figref idref="DRAWINGS">FIG. 7B</figref>, specifically being partial sectional drawings that show the formation process of the second electrode.

0044<figref idref="DRAWINGS">FIGS. 12A and 12B</figref> are partial sectional drawings that show the main portions of the semiconductor memory device of the third embodiment of the present invention.

0045<figref idref="DRAWINGS">FIGS. 13A and 13B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 12A</figref> and <figref idref="DRAWINGS">FIG. 12B</figref>, specifically being partial sectional drawings that show the formation steps of the first electrode and third electrode and the dielectric layer and variable resistance layer.

0046<figref idref="DRAWINGS">FIGS. 14A and 14B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 12A</figref> and <figref idref="DRAWINGS">FIG. 12B</figref>, specifically being partial sectional drawings that show the formation process of the second electrode and the fourth electrode dummy electrode.

0047<figref idref="DRAWINGS">FIGS. 15A and 15B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 12A</figref> and <figref idref="DRAWINGS">FIG. 12B</figref>, specifically being partial sectional drawings that show the process of deleting the fourth electrode dummy electrode.

0048<figref idref="DRAWINGS">FIGS. 16A and 16B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 12A</figref> and <figref idref="DRAWINGS">FIG. 12B</figref>, specifically being partial sectional drawings that show the formation process of the fourth electrode.

0049<figref idref="DRAWINGS">FIGS. 17A and 17B</figref> are partial sectional drawings that show the main portions of the semiconductor memory device of the fourth embodiment of the present invention.

0050<figref idref="DRAWINGS">FIGS. 18A and 18B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 17A</figref> and <figref idref="DRAWINGS">FIG. 17B</figref>, specifically being partial sectional drawings that show the formation process of the first electrode dummy electrode and the third electrode.

0051<figref idref="DRAWINGS">FIGS. 19A and 19B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 17A</figref> and <figref idref="DRAWINGS">FIG. 17B</figref>, specifically being partial sectional drawings that show the process of removing a portion of the first electrode dummy electrode.

0052<figref idref="DRAWINGS">FIGS. 20A and 20B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 17A</figref> and <figref idref="DRAWINGS">FIG. 17B</figref>, specifically being partial sectional drawings that show the process of forming the first electrode on the first electrode dummy electrode.

0053<figref idref="DRAWINGS">FIGS. 21A and 21B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 17A</figref> and <figref idref="DRAWINGS">FIG. 17B</figref>, specifically being partial sectional drawings that show the process of making the first electrode flat.

0054<figref idref="DRAWINGS">FIGS. 22A and 22B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 17A</figref> and <figref idref="DRAWINGS">FIG. 17B</figref>, specifically being partial sectional drawings that show the formation process of the dielectric layer and variable resistance layer and the second and fourth electrodes.

0055<figref idref="DRAWINGS">FIG. 23</figref> is a conceptual diagram explaining the address space of the region that performs the writing of the volatile mode by the volatile memory element in the semiconductor memory device of the present invention, and the region that performs writing of the non-volatile mode by the non-volatile memory element.

0056<figref idref="DRAWINGS">FIG. 24</figref> is a block diagram showing the system configuration of a mobile phone which uses the semiconductor memory device of the present invention.

0057<figref idref="DRAWINGS">FIG. 25</figref> is a cross-sectional schematic drawing showing the main portions of an example of a conventional semiconductor memory device.

0058<figref idref="DRAWINGS">FIG. 26</figref> is a cross-sectional schematic drawing showing the main portions of another example of a conventional semiconductor memory device.

DETAILED DESCRIPTION OF THE INVENTION

0059Hereinbelow, a method of manufacturing a semiconductor memory device of the present invention shall be described with reference to the drawings. Note that the drawings referred to in the description below are for describing a method of manufacturing a semiconductor memory device of the present embodiments, and size, thickness and dimensions of each portion illustrated may differ from the dimensional relationship of each portion in the actual semiconductor device and the manufacturing method thereof.

0000[First Embodiment]

0060First, a semiconductor memory device and the manufacturing method thereof of a first embodiment shall be described with reference to <figref idref="DRAWINGS">FIG. 1A</figref> to <figref idref="DRAWINGS">FIG. 6B</figref>. FIG <b>1</b>A and <figref idref="DRAWINGS">FIG. 1B</figref> are circuit diagrams that show the circuit composition of the semiconductor memory device of this embodiment, and <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref> are partial sectional drawings showing the main portions of the semiconductor memory device of the present embodiment. Also, <figref idref="DRAWINGS">FIG. 3A</figref> to <figref idref="DRAWINGS">FIG. 6B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>.

0000(Semiconductor Memory Device)

0061<figref idref="DRAWINGS">FIG. 1A</figref> is an equivalent circuit drawing of a group of non-volatile semiconductor memory elements, and <figref idref="DRAWINGS">FIG. 1B</figref> is an equivalent circuit drawing of a group of volatile semiconductor memory elements that are provided in the semiconductor memory device of the present embodiment.

0062As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, the group of non-volatile semiconductor memory elements is basically constituted from n×m non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm, n word lines WL<b>11</b> to WL<b>1</b><i>n</i>, m bit lines BL<b>11</b> to BL<b>1</b><i>m</i>, and m common plate lines PL<b>1</b>.

0063The non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm are basically constituted from a selection transistor QM<b>1</b> and a variable resistance element RM that is connected to the selection transistor QM<b>1</b>. Then, for example in the semiconductor memory element MCN<b>11</b>, the gate electrode of the section transistor QM<b>1</b> is connected to the world line WL<b>11</b>, and the source electrode is connected to the bit line BL<b>11</b>, and the drain electrode is connected to one electrode (first electrode) of the variable resistance element RM. Also, the other electrode (second electrode) of the variable resistance element RM is connected to the common plate line PL<b>1</b>.

0064The variable resistance element RM is an element whose resistance value changes depending on the direction of electrical current therethrough, and even in the state of a current not being impressed, that resistance value is maintained. Therefore, it is possible to make it operate as a non-volatile memory element by reading out this resistance value.

0065On the other hand, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>, the volatile semiconductor memory element group is so-called DRAM, so it is basically constituted from n×m volatile semiconductor memory elements MCD<b>11</b> to MCDnm, n word lines WL<b>21</b> to WL<b>2</b><i>n</i>, m bit lines BL<b>21</b> to BL<b>2</b><i>m</i>, and m common plate lines PL<b>2</b>.

0066The volatile semiconductor memory elements MCD<b>11</b> to MCDnm are basically constituted from a selection transistor QM<b>2</b> (a separate selection transistor) and a capacitance element CM that is connected to the selection transistor QM<b>2</b>.

0067For example, in the semiconductor memory element MCD<b>11</b>, the gate electrode of the selection transistor QM<b>2</b> is connected to the word line WL<b>21</b>, the source electrode is connected to the bit line BL<b>21</b>, and the drain electrode is connected to one electrode (the third electrode) of the capacitance element CM. Also, the other electrode (the fourth electrode) of the capacitance element CM is connected to the common plate line PL<b>2</b>.

0068The capacitance element CM is an element that is capable of retaining any electric charge, and so it is possible to make it operate as a volatile memory element by reading out the existence of an electrical charge.

0069Next, specific structures of the respective memory elements shall be described using the semiconductor memory element MCN<b>1</b><i>m </i>and the semiconductor memory element MCD<b>1</b><i>m </i>as examples and referring to <figref idref="DRAWINGS">FIG. 2A</figref> and <figref idref="DRAWINGS">FIG. 2B</figref>. <figref idref="DRAWINGS">FIG. 2A</figref> shows a sectional frame format of the non-volatile semiconductor memory element MCN<b>1</b><i>m</i>, and <figref idref="DRAWINGS">FIG. 2B</figref> is a sectional schematic view of the volatile semiconductor memory element MCD<b>1</b><i>m. </i>

0070In <figref idref="DRAWINGS">FIG. 2A</figref>, gate electrodes <b>3</b> that consist of polysilicon or the like are formed on a semiconductor substrate <b>1</b> that consists of, for example, single crystal silicon via a gate insulating film <b>2</b> that consists of silicon oxide. The gate electrodes <b>3</b> are formed by extending a portion of the word lines WL<b>11</b> to WL<b>1</b><i>n</i>. A sidewall <b>4</b> consisting of silicon nitride or the like is formed on both sides of each gate electrode <b>3</b>. A source region S and a drain region D in which an impurity element is diffused are formed in the semiconductor substrate <b>1</b> to be positioned on both sides of each gate electrode <b>3</b>. The source region S is connected to the bit line BL<b>1</b><i>m </i>through a bit line contact plug <b>5</b>, and, on the other hand, the drain region D is connected to the variable resistance element RM via a resistance contact plug <b>6</b>. The bit line contact plug <b>5</b> and the resistance contact plug <b>6</b> are for example made of a metal, such as tungsten. In this way, the section transistor QM<b>1</b> is constituted.

0071Moreover, a first interlayer insulation film <b>11</b> that consists of silicon oxide or the like is formed on the semiconductor substrate <b>1</b>, so that the gate electrode <b>3</b> is covered with the first interlayer insulation film <b>11</b>. Also, the bit line BL consisting of Al, Cu or the like is formed on the first interlayer insulating film <b>11</b>. And the bit line contact plug <b>5</b> that connects the bit line BL<b>1</b><i>m </i>and the source region S is formed so as to penetrate the first interlayer insulating film <b>11</b>. Furthermore, a second interlayer insulating film <b>12</b> is laminated on the first interlayer insulating film <b>11</b> and the bit line BL<b>1</b><i>m. </i>

0072Next, the variable resistance element RM is constituted by a first electrode <b>21</b> that is connected to the selection transistor QM<b>1</b> via a resistance contact plug <b>6</b>, a variable resistance layer <b>22</b> that connects to the first electrode <b>21</b>, and a second electrode <b>23</b> that connects to the variable resistance layer <b>22</b> that are laminated one by one. The first electrode <b>21</b> is formed on the second interlayer insulation film <b>12</b>, and the resistance contact plug <b>6</b> is connected to this first electrode <b>21</b>. The resistance contact plug <b>6</b> penetrates the first interlayer insulating film <b>11</b> and the second interlayer insulating film <b>12</b> to be connected to the drain region D. Thus, the drain region D of selection transistor QM<b>1</b> is connected to the first electrode <b>21</b>. Moreover, the third interlayer insulation film <b>13</b> is laminated on the second interlayer insulating film <b>12</b>, and so the upper surface of the first electrode and the upper surface of the third interlayer insulation film <b>13</b> form a continuous flat surface. Then, a variable resistance layer <b>22</b> and a second electrode <b>23</b> are laminated on this flat surface. Furthermore, a fourth interlayer insulating film <b>14</b> that consists of silicon oxide or the like, a wiring layer <b>31</b>, and a fifth interlayer insulating film <b>15</b> are laminated one by one on the second electrode <b>23</b>.

0073The first electrode <b>21</b> is formed with silver, copper, zinc, or the like, and is preferably formed with copper. On the other hand, the second electrode <b>23</b> is formed with tungsten, titanium, platinum, gold, or the like, being preferably formed with tungsten, and constitutes a portion of the common plate line PL<b>1</b>. Moreover, the variable resistance layer <b>22</b> consists of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide, with a transition metal oxide being particularly preferable. Examples of a transition metal oxide include tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide either singly or in combination, with hafnium oxide being particularly preferable.

0074The transition metal oxide or the like that constitutes the variable resistance layer <b>22</b> as described below can retain a conductive filament inside, and so by sandwiching this variable resistance layer <b>22</b> between the first electrode <b>21</b> and the second electrode <b>23</b>, it is possible to make it function as the variable resistance element RM.

0075Next, the volatile semiconductor memory element MCD<b>11</b> shall be described with reference to <figref idref="DRAWINGS">FIG. 2B</figref>. Similarly to <figref idref="DRAWINGS">FIG. 2A</figref>, the gate electrodes <b>3</b> are formed on the semiconductor substrate <b>1</b> via the gate insulating film <b>2</b>, the sidewall <b>4</b> is formed on both sides of each gate electrode <b>3</b>, and the source region S and the drain region D are formed in the semiconductor substrate <b>1</b> at locations on both sides of the gate electrode <b>3</b>. The source region S is connected to a bit line BL<b>2</b><i>m </i>through the bit line contact plug <b>5</b>, while the drain region D is connected to the capacitance element CM via the capacitance contact plug <b>7</b>. The bit line contact plug <b>5</b> and the capacitance contact plug <b>7</b> are, for example, constituted from a metal such as tungsten. Thus, the separate selection transistor QM<b>2</b> is constituted.

0076Also, the first interlayer insulating film <b>11</b> is formed on the semiconductor substrate <b>1</b> so as to cover the gate electrodes <b>3</b>, and the bit line BL<b>2</b><i>m </i>is formed on the first interlayer insulating film <b>11</b>. Then, the bit line contact plug <b>5</b> that connects the bit line BL<b>2</b><i>m </i>and the source region S is formed so as to penetrate the first interlayer insulating film <b>11</b>. Furthermore, the second interlayer insulating film <b>12</b> is laminated on the first interlayer insulating film <b>11</b> and the bit line BL<b>2</b><i>m. </i>

0077Next, the capacitance element CM is constituted by a third electrode <b>41</b> that is connected to the separate selection transistor QM<b>2</b> through the capacitance contact plug <b>7</b>, a dielectric layer <b>42</b> that connects to the third electrode <b>41</b>, and a fourth electrode <b>43</b> that connects to the dielectric layer <b>42</b> that are laminated one by one. The third electrode <b>41</b> is formed on the second interlayer insulation film <b>12</b>, and the capacitance contact plug <b>7</b> is connected to this third electrode <b>41</b>. The capacitance contact plug <b>7</b> penetrates the first interlayer insulating film <b>11</b> and the second interlayer insulating film <b>12</b> to be connected to drain region D. Thus, the drain region D of the separate selection transistor QM<b>2</b> is connected to the third electrode <b>41</b>. Moreover, the third interlayer insulating film <b>13</b> is laminated on the second interlayer insulating film <b>12</b>, and so the upper surface of the third electrode <b>41</b> and the upper surface of the third interlayer insulating film <b>13</b> form a continuous flat surface. Then, a dielectric layer <b>42</b> and a fourth electrode <b>43</b> are laminated on this flat surface. Furthermore, the fourth interlayer insulating film <b>14</b>, the wiring layer <b>31</b>, and the fifth interlayer insulating film <b>15</b> are laminated one by one on the fourth electrode <b>43</b>.

0078The third electrode <b>41</b> and the fourth electrode <b>43</b> consist of the same material as the second electrode <b>23</b>, being for example formed with tungsten. The fourth electrode <b>43</b> constitutes a portion of the common plate line PL<b>2</b>. Moreover, the dielectric layer <b>42</b> consists of the same material as the variable resistance layer <b>22</b>, consisting of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide, with a transition metal oxide being particularly preferable. Examples of a transition metal oxide include tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide either singly or in combination, with hafnium oxide being particularly preferable.

0079Since the transition metal oxide or the like that constitutes the dielectric layer <b>42</b> is a material that has a high dielectric constant, by sandwiching this dielectric layer <b>42</b> between the third electrode <b>41</b> and the fourth electrode <b>43</b>, it is possible to make it function as a capacitor (capacitance element CM).

0080Next, the operation of the semiconductor memory elements MCN<b>11</b> to MCNnm and the semiconductor memory elements MCD<b>11</b> to MCDnm shall be described.

0081First, the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm shall be described. When the selection transistor QM<b>1</b> is turned ON and current is flowed from the first electrode <b>21</b> to the second electrode <b>23</b>, the silver, copper, zinc, or the like which constitutes the first electrode <b>21</b> is oxidized (ionized) and moves through the second electrode <b>22</b> to be reduced and deposited at the second electrode <b>23</b> side. Thereby, a conductive filament that penetrates the variable resistance layer <b>22</b> is formed by silver or copper and the like between the first electrode <b>21</b> and the second electrode <b>23</b>, and the resistance value of the variable resistance layer <b>22</b> decreases. Conversely, when current is passed from the second electrode <b>23</b> to the first electrode <b>21</b>, the conductive filament oxidizes (ionizes) and disappears, and silver or copper and the like is reduced and deposited at the first electrode <b>21</b> side. Thus, the conductive filament between the first electrode <b>21</b> and the second electrode <b>23</b> disappears, and the resistance value of the variable resistance layer <b>22</b> increases. Since the resistance value of this variable resistance layer <b>22</b> is maintained even in the state where a voltage is not impressed between the first electrode <b>21</b> and the second electrode <b>23</b>, it can be operated as a non-volatile memory cell by reading out this resistance value.

0082Moreover, high-speed reading and writing on par with DRAM are possible for the variable resistance element RM of the above-mentioned constitution, and its use as non-volatile RAM is also possible.

0083Next, the volatile semiconductor memory elements MCD<b>11</b> to MCDnm shall be described. When an electric field is impressed between the third electrode <b>41</b> of the capacitance element CM and the fourth electrode <b>43</b> by raising the potential of a discretionary word line and bit line to turn ON the selection transistor QM<b>2</b>, the dielectric layer <b>42</b> is charged and maintained.

0084Conversely, when the potential of a discretionary bit line is lowered while maintaining the potential of a word line, the electric charge that was charged to the capacitance element CM is discharged. Since the electrical capacity in this capacitance element CM can be maintained by performing a refresh operation at any time, it can be operated as a volatile memory cell by reading this electrical capacity.

0000(Method of Manufacturing Semiconductor Memory Device)

0085Next, a method of manufacturing the abovementioned semiconductor memory device shall be described with reference to the drawings.

0086The method of manufacturing the semiconductor memory device of the present embodiment consists of a transistor formation process and an element formation process that forms the variable resistance element RM and the capacitance element CM. The method, in the element formation process, involves forming a first electrode dummy electrode and the third electrode with the same material, forming the first electrode with a material that differs from the third electrode after removing the first electrode dummy electrode, forming a dielectric layer and a variable resistance layer, and forming the second electrode and the fourth electrode.

0087Hereinbelow, <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> to <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> shall be referred to in the description below. <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> are partial sectional drawings that show the formation steps of the first electrode dummy electrode and the third electrode. <figref idref="DRAWINGS">FIGS. 4A and 4B</figref> are partial sectional drawings that show the steps of deleting the first electrode dummy electrode. <figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are partial sectional drawings that show the formation steps of the first electrode. <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are partial sectional drawings that show the formation steps of the dielectric layer and variable resistance layer and the second and fourth electrodes.

0088Note that <figref idref="DRAWINGS">FIGS. 3A to 6A</figref> are drawings that correspond to <figref idref="DRAWINGS">FIG. 2A</figref>, while <figref idref="DRAWINGS">FIGS. 3B to 6B</figref> are drawings that correspond to <figref idref="DRAWINGS">FIG. 2B</figref>. The same applies to the other embodiments.

0000Transistor Formation Process

0089First, the selection transistor and the separate selection transistor are formed on the semiconductor substrate as shown in <figref idref="DRAWINGS">FIG. 3A</figref> and <figref idref="DRAWINGS">FIG. 3B</figref>.

0090In describing the outline of the transistor formation process, first the gate insulating film <b>2</b> is formed on the semiconductor substrate <b>1</b> by for example a thermal oxidation method or the like, the gate electrode <b>3</b> and a sidewalls <b>4</b> are formed on the gate insulating film <b>2</b>, and next the source region S and the drain region D are formed by diffusing an impurity in the semiconductor substrate <b>1</b> by, for example, an ion infusion method.

0091Then, the first interlayer insulating film <b>11</b> is formed on the semiconductor substrate <b>1</b>, and a through-hole for the bit line contact plug is formed in the first interlayer insulation film <b>11</b>. Thereby, the source region S is exposed. Next, tungsten or the like is filled in the through-hole via for example the sputtering method to form the bit line contact plug <b>5</b> connected to the source region S. Furthermore, the bit lines BL<b>1</b><i>m </i>and BL<b>2</b><i>m </i>that are connected to the bit line contact plug <b>5</b> are formed on the first interlayer insulation film <b>11</b>.

0092Then, the second interlayer insulating film <b>12</b> is formed on bit lines BL<b>1</b><i>m</i>, BL<b>2</b><i>m </i>and the first interlayer insulation film <b>11</b>, and by forming a through-hole for the resistance contact plug <b>6</b> and a through-hole for the capacitance contact plug <b>7</b>, the drain region D is exposed. Next, by filling tungsten or the like in each through-hole by, for example, the sputtering method or the like, the resistance contact plug <b>6</b> and the capacitance contact plug <b>7</b> that are respectively connected to the drain region D are formed. Thus, the selection transistor QM<b>1</b> and the separate selection transistor QM<b>2</b> are formed on the semiconductor substrate <b>1</b>.

0000Element Formation Process

0093Then, the variable resistance element RM and the capacitance element CM are formed.

0094First, as shown in <figref idref="DRAWINGS">FIG. 3A</figref>, first electrode dummy electrode <b>21</b>A is formed on the resistance contact plugs <b>6</b>, and as shown in <figref idref="DRAWINGS">FIG. 3B</figref>, the third electrode <b>41</b> is formed on the capacitance contact plugs <b>7</b>. Specifically, a tungsten film is formed by the sputtering method over the entire surface of the second interlayer insulation film <b>12</b>, and by patterning the tungsten film by photolithography, the first electrode dummy electrode <b>21</b>A and the third electrodes <b>41</b> are formed simultaneously.

0095Next, as shown in <figref idref="DRAWINGS">FIG. 4A</figref>, by removing the first electrode dummy electrode <b>21</b>A by a means such as etching or the like, the resistance contact plug <b>6</b> is exposed on the second interlayer insulation film <b>12</b>. Specifically, for example as shown in <figref idref="DRAWINGS">FIG. 4B</figref>, after protecting the third electrode <b>41</b> by laminating a mask layer M<b>1</b> on the formation region of the third electrode <b>41</b>, etching processing is performed to remove the first electrode dummy electrode <b>21</b>A as shown in <figref idref="DRAWINGS">FIG. 4A</figref>.

0096Next, as shown in <figref idref="DRAWINGS">FIG. 5A</figref>, the first electrode <b>21</b> is formed on the resistance contact plug <b>6</b>. Specifically, a metal film such as silver, copper, or zinc and the like is formed over the entire surface of the second interlayer insulation film <b>12</b> by the sputtering method, and by patterning the formed metal film by photolithography, the first electrode <b>21</b> is formed on the resistance contact plug <b>6</b>. In the meantime, by laminating the mask layer M<b>1</b> as shown in <figref idref="DRAWINGS">FIG. 5B</figref> in the formation region of the third electrode <b>41</b>, the third electrode <b>41</b> is protected.

0097Next, as shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, after removing the mask layer M<b>1</b>, the dielectric layer <b>42</b> and the variable resistance layer <b>22</b>,and the second electrode <b>23</b> and the fourth electrode <b>43</b> are formed one by one. Specifically, as shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, the third interlayer insulating film <b>13</b> is laminated so as to cover the second interlayer insulation film <b>12</b>, and the first electrode <b>21</b> and third electrode <b>41</b>, and in addition to performing CMP processing to make the third interlayer insulating film <b>13</b> flat, the upper surface of the first electrode <b>21</b> and the third electrode <b>41</b> are exposed. At this time, the upper surface of the third interlayer insulation film <b>13</b> and the upper surfaces of the first electrode <b>21</b> and third electrode <b>41</b> may be flattened so as to be an identical flatness.

0098Next, as shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, a compound layer consisting of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide is laminated respectively on the third interlayer insulation film <b>13</b>, and the first electrode <b>21</b> and third electrode <b>41</b>. The compound layer laminated on the first electrode <b>21</b> becomes the variable resistance layer <b>22</b>, and the compound layer laminated on the third electrode <b>41</b> becomes the dielectric layer <b>42</b>. Thus, the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> are formed simultaneously.

0099Next, as shown in <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, a tungsten film is formed by the sputtering method on the variable resistance layer <b>22</b> and the dielectric layer <b>42</b>, and by patterning the tungsten film by photolithography, the second electrode <b>23</b> and the fourth electrode <b>43</b> are simultaneously formed.

0100Thus, the variable resistance element RM and the capacitance element CM are formed simultaneously.

0101Finally, by laminating the fourth interlayer insulation film <b>14</b>, a wiring layer <b>31</b>, and a fifth interlayer insulation film <b>15</b> one by one, the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> is manufactured.

0102According to the manufacturing method for the above-mentioned semiconductor memory device, in the element formation process of forming the variable resistance element RM and the capacitance element CM, by mutually forming the dielectric layer <b>42</b> and the variable resistance layer <b>22</b> with the same material, forming the first electrode <b>21</b> with a different material from the third electrode <b>41</b>, and forming the second electrode <b>23</b>, the third electrode <b>41</b>, and the fourth electrode <b>43</b> with the same material, it is possible to readily form the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm and the volatile semiconductor memory elements MCD<b>11</b> to MCDnm on the same semiconductor substrate <b>1</b>.

0103Also, according to the production method of the above-mentioned semiconductor memory device, other than forming the first electrode <b>21</b> with a different material from the third electrode <b>41</b> and the fourth electrode <b>43</b>, the process of forming the volatile semiconductor memory elements MCD<b>11</b> to MCDnm and the process of forming the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm are essentially the same. Therefore, it is possible to form these semiconductor memory elements nearly simultaneously.

0104Also, the production method of the above-mentioned semiconductor memory device is a method that consists of forming the first electrode dummy electrode <b>21</b>A simultaneously with the same material as the third electrode <b>41</b>, forming the first electrode <b>21</b> with a material different from the third electrode <b>41</b> after removing this first electrode dummy electrode <b>21</b>A, and then forming the dielectric layer <b>42</b> and the variable resistance layer <b>22</b>, and the second electrode <b>23</b> and the fourth electrode <b>43</b> one by one. Just by adding the series of steps of formation and removal of the first electrode dummy electrode <b>21</b>A and formation of the first electrode <b>21</b>, it is possible to readily and with a high integration form the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm and the volatile semiconductor memory elements MCD<b>11</b> to MCDnm on the same semiconductor substrate <b>1</b>.

0000[Second Embodiment]

0105Next, a semiconductor memory device and the manufacturing method thereof of a second embodiment shall be described with reference to <figref idref="DRAWINGS">FIGS. 7A and 7B</figref> to <figref idref="DRAWINGS">FIGS. 11A and 11B</figref>. <figref idref="DRAWINGS">FIGS. 7A and 7B</figref> are partial sectional drawings showing the main portions of the semiconductor memory device of the present embodiment. Also, <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> to <figref idref="DRAWINGS">FIGS. 11A and 11B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 7A and 7B</figref>.

0106The semiconductor memory device of the present embodiment is nearly the same as the semiconductor memory device of the first embodiment, except for the material of the first electrode and the second electrode. Accordingly, among the constituent elements shown in <figref idref="DRAWINGS">FIGS. 7A and 7B</figref> to <figref idref="DRAWINGS">FIGS. 11A and 11B</figref>, the same reference numerals as in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> to <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> shall be used to designate the constituent elements that are the same as the constituent elements shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref> to <figref idref="DRAWINGS">FIGS. 6A and 6B</figref>, with descriptions thereof being omitted or simplified.

0000(Semiconductor Memory Device)

0107The semiconductor memory device of the present embodiment is constituted by being provided with a non-volatile semiconductor memory element MCN<b>1</b><i>m </i>and a volatile semiconductor memory element MCD<b>1</b><i>m</i>, similarly to the case of the first embodiment. Since the volatile semiconductor memory element MCD<b>1</b><i>m </i>has the same constitution as in the first embodiment, the description thereof shall be omitted, and the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>shall be described here.

0108<figref idref="DRAWINGS">FIG. 7A</figref> is a sectional schematic view of the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>according to the present embodiment, and <figref idref="DRAWINGS">FIG. 7B</figref> is a sectional schematic view of the volatile semiconductor memory element MCD<b>1</b><i>m </i>according to the present embodiment.

0109In <figref idref="DRAWINGS">FIG. 7A</figref>, gate electrodes <b>3</b> are formed on the gate insulating film <b>2</b> on a semiconductor substrate <b>1</b>, a sidewall <b>4</b> is formed on both sides of each gate electrode <b>3</b>, and a source region S and a drain region D are formed in the semiconductor substrate <b>1</b> on both sides of each gate electrode <b>3</b>. The source region S is connected to a bit line BL<b>1</b><i>m </i>via a bit line contact plug <b>5</b>, and the drain region D is connected to the variable resistance element RM via a resistance contact plug <b>6</b>. In this way, the section transistor QM<b>1</b> is constituted.

0110Moreover, the first interlayer insulation film <b>11</b> is formed on the semiconductor substrate <b>1</b>, and the bit line BL<b>1</b><i>m </i>is formed on the first interlayer insulation film <b>11</b>. Also, the bit line contact plug <b>5</b> is formed so as to penetrate the first interlayer insulation film <b>11</b>. Furthermore, the second interlayer insulating film <b>12</b> is laminated on the first interlayer insulating film <b>11</b> and the bit line BL<b>1</b><i>m. </i>

0111Next, the variable resistance element RM is constituted by a first electrode <b>121</b>, a variable resistance layer <b>22</b> that contacts the first electrode <b>121</b>, and a second electrode <b>123</b> that contacts the variable resistance layer <b>22</b> being laminated one by one. The first electrode <b>121</b> is connected to a drain region D via a resistance contact plug <b>6</b>. Furthermore, a fourth interlayer insulation film <b>14</b> that consists of silicon oxide or the like, a wiring layer <b>31</b>, and a fifth interlayer insulating film <b>15</b> are laminated one by one on the second electrode <b>123</b>.

0112The first electrode <b>121</b> is formed with tungsten, titanium, gold, platinum, or the like similarly to the third and the fourth electrodes <b>41</b> and <b>43</b>, and is preferably formed with tungsten. Moreover, the second electrode <b>123</b> is formed with silver, copper, zinc, or the like, being preferably formed with copper, and constitutes a portion of the common plate line PL<b>1</b>. The variable resistance layer <b>22</b> is constituted with the same material as the dielectric layer <b>42</b>, similarly to the first embodiment. That is, the variable resistance layer <b>22</b> consists of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide, with a transition metal oxide being particularly preferable. Examples of a transition metal oxide that constitutes the variable resistance layer <b>22</b> include tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide either singly or in combination, with hafnium oxide being preferable.

0113Next, the operation of the semiconductor memory elements MCN<b>11</b> to MCNnm shall be described. When the selection transistor QM<b>1</b> is turned ON and current is flowed from the second electrode <b>123</b> of the variable resistance element RM to the first electrode <b>121</b>, the silver, copper, zinc, or the like which constitutes the second electrode <b>123</b> is oxidized (ionized) and moves through the variable resistance layer <b>22</b> to be reduced and deposited at the first electrode <b>121</b> side. Thereby, a conductive filament that penetrates the variable resistance layer <b>22</b> is formed between the first electrode <b>121</b> and the second electrode <b>123</b>, and the resistance value of the variable resistance layer <b>22</b> falls. Conversely, when current is passed from the first electrode <b>121</b> to the second electrode <b>123</b>, the conductive filament oxidizes (ionizes) to be reduced and deposited at the second electrode <b>123</b> side. Thereby, the conductive filament between the first electrode <b>121</b> and the second electrode <b>123</b> disappears, and the resistance of the variable resistance layer <b>22</b> increases. Since the resistance value of this variable resistance layer <b>22</b> is maintained even in the state where a voltage is not impressed between the first electrode <b>121</b> and the second electrode <b>123</b>, it can be operated as a nonvolatile memory cell by reading out this resistance value.

0000(Method of Manufacturing Semiconductor Memory Device)

0114Next, a method of manufacturing the abovementioned semiconductor memory device shall be described with reference to the drawings.

0115The method of manufacturing the semiconductor memory device of the present embodiment consists of a transistor formation process and an element formation process that forms the variable resistance element RM and the capacitance element CM. The method, in the element formation process, consists of simultaneously forming the first electrode <b>121</b> and the third electrode <b>41</b> with the same material, simultaneously forming the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> on the first electrode <b>121</b> and the third electrode <b>41</b>, respectively, and next simultaneously forming the second electrode dummy electrode <b>123</b>A and the fourth electrode <b>43</b> on the variable resistance layer <b>22</b> and the dielectric layer <b>42</b>, respectively, with the same material as the first and third electrodes <b>121</b>, <b>41</b>, and then forming the second electrode <b>123</b> with a material that differs from the first, third and fourth electrodes <b>121</b>, <b>41</b>, <b>43</b> after removing the second electrode dummy electrode <b>123</b>A.

0116Hereinbelow, the description shall be made with reference to <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> to <figref idref="DRAWINGS">FIGS. 11A and 11B</figref>. <figref idref="DRAWINGS">FIGS. 8A and 8B</figref> are partial sectional drawings that show the formation steps of the first electrode and third electrode and the dielectric layer and variable resistance layer. <figref idref="DRAWINGS">FIGS. 9A and 9B</figref> are partial sectional drawings that show the formation steps of the second electrode dummy electrode and the fourth electrode. <figref idref="DRAWINGS">FIG. 10A</figref> and <figref idref="DRAWINGS">FIG. 10B</figref> are partial sectional drawings that show the steps for eliminating the second electrode dummy electrode. <figref idref="DRAWINGS">FIG. 11A</figref> and <figref idref="DRAWINGS">FIG. 11B</figref> are partial sectional drawings that show the formation process of the second electrode.

0000Transistor Formation Process

0117First, as shown in <figref idref="DRAWINGS">FIG. 8A</figref> and <figref idref="DRAWINGS">FIG. 8B</figref>, the selection transistor QM<b>1</b> and selection transistor QM<b>2</b> are formed similarly to the case of the first embodiment.

0000Element Formation Process

0118Then, the variable resistance element RM and the capacitance element CM are formed.

0119First, as shown in <figref idref="DRAWINGS">FIG. 8A</figref>, the first electrode <b>121</b> is formed on the resistance contact plug <b>6</b>, and as shown in <figref idref="DRAWINGS">FIG. 8B</figref>, the third electrode <b>41</b> is formed on the capacitance contact plug <b>7</b>. Specifically, a tungsten film for example is formed by the sputtering method over the entire surface of the second interlayer insulation film <b>12</b>, and by patterning the tungsten film by photolithography, the first electrode <b>121</b> and the third electrode <b>41</b> are formed simultaneously.

0120Next, as shown in <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>, the third interlayer insulating film <b>13</b> is laminated so as to cover the second interlayer insulating film <b>12</b>, the first electrode <b>121</b>, and the third electrode <b>41</b>, CMP processing is performed to make the third interlayer insulating film <b>13</b> flat, and the upper surface of the first electrode <b>121</b> and the third electrode <b>41</b> are exposed.

0121Next, as shown in <figref idref="DRAWINGS">FIGS. 8A and 8B</figref>, a compound layer consisting of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide is laminated respectively on the third interlayer insulation film <b>13</b>, and the first electrode <b>121</b> and third electrode <b>41</b>. The compound layer laminated on the first electrode <b>121</b> becomes the variable resistance layer <b>22</b>, and the compound layer laminated on the third electrode <b>41</b> becomes the dielectric layer <b>42</b>. Thus, the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> are formed simultaneously.

0122Next, as shown in <figref idref="DRAWINGS">FIG. 9A</figref>, the second electrode dummy electrode <b>123</b>A is formed on the variable resistance layer <b>22</b>, and as shown in <figref idref="DRAWINGS">FIG. 9B</figref>, the fourth electrode <b>43</b> is formed on the dielectric layer <b>42</b>.

0123Specifically a tungsten film for example is formed by the sputtering method over the entire surface of the variable resistance layer <b>22</b> and the dielectric layer <b>42</b>, and by next patterning the tungsten film by photolithography, the second electrode dummy electrode <b>123</b>A and the fourth electrode <b>43</b> are formed simultaneously.

0124Next, as shown in <figref idref="DRAWINGS">FIG. 10A</figref>, by removing the second electrode dummy electrode <b>123</b>A by a means such as etching or the like, the variable resistance layer <b>22</b> is exposed. As specifically shown for example in <figref idref="DRAWINGS">FIG. 10B</figref>, after laminating a mask layer M<b>2</b> on the formation region of the fourth electrode <b>43</b> to protect the fourth electrode <b>43</b>, etching processing is performed to remove the second electrode dummy electrode <b>123</b>A as shown in <figref idref="DRAWINGS">FIG. 10A</figref>.

0125Next, as shown in <figref idref="DRAWINGS">FIG. 11A</figref>, the second electrode <b>123</b> on the variable resistance layer <b>22</b>. Specifically, a metal film such as silver, copper, or zinc and the like is formed over the entire surface of the variable resistance layer <b>22</b> by the sputtering method, and by patterning the formed metal film by photolithography, the second electrode <b>123</b> is formed on the variable resistance layer <b>22</b>. In the meantime, by leaving the mask layer M<b>2</b> laminated on the formation region of the fourth electrode <b>43</b>, the fourth electrode <b>43</b> is protected. The mask layer M<b>2</b> may be removed as shown in <figref idref="DRAWINGS">FIG. 11B</figref> as soon as the formation of the second electrode <b>123</b> is completed.

0126Thus, the variable resistance element RM and the capacitance element CM are formed simultaneously.

0127Finally, by laminating the fourth interlayer insulation film <b>14</b>, the wiring layer <b>31</b>, and the fifth interlayer insulation film <b>15</b> one by one, the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 7A and 7B</figref> is manufactured.

0128The manufacturing method for the above-mentioned semiconductor memory device is a method of forming the second electrode dummy electrode <b>123</b>A simultaneously with the fourth electrode <b>43</b> and with the same material, and forming the second electrode <b>123</b> with a material that differs from the first, third and fourth electrodes <b>121</b>, <b>41</b>, <b>43</b> after removing the second electrode dummy electrode <b>123</b>A. Just by adding the series of steps of formation and removal of the second electrode dummy electrode <b>123</b>A and formation of the second electrode <b>123</b>, it is possible to readily and with a high integration form the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm and the volatile semiconductor memory elements MCD<b>11</b> to MCDnm on the same semiconductor substrate <b>1</b>.

0000[Third Embodiment]

0129Next, a semiconductor memory device and the manufacturing method thereof of a third embodiment shall be described with reference to <figref idref="DRAWINGS">FIGS. 12A and 12B</figref> to <figref idref="DRAWINGS">FIGS. 16A and 16B</figref>. <figref idref="DRAWINGS">FIGS. 12A and 12B</figref> are partial sectional drawings showing the main portions of the semiconductor memory device of the present embodiment. Also, <figref idref="DRAWINGS">FIGS. 13A and 13B</figref> to <figref idref="DRAWINGS">FIGS. 16A and 16B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 12A and 12B</figref>.

0000(Semiconductor Memory Device)

0130The semiconductor memory device of the present embodiment is constituted by being provided with a non-volatile semiconductor memory element MCN<b>1</b><i>m </i>and a volatile semiconductor memory element MCD<b>1</b><i>m</i>, similarly to the case of the first embodiment. Since the volatile semiconductor memory element MCD<b>1</b><i>m </i>has the same constitution as in the first embodiment, the description thereof shall be omitted, and the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>shall be described here.

0131<figref idref="DRAWINGS">FIG. 12A</figref> is a sectional schematic view of the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>according to the present embodiment, and <figref idref="DRAWINGS">FIG. 12B</figref> is a sectional schematic view of the volatile semiconductor memory element MCD<b>1</b><i>m </i>according to the present embodiment.

0132In <figref idref="DRAWINGS">FIG. 12A</figref>, gate electrodes <b>3</b> are formed on the gate insulating film <b>2</b> on the semiconductor substrate <b>1</b>, the sidewall <b>4</b> is formed on both sides of each gate electrode <b>3</b>, and the source region S and the drain region D are formed in the semiconductor substrate <b>1</b> on both sides of each gate electrode <b>3</b>. The source region S is connected to the bit line BL<b>1</b><i>m </i>via the bit line contact plug <b>5</b>, and the drain region D is connected to the variable resistance element RM via the resistance contact plug <b>6</b>. In this way, the section transistor QM<b>1</b> is constituted.

0133Moreover, the first interlayer insulation film <b>11</b> is formed on the semiconductor substrate <b>1</b>, and the bit line BL<b>1</b><i>m </i>is formed on the first interlayer insulation film <b>11</b>. Also, the bit line contact plug <b>5</b> is formed so as to penetrate the first interlayer insulation film <b>11</b>. Furthermore, the second interlayer insulating film <b>12</b> is laminated on the first interlayer insulating film <b>11</b> and the bit line BL<b>1</b><i>m. </i>

0134Next, the variable resistance element RM is constituted by a first electrode <b>221</b>, a variable resistance layer <b>22</b> that connects to the first electrode <b>221</b>, and a second electrode <b>223</b> that connects to the variable resistance layer <b>22</b> being laminated one by one. The first electrode <b>221</b> is connected to a drain region D via a resistance contact plug <b>6</b>. Furthermore, a plate electrode <b>224</b> which consists of tungsten or the like is laminated on the second electrode <b>223</b>, and this plate electrode <b>224</b> constitutes a portion of common plate line PL<b>1</b>. Moreover, the plate electrode <b>224</b> is formed simultaneously with the fourth electrode <b>43</b> of the volatile semiconductor memory element MCD<b>1</b><i>m </i>as described below, and it has the almost same thickness as the fourth electrode <b>43</b>. Then, a fourth interlayer insulation film <b>14</b> that consists of silicon oxide or the like, a wiring layer <b>31</b>, and a fifth interlayer insulating film <b>15</b> are laminated one by one on the plate electrode <b>224</b>. Note that in the volatile semiconductor memory element MCD<b>1</b><i>m</i>, the fourth interlayer insulation film <b>14</b> is laminated on the fourth electrode <b>43</b>.

0135The first electrode <b>221</b> is formed with tungsten or the like similarly to the third electrode <b>41</b> and the and the fourth electrode <b>43</b> of the volatile semiconductor memory element MCD<b>1</b><i>m</i>. Moreover, the second electrode <b>223</b> is formed with silver, copper, zinc, or the like, and is formed thinner than the second electrode in the first and second embodiments. The variable resistance layer <b>22</b> is constituted with the same material as the dielectric layer <b>42</b>, similarly to the first embodiment. That is, the variable resistance layer <b>22</b> consists of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide, with a transition metal oxide being particularly preferable. Examples of a transition metal oxide that constitutes the variable resistance layer <b>22</b> include tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide either singly or in combination, with hafnium oxide being preferable.

0136Operation of the semiconductor memory elements MCN<b>11</b> to MCNnm is the same as that of the case of the second embodiment.

0000(Method of Manufacturing Semiconductor Memory Device)

0137Next, a method of manufacturing the abovementioned semiconductor memory device shall be described with reference to the drawings.

0138The method of manufacturing the semiconductor memory device of the present embodiment consists of a transistor formation process and an element formation process that forms the variable resistance element RM and the capacitance element CM. The method, in the element formation process, involves simultaneously forming the first electrode <b>221</b> and the third electrode <b>41</b> with the same material, simultaneously forming the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> on the first electrode <b>221</b> and the third electrode <b>41</b>, respectively, and next simultaneously forming the second electrode <b>223</b> and the fourth electrode dummy electrode <b>43</b>A on the variable resistance layer <b>22</b> and the dielectric layer <b>42</b>, respectively, with a material that differs from the first and third electrodes <b>121</b>, <b>41</b>, and then forming the fourth electrode <b>43</b> with the same material as the first and third electrodes <b>221</b>, <b>41</b> after removing the fourth electrode dummy electrode <b>43</b>A.

0139Hereinbelow, <figref idref="DRAWINGS">FIGS. 13A and 13B</figref> to <figref idref="DRAWINGS">FIGS. 16A and 16B</figref> shall be referred to in the description below. <figref idref="DRAWINGS">FIGS. 13A and 13B</figref> are partial sectional drawings that show the formation steps of the first electrode and third electrode and the dielectric layer and variable resistance layer. <figref idref="DRAWINGS">FIGS. 14A and 14B</figref> are partial sectional drawings that show the formation steps of the second electrode and the fourth electrode dummy electrode. <figref idref="DRAWINGS">FIGS. 15A and 15B</figref> are partial sectional drawings that show the steps of deleting the fourth electrode dummy electrode. <figref idref="DRAWINGS">FIGS. 16A and 16B</figref> are partial sectional drawings that show the formation steps of the fourth electrode.

0000Transistor Formation Process

0140First, the selection transistor QM<b>1</b> and the separate selection transistor QM<b>2</b> are formed as shown in <figref idref="DRAWINGS">FIG. 13A</figref> and <figref idref="DRAWINGS">FIG. 13B</figref>, similarly to the case of the first and second embodiments.

0000Element Formation Process

0141Then, the variable resistance element RM and the capacitance element CM are formed.

0142First, as shown in <figref idref="DRAWINGS">FIG. 13A</figref>, a first electrode <b>221</b> is formed on the resistance contact plug <b>6</b>, and as shown in <figref idref="DRAWINGS">FIG. 13B</figref>, the third electrode <b>41</b> is formed on the capacitance contact plug <b>7</b>. Specifically, a tungsten film is formed by the sputtering method over the entire surface of the second interlayer insulation film <b>12</b>, and by patterning the tungsten film by photolithography, the first electrode <b>221</b> and the third electrode <b>41</b> are formed simultaneously.

0143Next, the third interlayer insulating film <b>13</b> is laminated so as to cover the first electrode <b>221</b> and the third electrode <b>41</b>, the third interlayer insulating film <b>13</b> is subjected to CMP processing to make it flat, and the upper surface of the first electrode <b>221</b> and the third electrode <b>41</b> are exposed. Then, a compound layer consisting of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide is laminated on the third interlayer insulation film <b>13</b>, and the first electrode <b>221</b> and third electrode <b>41</b>. The compound layer laminated on the first electrode <b>221</b> becomes the variable resistance layer <b>22</b>, and the compound layer laminated on the third electrode <b>41</b> becomes the dielectric layer <b>42</b>. Thus, as shown in <figref idref="DRAWINGS">FIGS. 13A and 13B</figref>, the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> are formed simultaneously.

0144Next, as shown in <figref idref="DRAWINGS">FIGS. 14A and 14B</figref>, the second electrode <b>223</b> and the fourth electrode dummy electrode <b>43</b>A are formed simultaneously on the variable resistance layer <b>22</b> and the dielectric layer <b>42</b>, respectively. Specifically, a metal film such as silver, copper, or zinc and the like is formed over the entire surface of the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> by the sputtering method, and next by patterning the formed metal film by photolithography, a second electrode <b>223</b> and a fourth electrode dummy electrode <b>43</b>A consisting of silver, copper, zinc and the like are formed simultaneously.

0145Next, as shown in <figref idref="DRAWINGS">FIG. 15B</figref>, the dielectric layer <b>42</b> is exposed by removing the fourth electrode dummy electrode <b>43</b>A with a means such as etching. Specifically, for example as shown in <figref idref="DRAWINGS">FIG. 15A</figref>, after protecting the second electrode <b>223</b> by laminating a mask layer M<b>3</b> on the formation region of the second electrode <b>223</b>, the fourth electrode dummy electrode <b>43</b>A is removed by performing etching processing until the dielectric layer <b>42</b> is exposed as shown in <figref idref="DRAWINGS">FIG. 15B</figref>.

0146Next, as shown in <figref idref="DRAWINGS">FIGS. 16A and 16B</figref>, a plate electrode <b>224</b> and the fourth electrode <b>43</b> are simultaneously formed on the second electrode <b>223</b> and the dielectric layer <b>42</b>. Specifically, the mask layer M<b>3</b> is removed to expose the second electrode <b>223</b>. Next, a metal film consisting of tungsten or the like is formed by the sputtering method on the second electrode <b>223</b> and the dielectric layer <b>42</b>, and by next patterning the formed metal film by photolithography, the plate electrode <b>224</b> and the fourth electrode <b>43</b> each consisting of tungsten or the like are simultaneously formed.

0147Thus, the variable resistance element RM and the capacitance element CM are formed simultaneously.

0148Finally, by laminating the fourth interlayer insulation film <b>14</b>, the wiring layer <b>31</b>, and the fifth interlayer insulation film <b>15</b> one by one on the plate electrode <b>224</b> and the fourth electrode <b>43</b>, the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 12A and 12B</figref> is manufactured.

0149The manufacturing method for the above-mentioned semiconductor memory device is a method of simultaneously forming the fourth electrode dummy electrode <b>43</b>A with a material that differs from the first electrode <b>221</b> and the third electrode <b>41</b>, and forming the fourth electrode <b>43</b> with the same material as the first electrode <b>221</b> and the third electrode <b>41</b> after removing the fourth electrode dummy electrode <b>43</b>A. Just by adding the series of steps of formation and removal of the fourth electrode dummy electrode <b>43</b>A and formation of the fourth electrode <b>43</b>, it is possible to readily and with a high integration form the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm and the volatile semiconductor memory elements MCD<b>11</b> to MCDnm on the same semiconductor substrate <b>1</b>.

0000[Fourth Embodiment]

0150Next, a semiconductor memory device and the manufacturing method thereof of a fourth embodiment shall be described with reference to <figref idref="DRAWINGS">FIGS. 17A and 17B</figref> to <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>. <figref idref="DRAWINGS">FIGS. 17A and 17B</figref> are partial sectional drawings showing the main portions of the semiconductor memory device of the present embodiment. Also, <figref idref="DRAWINGS">FIGS. 18A and 18B</figref> to <figref idref="DRAWINGS">FIGS. 22A and 22B</figref> are process drawings for describing the method of manufacturing the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 17A and 17B</figref>.

0000(Semiconductor Memory Device)

0151The semiconductor memory device of the present embodiment is constituted by being provided with a non-volatile semiconductor memory element MCN<b>1</b><i>m </i>and a volatile semiconductor memory element MCD<b>1</b><i>m</i>, similarly to the case of the first to third embodiments. Since the volatile semiconductor memory element MCD<b>1</b><i>m </i>has the same constitution as in the first to third embodiments, the description thereof shall be omitted, and the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>shall be described here.

0152<figref idref="DRAWINGS">FIG. 17A</figref> is a sectional schematic view of the non-volatile semiconductor memory element MCN<b>1</b><i>m </i>according to the present embodiment, and <figref idref="DRAWINGS">FIG. 17B</figref> is a sectional schematic view of the volatile semiconductor memory element MCD<b>1</b><i>m </i>according to the present embodiment.

0153In <figref idref="DRAWINGS">FIG. 17A</figref>, gate electrodes <b>3</b> are formed on the gate insulating film <b>2</b> on a semiconductor substrate <b>1</b>, a sidewall <b>4</b> is formed on both sides of each gate electrode <b>3</b>, and a source region S and a drain region D are formed in the semiconductor substrate <b>1</b> on both sides of each gate electrode <b>3</b>. The source region S is connected to a bit line BL<b>1</b><i>m </i>via a bit line contact plug <b>5</b>, and the drain region D is connected to a variable resistance element RM via a resistance contact plug <b>6</b>. In this way, the section transistor QM<b>1</b> is constituted.

0154Moreover, the first interlayer insulation film <b>11</b> is formed on the semiconductor substrate <b>1</b>, and the bit line BL<b>1</b><i>m </i>is formed on the first interlayer insulation film <b>11</b>. Also, the bit line contact plug <b>5</b> is formed so as to penetrate the first interlayer insulation film <b>11</b>. Furthermore, the second interlayer insulating film <b>12</b> is laminated on the first interlayer insulating film <b>11</b> and the bit line BL<b>1</b><i>m. </i>

0155Next, the variable resistance element RM is constituted by a lower electrode <b>320</b> that is formed on the resistance contact plug <b>6</b>, a first electrode <b>321</b> that is laminated on the lower electrode <b>320</b>, the variable resistance layer <b>22</b> that contacts the first electrode <b>321</b>, and a second electrode <b>323</b> that contacts the variable resistance layer <b>22</b> that are laminated one by one. The first electrode <b>321</b> is connected to the drain region D via the lower electrode <b>320</b> and the resistance contact plug <b>6</b>. Moreover, the sum total thickness of the lower electrode <b>320</b> and the first electrode <b>321</b> is nearly the same as the third electrode <b>41</b> of the volatile semiconductor memory element MCD<b>1</b><i>m</i>. Moreover, the second electrode <b>323</b> constitutes a portion of common plate line PL<b>1</b>. Furthermore, a fourth interlayer insulation film <b>14</b> that consists of silicon oxide or the like, a wiring layer <b>31</b>, and a fifth interlayer insulating film <b>15</b> are laminated one by one on the second electrode <b>323</b>.

0156The lower electrode <b>320</b> is formed with for example tungsten similarly to the third electrode <b>41</b> and the fourth electrode <b>43</b> of the volatile semiconductor memory element MCD<b>11</b>. On the other hand, the first electrode <b>321</b> is formed with silver, copper, zinc, or the like. Moreover, the second electrode <b>323</b> is formed with for example tungsten similarly to the lower electrode <b>320</b>. The variable resistance layer <b>22</b> is constituted with the same material as the dielectric layer <b>42</b>, similarly to the first embodiment. That is, the variable resistance layer <b>22</b> consists of any one or a mixture of a transition metal oxide, an aluminum oxide, and a silicone oxide. Examples of a transition metal oxide that constitutes the variable resistance layer <b>22</b> include tantalum oxide, niobium oxide, hafnium oxide, and zirconium oxide either singly or in combination, with hafnium oxide being preferable.

0157The operation of the semiconductor memory elements MCN<b>11</b> to MCNnm of the present embodiment is the same as the case of the first embodiment.

0000(Method of Manufacturing Semiconductor Memory Device)

0158Next, a method of manufacturing the abovementioned semiconductor memory device shall be described with reference to the drawings.

0159The method of manufacturing the semiconductor memory device of the present embodiment consists of a transistor formation process and an element formation process that forms the variable resistance element RM and the capacitance element CM. The method, in the element formation process, consists of simultaneously forming the first electrode dummy electrode <b>321</b>A and the third electrode <b>41</b> with the same material, removing a portion of the first electrode dummy electrode <b>321</b>A to make the lower electrode <b>320</b>, forming the first electrode <b>321</b> on the lower electrode <b>320</b> (the remaining first electrode dummy electrode <b>321</b>A) with a material that differs from the third electrode <b>41</b>, simultaneously forming the dielectric layer <b>42</b> and the variable resistance layer <b>22</b>, and simultaneously forming the second electrode <b>323</b> and the fourth electrode <b>43</b> with the same material as the third electrode <b>41</b>.

0160Hereinbelow, the description shall be made with reference to <figref idref="DRAWINGS">FIGS. 18A and 18B</figref> to <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>. <figref idref="DRAWINGS">FIGS. 18A and 18B</figref> are partial sectional drawings that show the formation steps of the first electrode dummy electrode and the third electrode. <figref idref="DRAWINGS">FIGS. 19A and 19B</figref> are partial sectional drawings that show the step of removing a portion of the first electrode dummy electrode, and <figref idref="DRAWINGS">FIGS. 20A and 20B</figref> are partial sectional drawings that show the step of forming the first electrode on the first electrode dummy electrode. <figref idref="DRAWINGS">FIGS. 21A and 21B</figref> are partial sectional drawings that show the step of making the first electrode flat, and <figref idref="DRAWINGS">FIGS. 22A and 22B</figref> are partial sectional drawings that show the formation step of the dielectric layer and variable resistance layer and the second and fourth electrodes.

0000Transistor Formation Process

0161First, as shown in <figref idref="DRAWINGS">FIG. 18A</figref> and <figref idref="DRAWINGS">FIG. 18B</figref>, the selection transistor QM<b>1</b> and selection transistor QM<b>2</b> are formed similarly to the case of the first to third embodiments.

0000Element Formation Process

0162Then, the variable resistance element RM and the capacitance element CM are formed.

0163First, as shown in <figref idref="DRAWINGS">FIG. 18A</figref>, the first electrode dummy electrode <b>321</b>A is formed on the resistance contact plug <b>6</b>, and as shown in <figref idref="DRAWINGS">FIG. 18B</figref>, the third electrode <b>41</b> is formed on the capacitance contact plug <b>7</b>. Specifically, a tungsten film for example is formed by the sputtering method over the entire surface of the second interlayer insulation film <b>12</b>, and by patterning the tungsten film by photolithography, the first electrode dummy electrode <b>321</b>A and the third electrode <b>41</b> are formed simultaneously. Next, the third interlayer insulating film <b>13</b> is laminated so as to cover the second interlayer insulating film <b>12</b>, the first electrode dummy electrode <b>321</b>A, and the third electrode <b>41</b>, the third interlayer insulating film <b>13</b> is subjected to CMP processing to make it flat, and the upper surface of the first electrode dummy electrode <b>321</b>A and the third electrode <b>41</b> are exposed.

0164Next, as shown in <figref idref="DRAWINGS">FIG. 19A</figref>, a portion of the first electrode dummy electrode <b>321</b>A is removed by a means such as etching or the like. Specifically, for example after protecting the third electrode <b>41</b> by laminating a mask layer M<b>4</b> on the formation region of the third electrode <b>41</b> as shown in <figref idref="DRAWINGS">FIG. 19B</figref>, the first electrode dummy electrode <b>321</b>A is selectively etched by a means such as wet etching as shown in <figref idref="DRAWINGS">FIG. 19A</figref>, and the etching process is continued until for example the first electrode dummy electrode <b>321</b>A becomes a thickness of half. Thus, the lower electrode <b>32</b> is formed.

0165Next, as shown in <figref idref="DRAWINGS">FIG. 20A</figref>, a metal film <b>321</b>B which consists for example of a metal film such as silver, copper, zinc and the like is formed so that to cover the lower electrode <b>320</b> and the third interlayer insulating film <b>13</b>.

0166Next, as shown in <figref idref="DRAWINGS">FIG. 21A</figref>, by performing a CMP process on the metal film <b>321</b>B, it is flattened until the upper surface of the third interlayer insulating film <b>13</b> is exposed. Thereby, a state arises of the remainder of the metal film <b>321</b>B being exposed at the upper surface of the third interlayer insulating film <b>13</b>. Thus, the first electrode <b>321</b> consisting of a metal film such as silver, copper, zinc and the like is formed. Thereafter, the mask M<b>3</b> that had protected the third electrode <b>41</b> is removed as shown in <figref idref="DRAWINGS">FIG. 21B</figref>.

0167Next, as shown in <figref idref="DRAWINGS">FIG. 22A</figref> and <figref idref="DRAWINGS">FIG. 22B</figref>, a compound layer consisting of a transition metal oxide or the like is laminated on the first electrode <b>321</b> and the third electrode <b>41</b>. The compound layer laminated on the first electrode <b>321</b> becomes the variable resistance layer <b>22</b>, and the compound layer laminated on the third electrode <b>41</b> becomes the dielectric layer <b>42</b>. Thus, the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> are formed simultaneously.

0168Next, as shown in <figref idref="DRAWINGS">FIG. 22A</figref> and <figref idref="DRAWINGS">FIG. 22B</figref>, for example a tungsten film is formed on the variable resistance layer <b>22</b> and the dielectric layer <b>42</b> by the sputtering method, and by patterning the tungsten film with photolithography, the second electrode <b>323</b> and the fourth electrode <b>43</b> are formed simultaneously.

0169Thus, the variable resistance element RM and the capacitance element CM are formed simultaneously.

0170Finally, by laminating the fourth interlayer insulation film <b>14</b>, a wiring layer <b>31</b>, and a fifth interlayer insulation film <b>15</b> one by one, the semiconductor memory device shown in <figref idref="DRAWINGS">FIGS. 17A and 17B</figref> is manufactured.

0171The manufacturing method for the above-mentioned semiconductor memory device is a method of forming the first electrode dummy electrode <b>321</b>A simultaneously with the third electrode <b>41</b> and with the same material, and forming the first electrode <b>321</b> with a material that differs from the third electrode <b>41</b> after removing a portion of the first electrode dummy electrode <b>321</b>A to make the lower electrode <b>320</b>. Just by adding the series of steps of formation of the first electrode dummy electrode <b>321</b>A, removal of a portion thereof, and formation of the first electrode <b>321</b>, it is possible to readily and with a high integration form the non-volatile semiconductor memory elements MCN<b>11</b> to MCNnm and the volatile semiconductor memory elements MCD<b>11</b> to MCDnm on the same semiconductor substrate <b>1</b>.

0000[Application Example of the Semiconductor Memory Device]

0172Next, with reference to <figref idref="DRAWINGS">FIGS. 23 and 24</figref>, examples of application of the above-mentioned semiconductor memory device shall be described.

0173<figref idref="DRAWINGS">FIG. 23</figref> is a drawing that shows the setup of the memory space of the main memory system which uses the semiconductor memory device of any of the first to fourth embodiments and the aspect of the processor and data transfer. The region of the volatile semiconductor memory element (DRAM memory array) that is formed using the process of the present invention on the same chip is defined/set as a processor work array. On the other hand, the region of the non-volatile semiconductor memory element (non-volatile memory array) that is formed using the process of the present invention on the same chip is not frequently rewritten as a program code or data table or the like, but high-speed read out is require, and so is defined/set as a region that retains data even when the power is cut. By setting in this manner, with just one memory chip, it is possible to meet the required memory needs as a system.

0174<figref idref="DRAWINGS">FIG. 24</figref> shows the system configuration drawing of a portable telephone as an example of the system shown in <figref idref="DRAWINGS">FIG. 23</figref>.

0175This mobile telephone device is constituted by a system-in-package (SIP) that consists of a semiconductor memory device that stores program code, table data, and various parameters in the non-volatile memory cell region and uses a DRAM memory cell region as a work region and a media processor that are laminated and housed in a single package, and a baseband processor. By adopting this constitution, the system constitution is simplified, and a cost reduction and system miniaturization are realized.

0176While preferred embodiments of the invention have been described and illustrated above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.