US8624271B2

Light emitting devices

Summary by NHIP

LED Array Device

The light emitting device includes a substrate with a plurality of LEDs arranged in non-linear patterns and connected in series strings. A retention material is dispensed about the array, covering ESD protection devices and electrical connectors on substrates with more than 64 LEDs operating at 16 to 42 volts.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a substrate and a plurality of light emitting diodes (LEDs) disposed over the substrate in patterned arrays. The arrays can include one or more patterns of LEDs. A light emitting device can further include a retention material disposed about the array of LEDs. In one aspect, the retention material can be dispensed.

US8624271B2, drawing sheet 1 — Sheet 1 of 19

Term

4.2 yearsleft in the term

Expires 6 December 2030, including 14 days of term adjustment.

33 claims: 4 independent, 29 dependent

1
Broadest claimClaim Score 85, broad(NHIP)A light emitting device, comprising:a substrate;a plurality of light emitting diodes (LEDs) disposed over the substrate in an array, the array comprising a plurality of different patterns of LEDs, and wherein at least some of the LEDs in the array are connected in a first pattern that is non-linear;and a retention material dispensed about the array of LEDs.
15
A light emitting device, comprising:a substrate;one or more strings of light emitting diodes (LEDs) electrically connected in series over the substrate, each string comprising five or more LEDs, wherein at least a first string and a second string of five or more LEDs are connected in different patterns, and wherein either the first string or the second string is connected in a first pattern that is non-linear;and the LEDs being attached to the substrate using flux-assisted eutectic, metal-assisted non-eutectic, or thermal compression die attach.
27
A light emitting device, comprising:a substrate;a plurality of light emitting diodes (LEDs) disposed over the substrate in an array;a retention material disposed at least partially around and proximate to the array of LEDs;the array of LEDs comprising one or more different patterns of LEDs, wherein at least some of the LEDs in the array are connected in a first pattern that is non-linear and at least some of the plurality of LEDs are electrically connected by wirebonds to form separate strings of LEDs, and wherein each string of LEDs has at least one wirebond that is covered by the retention material.
33
A light emitting device comprising:a substrate;a plurality of light emitting diode (LED) chips disposed over the substrate;at least one electrostatic discharge (ESD) protection device disposed over the substrate;and a retention material provided over the substrate, wherein the retention material is adapted to retain a filling material over the plurality of LED chips;wherein the retention material covers the at least one ESD protection device.

Independent claims4

80 paragraphs in 6 sections, as filed

This application relates to and claims priority to U.S. Provisional Patent Application Ser. No. 61/416,184, filed Nov. 22, 2010, and is a continuation-in-part of and claims priority to each of U.S. Design patent application Ser. No. 29/379,636, filed Nov. 22, 2010 now U.S. Pat. No. D650760 and U.S. patent application Ser. No. 13/028,972, filed Feb. 16, 2011. The disclosures of each of these prior applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

The subject matter disclosed herein relates generally to light emitting devices and methods. More particularly, the subject matter disclosed herein relates to light emitting devices and methods comprising at least one pattern and/or array of light emitting diodes (LEDs).

BACKGROUND

Light emitting devices, such as light emitting diodes (LEDs), may be utilized in packages for providing white light (e.g., perceived as being white or near-white), and are developing as replacements for incandescent, fluorescent, and metal halide high-intensity discharge (HID) light products. A representative example of an LED device comprises a device having at least one LED chip, a portion of which can be coated with a phosphor such as, for example, yttrium aluminum garnet (YAG). The phosphor coating can convert light emitted from one or more LED chips into white light. For example, LED chips can emit light having desired wavelengths, and phosphor can in turn emit yellow fluorescence with a peak wavelength of about 550 nm, for example. A viewer perceives the mixture of light emissions as white light. As an alternative to phosphor converted white light, light emitting devices of red, green, and blue (RGB) wavelengths can be combined in one device or package or device to produce light that is perceived as white.

Despite availability of various LED devices and methods in the marketplace, a need remains for improved devices and improved manufacturability of devices suitable for industrial and commercial lighting products and replacement of conventional light sources, such as for example, 50 to 100 watt HID and high wattage compact fluorescent (CFL) lamps, outdoor lighting products, home luminaires, and retrofit light bulbs. A need remains for improved devices suitable for a range of low to high voltage applications. LED devices and methods described herein can advantageously enhance light output performance and accommodate various low to high voltage applications while promoting ease of manufacture.

SUMMARY

In accordance with this disclosure, novel light emitting devices and methods are provided that are well suited for a variety of applications, including industrial and commercial lighting products. It is, therefore, an object of the present disclosure herein to provide light emitting devices and methods comprising at least one pattern, arrangement, and/or array of light emitting devices optimized to enhance light output performance and accommodate various low to high voltage applications while providing energy savings.

These and other objects of the present disclosure as can become apparent from the disclosure herein are achieved, at least in whole or in part, by the subject matter disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

A full and enabling disclosure of the present subject matter including the best mode thereof to one of ordinary skill in the art is set forth more particularly in the remainder of the specification, including reference to the accompanying figures, in which:

<figref idref="DRAWINGS">FIG. 1</figref> illustrates a top perspective view of an embodiment of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 2</figref> illustrates a side view of an embodiment of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIGS. 3A and 3B</figref> illustrate top views of an embodiment of a light emitting device having one or more patterns of light emitting diodes (LEDs) according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 4</figref> illustrates a top perspective view of an embodiment of a light emitting device having one or more patterns of LEDs according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a top view of an embodiment of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 6</figref> illustrates a first cross-sectional view of a light emission area of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 7</figref> illustrates a second cross-sectional view of a light emission area of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 8</figref> illustrates a top view of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 9</figref> illustrates a cross-sectional view of a gap area of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIG. 10</figref> illustrates a top view of a light emitting device according to the disclosure herein;

<figref idref="DRAWINGS">FIGS. 11 to 14B</figref> illustrate top views of embodiments of a light emitting device having one or more patterns of LEDs according to the disclosure herein; and

<figref idref="DRAWINGS">FIGS. 15A and 15B</figref> illustrate die attach used for LED devices according to the disclosure herein.

DETAILED DESCRIPTION

Reference will now be made in detail to possible aspects or embodiments of the subject matter herein, one or more examples of which are shown in the figures. Each example is provided to explain the subject matter and not as a limitation. In fact, features illustrated or described as part of one embodiment can be used in another embodiment to yield still a further embodiment. It is intended that the subject matter disclosed and envisioned herein covers such modifications and variations.

As illustrated in the various figures, some sizes of structures or portions are exaggerated relative to other structures or portions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter. Furthermore, various aspects of the present subject matter are described with reference to a structure or a portion being formed on other structures, portions, or both. As will be appreciated by those of skill in the art, references to a structure being formed “on” or “above” another structure or portion contemplates that additional structure, portion, or both may intervene. References to a structure or a portion being formed “on” another structure or portion without an intervening structure or portion are described herein as being formed “directly on” the structure or portion. Similarly, it will be understood that when an element is referred to as being “connected”, “attached”, or “coupled” to another element, it can be directly connected, attached, or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected”, “directly attached”, or “directly coupled” to another element, no intervening elements are present.

Furthermore, relative terms such as “on”, “above”, “upper”, “top”, “lower”, or “bottom” are used herein to describe one structure's or portion's relationship to another structure or portion as illustrated in the figures. It will be understood that relative terms such as “on”, “above”, “upper”, “top”, “lower” or “bottom” are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, structure or portion described as “above” other structures or portions would now be oriented “below” the other structures or portions. Likewise, if devices in the figures are rotated along an axis, structure or portion described as “above”, other structures or portions would now be oriented “next to” or “left of” the other structures or portions. Like numbers refer to like elements throughout.

Light emitting devices according to embodiments described herein may comprise group III-V nitride (e.g., gallium nitride) based light emitting diodes (LEDs) or lasers fabricated on a growth substrate, for example, silicon carbide substrate, such as those devices manufactured and sold by Cree, Inc. of Durham, N.C. For example, Silicon carbide (SiC) substrates/layers discussed herein may be 4H polytype silicon carbide substrates/layers. Other silicon carbide candidate polytypes, such as 3C, 6H, and 15R polytypes, however, may be used. Appropriate SiC substrates are available from Cree, Inc., of Durham, N.C., the assignee of the present subject matter, and the methods for producing such substrates are set forth in the scientific literature as well as in a number of commonly assigned U.S. patents, including but not limited to U.S. Pat. No. Re. 34,861; U.S. Pat. No. 4,946,547; and U.S. Pat. No. 5,200,022, the disclosures of which are incorporated by reference herein in their entireties.

As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and one or more elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). The term also refers to binary, ternary, and quaternary compounds such as GaN, AlGaN and AlInGaN. The Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN), and quaternary (e.g., AlInGaN) compounds. These compounds may have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as AlxGa1-xN where 1>x>0 are often used to describe these compounds. Techniques for epitaxial growth of Group III nitrides have become reasonably well developed and reported in the appropriate scientific literature.

Although various embodiments of LEDs disclosed herein comprise a growth substrate, it will be understood by those skilled in the art that the crystalline epitaxial growth substrate on which the epitaxial layers comprising an LED are grown may be removed, and the freestanding epitaxial layers may be mounted on a substitute carrier substrate or submount which may have better thermal, electrical, structural and/or optical characteristics than the original substrate. The subject matter described herein is not limited to structures having crystalline epitaxial growth substrates and may be used in connection with structures in which the epitaxial layers have been removed from their original growth substrates and bonded to substitute carrier substrates.

Group III nitride based LEDs according to some embodiments of the present subject matter, for example, may be fabricated on growth substrates (such as a silicon carbide substrates) to provide horizontal devices (with both electrical contacts on a same side of the LED) or vertical devices (with electrical contacts on opposite sides of the LED). Moreover, the growth substrate may be maintained on the LED after fabrication or removed (e.g., by etching, grinding, polishing, etc.). The growth substrate may be removed, for example, to reduce a thickness of the resulting LED and/or to reduce a forward voltage through a vertical LED. A horizontal device (with or without the growth substrate), for example, may be flip chip bonded (e.g., using solder) to a carrier substrate or printed circuit board (PCB), or wire bonded. A vertical device (without or without the growth substrate) may have a first terminal solder bonded to a carrier substrate, mounting pad, or PCB and a second terminal wire bonded to the carrier substrate, electrical element, or PCB. Examples of vertical and horizontal LED chip structures are discussed by way of example in U.S. Publication No. 2008/0258130 to Bergmann et al. and in U.S. Publication No. 2006/0186418 to Edmond et al., the disclosures of which are hereby incorporated by reference herein in their entireties.

An LED can be coated, at least partially, with one or more phosphors with the phosphors absorbing at least a portion of the LED light and emitting a different wavelength of light such that the LED emits a combination of light from the LED and the phosphor. In one embodiment, the LED emits a white light combination of LED and phosphor light. An LED can be coated and fabricated using many different methods, with one suitable method being described in U.S. patent application Ser. Nos. 11/656,759 and 11/899,790, both entitled “Wafer Level Phosphor Coating Method and Devices Fabricated Utilizing Method”, and both of which are incorporated herein by reference. In the alternative, LEDs can be coated using other methods such an electrophoretic deposition (EPD), with a suitable EPD method described in U.S. patent application Ser. No. 11/473,089 entitled “Close Loop Electrophoretic Deposition of Semiconductor Devices”, which is also incorporated herein by reference. It is understood that LED devices and methods according to the present subject matter can also have multiple LEDs of different colors, one or more of which may be white emitting.

Referring now to <figref idref="DRAWINGS">FIGS. 1 to 15B</figref>, <figref idref="DRAWINGS">FIG. 1</figref> illustrates a top view of a light emitting or LED device, generally designated 10. LED device 10 can comprise a substrate 12 over which an emission area, generally designated 16, can be disposed. In one aspect, emission area 16 can be disposed substantially centrally with respect to LED device 10. In the alternative, emission area 16 can be disposed in any location over LED device 10, for example, in a corner or adjacent an edge. In one aspect, emission area 16 can comprise a substantially circular shape. In other aspects, emission area 16 can comprise any other suitable shape, for example, a substantially square, oval, or rectangle shape. LED device 10 can comprise a single emission area 16 or more than one emission area 16. Notably, LED device 10 can comprise a uniform optical source in the form of emission area which can simplify the manufacturing process for manufacturers of light products requiring a single component. LED device 10 can further comprise a retention material 14 disposed at least partially about emission area 16 where retention material 14 can be referred to as a dam. Retention material 14 can also be disposed over at least one electrostatic discharge (ESD) protection device, such as a Zener diode 44 (<figref idref="DRAWINGS">FIG. 9</figref>). In some aspects, retention material can be disposed over two Zener diodes 44 connected in series between two electrical elements (<figref idref="DRAWINGS">FIG. 8</figref>).

Substrate 12 can comprise any suitable mounting substrate, for example, a printed circuit board (PCB), a metal core printed circuit board (MCPCB), an external circuit, or any other suitable substrate over which lighting devices such as LEDs may mount and/or attach. Emission area 16 can be in electrical and/or thermal communication with substrate 12. One or more intervening layers can be disposed between emission area 16 and substrate 12 such that emission area 16 is indirectly disposed over substrate 12 thereby indirectly electrically and/or thermally communicating with substrate 12. In the alternative, emission area 16 can directly mount over substrate 12 thereby directly electrically and/or thermally communicating, or connecting, with substrate 12. In one aspect and for example only without limitation, substrate 12 can comprise a compact dimension of 22 millimeter (mm)×22-mm square footprint. In other aspects, substrate 12 can comprise any suitable dimension and/or shape, for example, a circular or rectangular shape.

Emission area 16 can comprise a plurality of LED chips, or LEDs 25 disposed within and/or below a filling material 40 such as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. LEDs 25 can comprise any suitable size and/or shape. For example, LEDs 25 can have a rectangle, square, or any other suitable shape. In one aspect, filling material 40 can comprise an encapsulant having a predetermined, or selective, amount of phosphors and/or lumiphors in an amount suitable for any desired light emission, for example, suitable for white light conversion. Filling material 40 can interact with light emitted from the plurality of LEDs 25 such that a perceived white light, or any suitable and/or desirable wavelength of light, can be observed. Any suitable combination of encapsulant and/or phosphors can be used, and combinations of different phosphors for resulting in desired light emission can be used. In other aspects, filling material 40 can comprise a molded lens material. Filling material 40 can be substantially opaque such that emission area 16 can be substantially opaque (as illustrated in <figref idref="DRAWINGS">FIG. 1</figref>), transparent, or semi-transparent depending upon, for example, the amount and type of phosphor used. Retention material 14 can be adapted for dispensing, or placing, about at least a portion of emission area 16. After placement of retention material 14, filling material 40 can be selectively filled to any suitable level within the space disposed between one or more inner walls of retention material 14. For example, filling material 40 can be filled to a level equal to the height of retention material 14 or to any level above or below retention material. The level of filling material 40 can be planar or curved in any suitable manner, such as concave or convex.

Still referring to <figref idref="DRAWINGS">FIG. 1</figref>, LED device 10 can also comprise at least one opening or hole, generally designated 20, that can be disposed through or at least partially through substrate 12 for facilitating attachment of LED device 10 to an external substrate or surface. For example, one or more screws can be inserted through the at least one hole 20 for securing device 10 to another member, structure, or substrate. LED device 10 can also comprise one or more electrical attachment surfaces 18. In one aspect, attachment surfaces 18 comprise electrical contacts such as solder contacts. Attachment surfaces 18 can be any suitable configuration, size, shape and/or location and can comprise positive and negative electrode terminals through which an electrical current or signal can pass when connected to an external power source. One or more conducting wires (not shown) can be attached and electrically connected to attachment surfaces 18 when welded, soldered, or any other suitable attachment method known. Electrical current or signal can pass into LED device 10 from the external wires electrically connected to the attachment surfaces 18 and into the emission area 16 to facilitate light output. Attachment surfaces 18 can electrically communicate with emission area 16 which comprises one or more LEDs 25. Attachment surfaces 18 can electrically communicate with first and second conductive traces 33 and 34 (see <figref idref="DRAWINGS">FIG. 8</figref>) and therefore LEDs 25 which may be electrically connected using electrical connectors. Electrical connectors can comprise wirebonds or other suitable members for electrically connecting LEDs 25 to first and second conductive traces 34 and 33.

LED device 10 can further comprise an indicator sign or symbol for denoting the electrical polarity for a given a side of LED device 10. For example, a first symbol 22 can comprise a “+” sign denoting the side of LED device 10 comprising the positive electrode terminal. A second symbol 23 can comprise a “−” sign denoting the side of LED device 10 comprising the negative electrode terminal. One or more test points 15 can be located adjacent either a positive or negative side of the device for testing the electrical and/or thermal properties of the LED device 10. In one aspect, test point 15 can be disposed adjacent the negative side, or terminal of LED device 10.

<figref idref="DRAWINGS">FIG. 2</figref> illustrates a side view of LED device 10. As illustrated by <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, retention material 14 can comprise a substantially circular dam disposed about at least a portion of emission area 16 and disposed over substrate 12. Retention material 14 can be dispensed, positioned or otherwise placed over substrate 12 and can comprise any suitable size and/or shape. Retention material 14 can comprise any suitable reflective material and can comprise a clear or opaque white material such as, for example, a silicone or epoxy material. Filler particles such as titanium dioxide (TiO2), for example, can be used and added to retention material 14 for providing an opaque material. Retention material 14 can be dispensed or deposited in place using an automated dispensing machine where any suitable size and/or shape of dam can be formed. In one aspect, a circular shape as shown can be dispensed, although any other configuration could also be provided such as, for example, a rectangular configuration, a curved configuration and/or any combination of desired configurations and cross-sectional shapes. As <figref idref="DRAWINGS">FIG. 2</figref> illustrates in a side view of LED device 10, retention material 14 can comprise a rounded outer wall 24 such that the upper surface of retention material 14 opposite substrate 12 is rounded. Rounding, or curving outer wall 24 of retention material 14 may further improve the amount of light reflected by LED device 10.

Retention material 14 can comprise any material known in the art, for example, a silicone material comprising 7% fumed silica+3% TiO2+methyl silicone. As illustrated in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, retention material 14 can be dispensed after wirebonding of the one or more LEDs 25 such that retention material 14 is disposed over and at least partially covers wirebonds 26 to contain at least a portion, such as one end of each of wirebonds 26 within retention material 14. In <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, wirebonds 26 for the first and last, or outermost edge LEDs 25A for a given set of LEDs such as LEDs 25 are disposed within retention material 14. In one aspect, retention material 14 can be “planed” during dispersion at room temperature for accurate volume and/or height control. The addition of TiO2 can increase reflection about the emission area 16 to further to optimize light emission of LED device 10. Fumed silica can be added as a thixotropic agent. Dispersing retention material 14 can allow increased board space and the ability to withstand higher voltages. In some aspects, LED device 10 can be operable at 42 volts (V) or higher.

<figref idref="DRAWINGS">FIGS. 3A</figref>, 3B and 4 illustrate emission area 16 without a layer of filling material 40. <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> illustrate LED device 10 and emission area 16 comprising at least one pattern, or arrangement, of LEDs. LEDs 25 can be arranged, disposed, or mounted over a conducting pad 30. LEDs 25 can be arranged or disposed in sets of LEDs, that can comprise one or more strings or LEDs, and a given set of LEDs can for example be one or more strings of LEDs electrically connected in series or any other suitable configuration. More than one set of LEDs can be provided, and each set of LEDs can be arranged in parallel to one or more other sets of LEDs. As described further herein, the LEDs in any given set or string of LEDs can be arranged in any suitable pattern or configuration, and even LEDs within a given set or string of LEDs can be arranged or disposed in one or more different patterns or configurations. For example, <figref idref="DRAWINGS">FIG. 3A</figref> illustrates at least three sets of LEDs arranged in three patterns, for example, a first pattern P1, a second pattern P2, and a third pattern P3. Each of patterns P1, P2, and P3 can comprise a consistent pattern design across emission area 16. More than one of patterns P1, P2, and/or P3 can be used. Each of patterns P1, P2, and/or P3 can alternate or be arranged in any suitable configuration. For illustration purposes, only three patterns are illustrated. Any number of patterns or arrangements is contemplated, and patterns can comprise any suitable design, for example, a checkerboard design or a grid design or arrangement wherein the LEDs can be at least substantially aligned in at least two directions. <figref idref="DRAWINGS">FIG. 3B</figref> illustrates at least three sets of LEDs arranged in patterns, for example, a first pattern P1A, second pattern P2, and a third pattern P3A which combine one or more of patterns P1, P2, and P3 illustrated in <figref idref="DRAWINGS">FIG. 3A</figref>. For example, patterns P1A and P3A can comprise a combination of more than one pattern. In one aspect, pattern NA can comprise a grid arrangement or pattern and a straight line arrangement or pattern. In one aspect, pattern P3A can comprise the checkerboard and straight line pattern designs. Each of patterns P1A and P3A can comprise 14 LEDs 25, seven LEDs of each pattern design. For illustration purposes, only two combinations are illustrated. However, please note that each set of LEDs can comprise a combination of having more than two patterns.

Still referring to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, conducting pad 30 can be electrically and/or thermally conducting and can comprise any suitable electrically and/or thermally conducting material. In one aspect, conducting pad 30 can comprise a conductive metal. In one aspect shown in <figref idref="DRAWINGS">FIG. 3A</figref>, emission area 16 can comprise one or more LEDs 25 arranged in a single pattern over conducting surface, or pad 30. In an alternative, LEDs can be provided that are a combination of more than one pattern of LEDs, such as LEDs 25, arranged over conducting pad 30 as <figref idref="DRAWINGS">FIG. 3B</figref> illustrates. As noted above, emission area 16 can comprise a combination of different arrangements or patterns, for example, a combination of first pattern P1, second pattern P2 and/or third pattern P3 for optimizing light emission and device brightness. Each set, or string of LEDs 25 disposed over conducting pad 30 can comprise outermost LEDs 25A with one or more LEDs 25 disposed therebetween. Each string of LEDs 25 can comprise the same or a different pattern, for example, patterns P1, P2, and/or P3. Strings of LEDs 25 can comprise diodes of the same and/or different colors, or wavelength bins, and different colors of phosphors can be used in the filling material 40 (<figref idref="DRAWINGS">FIG. 7</figref>) disposed over LEDS 25 that are the same or different colors in order to achieve emitted light of a desired wavelength. The one or more patterns of LEDs 25 can comprise an array of LEDs within emission area 16.

<figref idref="DRAWINGS">FIGS. 3A</figref>, 3B, and 4 illustrate emission area 16 comprising, for example, 10 lines, or strings, of LEDs 25. Each string of LEDs 25 can comprise any suitable number of LEDs electrically connected between outermost LEDs 25A which can connect to respective electrical elements. In one aspect, each string of LEDs 25 can comprise at least 14 LEDs. In one aspect, LED device can comprise at least 140 LEDs arranged in an array. The arrangements, patterns, and/or combination of multiple patterns herein can comprise an array for optimizing color uniformity and brightness of light emitted from LED device 10. The LEDs can be electrically connected in series using one or more wirebonds 26 for attaching bond pads of adjacent LEDs 25. In one aspect as shown in <figref idref="DRAWINGS">FIG. 3A</figref>, first pattern P1 can comprise the first and tenth strings of 14 LEDs 25. First pattern P1 can comprise two opposing lines of LEDs 25 disposed between the first and last, or outermost LEDs 25A of the series. In one aspect, first pattern P1 comprises what is referred to herein as a grid arrangement, pattern or design, where at least two LEDs are at least substantially aligned in at least two directions and can include single, unaligned LEDs at opposing ends of a set or string of LEDs. Each of the LEDs 25 comprising first pattern P1 can be electrically connected in series. In one aspect, second arrangement or second pattern P2 can be disposed adjacent first pattern P1, for example, located at the second and ninth strings of LEDs 25. In one aspect, second pattern P2 can comprise 14 total LEDs 25 wherein each of the 14 LEDs 25 can be arranged adjacent each other along a horizontal line in a straight line design, or arrangement, and each of the 14 LEDs 25 can be electrically connected in series. Any suitable number of LEDs 25 can be connected in any suitable configuration or arrangement such as in series to form a string having a suitable pattern. Care must be taken when connecting LEDs 25 in series such that the positive or negative electrode of a preceding LED electrically connects to an electrode of opposite electrical polarity for a subsequent LED for allowing electrical current to flow properly through the string of LEDs 25.

Third pattern P3 shown in <figref idref="DRAWINGS">FIG. 3A</figref> can comprise a checkerboard pattern having a checkerboard design, or arrangement of LEDs 25 electrically connected in series. In one aspect, at least 14 LEDs 25 can comprise the checkerboard pattern, and third pattern P3 can be disposed between and/or alternate with strings of LEDs having second pattern P2. The checkerboard pattern or third pattern P3 can comprise a set of LEDs 25 alternating both above and below a horizontal line. Patterns P1, P2, and P3 are not limited in the shape of pattern or to at least 14 LEDs, but rather, patterns can comprise any suitable arrangement and any suitable number of LEDs 25. For illustration purposes, only three patterns are shown although any suitable number of patterns could be utilized. The alternating LEDs 25 of third pattern P3 can optimize light output by ensuring uniform coverage and spatial alignment over conducting pad 30 such that light emission is uniform and improved. Third pattern P3 can repeat from the third through the eighth string of LEDs 25. First and last LEDs 25A in a given string of LEDs 25 for each of patterns P1, P2, and/or P3 can electrically connect to first and second conductive traces 33 and 34 (see <figref idref="DRAWINGS">FIGS. 7</figref>, 8) for receiving and transmitting electrical current or signal through and illuminating a given string of LEDs 25.

The LEDs even in a single set or string in emission area 16 can comprise LEDs in more than one pattern or configuration. For example, <figref idref="DRAWINGS">FIG. 3B</figref> illustrates one aspect of a possible arrangement of LEDs in emission area 16 where there are at least two sets, shown here as strings without limitation, of LEDs 25 and where LEDs 25 for some sets or strings are arranged in different patterns or configurations with respect to another set or string of LEDs and even within one single set or string of LEDs. Any two given separate sets or strings of LEDs 25 can be electrically connected in a pattern such that some or all of the LEDs within each of the two sets or strings of LEDs can be arranged in different patterns, in identical patterns, or in any combination of patterns. In other words, the LEDs in any given set or string can be disposed in different or identical patterns with respect not only to the LEDs in that set or string but can also be disposed in any pattern with respect to another set or string of LEDs and the two sets or strings can in one aspect be parallel to one another. For example, LEDs 25 in <figref idref="DRAWINGS">FIG. 3B</figref> can be disposed in one aspect such that emission area 16 comprises a combination of different arrangements or patterns, for example, a first pattern P1A, a second pattern P2A and/or a third pattern P3A for optimizing light emission and device brightness. As noted earlier, patterns P1A and P3A illustrate a combination of two different patterns, for example at least two of the checkerboard, straight line and/or grid arrangement, however, combinations of more than two patterns is hereby contemplated. Only three pattern arrangements have been disclosed (i.e., checkerboard, grid, straight line), but any suitable arrangement or pattern design can be used. Each string of LEDs 25 disposed over conducting pad 30 can comprise outermost LEDs 25A with one or more LEDs 25 disposed therebetween. Each set or string of LEDs 25 can comprise the same or a different pattern, for example, patterns P1A, P2A, and/or P3A. Sets or strings of LEDs 25 can comprise diodes of the same and/or different colors, or wavelength bins, and different colors of phosphors can be used in the filling material 40 (<figref idref="DRAWINGS">FIG. 7</figref>) disposed over LEDS 25 that are the same or different colors in order to achieve emitted light of a desired wavelength. The one or more patterns of LEDs 25 can comprise an array of LEDs within emission area 16. As <figref idref="DRAWINGS">FIG. 3B</figref> illustrates, for example, in pattern P3A, sets of LEDS 25 can comprise rectangular LEDs arranged where the major (i.e., long) axis of a first LED is disposed in a different orientation than the major axis of at least a second LED. That is, a given set of LEDs 25 can comprise LEDs 25 in different orientations. In other aspects, as illustrated in <figref idref="DRAWINGS">FIG. 3A</figref> for example, pattern P2 and pattern P3 can comprise sets of rectangular LEDs 25 where the major axis is the same is the same for the given set but different from the orientation of other sets.

The various LED arrangements and device designs as described herein are advantageous for providing a light emitting device with excellent performance and output while still being a small light emitting device where pressure exists to provide small devices while maintaining quality performance and light output.

<figref idref="DRAWINGS">FIG. 5</figref> illustrates a second embodiment of an LED device, generally designated 50 which is similar in form and function to LED device 10. LED device 50 can comprise substrate 12 and emission area 16 disposed over substrate 12. Emission area 16 can comprise any suitable size, shape, number and/or be disposed at any suitable location over substrate 12. Retention material 14 can be disposed over substrate 12 and at least partially about emission area 16. LED device 50 can comprise one or more openings or holes 20, disposed through substrate 12 for facilitating attachment of LED device 10 to an external substrate or surface. LED device 50 can comprise first and second symbols 22 and 23 for denoting the electrical polarity of LED device 50. LED device 50 illustrates test point 15 disposed adjacent the positive or side of the device for testing the electrical and/or thermal properties of the LED device 50. LED device 50 further can comprise at least one electrical attachment surface 18 that can electrically connect to one or more external wires (not shown) for facilitating the flow of electric current into emission area 16 of LED device 50. In one aspect, attachment surface 18 can comprise a shape having curved corners. Rounding the corners, or edges of attachment surfaces 18 may better contain the flow of solder over the device than sharp corners when attaching one or more external conductive wires (not shown) to LED device 50.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates a portion of a cross-section along an edge of conducting pad 30 of <figref idref="DRAWINGS">FIGS. 3A and 3B</figref> wherein the emission area 16 has not been filled with filling material 40 such as encapsulant and/or phosphors. <figref idref="DRAWINGS">FIG. 6</figref> illustrates LEDs 25 comprising an outermost LED 25A and adjacent LED for a given string of LEDs within emission area 16. <figref idref="DRAWINGS">FIG. 7</figref> illustrates a portion of a cross-section of <figref idref="DRAWINGS">FIG. 1</figref> wherein filling material 40 is disposed over emission area 16. For illustration purposes, four LEDs 25 are illustrated and electrically connected in series in <figref idref="DRAWINGS">FIG. 7</figref>. However, as noted earlier, each string, or pattern of LEDs 25 can comprise any suitable number of LEDs 25. In one aspect, each string of LEDs can comprise 14 LEDs 25. <figref idref="DRAWINGS">FIGS. 6 and 7</figref> illustrate one or more LEDs 25 connected in series by one or more wirebonds 26. LEDs 25 can be arranged over conducting pad 30 and can thermally communicate directly with conducting pad 30 or indirectly through one or more intervening layers. LEDs 25 can attach to conducting pad 30 or intervening layers using any attachment means known in art. In one aspect, LEDs 25 can attach using solder pastes, epoxies, or flux. Conducting pad 30 can be formed integral as one piece of substrate 12 or can comprise a separate layer disposed over substrate 12. Conducting pad 30 can dissipate heat generated by the one or more LEDs 25.

As <figref idref="DRAWINGS">FIGS. 6 and 7</figref> further illustrate, the outermost LEDs 25A for a series, string, or pattern of LEDs 25 can electrically communicate or connect to one or more electrical elements. Electrical elements can comprise first and second conductive traces 33 and 34 configured to flow, or supply electrical signal or current to the respective strings of LEDs 25. One of first and second conductive traces 33 and 34 can comprise an anode and the other a cathode. The electrical polarity can be denoted by first and second symbols 22 and 23 (<figref idref="DRAWINGS">FIG. 1</figref>) as discussed earlier. Conducting pad 30 and conductive traces 33 and 34 can comprise any suitable electrical and thermally conductive materials and can comprise either the same or different materials. In one aspect, conducting pad 30 and conductive traces can comprise a layer of copper (Cu) deposited over substrate using any suitable technique. An electrically insulating solder mask 32 can be disposed at least partially between conducting pad 30 and respective conductive traces 33 and 34 such that when solder is used to attach one or more LEDs 25 over conducting pad 30, the solder cannot electrically connect with the conductive traces 33 and 34 thereby causing one or more strings of LEDs 25 to become electrically shorted.

<figref idref="DRAWINGS">FIG. 6</figref> illustrates various placement areas, positions, or locations of retention material 14 about emission area 16. In one aspect, retention material 14 can be dispensed about at least a portion, or entirely about emission area 16. Conventional devices can comprise a molded as opposed to dispensed dam placed at a location such as prior art location PA shown in broken lines in <figref idref="DRAWINGS">FIG. 6</figref> and disposed along an edge of where solder mask 32 contacts first conductive trace 34. The present subject matter envisions retention material 14 disposed in areas, positions, or locations R1, R2, and/or any location therebetween. When retention material 14 is disposed in locations R1 or R2, it can be disposed over and cover at least a portion of one or more wirebonds 26 connecting outermost LEDs 25A to electrical elements, such as conductive trace 34. When in location R1, retention material 14 can be disposed at least partially over each of solder mask 32 and wirebond 26 connected to outermost LED 25A for a respective string of LEDs 25. In one aspect, retention material 14 can be disposed entirely over the portion of solder mask 32 disposed between conducting pad 30 and conductive trace 34 and/or entirely over wirebond 26 when in location R1. In another aspect, retention material 14 can be disposed over and at least partially or entirely cover each of the wirebonds 26 of each of the outermost LEDs 25A for each string of LEDs 25 disposed in emission area 16. The retention material can be dispensed in a predetermined location on the substrate 12 for providing a suitable distance between the retention material 14 and the one or more LEDs 25. Notably, when in location R1, retention material 14 can eliminate the need for solder mask 32 as retention material would be disposed between conducting pad 30 and first and/or second conductive traces 33, 34. Location R2 illustrates retention material 14 disposed at least partially over solder mask 32 and at least partially over wirebond 26 of outermost LED 25A. As illustrated, retention material 14 according to the subject matter herein can comprise a substantially rounded or hemispheric shaped cross-section. Rounding retention material 14 can increase the surface area from which light may be emitted and/or reflected.

<figref idref="DRAWINGS">FIG. 7</figref> illustrates a string of one or more LEDs 25, for illustration purposes four LEDs 25 are shown but strings of LEDs 25 can comprise any suitable number of LEDs, for example, 14 LEDs 25 arranged in series. <figref idref="DRAWINGS">FIG. 7</figref> illustrates a cross-section of substrate 12 over which LEDs 25 can be mounted or otherwise arranged. Substrate 12 can comprise, for example, conducting pad 30, first and second conductive traces 33 and 34, and solder mask 32 at least partially disposed between conducting pad 30 and each of conductive traces 33 and/or 34. As noted earlier, if retention material is positioned adjacent outermost LEDs 25A, for example in location R1, solder mask 32 between conducting pad 30 and first and second conductive traces 33 and 34 can be eliminated as it would no longer be necessary. Solder mask 32 can be disposed between conductive traces 33 and 34 and attachment surfaces 18 (<figref idref="DRAWINGS">FIG. 8</figref>), the proximal edges of which can be seen in <figref idref="DRAWINGS">FIG. 7</figref> adjacent retention material 14, adjacent the outer wall 24 of retention material 14. Substrate 12 can further comprise a dielectric layer 36, and a core layer 38. For illustration purposes, substrate 12 can comprise a MCPCB, for example, those available and manufactured by The Bergquist Company of Chanhassan, Minn. Any suitable substrate 12 can be used, however. Core layer 38 can comprise a conductive metal layer, for example copper or aluminum. Dielectric layer 36 can comprise an electrically insulating but thermally conductive material to assist with heat dissipation through substrate 12. <figref idref="DRAWINGS">FIG. 7</figref> illustrates retention material 14 arranged, for example, in position R2 at least partially over each of solder mask 32 and the wirebond 26 connecting to conductive traces 33 and 34. <figref idref="DRAWINGS">FIG. 7</figref> illustrates filling material 40 disposed over the one or more LEDs 25. Filling material 40 can be selectively filled to any suitable level higher, lower, or equal to the height of retention material 14. Wirebonds 26 of the outermost LEDs 25A as shown can be at least partially disposed within retention material 14.

<figref idref="DRAWINGS">FIG. 7</figref> further illustrates examples of first and second heights H1 and H2 of filling material 40 which can be selectively filled within LED device 10. First height H1 can comprise a height at which filling material 40 is disposed over the LEDs 25. The height may vary due to process variability, so an average height above the string of LEDs 25 can be used and controlled for optimal brightness. Second height H2 can comprise a height at which filling material 40 is selectively disposed over a top surface of conducting pad 30. Second height H2 can be controlled, for example, by controlling the location of retention material 14 and whether it assumes location R1, R2 or any position therebetween. Second height H2 can also be controlled by controlling the amount of filling material 40 dispensed into the cavity defined by retention material 14.

Controlling the volume of filling material 40 within the cavity, or dam defined by retention material 14 can affect first and second heights H1 and/or H2 and can notably allow for fine-tuning, or micro-tuning the color, or wavelength, of light emitted from LED device 10. Micro-tuning the color of LED devices 10 can therefore ideally increase product yields to 100%. For example, the amount of color affecting components, including but not limited to phosphors, contained in filling material 40 can be selectively added and the first and/or second heights H1, H2 can be selectively controlled by under or over filling the filling material 40 within emission area 16 depending on the wavelength of LEDs 25 used within device 10. Location of retention material 14, for example, locating retention material at R1, R2, or any position or distance therebetween can also affect first and/or second heights H1 and H2. Micro-tuning color can be achieved over multiple devices or on a per device, or package, basis by changing, for example the ratio of volume of phosphor to overall dispense capability volume of filling material 40. The ratio of volume of phosphor to overall dispense capability volume of filling material 40 can be adjusted based on the wavelength bin of LEDs 25 selected for use in a given device to attain the desired overall wavelength output of LED device 10. By manipulating, for example, the diameter of the dam provided by retention material 14 and/or the height of retention material 14, each of which can affect heights H1 and/or H2 and therefore the volume of fill material, the color of individual devices 10 can be micro-tuned thereby attaining higher process yields. Notably, selectively controlling a volume of the fill material such that color-affecting components of the fill material can be fine-tuned allows for light produced by the one or more LEDs to fall within a predetermined and precise color range.

<figref idref="DRAWINGS">FIG. 8</figref> illustrates LED device 10 comprising substrate 12 prior to arranging, dispensing, or otherwise placing retention material 14 about at least a portion of emission area 16. For illustration purposes, only a first string of LEDs 25 is illustrated, however, as noted earlier, emission area can comprise more than one strings of LEDs 25 electrically connected in series. In one aspect, LED device 10 comprises 10 strings of LEDs 25 connected in series. As illustrated, prior to placing retention material 14, substrate 12 can comprise first and second conductive traces 33 and 34 arranged in a substantially circular arrangement about conducting pad 30 such that LEDs arranged over conducting pad 30 can electrically communicate to each trace by wirebonding and wirebonds 26 or by any other suitable attachment method. As illustrated, outermost LEDs 25A for a respective string of LEDs 25 can electrically connect to conductive traces.

At least one gap 42 can exist between conductive traces 33 and 34. LED device 10 and devices disclosed herein can further comprise elements to protect against damage from ESD positioned, or disposed in the gap 42. In one aspect, different elements can be used such as various vertical silicon (Si) Zener diodes, different LEDs arranged reverse biased to LEDs 25, surface mount varistors and lateral Si diodes. In one aspect, at least one Zener diode 44 can be disposed between ends of first and second conductive traces 33 and 34 and reversed biased with respect to the strings of LEDs 25. In one aspect, two Zener diodes 44 can be electrically connected in series using one or more wirebonds 46 between first and second conductive traces 33 and 34 for higher voltage applications. As Zener diodes 44 are typically black and absorb light, placing the at least one Zener diode 44 in gap 42 between conductive traces 33 and 34 and also beneath retention material 14 can further improve light output intensity.

<figref idref="DRAWINGS">FIG. 8</figref> also illustrates one possible location for conducting pad 30. That is, conducting pad 30 can comprise a substantially centrally located circular pad disposed between conductive traces 33 and 34. Conducting pad 30 however, can be located at any suitable location over substrate and any location other than substantially center the device. Solder mask 32 can be disposed at least partially between respective conductive traces and conducting pad 30, such that the solder mask 32 comprises a substantially circular arrangement about conducting pad 30. Solder mask 32 can also be disposed in areas outside of the conductive traces, for example, between the respective conductive traces and one or more attachment surfaces 18. Broken lines 52 illustrate one possible aspect of the size and/or shape of conducting material comprising the conductive traces 33 and 34. The lines are broken to illustrate how the material can be disposed under solder mask 32. Thus, attachment surfaces 18 electrically and/or thermally communicate with respective conductive traces, and can comprise the same layer of material. External, conductive wires (not shown) can electrically connect to attachment surfaces 18, and electrical current or signal can flow from the attachment surfaces 18 to the respective conductive traces. The electrical current can flow along the conducting material designated by dotted lines 52 disposed below the layer of solder mask 32. The electrical current can flow into and/or out of the conductive traces and therefore into and out of respective strings of LEDs 25 mounted over conducting pad 30.

As noted earlier, Zener diodes 44 are typically black and absorb light. <figref idref="DRAWINGS">FIG. 9</figref> illustrates Zener diode 44 upon placement of the retention material. In one aspect, retention material 14 can be disposed at least partially over the at least one Zener diode 44. In another aspect, retention material 14 can be disposed entirely over the at least one Zener diode 44 such that the diode is completely covered for further improving light output intensity. Zener diode 44 can be disposed over an electrically and/or thermally conducting surface or area 54 such that current can flow through the diode 44, into the wirebonds 46, and to respective conductive traces 33 and 34.

LED devices disclosed herein can advantageously consume less energy while delivering equal or greater illumination. In one aspect, when used in traditional downlight applications, luminaires based on LED devices 10 and/or 50 can deliver 38% more illumination than a 26-watt CFL or a 100-watt incandescent bulb, while consuming only 14 watts. In one aspect, LED device 10 can enable a 60-watt A-lamp equivalent while consuming only 11 watts. LED device 10 can comprise a light output of 1050 lumens at 11 watts, or 2000 lumens at 27 watts, with a 3000-K warm-white color temperature.

<figref idref="DRAWINGS">FIG. 10</figref> illustrates another embodiment of an LED device, generally designated 55. LED device 55 illustrates substrate 12 prior to arranging, dispensing, or otherwise placing retention material 14 (<figref idref="DRAWINGS">FIG. 11</figref>) about at least a portion of emission area 16. For illustration purposes, only a first string of LEDs 25 is illustrated, however, emission area can comprise more than one string of LEDs 25 electrically connected in series. Each string of LEDs 25 can comprise the same or a different pattern. LED device 60 is similar in form and function to LED device 10 previously described with respect to <figref idref="DRAWINGS">FIG. 8</figref>. For example, prior to placing retention material 14, substrate 12 can comprise first and second conductive traces 33 and 34 arranged in a substantially circular arrangement about conducting pad 30 such that LEDs arranged over conducting pad 30 can electrically communicate to each trace by wirebonding via wirebonds 26 or any other suitable attachment method. As illustrated, outermost LEDs 25A for a respective string of LEDs 25 can electrically connect to the conductive traces. In fact, for LED devices described herein, emission area 16 can comprise a single, undivided mounting area at least partially defined by outermost LEDs 25A, with the outermost LEDs 25A being wirebonded via wirebonds 26 to contact areas, such as conductive traces 33 and 34. LEDs 25 that are not the outermost LEDs 25A are wirebonded via wirebonds 26 in strings having one or more patterns or arrays.

At least one gap 42 can exist between conductive traces 33 and 34. In this embodiment, one or more ESD protection device or Zener diode 44 can be disposed in gap 42 and can be electrically connected, or mounted to conductive area 54. In this embodiment, conductive area 54 can comprise an area larger than a footprint of Zener diode 44. Zener diode 44 can be positioned over conductive area 54 between ends of first and second conductive traces 33 and 34. Zener diode 44 can be reversed biased with respect to the one or more strings of LEDs 25. For example, when one Zener diode 44 is used, one or more wirebonds 46 can connect conductive area 54 to one of first and second conductive traces 33 and 34 such that Zener diode 44 can be reverse biased with respect to the strings of LEDs 25. As Zener diodes 44 are typically black and absorb light, placing the at least one Zener diode 44 in gap 42 between conductive traces 33 and 34 and also beneath retention material 14 (<figref idref="DRAWINGS">FIG. 9</figref>) can further improve light output intensity.

<figref idref="DRAWINGS">FIG. 10</figref> also illustrates one possible location for test point 15. Test point 15 can be disposed within the area marked by broken lines 52 which correspond to conducting material disposed under solder mask. Broken lines 52 illustrate one possible aspect of the size and/or shape of the conducting material which can be deposited on or in substrate 12 for electrically coupling conductive traces 33 and 34 and attachment surfaces 18. The electrical coupling allows electrical current to be communicated from attachment surfaces 18 to the one or more strings of LEDs 25 electrically connected to traces 33 and 34. The lines are broken to illustrate how the material can be disposed under solder mask 32. Thus, test point 15 and attachment surfaces 18 electrically and/or thermally communicate with respective conductive traces, and can comprise the same layer of material. Solder mask 32 can be deposited or disposed at least partially between respective conductive traces and conducting pad 30, such that the solder mask 32 comprises a substantially circular arrangement about conducting pad 30. Conductive pad 30 can comprise one or more marks or notches 62 for orientation purposes and for proper alignment of retention material 14.

Solder mask 32 can also be deposited in areas outside of the conductive traces, for example, between the respective conductive traces and one or more attachment surfaces 18 and/or test point 15. External, conductive wires (not shown) can electrically connect to attachment surfaces 18, and electrical current or signal can flow from the attachment surfaces 18 to the respective conductive traces. The electrical current can flow along the conducting material designated by dotted lines 52 disposed below the layer of solder mask 32. The electrical current can flow into and/or out of the conductive traces and therefore into and out of respective strings of LEDs 25 mounted over conducting pad 30. In one aspect, test point 15 can allow electrical properties of the device to be tested when probed with an electrically conductive test wire or device (not shown). The arrangement illustrated by <figref idref="DRAWINGS">FIG. 10</figref>, i.e., the location of conductive traces 33 and 34, conductive area 54, Zener diode 44, and test point 15 prior to placing retention material 14 can correspond to any one of the previously described LED devices e.g., 10 and 50 or any of the devices described in <figref idref="DRAWINGS">FIGS. 11-14</figref>. For example, LED devices described in <figref idref="DRAWINGS">FIG. 11-14</figref> can comprise at least one opening or hole, generally designated 20, that can be disposed through or at least partially through substrate 12 for facilitating attachment of the LED devices to an external substrate or surface. In addition first symbol 22 and second symbols can be used to denote the portions of the LED devices comprising positive and negative electrode terminals. One or more test points 15 can be located adjacent either a positive or negative side of the device for testing the electrical and/or thermal properties of the LED devices.

<figref idref="DRAWINGS">FIGS. 11 to 14</figref> illustrate top views of different embodiments of LED devices. Such devices may be similar in many aspects to previously described LED devices 10 and 50, but can also be useful for a range of low and/or high voltage applications in addition to attaining different light output by pattern variation. For example, <figref idref="DRAWINGS">FIG. 11</figref> illustrates one embodiment of an LED device, generally designated 60 which can be used in lower voltage applications. In one aspect and for example only without limitation, LED device 60 can be operable at approximately 16 V. In one aspect, LED device 60 can be operable at less than approximately 16 V, for example, 14 to 16 V. In one aspect, LED device 60 can be operable at more than approximately 16 V, for example, 16 to 18 V. In one aspect, using more than 140 LEDs 25, e.g., more than LED device 10 and changing the pattern of LEDs 25 can allow LED device 60 to be operable at lower voltage applications. In one aspect, the pattern can be changed by electrically connecting less than 14 LEDs 25 together in a series or string.

<figref idref="DRAWINGS">FIG. 11</figref> illustrates at least two sets of LEDs arranged in two patterns forming a reticulated array of LEDs 25 within emission area 16. For example, a first set of LEDs can comprise second pattern P2, previously described. A second set of LEDs can comprise a fourth pattern P4. Each pattern can comprise, for example, 30 strings of five LEDs 25 electrically connected in series. That is, fewer than 14 (<figref idref="DRAWINGS">FIGS. 3A</figref>, 3B) LEDs 25 can be electrically connected in series in a given string. The first and last strings of LEDs 25 can comprise five LEDs 25 electrically connected in series according to previously described second pattern P2. The second to twenty-ninth strings can comprise another pattern different from the first and thirtieth strings. For example, <figref idref="DRAWINGS">FIG. 11</figref> illustrates five LEDs 25 electrically connected in series according to pattern P2, the strings can be disposed on conducting pad 30 proximate one or more rounded outer edges of emission area 16. LEDs 25 arranged in the first and thirtieth strings can, for example and without limitation, be spaced equidistant from each other and uniformly across emission area 16 according to pattern P2. LEDs 25 arranged in pattern P2 can comprise a straight line arrangement in which longer axes of LEDs 25 are substantially parallel. The shorter axes of LEDs 25 in pattern P2 can also be at least substantially parallel. Longer axes of LEDs 25 arranged in pattern P2 can be aligned perpendicular to wirebonds 26. In addition, longer axes of LEDs 25 arranged in pattern P2 can be perpendicular to longer axes of LEDs 25 arranged in adjacent patterns, e.g., pattern P4.

In one aspect, pattern P4 can comprise five LEDS 25 electrically connected in series across conducting pad 30. Pattern P4 can comprise a straight line of LEDs, and each of the five LEDs 25 can be positioned such that longer axes of LEDs 25 are substantially aligned along a straight line. In one aspect, longer axes of each LED 25 can be aligned in a same direction as the direction of wirebonds 26 connecting the LEDs 25 to conductive traces 33 and 34 disposed below retention material 14. Adjacent strings, e.g., adjacent strings in the second through twenty-ninth strings of LEDs 25 connected in pattern P4 can alternate above and below a straight line such that the LEDs 25 form a substantially checkerboard type arrangement. That is, a first string of LEDs 25 arranged in pattern P4 (i.e., the second overall string of LEDs 25 disposed below the first string comprising pattern P2) can comprise five LEDs 25 spaced equidistant apart, leaving a space in between adjacent LEDs 25. In the alternative, LEDs 25 in pattern P4 could be wirebonded in a checkerboard arrangement, but that could increase the voltage at which device 60 is operable. Below the first string of LEDs 25 arranged in pattern P4, a subsequent string of LEDs 25 arranged in pattern P4 can be positioned or placed such that the LEDs 25 are substantially within and/or slightly below the space between adjacent LEDs 25 of the preceding string. That is, LEDs 25 arranged in pattern P4 can comprise a first string aligned such that a bottom edge of each LED 25 in the string is aligned along a same first straight line. LEDs 25 in a neighboring subsequent string of pattern P4 can be aligned such that a top edge of each LED 25 is also aligned along the same first straight line as the bottom edge of LEDs 25 in the preceding string. Thus, LEDs 25 of preceding and subsequent strings alternate above and/or below spaces between adjacent LEDs 25 in a given string, and the top and bottom edges of LEDs 25 in adjacent strings can be aligned along a same line. This arrangement comprises a substantially checkerboard shaped orientation which can advantageously allow LEDs 25 to uniformly emit light from LED device 60 without one or more adjacent LEDs blocking light.

Additional strings of LEDs 25 arranged in pattern P4 can alternate according to the first two strings just described. Strings of LEDs 25 comprising pattern P4 can comprise a same or similar width over emission area 16. That is, each adjacent LED 25 of a given string can be spaced apart at equidistant lengths, but the overall string length may not be uniformly across emission area 16. Rather, LEDs 25 can be spaced such that the second to twenty-ninth rows form a substantially reticulated array over emission area 16. In one aspect, LEDs 25 form a rectangular array over emission area 16 which utilizes a substantially uniform portion of horizontal segments, or chords of conducting pad 30. In one aspect, LED device 60 can comprise at least one group of LEDs 25 arranged in more than one string of LEDs, where the overall configuration can be in a predetermined geometrical shape, such as for example and without limitation, a rectangle. Any suitable number of LEDs 25 may be connected in series. Fewer number of LEDs 25, for example five LEDs 25 connected in series as illustrated in <figref idref="DRAWINGS">FIG. 11</figref> can allow LED device 60 to be suitable for lower voltage applications, for example 16 V applications. For illustration purposes, 30 strings of five LEDs 25 arranged in one or more patterns are illustrated for operation at lower voltages, however, any suitable number of strings and/or LEDs 25 electrically connected in series is contemplated.

LED device 60 can comprise outermost LEDs 25A electrically connected via electrical connectors such as wirebonds 26 to conductive traces 33, 34 (<figref idref="DRAWINGS">FIG. 10</figref>). Retention material 14 can then be dispensed at least partially about conducting pad 30 and at least partially over wirebonds 26. Retention material 14 can be dispensed about emission area 16 which can comprise a plurality of LED chips, or LEDs 25 disposed within and/or below filling material 40 such as illustrated in <figref idref="DRAWINGS">FIG. 7</figref>. Filling material 40 can be at least partially contained by retention material 14, and retention material can be used to control or adjust various heights of filling material as may be desirable. Notably, LED device 60 can comprise a uniform optical source in the form of single, cohesive, and undivided emission area which can simplify the manufacturing process for manufacturers of light products requiring a single component. LEDs 25 can be spaced a suitable distance apart such that device 60 can advantageously emit uniform light without having any light blocked by one or more adjacent LEDs 25. The patterns and pattern spacing (i.e., spacing between adjacent LEDs 25 and spacing between adjacent strings of LEDs 25) disclosed for example in LED devices 10 and 60 allow for optimization of light extraction by reducing the amount of light blocked by adjacent LEDs 25 and adjacent strings of LEDs 25. The pattern spacing disclosed for example in LED devices 10 and 60 can further be configured and expanded, for example, by increasing the spacing between adjacent LEDs 25 (e.g., to pattern spacing illustrated in <figref idref="DRAWINGS">FIGS. 12-14B</figref>) to maximum spacing within a given string and between one or more strings to further maximize and attain a higher efficiency and light extraction within a given LED device.

<figref idref="DRAWINGS">FIGS. 12 to 14B</figref> illustrate top views of LED devices which can be operable at higher voltages such as, for example only and not limited to approximately 42 V. In one aspect, LED devices illustrated by <figref idref="DRAWINGS">FIGS. 12 to 14B</figref> can comprise more than five LEDs 25 per string such that the device is configured to operate at greater than approximately 16 V. <figref idref="DRAWINGS">FIG. 12</figref> illustrates an LED device generally designated 70 having, for example, five strings of 14 LEDs 25. LED device 70 can comprise strings of LEDs 25 arranged in one or more different patterns. For example, the first and last strings proximate rounded edges of conducting pad 30 can comprise 14 LEDs 25 arranged in previously described pattern P2. The longitudinal axes of adjacent LEDs 25 in pattern P2 can be aligned such that they are at least substantially parallel. The longitudinal axes of adjacent LEDs 25 in pattern P2 can be at least substantially perpendicular to the direction of wirebonds 26 connecting adjacent LEDs 25. For each LED device described, any shape, orientation, or structure of LEDs is contemplated. In one aspect, LED device 70 can comprise 70 total LEDs 25.

Still referring to <figref idref="DRAWINGS">FIG. 12</figref>, strings of LEDs 25 disposed between outermost strings of second pattern P2 can comprise a different pattern, for example, third pattern P3 previously described in <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>. Third pattern P3 can comprise a substantially checkerboard pattern or arrangement of LEDs 25 electrically connected in series. In one aspect, pattern P3 can be disposed between and/or alternate with strings of LEDs having second pattern P2. The checkerboard pattern or third pattern P3 can comprise a set of LEDs 25 alternating both above and below a horizontal line. LED device 70 can be disposed uniformly across emission area 16 and/or conducting pad 30, for example. In general, adjacent LEDs 25 in each of the strings of LED device 70 can be spaced at equidistant intervals to utilize a substantial portion of horizontal segments of conducting pad 30. That is, LEDs 25 in device 70 can occupy a greater amount of surface area and length of horizontal segments of conducting pad 30 than previously described LED device 60. For illustration purposes, five strings of 14 LEDs 25 arranged in two different patterns are illustrated, however, any suitable number of strings and/or LEDs 25 electrically connected in series is contemplated.

<figref idref="DRAWINGS">FIGS. 13A and 13B</figref> illustrate further embodiments of LED devices. In one aspect, LED devices in <figref idref="DRAWINGS">FIGS. 13A and 13B</figref> comprise six strings of 14 LEDs 25, for a total of 84 LEDs 25. Referring to <figref idref="DRAWINGS">FIG. 13A</figref>, LED device, generally designated 80 can comprise one or more strings of LEDs 25 arranged for example in a single pattern across conducting pad 30. The one or more strings of device 80 can have the same and/or different patterns. For illustration purposes, previously described pattern P3 is illustrated. LEDs 25 can be arranged in a checkerboard pattern alternating above and below a horizontal line. Adjacent LEDs 25 can be spaced a substantially uniform distance from each other across a large portion of the surface area of conducting pad 30. Checkerboard arrangements, e.g., pattern P3 can advantageously allow the LEDs 25 to uniformly emit light from LED device 80 without one or more adjacent LEDs 25 blocking light.

<figref idref="DRAWINGS">FIG. 13B</figref> illustrates another embodiment of a six string LED device, generally designated 85. Like LED device 80, LED device 85 can comprise six strings of 14 LEDS 25. Spacing between adjacent LEDs 25 within the same string and adjacent LEDs 25 within different strings has been maximized to minimize the amount of light absorbed by adjacent LEDs. In one aspect, LED device 85 comprises previously illustrated first pattern P1 (<figref idref="DRAWINGS">FIG. 3A</figref>) as the first and last strings. Notably, LEDs 25 of patterns P1 and P3 extend at least substantially the full length and width of conducting pad 30. The second through fifth strings of LEDs 25 within LED device 85 comprise pattern P3. When comparing the six string arrangement of <figref idref="DRAWINGS">FIG. 13A</figref> to the six string arrangement of <figref idref="DRAWINGS">FIG. 13B</figref>, it is apparent that the strings of <figref idref="DRAWINGS">FIG. 13B</figref> are more spread out, i.e., vertically and horizontally spaced further apart on conducting pad 30 to utilize more of the mounting area. Maximizing the space between strings of LEDs 25 can minimize the amount of light absorbed or blocked by neighboring LEDs 25.

In one aspect, inter-string spacing, that is, spacing between adjacent LEDs 25 of the same string has been increased by at least approximately 31%, or by 125 μm, or greater in the vertical direction for pattern P3 from LED device 80 to LED device 85. Similarly, inter-string spacing of LEDs 25 in pattern P1 has been increased and/or optimized in both the horizontal and vertical directions. For example, spacing has been increased approximately 41%, or by 225 μm, or greater, in the horizontal direction and by at least approximately 27%, or by 210 μm, or greater in the vertical direction from P1 in LED device 10 to P1 in LED device 85. Intra-string spacing i.e., spacing between LEDs 25 of adjacent strings can be increased by at least approximately 68%, or by 750 μm, or greater in LED device 85. Notably, although LED device 85 can comprise the same number of LEDs 25 as LED device 80, e.g., 84 LEDs, LED device 85 can comprise at least approximately a 1% to 3%, or greater, increase in efficiency and brightness when compared to LED device 80. In one aspect, increasing the spacing between adjacent LEDs 25 as described can increase the efficiency by at least approximately 2.5% or greater from one six string arrangement to another, e.g., LED device 85 can comprise a 2.5% or greater increase in efficiency over LED device 80. For example, LED device 85 can have a light output of at least approximately 2.5% or higher than the light output of LED device 80 described above, which can comprise approximately 1050 lumens or more at 11 watts, or approximately 2000 lumens or more at 27 watts.

<figref idref="DRAWINGS">FIGS. 14A and 14B</figref> illustrate further embodiments of LED devices. In one aspect, the LED devices in <figref idref="DRAWINGS">FIGS. 14A and 14B</figref> comprise eight strings of 14 LEDs 25. Referring to <figref idref="DRAWINGS">FIG. 14A</figref>, an LED device generally designated 90 is illustrated, and can be operable at higher voltages, not limited to greater than or equal to approximately 42 V. LED device 90 can comprise one or more strings of LEDs 25 arranged in one or more patterns across emission area 16 and/or conducting pad 30. In one aspect, LED device 90 can comprise eight strings of LEDs 25 arranged in more than one pattern. Each string of LEDs 25 can comprise 14 LEDs 25, or 112 total LEDs. In one aspect, the first and last strings can comprise previously described pattern P2. The second through seventh strings of LEDs 25 can comprise previously described pattern P3. Notably, LED devices illustrated by <figref idref="DRAWINGS">FIGS. 11 to 14B</figref> can comprise a uniform optical source in the form of single, cohesive, and undivided emission area which can simplify the manufacturing process for manufacturers of light products requiring a single component.

<figref idref="DRAWINGS">FIG. 14B</figref> illustrates another embodiment of an eight string LED device, generally designated 95. Like LED device 90, LED device 95 can comprise eight strings of 14 LEDS 25. Spacing between adjacent LEDs 25 within the same string and adjacent LEDs 25 within different strings has been maximized to minimize the amount of light absorbed by adjacent LEDs. In one aspect, LED device 95 can comprise previously illustrated first pattern P1 (<figref idref="DRAWINGS">FIG. 3A</figref>) as the first and last strings. The second and seventh strings can comprise pattern P2, and the third through sixth strings can comprise pattern P3. Notably, LEDs 25 of patterns P1, P2, and P3 extend at least substantially the full length and width of conducting pad 30. LEDs 25 of P1, P2, and P3 can be spaced further apart horizontally and/or vertically such that an amount of light blocked by adjacent LEDs 25 can be decreased. In one aspect, pattern P1 spacing has been increased at least approximately 41%, or by 225 μm, or greater in the horizontal direction and by at least approximately 27%, or by 210 μm, or greater in the vertical direction from P1 in LED device 10 to P1 in LED device 95. Similarly, horizontal and/or vertical spacing between LEDs 25 in pattern P2 can be increased at least approximately 4% or greater over P2 in LED device 90. Intra-string spacing i.e., spacing between LEDs 25 of adjacent strings can be increased by at least approximately 68%, or by 750 μm, or greater in LED device 95. Notably, although LED device 95 can comprise the same number of LEDs 25 as LED device 90, e.g., 112 LEDs, LED device 95 can have at least an approximate 1% to 2%, or greater, increase in efficiency and brightness when compared to LED device 90.

In one aspect, LED devices 10, 60, 70, 80, and 90 disclosed by <figref idref="DRAWINGS">FIGS. 3A</figref>, 3B, and 11 to 14B can comprise a large quantity of LEDs 25 arranged in one or more patterns over conducting pad 30. In one aspect, LED devices disclosed herein comprise a quantity of more than 64 LEDs 25. For example, in one aspect and without limitation, LED device 10 can comprise 140 total LEDs, or 10 strings of LEDs 25 electrically connected in series. LED device 60 can comprise 150 total LEDs, or 30 strings of five LEDs 25 electrically connected in series. LED device 70 can comprise 70 total LEDs, or five strings of 14 LEDs 25. LED device 80 can comprise 84 total LEDs, or six strings of 14 LEDs 25. LED device 90 can comprise 112 total LEDs, or eight strings of 14 LEDs 25. LEDs 25 used in LED devices described herein can comprise a small footprint, or surface area when compared to conducting pad 30. For example and without limitation, LEDs 25 can comprise chips of the following dimensions in Table 1 below:

<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="offset" colwidth="77pt" align="left" /><colspec colname="1" colwidth="42pt" align="center" /><colspec colname="2" colwidth="98pt" align="center" /><thead><row><entry /><entry namest="offset" nameend="2" rowsep="1">TABLE 1</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row><row><entry /><entry>Length (μm)</entry><entry>Width (μm)</entry></row><row><entry /><entry namest="offset" nameend="2" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="28pt" align="left" /><colspec colname="1" colwidth="49pt" align="left" /><colspec colname="2" colwidth="42pt" align="center" /><colspec colname="3" colwidth="98pt" align="center" /><tbody valign="top"><row><entry /><entry>LED</entry><entry>350</entry><entry>470</entry></row><row><entry /><entry>chip</entry><entry>230</entry><entry>660</entry></row><row><entry /><entry>size</entry><entry>500</entry><entry>500</entry></row><row><entry /><entry /><entry>520</entry><entry>700</entry></row><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

In one aspect and without limitation, conducting pad 30 can comprise a radius of approximately 6.568 mm and an area of approximately 135.7 mm2. Thus, the ratio of the area of a single LED chip 25 and the area of conducting pad 30 can comprise approximately 0.0027 or less. In one aspect, the ratio of the area of a single LED chip 25 and the area of conducting pad 30 can comprise approximately 0.0018 or less. In other aspects, the ratio can comprise approximately 0.0012 or less. Table 2 below lists various LED 25 chip sizes and the area of conducting pad 30. LEDs 25 can comprise chips that are small compared to the area of conducting pad, that is, approximately 0.0027 of the area of the conducting pad or less. Any chip size may be used however.

<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="70pt" align="center" /><colspec colname="2" colwidth="56pt" align="center" /><colspec colname="3" colwidth="91pt" align="center" /><thead><row><entry namest="1" nameend="3" rowsep="1">TABLE 2</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>Conducting Pad</entry><entry>Ratio of Chip Area to</entry></row><row><entry>Chip Size (μm)</entry><entry>Area (mm)</entry><entry>Conducting Pad Area</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry>350 × 470</entry><entry>135.7098</entry><entry>0.0012</entry></row><row><entry>230 × 660</entry><entry>135.7098</entry><entry>0.0011</entry></row><row><entry>500 × 500</entry><entry>135.7098</entry><entry>0.0018</entry></row><row><entry>520 × 700</entry><entry>135.7098</entry><entry>0.0027</entry></row><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

Using a large quantity of LEDs 25 comprising a smaller footprint over a single emission area can advantageously allow for more uniform light output in addition to desirable optical properties such as high brightness as the LEDs 25 can be arranged into one or more uniform patterns over a portion of emission area 16. The concentrated patterns of LEDs 25 can allow for concentrated light emission. In one aspect, the density or spacing of LEDs 25 in the one or more patterns described herein can be adjusted such that light will not be absorbed or blocked by adjacent LEDs 25. That is, patterns and arrangements of LEDs 25 disclosed herein may improve light extraction by minimizing the amount of light absorbed by adjacent, or neighboring LEDs 25. The number of LEDs 25 per string can allow LED devices to be operable at low to high voltages. For illustration purposes, four patterns have been illustrated. However, any suitable pattern of LEDs 25 is contemplated. Each string of LEDs 25 can comprise a single pattern or a combination of more than one pattern.

<figref idref="DRAWINGS">FIGS. 15A and 15B</figref> illustrate methods of die attach that can, for example and without limitation, be used for LED devices according to the disclosure herein. LED 25 can comprise a backside metal pad or bonding layer 100 for mounting over conducting pad 30. Bonding layer 100 can comprise a length of the entire bottom surface LED 25 or a portion thereof. For illustration purposes, bonding layer 100 is illustrated as having a same length as the entire bottom surface of LED 25, however, any configuration is contemplated. LED 25 can comprise lateral sides 104 which can extend between an upper surface and the bottom surface of LED 25. <figref idref="DRAWINGS">FIGS. 15A and 15B</figref> illustrate inclined lateral sides 104, however, lateral sides 104 can be substantially vertical or straight where a straight-cut LED is selected. <figref idref="DRAWINGS">FIGS. 15A and 15B</figref> illustrate LEDs 25 having an upper surface of a greater surface area than an area of bottom surface comprising bonding layer 100. However, upper surface can be of a smaller surface area than the surface area of bonding surface. LEDs 25 can comprise a square, rectangle, or any suitable shape in addition to having any suitable lateral side configuration.

Any suitable die attach method can be used to mount LED 25 over conducting pad 30 in any of the LED devices previously described. In one aspect, any suitable optimized die attach method and/or materials can be used. For example, optimized die attach methods can comprise metal-to-metal die attach methods for facilitating attachment of one or more metals on and/or between LED 25 and conducting pad 30. <figref idref="DRAWINGS">FIG. 15A</figref> illustrates an example of a metal-to-metal die attach method which can be eutectic or non-eutectic. This metal-to-metal die attach method can comprise using an assist material 106 to facilitate the metal-to-metal die attach. In one aspect, a flux-assisted eutectic metal-to-metal die attach method can be used and in other aspects a metal-assisted non-eutectic metal-to-metal die attach method can be used. In a flux-assisted eutectic, or flux eutectic, die attach method, bonding layer 100 can comprise a metal alloy having a eutectic temperature, for example, but not limited to, an alloy of gold (Au) and tin (Sn). For example, bonding layer 100 can comprise an 80/20 Au/Sn alloy having a eutectic temperature of approximately 280° C. In the flux eutectic technique, assist material 106 can comprise a flux material. In the non-eutectic technique, assist material 106 can comprise a metallic material. The assist material 106 can comprise a conduit for facilitating the metal-to-metal die attach between the bonding layer 100 and conducting pad 30 when the bonding layer 100 is heated above the eutectic temperature. The metal of bonding layer 100 can flow into and attach to the metal of conducting pad 30. The metal of bonding layer 100 or can atomically diffuse and bond with atoms of the underlying mounting conducting pad 30. In one aspect, flux used in a flux-assisted eutectic method can comprise a composition, for example, 55-65% rosin and 25-35% polyglycol ether in addition to small amounts of other components. Any suitable flux material can be used however.

Flux-assisted eutectic die attach methods can be tedious, and it is unexpected to use such methods when attaching a large quantity of LEDs 25 in predetermined arrangements and/or an array. Flux eutectic die attach according to the present subject matter can comprise dispensing flux assist material 106, that can be liquid at room temperature, in an amount to be precisely the right volume to avoid either swimming of the LEDs 25 or poor die attach if too much or too little flux is used. Flux-assisted eutectic die attach according to the present subject matter can also require the right composition for each of the flux assist material 106 and bonding metal 100 of the emitter chips. Flux-assisted eutectic die attach according to the present subject matter can optimally utilize a very clean and flat surface and substrates that do not move or bend during heating and cooling such to stress the solder joint. Flux-assisted eutectic according to the present subject matter can utilize a fine surface roughness that is small enough not to encumber the Au/Sn bonding surface of the emitter chips while being rough enough to allow flux to escape during heating. The heating profile can be matched perfectly to the bonding metal 100, such as Au or AuSn, to ensure a good weld between the bonding metal 100 and underlying conducting pad 30. Using flux-assisted eutectic for die attach according to the present subject matter also can utilize an inert atmosphere, such as a nitrogen atmosphere, to reduce oxygen gas (O2) levels and also allow gravity to apply a downward force on LEDs 25. This can reduce the amount of oxidation at the metal-to-metal bond between bonding layer 100 and underlying conducting pad 30.

Still referring to <figref idref="DRAWINGS">FIG. 15A</figref>, a non-eutectic metal-to-metal die attach method can be used which can also comprise an assist material 106, wherein the assist material 106 can comprise a metallic material. In this aspect, bonding layer 100 can comprise a single metal or a metal alloy. For example, bonding layer 100 can comprise Au, Sn, or AuSn. In non-eutectic methods, the bonding layer does not need to reach or exceed a temperature, for example, a eutectic temperature. In this aspect, assist material 106 can comprise a metallic material to facilitate the metal-to-metal bonding. For example, assist material 106 can comprise AuSn paste or Ag epoxy. Any suitable metallic assist material 106 can be used. The metal of bonding layer 100 can attach to the metal of the assist material 106. The metal of the assist material 106 can also attach to the metal of conducting pad 30. In one aspect, a metal “sandwich” forms between bonding layer 100, assist material 106, and conducting pad 30 in non-eutectic metal-to-metal attach techniques where a metallic assist material 106 is used. Metal-assisted, non-eutectic die attach can be tedious, just as flux-assisted methods, and it is also unexpected to use such methods when attaching LEDs 25 within one or more patterns for LED devices described herein. Metal-to-metal attachment using an assist material 106 can be hard to control and tedious when attaching multiple small footprint LEDs within a device.

<figref idref="DRAWINGS">FIG. 15B</figref> illustrates a metal-to-metal die attach technique which does not require an assist material 106. One such method can comprise a thermal compression die attach method wherein the metal of bonding layer 100 will directly attach to the metal of conducting pad 30. The thermal compression method can be eutectic or non-eutectic. In one aspect, thermal compression can be used when bonding layer 100 comprises an alloy having a eutectic temperature. In other aspects, bonding layer 100 can comprise a metal not having a eutectic temperature. Conducting pad 30 can comprise any suitable metal, not limited to a Cu, Al, Ag, or Pt layer within a metal core printed circuit board (MCPCB). Bonding layer 100 comprises any suitable metal. In one aspect, bonding layer 100 can comprise a layer of Sn having any suitable thickness. In one aspect, bonding layer 100 can comprise a thickness greater than approximately 0 μm. In one aspect, bonding layer 100 can comprise a bonding layer equal to or greater than at least approximately 0.5 μm. In one aspect, bonding layer 100 can comprise a layer of Sn having a thickness of at least equal to or greater than approximately 2.0 μm. Unlike the flux-assisted eutectic or metal-assisted non-eutectic methods just described, thermal compression metal-to-metal die attach techniques can utilize an external downward force F as illustrated in <figref idref="DRAWINGS">FIG. 15B</figref>.

Force F can comprise a compression delivered in a heated environment, thus deemed a thermal compression, as opposed to dispensing a flux or metallic assist material 106. The thermal compression technique is an alternative die attach method developed to reduce metal squeeze out along the conducting pad 30 which can form Shottky or Shunt defects and allow subsequent leakage of current and other various and related problems. In one aspect, the bonding temperature in thermal compression techniques can be approximately 255-265° C. after optionally subjecting conducting pad 30 to a pre-heat treatment or process. Conducting pad 30 can be heated to a mounting temperature of at least 20° C. above the melting temperature of the bonding layer 100. The bonding time can be approximately 300 msec and the bonding force can be approximately 50+/−10 grams (g). Predetermined settings can be important for this method, including adequate preheat, bonding temperature, bonding time, and bonding force. The equipment and predetermined settings for use with thermal compression methods can be difficult to use and/or maintain, and it is unexpected to use such methods when attaching a large quantity of LEDs 25 in an array and/or one or more patterns. Metal-to-metal methods for attaching an array of LEDs in LED devices is not known and is unexpected to use flux-assisted eutectic, metal-assisted non-eutectic, or thermal compression die attach techniques for attaching one or more strings of LEDs 25 in an array or pattern arrangement.

Embodiments of the present disclosure shown in the drawings and described above are exemplary of numerous embodiments that can be made within the scope of the appended claims. It is contemplated that the configurations of LED devices and methods of making the same can comprise numerous configurations other than those specifically disclosed.

Contents6

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USD650760S	United States of America	S	2011-12-20
US2011316022A1	United States of America	A1	2011-12-29
WO2012005984A1	World Intellectual Property Organization (WIPO)	A1	2012-01-12
WO2012021238A1	World Intellectual Property Organization (WIPO)	A1	2012-02-16
KR20120015362A	Republic of Korea	A	2012-02-21
TW201212299A	Taiwan Province of China	A	2012-03-16
TWD146222S	Taiwan Province of China	S	2012-04-01
EP2438631A2	European Patent Office (EPO)	A2	2012-04-11
WO2012050994A2	World Intellectual Property Organization (WIPO)	A2	2012-04-19
USD659657S	United States of America	S	2012-05-15
CN102460751A	China	A	2012-05-16
US2012126255A1	United States of America	A1	2012-05-24
US2012126257A1	United States of America	A1	2012-05-24
US2012127720A1	United States of America	A1	2012-05-24
WO2012071136A2	World Intellectual Property Organization (WIPO)	A2	2012-05-31
WO2012071138A2	World Intellectual Property Organization (WIPO)	A2	2012-05-31
WO2012071139A2	World Intellectual Property Organization (WIPO)	A2	2012-05-31
TW201222900A	Taiwan Province of China	A	2012-06-01
TW201222902A	Taiwan Province of China	A	2012-06-01
USD661264S	United States of America	S	2012-06-05
US2012153317A1	United States of America	A1	2012-06-21
WO2012050994A3	World Intellectual Property Organization (WIPO)	A3	2012-07-05
TWD148144S1	Taiwan Province of China	S1	2012-07-11
WO2012071139A3	World Intellectual Property Organization (WIPO)	A3	2012-07-12
TW201230398A	Taiwan Province of China	A	2012-07-16
WO2012071138A3	World Intellectual Property Organization (WIPO)	A3	2012-07-19
WO2012100060A2	World Intellectual Property Organization (WIPO)	A2	2012-07-26
CN102623612A	China	A	2012-08-01
TW201232813A	Taiwan Province of China	A	2012-08-01
TW201232852A	Taiwan Province of China	A	2012-08-01
US2012193651A1	United States of America	A1	2012-08-02
WO2012071136A3	World Intellectual Property Organization (WIPO)	A3	2012-08-09
WO2012106312A1	World Intellectual Property Organization (WIPO)	A1	2012-08-09
US2012205689A1	United States of America	A1	2012-08-16
WO2012109225A1	World Intellectual Property Organization (WIPO)	A1	2012-08-16
US8251963B2	United States of America	B2	2012-08-28
TW201236219A	Taiwan Province of China	A	2012-09-01
US8269244B2	United States of America	B2	2012-09-18
USD667803S	United States of America	S	2012-09-25
US2012250310A1	United States of America	A1	2012-10-04
USD669273S	United States of America	S	2012-10-23
WO2012100060A3	World Intellectual Property Organization (WIPO)	A3	2012-11-08
WO2012151270A1	World Intellectual Property Organization (WIPO)	A1	2012-11-08
JP2012529176A	Japan	A	2012-11-15
US2012289911A1	United States of America	A1	2012-11-15
US2012299022A1	United States of America	A1	2012-11-29
US2012300491A1	United States of America	A1	2012-11-29
US2012306370A1	United States of America	A1	2012-12-06
US2012306375A1	United States of America	A1	2012-12-06
US2012307481A1	United States of America	A1	2012-12-06
WO2012166791A2	World Intellectual Property Organization (WIPO)	A2	2012-12-06
WO2012166904A1	World Intellectual Property Organization (WIPO)	A1	2012-12-06
TW201251132A	Taiwan Province of China	A	2012-12-16
TW201251140A	Taiwan Province of China	A	2012-12-16
US2013003375A1	United States of America	A1	2013-01-03
US2013011946A1	United States of America	A1	2013-01-10
WO2012166791A3	World Intellectual Property Organization (WIPO)	A3	2013-01-24
USD676000S	United States of America	S	2013-02-12
USD676395S	United States of America	S	2013-02-19
CN102959748A	China	A	2013-03-06
KR20130023269A	Republic of Korea	A	2013-03-07
WO2013032737A2	World Intellectual Property Organization (WIPO)	A2	2013-03-07
US2013077299A1	United States of America	A1	2013-03-28
USD679842S	United States of America	S	2013-04-09
CN103080646A	China	A	2013-05-01
CN103098217A	China	A	2013-05-08
WO2013032737A3	World Intellectual Property Organization (WIPO)	A3	2013-05-10
WO2013070696A1	World Intellectual Property Organization (WIPO)	A1	2013-05-16
US8455908B2	United States of America	B2	2013-06-04
EP2603930A1	European Patent Office (EPO)	A1	2013-06-19
WO2013096431A1	World Intellectual Property Organization (WIPO)	A1	2013-06-27
KR20130077901A	Republic of Korea	A	2013-07-09
US8497522B2	United States of America	B2	2013-07-30
USD686824S	United States of America	S	2013-07-30
US2013200406A1	United States of America	A1	2013-08-08
US2013200420A1	United States of America	A1	2013-08-08
EP2628196A2	European Patent Office (EPO)	A2	2013-08-21
WO2013122831A1	World Intellectual Property Organization (WIPO)	A1	2013-08-22
CN103270614A	China	A	2013-08-28
TW201336118A	Taiwan Province of China	A	2013-09-01
CN103329290A	China	A	2013-09-25
CN103329291A	China	A	2013-09-25

Showing 100 of 234

82 transactions on the USPTO file

Allowed after 1 non-final rejection and 1 RCE.

Non-final rejections: 1
Final rejections: 0
RCEs: 1
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2025-07-07	Payment of Maintenance Fee, 12th Year, Large EntityM1553	M1553
2021-07-07	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2014-01-07	Recordation of Patent Grant MailedPGM/	PGM/
2014-01-07	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2013-12-19	Email NotificationEML_NTR	EML_NTR
2013-12-18	Issue Notification MailedAllowedWPIR	WPIR
2013-12-05	Dispatch to FDCD1935	D1935
2013-12-03	Application Is Considered Ready for IssuePILS	PILS
2013-11-27	Response to Reasons for AllowanceREAS	REAS
2013-11-27	Issue Fee Payment VerifiedN084	N084
2013-11-27	Issue Fee Payment ReceivedIFEE	IFEE
2013-10-30	Email NotificationEML_NTR	EML_NTR
2013-10-30	Mail Miscellaneous Communication to ApplicantMM327	MM327
2013-10-27	Miscellaneous Communication to Applicant - No Action CountM327	M327
2013-10-25	Pubs Case Remand to TCPUBTC	PUBTC
2013-10-21	Email NotificationEML_NTR	EML_NTR
2013-10-21	Printer Rush- No mailingTCPB	TCPB
2013-10-21	Mail Miscellaneous Communication to ApplicantMM327	MM327
2013-10-15	Miscellaneous Communication to Applicant - No Action CountM327	M327
2013-10-09	Pubs Case Remand to TCPUBTC	PUBTC
2013-09-17	Information Disclosure Statement consideredIDSC	IDSC
2013-09-17	Information Disclosure Statement (IDS) FiledM844	M844
2013-09-17	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-08-28	Electronic ReviewELC_RVW	ELC_RVW
2013-08-28	Email NotificationEML_NTF	EML_NTF
2013-08-28	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2013-08-23	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2013-08-21	Examiner's Amendment CommunicationEX.A	EX.A
2013-08-13	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2013-08-12	Information Disclosure Statement consideredIDSC	IDSC
2013-08-12	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-08-12	Reference capture on IDSRCAP	RCAP
2013-08-12	Information Disclosure Statement (IDS) FiledM844	M844
2013-08-12	Request for Continued Examination (RCE)RCEX	RCEX
2013-08-12	Workflow - Request for RCE - BeginBRCE	BRCE
2013-07-01	Electronic ReviewELC_RVW	ELC_RVW
2013-07-01	Email NotificationEML_NTF	EML_NTF
2013-07-01	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2013-06-05	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2013-05-16	Information Disclosure Statement consideredIDSC	IDSC
2013-05-16	Reference capture on IDSRCAP	RCAP
2013-05-16	Information Disclosure Statement (IDS) FiledM844	M844
2013-05-16	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-05-09	Date Forwarded to ExaminerFWDX	FWDX
2013-05-03	Response after Non-Final ActionA...	A...
2013-05-03	Request for Extension of Time - GrantedXT/G	XT/G
2013-01-16	Information Disclosure Statement consideredIDSC	IDSC
2013-01-16	Reference capture on IDSRCAP	RCAP
2013-01-16	Information Disclosure Statement (IDS) FiledM844	M844
2013-01-16	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2013-01-03	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2012-12-30	Non-Final RejectionNon-final rejectionCTNF	CTNF
2012-12-12	Date Forwarded to ExaminerFWDX	FWDX
2012-12-10	Response to Election / Restriction FiledELC.	ELC.
2012-12-10	Request for Extension of Time - GrantedXT/G	XT/G
2012-10-10	Mail Restriction RequirementMCTRS	MCTRS
2012-10-05	Restriction/Election RequirementCTRS	CTRS
2012-08-27	Case Docketed to Examiner in GAUDOCK	DOCK
2012-07-10	Information Disclosure Statement consideredIDSC	IDSC
2012-07-10	Reference capture on IDSRCAP	RCAP
2012-07-10	Information Disclosure Statement (IDS) FiledM844	M844
2012-07-10	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-05-24	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2012-05-14	Case Docketed to Examiner in GAUDOCK	DOCK
2012-01-30	Case Docketed to Examiner in GAUDOCK	DOCK
2011-09-21	Application Dispatched from OIPEOIPE	OIPE
2011-08-31	Application Is Now CompleteCOMP	COMP
2011-08-31	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2011-08-31	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2011-08-30	Sent to Classification ContractorPGPC	PGPC
2011-08-23	Payment of additional filing fee/PreexamFLFEE	FLFEE
2011-08-23	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2011-08-23	Applicants have given acceptable permission for participating foreignAPPERMS	APPERMS
2011-06-20	Information Disclosure Statement consideredIDSC	IDSC
2011-06-20	Reference capture on IDSRCAP	RCAP
2011-06-20	Information Disclosure Statement (IDS) FiledM844	M844
2011-06-20	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-05-25	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2011-05-25	Filing ReceiptFLRCPT.O	FLRCPT.O
2011-05-12	Cleared by OIPE CSRL194	L194
2011-05-10	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2011-05-10	Initial Exam Team nnIEXX	IEXX

12 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2025-07-07	Maintenance fee paymentMAFP	MAFP
2025-06-30	AssignmentAS	AS
2025-06-25	AssignmentAS	AS
2025-06-25	AssignmentAS	AS
2025-06-25	AssignmentAS	AS
2025-06-25	AssignmentAS	AS
2022-02-07	AssignmentAS	AS
2021-03-31	AssignmentAS	AS
2020-12-07	Maintenance fee paymentMAFP	MAFP
2017-06-22	Fee paymentFPAY	FPAY
2013-12-18	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2011-08-23	AssignmentAS	AS

Light emitting devices

Summary by NHIP

Claim Score by NHIP

Abstract