Defective memory block remapping method and system, and memory device and processor-based system using same

CROSS REFERENCE TO RELATED APPLICATION(S)

0001This application is a continuation of U.S. patent application Ser. No. 12/788,053, filed May 26, 2010, U.S. Pat. No. 7,958,439, which is a divisional of U.S. patent application Ser. No. 11/656,577, filed Jan. 22, 2007, U.S. Pat. No. 7,743,303. These applications and patents are incorporated herein by reference, in their entirety, for any purpose.

TECHNICAL FIELD

0002This invention relates generally to non-volatile memory devices, and more particularly, to a system and method for remapping to functional blocks of memory accesses to defective blocks of memory for erase, programming and read operations.

BACKGROUND OF THE INVENTION

0003Non-volatile memory is memory that can continue to store data after power is no longer provided to the memory. “Flash memory,” called this because data can be erased from multiple memory cells simultaneously, is an example of non-volatile memory. A typical flash memory comprises an array of memory cells arranged in rows and columns. The array is divided into blocks of memory cells, with 2048 or 4096 blocks in a typical flash memory device. Although each of the cells within a block can be electrically programmed to store data individually, data is erased from the cells at the block level.

0004A common example of flash memory is NAND flash memory. The array of memory cells for NAND flash memory devices are arranged such that a control gate of each memory cell of a row of the array is connected to a word line. However, each memory cell is not directly connected to a column bit line. Instead, the memory cells of the array are arranged together in strings (“NAND strings”), with the memory cells connected together in series, source to drain, between a source line and a column bit line. The NAND strings in each block typically have as many as 32 memory cells between the source line and the column bit line.

0005The memory array for NAND flash memory devices is accessed by a row decoder activating a row of memory cells by selecting the word line connecting the control gates of the memory cells. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven so that the respective memory cell passes current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series connected string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines to be sense and amplified before being output as data, as well known.

0006After memory devices have been fabricated, they normally undergo testing to determine if they are functioning properly. It is not uncommon to find that many memory cells in the device are defective. For example, in flash memory device, it is common for functional testing to reveal that one or more blocks of memory cells are defective. In order to increase the yield from each semiconductor die, memory devices, including flash memory devices, are normally manufactured with extra columns and extra blocks of memory cells, which are sometimes referred to as “redundant columns” and “redundant blocks,” respectively. When a column or block of memory cells is found to be defective during testing, the defective column or block may be repaired by substituting a redundant column or block of memory cells. This is typically accomplished by programming a bank of fuses or anti-fuses with the address of the defective column or block. When an attempt is made to access the defective column or block, the corresponding address is detected, and the access is redirected to the redundant column or block, respectively.

0007The ability to perform post-fabrication repair of defective flash memory devices increases the die yield because it allows such devices to be sold. To further increase die yield and thereby minimize the cost of flash memory devices, standard specifications for NAND flash memory allow a manufacturer to sell NAND flash devices having a percentage of defective blocks of memory, which are referred to as “initial bad blocks” of memory. The bad blocks do not affect the performance of good blocks of memory because each block is independently accessible.

0008Generally the process of identifying initial bad blocks occurs during testing by the manufacturer. A conventional manner of marking the bad blocks is to program specific locations within each bad block with data that is used to indicate that the block is defective. Upon use of the memory device, a bad block disable process is performed. During this process, the specific locations are queried to identify which blocks of memory are bad. Control logic included in the memory device identifies the bad blocks by checking for the data that is indicative of a bad block. If such data is present, the block can be disabled using a conventional technique of setting a latch in the respective block decoder circuits for the bad block. Setting the latch prevents access to the bad block and provides a hardware mechanism for disabling bad blocks prior to operation. Although the technique of programming bad blocks with indicating data is effective in marking initial bad blocks, some users choose not to read the array for the bad block information prior to use, and simply erase the entire array. As a result, the data programmed to identify the bad blocks are erased, thus, eliminating any way to identify which blocks are bad after the erasing process. Also, this process requires that the user be involved in identifying of bad blocks and ensuring that they are not accessed. The user must therefore adapt a system containing the flash memory device to carry out these functions. Furthermore, if these functions are performed improperly, the flash memory device may provide erroneous data.

0009One approach to identifying bad blocks even in the case where the entire memory array is erased prior to use is to program initial bad block information in a user-inaccessible memory that is separate from the flash memory array. One technique is to program the initial bad block information into specific circuits designed to store this information. An example of this type of circuit is described in U.S. Pat. No. 5,864,499 to Roohparvar et al. The circuits described therein are small arrays of non-volatile memory cells having dedicated sense amplifiers. The memory cells can be programmed and function as “fuses” to store information identifying the initial bad blocks. One problem resulting from this approach is that as the number of memory blocks in a memory device increases, and there are a greater absolute number of bad blocks, the number of the dedicated “fuse circuits” must also increase. The additional fuse circuits occupy more space on the die, which is generally undesirable.

0010There is therefore a need for a system and method for identifying initial bad blocks and remapping accesses to initial bad blocks in a manner that is transparent to the user and does not require a large number of dedicated fuse circuits even though the memory device contains a large number of potentially defective blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

0011<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a flash memory device according to one example of the invention.

0012<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of one example of a block remapping system that may be used in the flash memory device of <figref idref="DRAWINGS">FIG. 1</figref>.

0013<figref idref="DRAWINGS">FIG. 3</figref> is a table showing one example of mapping data provided by a fuse bank in the block remapping system of <figref idref="DRAWINGS">FIG. 2</figref>.

0014<figref idref="DRAWINGS">FIG. 4</figref> is a table showing one example of a technique for designating the number of contiguous bad blocks starting at a specific block address that may be used in the block remapping system of <figref idref="DRAWINGS">FIG. 2</figref>.

0015<figref idref="DRAWINGS">FIG. 5</figref> is a table showing various examples of bad block remapping using the block remapping system of <figref idref="DRAWINGS">FIG. 2</figref>.

0016<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of a processor-based system using the flash memory device of <figref idref="DRAWINGS">FIG. 1</figref> or a non-volatile memory device according to another example of the invention.

0017<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart of a method of addressing a memory according to an embodiment of the invention.

0018<figref idref="DRAWINGS">FIG. 8</figref> is a flow chart of a method of replacing bad memory blocks of a memory according to an embodiment of the invention.

DETAILED DESCRIPTION

0019A flash memory device <b>100</b> according to one example of the invention is shown in <figref idref="DRAWINGS">FIG. 1</figref>. The flash memory device <b>100</b> includes an array <b>130</b> of flash memory cells arranged in rows and columns. The array <b>130</b> is divided into a large number of blocks, each of which contains a specific number of rows of the array <b>130</b>. The flash memory cells in the array <b>130</b> have their control gates coupled to respective word lines, and NAND strings of memory cells in each block are connected in series, source to drain, between a source line and a respective column bit line. The flash memory array <b>130</b> may contain, for example, 2048 or 4096 blocks of memory cells.

0020The memory device <b>100</b> includes an I/O bus <b>134</b> through which sequential input/output (“I/O”) signals corresponding to memory commands, addresses and write data are applied to the memory device <b>100</b>. Similarly, I/O signals corresponding to read data are output from the flash memory device <b>100</b> through the I/O bus <b>134</b>. The I/O bus is connected to an I/O control unit <b>140</b> that routes the signals between the I/O bus <b>134</b> and an internal data bus <b>142</b>, an address register <b>144</b>, a command register <b>146</b> and a status register <b>148</b>.

0021The flash memory device <b>100</b> also includes a control logic unit <b>150</b> that receives a number of control signals, including an active low chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, an active low write enable signal WE#, an active low read enable signal RE#, and an active low write protect WP# signal. When the chip enable signal CE# is active low, I/O signals corresponding to commands, addresses and data may be transferred between the memory device <b>100</b> and a memory access device (not shown). When the command latch enable signal CLE is active high and the ALE signal is low, the control logic unit <b>150</b> causes the I/O control unit <b>140</b> to route signals received through the I/O bus <b>134</b> to the command register <b>146</b> responsive to the rising edge of the WE# signal. Similarly, when the address latch enable signal ALE is active high and the CLE signal is low, the I/O control unit <b>140</b> routes signals received through the I/O bus <b>134</b> to the address register <b>144</b> responsive to the rising edge of the WE# signal. The write enable signal WE# is also used to gate signals corresponding to write data from the memory access device (not shown) to the memory device <b>100</b>, and the read enable signal RE# is used to gate signals corresponding to read data from the memory device <b>100</b> to the memory access device (not shown). The I/O control unit <b>140</b> transfers signals corresponding to write data and read data between the I/O bus <b>134</b> and the internal data bus <b>142</b> when the CLE and ALE signals are both low. Finally, an active low write protect signal WP# prevents the memory device <b>100</b> from inadvertently performing programming or erase functions.

0022The status register <b>148</b> can be read responsive to a read status command. After the read status command, all subsequent read commands will result in status data being read from the status register <b>148</b> until a subsequent page read command is received. The status data read from the status register <b>148</b> provides information about the operation of the memory device <b>100</b>, such as whether programming and erase operations were completed without error.

0023The address register <b>144</b> stores address signals corresponding to rows and columns of memory cells in the array <b>130</b>. The address register <b>144</b> then outputs signals corresponding to an addressed row to a block remapping system <b>160</b>. As explained in greater detail below, when the block remapping system <b>160</b> receives each address, it executes a remapping procedure. This remapping procedure uses information stored in the system <b>160</b> that identifies the bad blocks to translate the address of a row in a bad block to an address of a row that is in a good block. As also explained in further detail below, the system <b>160</b> performs the remapping process by decoding extra, redundant blocks of memory cells as an extension of the array <b>130</b> and uses them to map over bad blocks if necessary. The block remapping system <b>160</b> includes repair fuse sets (not shown in <figref idref="DRAWINGS">FIG. 2</figref>), each of which contains information identifying the starting address of a bad block and the number of contiguous bad blocks following the identified bad block. Each of the relatively few fuse sets can be used to identify any of the relatively large number of blocks that may be defective. As a result, and because one fuse set can also identify a large number of contiguous bad blocks, the block remapping system <b>160</b> requires only a relatively small number of fuse sets. As further explained below, the entire remapping process is transparent to the user, and a system containing the memory device <b>100</b> need not be specially adapted to accommodate the block remapping system <b>160</b>. More specifically, an address map for the memory device <b>100</b> shows one contiguous address space of only good blocks, thereby freeing the user of the need to tag bad blocks, which are no longer accessible to the user.

0024After the address signals stored in the address register <b>144</b> have been remapped if necessary by the block remapping system <b>160</b>, signals corresponding to the remapped address are applied to a row decoder <b>162</b>, and the column address signals to a column decoder <b>164</b>. The row decoder <b>162</b> asserts the word line corresponding to the decoded row address. Similarly, the column decoder <b>164</b> enables write data signals to be applied to bit lines for columns corresponding to the column address and allows read data to be coupled from bit lines for columns corresponding to the column address signals.

0025In response to the memory commands decoded by the control logic unit <b>150</b>, the flash memory cells in the array <b>130</b> are erased, programmed, or read. The memory array <b>130</b> is programmed on a row-by-row or page-by-page basis. After the signals corresponding to a row address have been loaded into the address register <b>144</b> and output from the block remapping system <b>160</b>, the I/O control unit <b>140</b> routes signals corresponding to write data to a cache register <b>170</b>. The write data signals are stored in the cache register <b>170</b> in successive sets each having a size corresponding to the width of the I/O bus <b>134</b>. The cache register <b>170</b> sequentially stores the sets of write data signals for an entire row or page of memory cells in the array <b>130</b>. All of the stored write data signals are then used to program a row or page of memory cells in the array <b>130</b> selected by the row address output from the block remapping system <b>160</b>. In a similar manner, during a read operation, read data signals from a row or page of memory cells selected by the row address stored in the address register <b>144</b> and output from the block remapping system <b>160</b> are stored in a data register <b>180</b>. Sets of data signals corresponding in size to the width of the I/O bus <b>134</b> are then sequentially transferred through the I/O control unit <b>140</b> from the data register <b>180</b> to the I/O bus <b>134</b>. Although the array <b>130</b> is typically read on a row-by-row or page-by-page basis, a selected portion of a selected row or page may be read by specifying a corresponding column address.

0026The flash memory device <b>130</b> also includes an NMOS transistor <b>190</b> having its gate coupled to receive a signal from the control logic unit <b>150</b>. When the memory device <b>100</b> is busy processing a programming, erase or read command, the control logic unit <b>150</b> outputs a high signal to cause the transistor <b>190</b> to output an active low read/busy signal R/B#. At other times, the transistor <b>190</b> is turned OFF to indicate to a memory access devices that the device <b>100</b> is able to accept and process memory commands.

0027A block remapping system <b>200</b> according to one example of the invention is shown in <figref idref="DRAWINGS">FIG. 2</figref>. The block remapping system <b>200</b> may be used as the block remapping system <b>160</b> in the memory device of <figref idref="DRAWINGS">FIG. 1</figref>, or in some other non-volatile memory device, such as a flash memory, in which the rows of memory cells are divided into multiple blocks. The block remapping system <b>200</b> performs a block remapping process responsive to each read, program and erase operation in a memory device containing the system <b>160</b>. The block remapping system <b>200</b> includes 16 block redundancy fuse sets <b>204</b> that are accessed responsive to a corresponding one of 16 decoder signals YDEC<<b>15</b>:<b>0</b>>. As shown in <figref idref="DRAWINGS">FIG. 3</figref>, when each fuse set is accessed, it outputs a 14-bit signal that consists of an 11-bit block address FUSE_ADDR<<b>10</b>:<b>0</b>>, which corresponds to the address of a defective block, a 2-bit BLOCK_SIZE<<b>12</b>:<b>11</b>>, which specifies the number of rows in each block, and an ENABLE<<b>13</b>> bit, which causes the block remapping system <b>200</b> to treat the block designated by the 11-bit block address FUSE_ADDR<<b>10</b>:<b>0</b>> as being defective. The 16 values of block address FUSE_ADDR<<b>10</b>:<b>0</b>> are stored in the fuse sets <b>204</b> in a manner that causes them to be accessed by values of YDEC<<b>15</b>:<b>0</b>> in ascending order. As a result, the fuse sets <b>204</b> outputs addresses of bad blocks from bad blocks having lower addresses to bad blocks having higher addresses.

0028The block remapping system also includes global fuse sets <b>206</b>, which provides two pieces of information. First, it outputs a 3-bit MULTIPLIER<<b>2</b>:<b>0</b>>, which is used by the system <b>200</b> to increase the block size corresponding to the BLOCK_SIZE<<b>12</b>:<b>11</b>> bits to a higher number. Second, it outputs an 11-bit MAX_ADDR<<b>10</b>:<b>0</b>> designating the highest numbered block in the memory device containing the system <b>200</b>. The value of MAX_ADDR<<b>10</b>:<b>0</b>> corresponds to all of the blocks in the memory device, including the redundant blocks. Both of the items of information stored in the global fuse sets <b>206</b> are specific to a specific memory device, and the fuse sets <b>206</b> may be programmed during post-fabrication testing when the fuse sets <b>204</b> are programmed. Although fuse sets <b>204</b>, <b>206</b> would normally be programmed during post-fabrication testing, the global fuse sets <b>206</b> may alternatively be programmed during fabrication.

0029The values of YDEC<<b>15</b>:<b>0</b>>, which are used to access the block redundancy fuse sets <b>204</b>, are provided by a y-decoder <b>210</b>. The y-decoder <b>210</b> receives 4 bits ACNT<<b>3</b>:<b>0</b>> from a counter <b>212</b>, and decodes the 4 bits into one of the 16 YDEC<<b>15</b>:<b>0</b>>, which select a corresponding one of the 16 fuse sets <b>204</b>. The counter <b>212</b> is incremented by a clock signal INC that is present in the memory device containing the system <b>200</b>. The counter begins incrementing in response to an address reset signal ADRST, which occurs each time the address register <b>144</b> applies an address IN_ADDR<<b>10</b>:<b>0</b>> to the block remapping system <b>200</b>. A comparator <b>216</b> first compares the address IN_ADDR<<b>10</b>:<b>0</b>> to the maximum block address MAX_ADDR<<b>10</b>:<b>0</b>> stored in the global fuse sets <b>206</b>. If IN_ADDR<<b>10</b>:<b>0</b>> is for a value greater than the value of MAX_ADDR<<b>10</b>:<b>0</b>>, the comparator <b>216</b> outputs a RESET signal in the memory device containing the system <b>200</b> to abort the operation for which IN_ADDR<<b>10</b>:<b>0</b>> was provided. If IN_ADDR<<b>10</b>:<b>0</b>> is for a value less than or equal to the value of MAX_ADDR<<b>10</b>:<b>0</b>>, the comparator <b>216</b> applies the address IN_ADDR<<b>10</b>:<b>0</b>> to one input of a multiplexer <b>220</b>.

0030When the lowest bad block address value FUSE_ADDR<<b>10</b>:<b>0</b>> is output from the block redundancy fuse sets <b>204</b> responsive to the zero value of ACNT<<b>3</b>:<b>0</b>>, this zero value of ACNT<<b>3</b>:<b>0</b>> is detected by a comparator <b>224</b>, which controls the operation of the multiplexer <b>220</b>. In response to the zero value of ACNT<<b>3</b>:<b>0</b>>, the comparator <b>224</b> causes the multiplexer <b>220</b> to output the IN_ADDR<<b>10</b>:<b>0</b>> received from the comparator <b>216</b> as a selected address SEL_ADDR<<b>10</b>:<b>0</b>>.

0031The SEL_ADDR<<b>10</b>:<b>0</b>> is applied to one input of an adder <b>230</b>, to a comparator <b>232</b>, and to one input of a multiplexer <b>234</b>, which receives the output of the adder <b>230</b> as its other input. The comparator <b>232</b> compares the value of SEL_ADDR<<b>10</b>:<b>0</b>> to the value of FUSE_ADDR<<b>10</b>:<b>0</b>>, which, in response to the initially generated ACNT<<b>3</b>:<b>0</b>>=0, is the value of the lowest defective block of memory cells. If the value of SEL_ADDR<<b>10</b>:<b>0</b>> is less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>, it means there are no defective blocks between block <b>0</b> and the block indicated by the currently received IN_ADDR<<b>10</b>:<b>0</b>>. In such case, no remapping is required. Therefore, the comparator <b>232</b> outputs a signal to a comparator <b>236</b>, which determines if the ENABLE bit from the block redundancy fuse set <b>204</b> is true. If so, the comparator <b>236</b> outputs a control signal to the multiplexer <b>234</b> that causes it to pass SEL_ADDR<<b>10</b>:<b>0</b>> to the input of an output address register <b>240</b>. The output address register <b>240</b> then outputs SEL_ADDR<<b>10</b>:<b>0</b>> as an output address OUT_ADDR<<b>10</b>:<b>0</b>>, which is applied to the row decoder <b>162</b> (<figref idref="DRAWINGS">FIG. 1</figref>). Therefore, as long as there were no bad blocks between block <b>0</b> and the block corresponding to IN_ADDR<<b>10</b>:<b>0</b>>, IN_ADDR<<b>10</b>:<b>0</b>> is used as OUT_ADDR<<b>10</b>:<b>0</b>>.

0032When the next IN_ADDR<<b>10</b>:<b>0</b>> is received, the above-described process is repeated. Let us assume in this case that there is at least one bad block between block <b>0</b> and the block corresponding to IN_ADDR<<b>10</b>:<b>0</b>>. The comparator <b>232</b> will detect such case since the value of SEL_ADDR<<b>10</b>:<b>0</b>> will be less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>. The comparator <b>232</b> will therefore cause the multiplexer <b>234</b> to couple the output of the adder <b>230</b> to the output address register <b>240</b>. However, the system must determine how many bad blocks there are between block <b>0</b> and the block corresponding to IN_ADDR<<b>10</b>:<b>0</b>>. For this reason, a decoder <b>246</b> provides a BLOCK_NUM indication corresponding to the number of bad blocks starting at the block address corresponding to the lowest bad block address FUSE_ADDR<<b>10</b>:<b>0</b>> since acnt<<b>3</b>:<b>0</b>>=0 is initially used to access the block redundancy fuse sets <b>204</b>. The decoder <b>246</b> is able to determine the number of bad blocks based upon the BLOCK_SIZE indication from the fuse sets <b>204</b> and the MULTIPLIER value from the global fuse sets <b>206</b>.

0033The manner in which BLOCK_NUM is determined based upon the BLOCK_SIZE and MULTIPLIER is shown in <figref idref="DRAWINGS">FIG. 4</figref>. For example, if the MULTIPLIER is “000,” the block size is 1, 2, 4, and 8 for an increasing series of two binary numbers. However, if the MULTIPLIER is “011,” then the block sizes corresponding to “00” and “01” are multiplied by 2, and the block sizes corresponding to “10” and “11” are multiplied by 4.

0034Once the decoder <b>246</b> has determined the number of bad blocks between block <b>0</b> and the block corresponding to IN_ADDR<<b>10</b>:<b>0</b>>, the adder outputs a value of TMP_ADDR<<b>10</b>:<b>0</b>> that has a value equal to the sum of the value of IN_ADDR<<b>10</b>:<b>0</b>> and the value corresponding to BLOCK_SIZE. This sum TMP_ADDR<<b>10</b>:<b>0</b>> corresponds to the physical address of potentially the good block of memory cells that should be accessed by IN_ADDR<<b>10</b>:<b>0</b>> since TMP_ADDR<<b>10</b>:<b>0</b>> is offset from IN_ADDR<<b>10</b>:<b>0</b>> by the number of bad blocks indicated by the BLOCK_NUM value. For example, if IN_ADDR<<b>10</b>:<b>0</b>> has a value of 80, FUSE_ADDR<<b>10</b>:<b>0</b>> has a value of 35, and BLOCK_NUM is equal to 4, the physical address of the block that should be accessed is 84, assuming there were no bad blocks between block <b>39</b> and block <b>84</b>. The next good block following the first block, i.e., block <b>39</b>, should not be used because that block would be accessed by an IN_ADDR<<b>10</b>:<b>0</b>> with a value of 35.

0035As mentioned above, there may be one or more additional contiguous bad blocks between the lowest non-defective block identified using the first value of FUSE_ADDR<<b>10</b>:<b>0</b>> and the initially remapped block corresponding to IN_ADDR<<b>10</b>:<b>0</b>> (in the above example, between block <b>39</b> and block <b>84</b>. For this reason, the counter <b>212</b> is incremented on the next cycle of INC, and the above-described process is repeated. Each time the comparator <b>232</b> compares the value of IN_ADDR<<b>10</b>:<b>0</b>> to the next value of FUSE_ADDR<<b>10</b>:<b>0</b>>. If the value of IN_ADDR<<b>10</b>:<b>0</b>> is greater than or equal to the next value of FUSE_ADDR<<b>10</b>:<b>0</b>>, the value of TEMP_ADDR<<b>10</b>:<b>0</b>> is incremented with a value corresponding to the size of a defective block, as described above. Eventually, as long as there are not an excessive number of bad blocks, the comparator <b>232</b> will determine that IN_ADDR<<b>10</b>:<b>0</b>> is less than the value of the current FUSE_ADDR<<b>10</b>:<b>0</b>>. In such case, the process terminates, and the current value of TMP_ADDR<<b>10</b>:<b>0</b>> stored in the output address register <b>240</b> is used by the row decoder <b>162</b> (<figref idref="DRAWINGS">FIG. 1</figref>) as OUT_ADDR<<b>10</b>:<b>0</b>>>.

0036Some specific examples showing the operation of the block remapping system <b>200</b> in a flash memory device having <b>10</b> bad blocks is shown in <figref idref="DRAWINGS">FIG. 5</figref>. The left hand column of <figref idref="DRAWINGS">FIG. 5</figref> shows the user addresses corresponding to IN_ADDR<<b>10</b>:<b>0</b>>, the next column shows the addresses of the bad blocks and the logical addresses to which the user addresses must be remapped, the next column shows the remapped physical addresses corresponding to the user addresses, and the column on the right shows the information stored in the block redundancy fuse sets <b>204</b> and the multiplier stored in the global fuse sets <b>206</b>, which is a multiplier of 1.

0037In the first example, IN_ADDR<<b>10</b>:<b>0</b>> corresponds to block <b>2</b>, and the FUSE_ADDR<<b>10</b>:<b>0</b>> for the first bad block corresponds to block <b>1</b>. Therefore, the comparator <b>232</b> determines that the value of IN_ADDR<<b>10</b>:<b>0</b>> is not less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>, which is indicative of one or more bad blocks between block <b>0</b> and block <b>2</b>. The block size (“00”) for the bad block starting at FUSE_ADDR<<b>10</b>:<b>0</b>> is then used by the decoder <b>246</b> to produce a value of BLOCK_NUM equal to 1. The adder <b>230</b> therefore adds the block size of 1 to the value of 2 for IN_ADDR<<b>10</b>:<b>0</b>> to obtain a TMP_ADDR<<b>10</b>:<b>0</b>> of 3. Since the value of IN_ADDR<<b>10</b>:<b>0</b>> is not less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>, the comparator <b>232</b> causes the multiplexer <b>234</b> to output the TMP_ADDR<<b>10</b>:<b>0</b>> to the data input of the output address register <b>240</b>.

0038The next cycle of INC latches the TMP_ADDR<<b>10</b>:<b>0</b>> of 3 to the output of the output address register <b>240</b>, which is fed back to the multiplexer <b>220</b>. The next cycle of INC makes ACNT no longer equal to 0, so the multiplexer <b>220</b> makes the output SEL_ADDR<<b>10</b>:<b>0</b>> equal to the value (3) of TMP_ADDR<<b>10</b>:<b>0</b>>. The next cycle of INC also increments the counter <b>212</b> to the FUSE_ADDR<<b>10</b>:<b>0</b>> value 4 of FUSE_ADDR<<b>10</b>:<b>0</b>> is compared to the SEL_ADDR<<b>10</b>:<b>0</b>> value of 3 by the comparator <b>232</b>. Since the value (3) of SEL_ADDR<<b>10</b>:<b>0</b>> is less than the value (4) of FUSE_ADDR<<b>10</b>:<b>0</b>>, the comparator <b>232</b> causes the multiplexer <b>234</b> to output the SEL_ADDR<<b>10</b>:<b>0</b>>> value of 3 to the input of the output address register <b>240</b>. The next INC pulse latches the SEL_ADDR< > value (3) to the output of the output address register <b>240</b>. The process then continues with INC incrementing the counter <b>212</b> until the 16^thFUSE_ADDR<<b>10</b>:<b>0</b>> value is output from the block redundancy fuse sets. However, in each case, the value (3) of SEL_ADDR<<b>10</b>:<b>0</b>> will less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>, so the comparator <b>232</b> will causes the multiplexer <b>234</b> to finally output the OUT_ADDR<<b>10</b>:<b>0</b>>> value of 3. Therefore, the user address of 2 is remapped to a physical address of 3. Alternatively, the process of mapping bad blocks could end the first time that the comparator <b>232</b> detects an SEL_ADDR<<b>10</b>:<b>0</b>> that is less than the value of FUSE_ADDR<<b>10</b>:<b>0</b>>.

0039In the next example, the user address IN_ADDR<<b>10</b>:<b>0</b>> is for block <b>5</b>. After the comparison is made with the value (1) of FUSE_ADDR<<b>10</b>:<b>0</b>> for the first bad block as explained in the first example, the adder <b>230</b> will produce a value of 6 (5+1) for TMP_ADDR<<b>10</b>:<b>0</b>> since the comparator <b>224</b> will cause the multiplexer <b>220</b> to the output the IN_ADDR<<b>10</b>:<b>0</b>> of 5 to the adder <b>230</b>, and the adder <b>230</b> will add the bad block size of 1 for bad block <b>1</b>, as explained above. The next cycle of INC increments the counter <b>212</b> so that ACNT is no longer equal to 0. As a result, the comparator <b>224</b> causes the multiplexer <b>220</b> to couple OUT_ADDR<<b>10</b>:<b>0</b>> to the adder <b>230</b> and to the comparator <b>232</b>. The comparator <b>232</b> then compares this value (6) with the value 4 of the next of FUSE_ADDR<<b>10</b>:<b>0</b>>, as explained above. The comparator <b>232</b> determines that the value (6) is not less than the value (4) of FUSE_ADDR<<b>10</b>:<b>0</b>>. Therefore, the value of IN_ADDR<<b>10</b>:<b>0</b>> must be offset by the number of any additional bad blocks between block <b>1</b> and block <b>6</b> to obtain the value of OUT_ADDR<<b>10</b>:<b>0</b>>. The adder <b>230</b> then uses the block_size “01,” which is equal to 2, to add to the current value 6 of OUT_ADDR<<b>10</b>:<b>0</b>> to produce a new value of 8 from the output address register <b>240</b>. This value (8) is fed back to the multiplexer on the next INC pulse to become the new value of SEL_ADDR<<b>10</b>:<b>0</b>>. The comparator <b>232</b> then determines that the next value of FUSE_ADDR<<b>10</b>:<b>0</b>>, which is 8, is not greater than the SEL_ADDR<<b>10</b>:<b>0</b>> value of 8. Therefore, the bad blocks starting at block <b>8</b> must be added to SEL_ADDR<<b>10</b>:<b>0</b>> value of 8. The decoder <b>246</b> provides a block size value BLOCK_NUM of “10,” which the adder <b>230</b> sums with the SEL_ADDR<<b>10</b>:<b>0</b>> value of 8 to obtain a new TMP_ADDR<<b>10</b>:<b>0</b>> of 12. On the next INC pulse, the TMP_ADDR<<b>10</b>:<b>0</b>> value of 12 is fed back through the multiplexer to become the next SEL_ADDR<<b>10</b>:<b>0</b>> value. The next INC pulse also increments the counter <b>212</b> so that the block redundancy fuse sets <b>204</b> outputs the fourth FUSE_ADDR<<b>10</b>:<b>0</b>> value of 15. This value (15) is compared to the new value (12) of SEL_ADDR<<b>10</b>:<b>0</b>> by the comparator. Since FUSE_ADDR<<b>10</b>:<b>0</b>> is now greater than SEL_ADDR<<b>10</b>:<b>0</b>>, the value (12) of SEL_ADDR<<b>10</b>:<b>0</b>> continues to be used as OUT_ADDR<<b>10</b>:<b>0</b>> for the fourth and all remaining values of FUSE_ADDR<<b>10</b>:<b>0</b>>. Thus, the input block address IN_ADDR<<b>10</b>:<b>0</b>> of 5 is mapped to block <b>12</b>.

0040In the same manner as explained above, the next user block address IN_ADDR<<b>10</b>:<b>0</b>> of 9 is mapped to block <b>20</b>, and the user block address IN_ADDR<<b>10</b>:<b>0</b>> of 16 is mapped to block <b>27</b>. In each case, the block remapping system <b>200</b> provides a remapped output address that is obtained by, in effect, adding to the received user block address IN_ADDR<<b>10</b>:<b>0</b>> any addresses corresponding to the sizes of any and all non-functional blocks of memory cells having respective addresses that are lower than or equal to the final output address. Thus, for example, the IN_ADDR<<b>10</b>:<b>0</b>> of 9 is added to the 11 bad blocks between block <b>0</b> and block <b>20</b> to provide a remapped output address of <b>20</b>. Conversely, the number of bad blocks is equal to the final output address less the value of IN_ADDR<<b>10</b>:<b>0</b>>.

0041<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of a processor-based system <b>500</b> using the flash memory device of <figref idref="DRAWINGS">FIG. 1</figref> or a non-volatile memory device according to another example of the invention. The processor-based system <b>500</b> includes processor circuitry <b>502</b> having volatile memory <b>510</b>. The processor circuitry <b>502</b> is coupled through address, data, and control buses to the volatile memory <b>510</b> to provide for writing data to and reading data from the volatile memory <b>510</b>. The processor circuitry <b>502</b> includes circuitry for performing various processing functions, such as executing specific software to perform specific calculations or tasks. The processor-based system <b>500</b> also includes one or more input devices <b>504</b> coupled to the processor circuitry <b>502</b> to allow an operator to interface with the processor-based system <b>500</b>. Examples of input devices <b>504</b> include keypads, touch screens, and scroll wheels. The processor-based system <b>500</b> also includes one or more output devices <b>506</b> coupled to the processor circuitry <b>502</b> to provide output information to the operator. In one embodiment, the output device <b>506</b> is a visual display providing visual information to the operator. Data storage <b>508</b> is also coupled to the processor circuitry <b>502</b> to store data that is to be retained even when power is not supplied to the processor-based system <b>500</b> or to the data storage <b>508</b>. The NAND flash memory <b>100</b>, or another embodiment of a NAND flash memory according to the present invention, can be used for the data storage <b>508</b>.

0042<figref idref="DRAWINGS">FIG. 7</figref> is a flow chart of a method <b>700</b> of addressing a memory according to an embodiment of the invention. At step <b>705</b>, an input address for access to the memory may be received. At step <b>710</b>, a number of non-functional memory blocks between an initial address of the memory and the input address ma be determined. At step <b>715</b>, the input address may be incremented by the number of non-functional memory blocks to yield an output address. At step <b>720</b>, the memory may be accessed using the output address.

0043<figref idref="DRAWINGS">FIG. 8</figref> is a flow chart of a method <b>800</b> of replacing bad memory blocks of a memory according to an embodiment of the invention. At step <b>805</b> addresses for the bad memo blocks in an array may be mapped to next available good memory blocks in the array. At step <b>810</b>, the addresses and respective sizes of the bad memory blocks in the array may be stored, the stored addresses and respective sizes of the bad memory blocks used in calculating remapped block, addresses for the next available good memory blocks in the array.

0044From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.