Arbitration device, arbitration system, arbitration method, semiconductor integrated circuit, and image processing device

TECHNICAL FIELD

The present invention relates to arbitration devices that arbitrate resource use requests from a plurality of masters.

BACKGROUND ART

In some systems, a plurality of devices such as a processor, decoder, etc. (hereinafter referred to as “masters”) are connected by a bus to a memory so that the masters share the memory.

In such a system, an arbitration device is provided to address the issue of memory contention among memory use requests from the masters. The arbitration device selects one of the contending memory use requests and outputs it as the memory use request having the highest priority.

Based, for example, on previously determined information that indicates a priority ranking of memory use requests, the arbitration device selects and outputs the contending memory use request having the highest priority.

In systems where a plurality of masters use the memory, only the master that issued the memory use request having the highest priority output by the arbitration device is permitted to use the memory via the bus.

Patent Literature 1, for example, discloses technology for a plurality of masters to share a memory.

In systems where a plurality of masters share the memory, arbitration devices may be structured hierarchically out of consideration for timing or the length of physical wiring in cases such as when the number of masters is large, or when the masters are physically separate from one another.

Hierarchically structured arbitration devices are structured with an arbitration device at each level in the hierarchy to arbitrate memory use requests at that level. These arbitration devices are connected to each other in a daisy-chain or tournament style.

The arbitration device at a lower level in the hierarchy receives memory use requests from masters belonging to that level, selects the memory use request having the highest priority, and outputs the selected memory use request to the arbitration device that is one level higher.

The arbitration device that is one level higher in the hierarchy receives memory use requests from masters belonging to that level and from the arbitration device at the lower level, selects the memory use request having the highest priority, and outputs the selected memory use request to the arbitration device that is yet one level higher.

In this way, starting at the lowest level of the hierarchy, each arbitration device in the hierarchy selects the memory use request having the highest priority among the level of the arbitration device and lower levels and outputs the memory use request to the arbitration device that is the next level up in the hierarchy. Ultimately, the memory use request having the highest priority as output by the arbitration device at the highest level in the hierarchy becomes the memory use request having the highest priority in the system.

However, since the arbitration devices in the hierarchy arbitrate in order from the lowest level, it is difficult to physically dispose the circuit so as to shorten processing time between the start of arbitration and the output of the memory use request having the highest priority.

Typically, when a memory controller or the like receives the memory use request having the highest priority output from the arbitration device, the memory controller allows the master that issued the memory use request to use the memory.

The interval from the arbitration device outputting the memory use request having the highest priority and the master receiving a response signal from the memory controller for the memory use request until the next memory use request having the highest priority occurs is hereinafter referred to as “latency”. When the period of memory used by the master receiving the response signal is shorter than the latency, the memory is not used during the time difference between the latency and the period of memory use, a phenomenon hereinafter referred to as the “bubble phenomenon”.

In a memory use system employing hierarchical arbitration devices, it is difficult to reduce the latency of the hierarchical arbitration devices, and therefore the problem of the bubble phenomenon may occur.

Patent Literature 2 discloses an example of technology to reduce occurrence of the bubble phenomenon in a memory use system employing hierarchical arbitration devices.

This technology for hierarchical arbitration devices provides, between a lower level and an upper level, a cache memory for temporarily storing data in the main memory used in response to a memory use request. If the memory use request having the highest priority in the lower level hits the cache memory, the cache memory is used instead of the main memory.

With this technology, if a memory use request at a lower level hits the cache memory, the cache memory is used without waiting for the results of arbitration at higher levels. Accordingly, when the memory use request hits the cache memory, the memory use system employing hierarchical arbitration devices performs as though the above latency had become shorter.

CITATION LIST

Patent Literature

<ul><li id="ul0001-0001" num="0019">Patent Literature 1: Japanese Patent Application Publication No. 2004-288021</li><li id="ul0001-0002" num="0020">Patent Literature 2: Japanese Patent Application Publication No. 9-128346</li></ul>

SUMMARY OF INVENTION

Technical Problem

In the above conventional technology, however, a memory use request only hits the cache memory if the master repeatedly issues identical memory use requests. This causes a problem in that in a system where a master does not repeatedly issue identical memory use requests, the effect of shortened latency is not achieved by using a cache.

In light of the above problem, it is an object of the present invention to provide an arbitration system that reduces occurrence of the bubble phenomenon even in a system in which a master does not repeatedly issue identical memory use requests, as well as to provide an arbitration device useful in the arbitration system.

Solution to Problem

To solve the above problem, an arbitration system according to the present invention comprises one or more arbitration devices that each include a first receiving unit operable to receive one or more resource use request commands from a plurality of devices; an arbitration unit operable, when the first receiving unit receives a set of two or more resource use request commands during each of a plurality of predetermined cycles, to evaluate a priority of each resource use request command in the set and to select from the set a first resource use request command having a highest priority and a second resource use request command having a second highest priority; an output unit operable to output the first resource use request command and the second resource use request command selected by the arbitration unit to an external destination during each of the predetermined cycles; and a second receiving unit operable to receive a resource use response signal that includes information identifying a resource use request command, wherein upon receipt of the resource use response signal by the second receiving unit, the arbitration unit is operable to remove the resource use request command identified by the resource use response signal from the set from which the first resource use request command and the second resource use request command are selected. The arbitration system according to the present invention also comprises a third receiving unit operable to receive the first resource use request command and the second resource use request command output by the first arbitration device and a resource use request command from one or more devices; a final arbitration unit operable, for a set of resource use request commands received by the third receiving unit during each of the predetermined cycles, to evaluate a priority of each resource use request command in the set and to select from the set a top priority resource use request command having a highest priority; a final output unit operable to output, during each of the predetermined cycles, the top priority resource use request command selected by the final arbitration unit; a resource use request command receiving unit operable to receive the top priority resource use request command output by the final output unit; a fourth receiving unit operable to receive a resource use response signal; and a resource use response signal output unit operable, when the resource use request command receiving unit receives the top priority resource use request command, to output a resource use response signal including information identifying the top priority resource use request command to the second receiving unit and the fourth receiving unit, wherein upon receipt of the resource use response signal by the fourth receiving unit, the final arbitration unit is operable to remove the resource use request command identified by the resource use response signal from the set from which the top priority resource use request command is selected.

Advantageous Effects of Invention

In the arbitration system according to the present invention with the above structure, the first arbitration device outputs the resource use request command having the highest priority and the second resource use request command having the second highest priority.

Accordingly, occurrence of the bubble phenomenon is reduced during arbitration by the first arbitration device even when latency of arbitration performed by the first arbitration device is longer than the period of resource use by the top priority resource use request command. This is because after the resource use request command receiving unit receives the resource use request command having the highest priority as the top priority resource use request command, the final arbitration unit selects the resource use request command having the second highest priority, as was already output by the first arbitration device, as the new top priority resource use request command once the fourth receiving unit receives the resource use response signal.

In the above arbitration system, each resource use request command received by each first receiving unit may include information identifying a period of resource use, and the output unit in each of the one or more arbitration devices may output the second resource use request command during a same cycle as the first resource use request command only when the period of resource use of the first resource use request command is equal to or less than a predetermined period.

The bubble phenomenon only occurs when the period of resource use by a resource use request command is shorter than the latency of arbitration performed by the arbitration system.

Accordingly, after an arbitration device outputs the resource use request command having the highest priority, if the period of resource use by the request command having the highest priority is longer than the latency of arbitration that is initiated by the arbitration device, the resource use request command having the second highest priority output by the arbitration device is not effectively used.

In the arbitration system with the above structure, unnecessary power consumption is avoided, since when the predetermined time for each arbitration device is shorter than the latency of arbitration initiated by the arbitration device, each arbitration device does not output a resource use request command having the second highest priority, as such a command would not be used effectively.

In the above arbitration system, each resource use request command received by each first receiving unit may include information identifying a period of resource use, and the output unit in each of the one or more arbitration devices may output the second resource use request command during a same cycle as the first resource use request command only when a predetermined relationship is satisfied between (i) the period of resource use of the first resource use request command and (ii) a time lag until the first resource use request command arrives at the resource use request command receiving unit.

The bubble phenomenon only occurs when the period of resource use by a resource use request command is shorter than the latency of arbitration performed by the arbitration system.

Accordingly, after an arbitration device outputs the resource use request command having the highest priority, if the period of resource use by the request command having the highest priority is longer than the latency of arbitration that is initiated by the arbitration device, the resource use request command having the second highest priority output by the arbitration device is not effectively used.

In the arbitration system with the above structure, unnecessary power consumption is avoided, since when the predetermined relationship for each arbitration device is such that a period of resource use by the first resource use command is longer than the latency of arbitration initiated by the arbitration device, each arbitration device does not output a resource use request command having the second highest priority, as such a command would not be used effectively.

In the above arbitration system, each resource use request command may be for memory, and the resource use response signal output unit may output a signal to the memory to initiate output of data from an identified region of the memory when the top priority resource use request command, received by the resource use request command receiving unit, indicates reading from the identified region.

In the arbitration system with this structure, during reading of data from memory, occurrence of the bubble phenomenon is reduced.

In the above arbitration system, each resource use request command may be for memory, and the resource use response signal output unit may output a signal to the memory to initiate writing of data to an identified region of the memory when the top priority resource use request command, received by the resource use request command receiving unit, indicates writing to the identified region.

In the arbitration system with this structure, during writing of data to memory, occurrence of the bubble phenomenon is reduced.

To solve the above problem, an arbitration device according to the present invention comprises: a first receiving unit operable to receive one or more resource use request commands from a plurality of devices; an arbitration unit operable, when the first receiving unit receives a set of two or more resource use request commands during each of a plurality of predetermined cycles, to evaluate a priority of each resource use request command in the set and to select from the set a first resource use request command having a highest priority and a second resource use request command having a second highest priority; an output unit operable to output the first resource use request command and the second resource use request command selected by the arbitration unit to an external destination during each of the predetermined cycles; and a second receiving unit operable to receive a resource use response signal that includes information identifying a resource use request command, wherein upon receipt of the resource use response signal by the second receiving unit, the arbitration unit is operable to remove the resource use request command identified by the resource use response signal from the set from which the first resource use request command and the second resource use request command are selected.

The arbitration device according to the present invention with the above structure outputs the resource use request command having the highest priority and the second resource use request command having the second highest priority.

The above arbitration device is used at any level other than the top hierarchical level of an arbitration system in which a plurality of arbitration devices are connected in series. When the resource use request command receiving unit receives, as the top priority resource use request command, the resource use request command having the highest priority output by the above arbitration device, the arbitration device that is one level higher in the hierarchy and is connected to the above arbitration device selects the resource use request command having the second highest priority, as was already output by the above arbitration device, as the new top priority resource use request command.

Accordingly, even if the period of memory use by the resource use request command having the highest priority as output by the above arbitration device is shorter than the latency of arbitration by the first arbitration device, occurrence of the bubble phenomenon is reduced.

Therefore, this arbitration device is useful in an arbitration system that reduces occurrence of the bubble phenomenon.

In the above arbitration device, each resource use request command received by the first receiving unit may include information identifying a period of resource use, and the output unit may output the second resource use request command during a same cycle as the first resource use request command only when the period of resource use of the first resource use request command is equal to or less than a predetermined period.

The bubble phenomenon only occurs when the period of resource use by a resource use request command is shorter than the latency of arbitration performed by the arbitration device.

Accordingly, if the period of resource use by the request command with the highest priority is longer than the latency of arbitration performed by the arbitration device, the resource use request command having the second highest priority is not effectively used.

In the arbitration device with the above structure, unnecessary power consumption is avoided, since when a predetermined time is shorter than latency of arbitration, the arbitration device does not output a resource use request command having the second highest priority, as such a command would not be used effectively.

BRIEF DESCRIPTION OF DRAWINGS

<figref idrefs="DRAWINGS">FIG. 1</figref> is a functional block diagram of a system LSI <b>100</b>.

<figref idrefs="DRAWINGS">FIG. 2A</figref> is a data structure diagram of a memory use request command, and

<figref idrefs="DRAWINGS">FIG. 2B</figref> is a data structure diagram of an acknowledge signal.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a configuration diagram of a bus interface unit <b>150</b>.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a configuration diagram of an arbiter <b>141</b>.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram showing masters and a priority ranking of memory use request commands issued by the masters.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a configuration diagram of an arbiter <b>140</b>.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a flowchart showing arbitration by hierarchical level.

<figref idrefs="DRAWINGS">FIG. 8</figref> is a flowchart showing final arbitration.

<figref idrefs="DRAWINGS">FIG. 9</figref> is a timing chart of internal signals in the system LSI <b>100</b>.

<figref idrefs="DRAWINGS">FIG. 10</figref> is a timing chart of internal signals in the system LSI <b>100</b> when the functionality of each arbitration device is restricted.

<figref idrefs="DRAWINGS">FIG. 11</figref> is a configuration diagram of an arbitration device <b>1131</b>.

<figref idrefs="DRAWINGS">FIG. 12</figref> is part 1 of a flowchart showing first modified arbitration by hierarchical level.

<figref idrefs="DRAWINGS">FIG. 13</figref> is part 2 of the flowchart showing first modified arbitration by hierarchical level.

<figref idrefs="DRAWINGS">FIG. 14</figref> is a timing chart of internal signals in the first modified system LSI <b>100</b>.

<figref idrefs="DRAWINGS">FIG. 15</figref> is a data structure diagram of a memory use request command.

<figref idrefs="DRAWINGS">FIG. 16</figref> is a configuration diagram of an arbitration device <b>1631</b>.

<figref idrefs="DRAWINGS">FIG. 17</figref> is part 1 of a flowchart showing second modified arbitration by hierarchical level.

<figref idrefs="DRAWINGS">FIG. 18</figref> is part 2 of the flowchart showing second modified arbitration by hierarchical level.

<figref idrefs="DRAWINGS">FIG. 19</figref> is a configuration diagram of a Blu-ray recorder system <b>1900</b>.

DESCRIPTION OF EMBODIMENTS

Embodiment 1

&lt;Outline&gt;

The following describes, as an embodiment of an arbitration device according to the present invention, a system LSI provided with a plurality of masters that use a shared memory and hierarchical arbitration devices that arbitrate memory use requests from the masters.

The hierarchical arbitration devices provided in the system LSI are composed of a plurality of arbitration devices, connected to each other in a hierarchical structure, that operate in synchronization with a shared clock signal.

Each arbitration device receives memory use requests from masters belonging to the level of the arbitration device and memory use requests from the arbitration device that is one level lower, selects the memory use request having the highest priority and the memory use request having the second highest priority, and outputs these two memory use requests to the arbitration device that is one level higher.

The arbitration device at the highest level of the hierarchy selects the memory use request having the highest priority and outputs this memory request to the memory control unit as a top priority memory use request.

After outputting the memory use request having the highest priority to the memory control unit as the top priority memory use request, when the arbitration device at the highest level of the hierarchy receives an acknowledge signal from the memory control unit indicating receipt of the memory use request, then the arbitration device selects the memory use request having the second highest priority and outputs this memory request to the memory control unit as a next top priority memory use request.

The following describes the configuration of a system LSI according to Embodiment 1 with reference to the drawings.

&lt;Configuration&gt;

&lt;Overall Configuration&gt;

<figref idrefs="DRAWINGS">FIG. 1</figref> is a block diagram showing the configuration of the system LSI <b>100</b>.

The system LSI <b>100</b> is provided with a processor <b>110</b>, video output engine <b>111</b>, encryption engine <b>112</b>, stream engine <b>113</b>, decoder A <b>114</b>, decoder B <b>115</b>, encoder <b>116</b>, image enhancement engine <b>117</b>, hierarchical arbitration device <b>105</b>, memory control unit memory control unit <b>118</b>, main bus <b>120</b>, etc. The system LSI <b>100</b> is connected to an external memory <b>101</b>.

The processor <b>110</b> is connected to the hierarchical arbitration device <b>105</b> and, by executing programs stored in the external memory <b>101</b>, achieves control of the video output engine <b>111</b>, encryption engine <b>112</b>, stream engine <b>113</b>, decoder A <b>114</b>, decoder B <b>115</b>, encoder <b>116</b>, image enhancement engine <b>117</b>, hierarchical arbitration device <b>105</b>, memory control unit <b>118</b>, etc.

The video output engine <b>111</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to superimpose subtitles, graphics, etc. on movie data or still image data stored in the external memory <b>101</b>.

The encryption engine <b>112</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to decrypt encrypted data stored in the external memory <b>101</b>.

The stream engine <b>113</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to perform streaming of stream data received via a tuner (streaming refers to processing of stream data, for example processing to separate audio data and video data from stream data in which audio data and video data converge, thus generating audio stream data and video stream data, which are written in the external memory <b>101</b>).

The decoder A <b>114</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to decode data in Moving Picture Experts Group (MPEG)-2 format stored in the external memory <b>101</b>.

The decoder B <b>115</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to decode data in MPEG-4 Advanced Video Coding (AVC) format stored in the external memory <b>101</b>.

The encoder <b>116</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to encode movie data in MPEG-4 AVC format stored in the external memory <b>101</b>.

The image enhancement engine <b>117</b> is connected to the hierarchical arbitration device <b>105</b> and is controlled by the processor <b>110</b> to perform image enhancement processing on movie data or still image data stored in the external memory <b>101</b> (image enhancement processing is processing to generate enhanced data from movie or still image data, for example by generating data that sharpens the outline of objects).

The processor <b>110</b>, video output engine <b>111</b>, encryption engine <b>112</b>, stream engine <b>113</b>, decoder A <b>114</b>, decoder B <b>115</b>, encoder <b>116</b>, and image enhancement engine <b>117</b> are masters sharing the external memory <b>101</b> as a slave.

When each master is to use the external memory <b>101</b>, i.e. the slave, the master does not immediately use the external memory <b>101</b>, but rather outputs a memory use request command to the hierarchical arbitration device <b>105</b>.

<figref idrefs="DRAWINGS">FIG. 2A</figref> is a data structure diagram of a memory use request command output by the masters.

As shown in <figref idrefs="DRAWINGS">FIG. 2A</figref>, the memory use request command includes a starting address <b>201</b>, master identifying information <b>202</b>, and command type information <b>203</b>.

The starting address <b>201</b> is 32 bits of data indicating the starting address of the memory region to be used.

The master identifying information <b>202</b> is four bits of data for identifying the master that output the memory use request command. For example, “0000” indicates the processor <b>110</b>, “0001” indicates the video output engine <b>111</b>, “0010” indicates the encryption engine <b>112</b>, “0011” indicates the stream engine <b>113</b>, “0100” indicates the decoder A <b>114</b>, “0101” indicates the decoder B <b>115</b>, “0110” indicates the encoder <b>116</b>, and “0111” indicates the image enhancement engine <b>117</b>.

The command type information <b>203</b> is one bit of data that is set to “0” when the use of the memory is to write to a memory region and to “1” when the use of the memory is to read from a memory region.

Note that the size of the data that each master either writes to or reads from a memory region is a fixed length of 64 bytes.

The following is a continued explanation of the configuration of the system LSI with reference again to <figref idrefs="DRAWINGS">FIG. 1</figref>.

The main bus <b>120</b> is a bidirectional bus connected to the hierarchical arbitration device <b>105</b> and the memory control unit <b>118</b>. The bus width is 32 bytes. Accordingly, the main bus <b>120</b> transmits 64 bytes of data in two cycles.

The memory control unit <b>118</b> is connected to the hierarchical arbitration device <b>105</b> and the external memory <b>101</b> and has the following two functions.

Function 1: the memory control unit <b>118</b> receives a memory use request command that is output from the hierarchical arbitration device <b>105</b> and outputs an acknowledge signal to the hierarchical arbitration device <b>105</b>.

Function 2: if the main bus <b>120</b> and external memory <b>101</b> are not in use at the time of receiving a memory use request command output from the hierarchical arbitration device <b>105</b>, the memory control unit <b>118</b> reads data from the external memory <b>101</b> or writes data to the external memory <b>101</b> in accordance with the received memory use request command.

<figref idrefs="DRAWINGS">FIG. 2B</figref> is a data structure diagram of an acknowledge signal output by the memory control unit <b>118</b>.

As shown in <figref idrefs="DRAWINGS">FIG. 2B</figref>, the acknowledge signal includes acknowledge information <b>211</b> and master identifying information <b>202</b>.

The acknowledge information <b>211</b> is a one-bit signal indicating whether the acknowledge signal is valid. The acknowledge information <b>211</b> is set to “1” if the acknowledge signal is valid and to “0” if the acknowledge signal is invalid.

The master identifying information <b>212</b> is information for identifying the master that is the source of the acknowledge signal and is the same as the master identifying information <b>202</b> included in the memory use request command received before the memory control unit <b>118</b> outputs the acknowledge signal.

The following is a continued explanation of the configuration of the system LSI with reference again to <figref idrefs="DRAWINGS">FIG. 1</figref>.

The hierarchical arbitration device <b>105</b> is connected to the processor <b>110</b>, video output engine <b>111</b>, encryption engine <b>112</b>, stream engine <b>113</b>, decoder A <b>114</b>, decoder B <b>115</b>, encoder <b>116</b>, image enhancement engine <b>117</b>, main bus <b>120</b>, and memory control unit <b>118</b> and uses each constituent element described below to achieve the following two functions.

Function 1: the hierarchical arbitration device <b>105</b> receives and stores memory use request commands from the masters, selects the memory use request command having the highest priority from among the stored memory use request commands, and outputs the memory use request command having the highest priority to the memory control unit <b>118</b>.

Function 2: the hierarchical arbitration device <b>105</b> arbitrates the exchange of data between each master and the main bus <b>120</b>.

The hierarchical arbitration device <b>105</b> includes a first arbitration device <b>130</b>, second arbitration device <b>131</b>A, third arbitration device <b>131</b>B, fourth arbitration device <b>131</b>C, first arbitration candidate signal line <b>161</b>A, first arbitration candidate signal line <b>161</b>B, first arbitration candidate signal line <b>161</b>C, second arbitration candidate signal line <b>162</b>A, second arbitration candidate signal line <b>162</b>B, second arbitration candidate signal line <b>162</b>C, etc.

The first arbitration device <b>130</b> is connected to the processor <b>110</b>, video output engine <b>111</b>, memory control unit <b>118</b>, and main bus <b>120</b>, is further connected to the second arbitration device <b>131</b>A via the first arbitration candidate signal line <b>161</b>A and second arbitration candidate signal line <b>162</b>A, and includes the following four functions.

Function 1: the first arbitration device <b>130</b> receives and stores memory use request commands from the processor <b>110</b> and video output engine <b>111</b>.

Function 2: The first arbitration device <b>130</b> selects a memory use request command having the highest priority and a memory use request command having the second highest priority from among the stored memory use request commands, the memory use request command input from the second arbitration device <b>131</b>A via the first arbitration candidate signal line <b>161</b>A, and the memory use request command input from the second arbitration device <b>131</b>A via the second arbitration candidate signal line <b>162</b>A. The first arbitration device <b>130</b> also sets the memory use request command having the highest priority as a top priority memory use request command and outputs the top priority memory use request command to the memory control unit <b>118</b> in synchronization with the clock signal.

Function 3: After outputting the memory use request command having the highest priority to the memory control unit <b>118</b> as the top priority memory use request, when receiving an acknowledge signal from the memory control unit <b>118</b> indicating that the memory use request was received, then if the first arbitration device <b>130</b> was storing a memory use request corresponding to the acknowledge signal, the first arbitration device <b>130</b> deletes the memory use request. The first arbitration device <b>130</b> then outputs, as the top priority memory use request, the memory use request command having the second highest priority that was selected during the clock cycle in which the acknowledge signal was received. The output occurs during the next clock cycle.

Function 4: The first arbitration device <b>130</b> functions as a bus interface between the processor <b>110</b> and main bus <b>120</b>, and as a bus interface between the video output engine <b>111</b> and main bus <b>120</b>.

The second arbitration device <b>131</b>A is connected to the encryption engine <b>112</b>, stream engine <b>113</b>, memory control unit <b>118</b>, main bus <b>120</b>, etc., and is further connected to the first arbitration device <b>130</b> via the first arbitration candidate signal line <b>161</b>A and second arbitration candidate signal line <b>162</b>A, as well as to the third arbitration device <b>131</b>B via the first arbitration candidate signal line <b>161</b>B and second arbitration candidate signal line <b>162</b>B. The second arbitration device <b>131</b>A includes the following four functions.

Function 1: the second arbitration device <b>131</b>A receives and stores memory use request commands from the encryption engine <b>112</b> and stream engine <b>113</b>.

Function 2: the second arbitration device <b>131</b>A selects a memory use request command having the highest priority and a memory use request command having the second highest priority from among the stored memory use request commands, the memory use request command input from the third arbitration device <b>131</b>B via the first arbitration candidate signal line <b>161</b>B, and the memory use request command input from the third arbitration device <b>131</b>B via the second arbitration candidate signal line <b>162</b>B. The second arbitration device <b>131</b>A also outputs the memory use request command having the highest priority and memory use request command having the second highest priority to the first arbitration device <b>130</b> via the first arbitration candidate signal line <b>161</b>A and the second arbitration candidate signal line <b>162</b>A, respectively, in synchronization with the clock signal.

Function 3: After outputting the memory use request command having the highest priority to the first arbitration device <b>130</b> as the top priority memory use request, when receiving an acknowledge signal from the memory control unit <b>118</b> indicating that the memory use request was received, then if the second arbitration device <b>131</b>A was storing a memory use request corresponding to the acknowledge signal, the second arbitration device <b>131</b>A deletes the memory use request. The second arbitration device <b>131</b>A then outputs, as the memory use request command having the highest priority, the memory use request command having the second highest priority that was selected during the clock cycle in which the acknowledge signal was received. The output occurs during the next clock cycle.

Function 4: The second arbitration device <b>131</b>A functions as a bus interface between the encryption engine <b>112</b> and main bus <b>120</b>, and as a bus interface between the stream engine <b>113</b> and main bus <b>120</b>.

The third arbitration device <b>131</b>B has the same structure as the second arbitration device <b>131</b>A, is connected to the decoder A <b>114</b>, decoder B <b>115</b>, memory control unit <b>118</b>, main bus <b>120</b>, etc., and is further connected to the second arbitration device <b>131</b>A via the first arbitration candidate signal line <b>161</b>B and second arbitration candidate signal line <b>162</b>B, as well as to the fourth arbitration device <b>131</b>C via the first arbitration candidate signal line <b>161</b>C and second arbitration candidate signal line <b>162</b>C.

The fourth arbitration device <b>131</b>C has the same structure as the second arbitration device <b>131</b>A and third arbitration device <b>131</b>B and is connected to the encoder <b>116</b>, image enhancement engine <b>117</b>, memory control unit <b>118</b>, main bus <b>120</b>, etc.

Note that since no arbitration device exists at a level lower than the fourth arbitration device <b>131</b>C, no memory use requests are input from a level lower than the fourth arbitration device <b>131</b>C.

&lt;Structure of Arbitration Devices&gt;

The first arbitration device <b>130</b> includes a bus interface unit <b>150</b>A and arbiter <b>140</b>. The second arbitration device <b>131</b>A through the fourth arbitration device <b>131</b>C respectively include bus interface units <b>150</b>B-<b>150</b>D and arbiters <b>141</b>A-<b>141</b>C.

The following is a detailed description, with reference to the drawings, of the structure of the first arbitration device <b>130</b> as well as the second arbitration device <b>131</b>A through fourth arbitration device <b>131</b>C.

Note that since the second arbitration device <b>131</b>A through the fourth arbitration device <b>131</b>C have the same structure, these arbitration devices are simply referred to as arbitration device <b>131</b>, the bus interface units <b>150</b>B-<b>150</b>D are simply referred to as bus interface unit <b>150</b>, and the arbiters <b>141</b>A-<b>141</b>C are simply referred to as arbiter <b>141</b>, except for when there is a particular need for distinction.

Furthermore, the bus interface unit <b>150</b>A has the same structure as the bus interface unit <b>150</b>. Therefore, in the following description, the bus interface unit <b>150</b>A is also simply referred to as bus interface unit <b>150</b>, except for when there is a particular need for distinction.

<figref idrefs="DRAWINGS">FIG. 3</figref> is a configuration diagram of the bus interface unit <b>150</b> in the arbitration device <b>130</b> and arbitration device <b>131</b>.

As shown in <figref idrefs="DRAWINGS">FIG. 3</figref>, the bus interface unit <b>150</b> is connected to a master A <b>350</b>, a master B <b>351</b>, the processor <b>110</b>, memory control unit <b>118</b>, main bus <b>120</b>, and arbiter <b>141</b> (for example, in the case of the bus interface unit <b>150</b>B, the master A <b>350</b> is the encryption engine <b>112</b>, and the master B <b>351</b> is the stream engine <b>113</b>). The bus interface unit <b>150</b> includes a master-side command control unit <b>310</b>, memory-side command control unit <b>311</b>, master-side data control unit <b>320</b>, memory-side data control unit <b>321</b>, acknowledge control unit <b>330</b>, setting register <b>340</b>, command buffer A <b>312</b>A, command buffer B <b>312</b>B, data buffer A <b>322</b>, and data buffer B <b>323</b>.

The command buffer A <b>312</b>A and command buffer B <b>312</b>B are both connected to the master-side command control unit <b>310</b>, memory-side command control unit <b>311</b>, and acknowledge control unit <b>330</b>, and are buffers for temporarily storing memory use requests output by the master-side command control unit <b>310</b>.

The master-side command control unit <b>310</b> is connected to the master A <b>350</b>, master B <b>351</b>, command buffer A <b>312</b>A, and command buffer B <b>312</b>B. The master-side command control unit <b>310</b> includes the function of receiving a memory use request command from the master A via handshaking and writing the received memory use request command into the command buffer A <b>312</b>A, as well as the function of receiving a memory use request command from the master B via handshaking and writing the memory use request command into the command buffer B <b>312</b>B.

The memory-side command control unit <b>311</b> is connected to the command buffer A <b>312</b>A, command buffer B <b>312</b>B, and arbiter <b>141</b>, operates in synchronization with the clock signal, and includes the following two functions.

Function 1: when the clock signal rises, the memory-side command control unit <b>311</b> reads the oldest memory use request command from the command buffer A <b>312</b>A and outputs this command to the arbiter <b>141</b> as the master A first memory use request command. The memory-side command control unit <b>311</b> also reads the second oldest memory use request command and outputs this command to the arbiter <b>141</b> as the master A second memory use request command.

Function 2: when the clock signal rises, the memory-side command control unit <b>311</b> reads the oldest memory use request command from the command buffer B <b>312</b>B and outputs this command to the arbiter <b>141</b> as the master B first memory use request command. The memory-side command control unit <b>311</b> also reads the second oldest memory use request command and outputs this command to the arbiter <b>141</b> as the master B second memory use request command.

Note that in functions 1 and 2, if no corresponding memory use request command is stored in the command buffer, the memory-side command control unit <b>311</b> outputs a signal with all zeros as the memory use request command to indicate non-existence of a memory use request command.

The data buffer A <b>322</b> is a First In, First Out (FIFO) buffer temporarily storing 32-byte long data and is connected to the master-side data control unit <b>320</b> and memory-side data control unit <b>321</b>.

The data buffer B <b>323</b> is a FIFO buffer temporarily storing 32-byte long data and is connected to the master-side data control unit <b>320</b> and memory-side data control unit <b>321</b>.

The master-side data control unit <b>320</b> is connected to the master A <b>350</b>, master B <b>351</b>, data buffer A <b>322</b>, and data buffer B <b>323</b> and includes the following three functions.

Function 1: the master-side data control unit <b>320</b> receives data from the master A via handshaking and writes the received data in the data buffer A <b>322</b>.

Function 2: the master-side data control unit <b>320</b> receives data from the master B via handshaking and writes the received data in the data buffer A <b>322</b>.

Function 3: when data is stored in the data buffer B <b>323</b>, the master-side data control unit <b>320</b> transmits the data via handshaking, in order from the oldest data, to the master that is the destination of the data.

The memory-side data control unit <b>321</b> is connected to the data buffer A <b>322</b> and data buffer B <b>323</b>, operates in synchronization with the clock signal, and includes the following two functions.

Function 1: when the clock signal rises, the memory-side data control unit <b>321</b> reads the oldest data from among the data stored in the data buffer A <b>322</b> and outputs the read data to the main bus <b>120</b>.

Function 2: at the time of receiving, from the main bus <b>120</b>, data whose destination is the master A <b>350</b> or master B <b>351</b>, the memory-side data control unit <b>321</b> writes the data in the data buffer B <b>323</b> when the clock signal rises.

The acknowledge control unit <b>330</b> is connected to the command buffer A <b>312</b>A, command buffer B <b>312</b>B, master A <b>350</b>, master B <b>351</b>, and memory control unit <b>118</b> and includes the following two functions.

Function 1: at the time of receiving, from the memory control unit <b>118</b>, an acknowledge signal that includes master identifying information <b>212</b> indicating the master A <b>350</b>, the acknowledge control unit <b>330</b> transmits the acknowledge signal to the master A <b>350</b> and deletes the oldest memory use request command stored in the command buffer A <b>312</b>A.

Function 2: after receiving, from the memory control unit <b>118</b>, an acknowledge signal that includes master identifying information <b>212</b> indicating the master B <b>351</b>, the acknowledge control unit <b>330</b> transmits the acknowledge signal to the master B <b>351</b> and deletes the oldest memory use request command stored in the command buffer B <b>312</b>B.

The setting register <b>340</b> is connected to the processor <b>110</b> and is controlled by the processor <b>110</b> to set the number of memory use request commands that can be temporarily stored in the command buffer A <b>312</b>A and the command buffer B <b>312</b>B, as well as the number of pieces of data that can be temporarily stored in the data buffer A <b>322</b> and data buffer B <b>323</b>.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a configuration diagram of the arbiter <b>141</b> in the arbitration device <b>131</b>.

As shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, the arbiter <b>141</b> is connected to the bus interface unit <b>150</b> and the memory control unit <b>118</b>. The arbiter <b>141</b> is further connected to the following components, the parenthetical examples being for the case of the arbiter <b>141</b>A: the higher level arbiter (arbiter <b>140</b>) via the first arbitration candidate signal line A <b>411</b>A (first arbitration candidate signal line <b>161</b>A) and the second arbitration candidate signal line A <b>412</b>A (second arbitration candidate signal line <b>162</b>A) as well as to the lower level arbiter (arbiter <b>141</b>B) via the first arbitration candidate signal line B <b>411</b>B (first arbitration candidate signal line <b>161</b>B) and the second arbitration candidate signal line B <b>412</b>B (second arbitration candidate signal line <b>162</b>B). The arbiter <b>141</b> includes a first candidate arbiter <b>400</b>, mask unit <b>401</b>, second candidate arbiter <b>402</b>, and arbitration result output control unit <b>403</b>.

The first candidate arbiter <b>400</b> is connected to the bus interface unit <b>150</b>, mask unit <b>401</b>, arbitration result output control unit <b>403</b>, and first arbitration candidate signal line B <b>411</b>B, and receives input of a first arbitration candidate memory use request command (described below) from the first arbitration candidate signal line B <b>411</b>B, and the master A first memory use request command and the master B first memory use request command from the bus interface unit. Upon input of these three memory use request commands, the first candidate arbiter <b>400</b> selects the memory use request command having the highest priority as a first command, outputting the first command to the arbitration result output control unit <b>403</b> and mask unit <b>401</b>.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a table showing masters and a priority ranking of memory use request commands issued by the masters.

A master name <b>501</b> indicates the name of the master, and a priority <b>502</b> indicates the priority of the memory use request command issued by the master.

The first candidate arbiter <b>400</b> is previously set to select the first command in accordance with the priority ranking of the memory use request commands shown in <figref idrefs="DRAWINGS">FIG. 5</figref>.

The mask unit <b>401</b> is connected to the bus interface unit <b>150</b>, first candidate arbiter <b>400</b>, second candidate arbiter <b>402</b>, first arbitration candidate signal line B <b>411</b>B, and second arbitration candidate signal line B <b>412</b>B. The mask unit <b>401</b> receives input of six memory use request commands the first arbitration candidate memory use request command (described below) from the first arbitration candidate signal line B <b>411</b>B, second arbitration candidate memory use request command (described below) from the second arbitration candidate signal line B <b>412</b>B, and master A first memory use request command, master B first memory use request command, master A second memory use request command, and master B second memory use request command from the bus interface unit <b>150</b>. Upon receiving the memory use request command output by the first candidate arbiter <b>400</b>, the mask unit <b>401</b> outputs five memory use request commands to the second candidate arbiter <b>402</b>, namely the above six memory use commands with the exception of the memory use request command output by the first candidate arbiter <b>400</b>.

The second candidate arbiter <b>402</b> is connected to the mask unit <b>401</b>, arbitration result output control unit <b>403</b>, first arbitration candidate signal line B <b>411</b>B, and second arbitration candidate signal line B <b>412</b>B, and selects, from among the five memory use request commands output by the mask unit <b>401</b>, the memory use request command having the highest priority as a second command, outputting the second command to the arbitration result output control unit <b>403</b>.

The second candidate arbiter <b>402</b> selects the second command in accordance with the priority ranking of memory use request commands shown in <figref idrefs="DRAWINGS">FIG. 5</figref>. When selecting the second command, the second candidate arbiter <b>402</b> ensures that the master A second memory use request command output by the bus interface unit <b>150</b> has higher priority than the master B second memory use request command output by the bus interface unit <b>150</b>. The second candidate arbiter <b>402</b> also ensures that when the first arbitration candidate memory use request command (described below) output by the first arbitration candidate signal line B <b>411</b>B and the second arbitration candidate memory use request command (described below) output by the second arbitration candidate signal line B <b>412</b>B are memory use request commands output by the same master, the first arbitration candidate memory use request command has higher priority.

The arbitration result output control unit <b>403</b> is connected to the first candidate arbiter <b>400</b>, second candidate arbiter <b>402</b>, memory control unit <b>118</b>, first arbitration candidate signal line A <b>411</b>A, and second arbitration candidate signal line A <b>412</b>A, operates in synchronization with the clock signal, and includes the following two functions.

Function 1: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>403</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>403</b> outputs the first command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs the second command to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

Function 2: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>403</b> receives from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>403</b> outputs the second command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs a signal with all zeros to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a configuration diagram of the arbiter <b>140</b> in the arbitration device <b>130</b>.

The arbiter <b>140</b> differs from the arbiter <b>141</b> in that the arbitration result output control unit <b>403</b> is changed to an arbitration result output control unit <b>603</b>.

The following is a description of the difference between the arbiter <b>140</b> and the arbiter <b>141</b>, i.e. the arbitration result output control unit <b>603</b>.

The arbitration result output control unit <b>603</b> is connected to the first candidate arbiter <b>400</b>, second candidate arbiter <b>402</b>, and memory control unit <b>118</b>, operates in synchronization with the clock signal, and includes the following two functions.

Function 1: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>603</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>603</b> outputs the first command to the memory control unit <b>118</b> as the top priority memory use request command.

Function 2: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>603</b> receives from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>603</b> outputs the second command to the memory control unit <b>118</b> as the top priority memory use request command.

The following is a description, with reference to the drawings, of the operations of the system LSI <b>100</b> with the above configuration.

&lt;Operations&gt;

Among the operations of the system LSI <b>100</b>, the following is a description of representative operations, namely arbitration by hierarchical level by the arbitration device <b>131</b>, final arbitration by the first arbitration device <b>130</b>, and arbitration by the hierarchical arbitration device <b>105</b>.

&lt;Arbitration by Hierarchical Level&gt;

<figref idrefs="DRAWINGS">FIG. 7</figref> is a flowchart showing arbitration by hierarchical level performed by the arbitration device <b>131</b>.

Arbitration by hierarchical level is processing whereby the arbitration device <b>131</b> arbitrates memory use request commands at the level to which the device belongs and, as the result of arbitration, outputs a first arbitration candidate memory use request command and a second arbitration candidate memory use request command to the arbitration device that is one level higher.

Arbitration by hierarchical level is performed in synchronization with the clock signal and starts when the clock signal rises.

When the clock signal rises, the first candidate arbiter <b>400</b> receives the master A first memory use request command and master B first memory use request command output by the memory-side command control unit <b>311</b> and receives the first arbitration candidate memory use request command output by the arbitration result output control unit <b>403</b> of the arbitration device <b>131</b> at the next lower level (step S<b>700</b>). The mask unit <b>401</b> receives the master A first memory use request command, master A second memory use request command, master B first memory use request command, and master B second memory use request command output by the memory-side command control unit <b>311</b> and receives the first arbitration candidate memory use request command and second arbitration candidate memory use request command output by the arbitration result output control unit <b>403</b> of the arbitration device <b>131</b> at the next lower level.

Upon input of the master A first memory use request command, master B first memory use request command, and first arbitration candidate memory use request command, the first candidate arbiter <b>400</b> selects, from among these three memory use request commands, the memory use request command having the highest priority as the first command, outputting the first command to the arbitration result output control unit <b>403</b> and mask unit <b>401</b> (step S<b>705</b>).

Upon input of the first command, the mask unit <b>401</b> selects five memory use request commands from among already input memory use request commands, namely the master A first memory use request command, master A second memory use request command, master B first memory use request command, master B second memory use request command, master A first memory use request command, master A second memory use request command, master B first memory use request command, and master B second memory use request command, with the exception of the memory use request command that matches the input first command. The mask unit <b>401</b> outputs the selected five memory use request commands to the second candidate arbiter <b>402</b> (step S<b>710</b>).

Upon input of the five memory use request commands, the second candidate arbiter <b>402</b> selects the memory use request command having the highest priority among the five commands, outputting the selected command to the arbitration result output control unit <b>403</b> as the second command (step S<b>715</b>).

Upon receiving input of the first command from the first candidate arbiter <b>400</b> and of the second command from the second candidate arbiter <b>402</b>, the arbitration result output control unit <b>403</b> waits until the rise of the next clock signal (step S<b>720</b>).

If the arbitration result output control unit <b>403</b> receives an acknowledge signal from the memory control unit <b>118</b> while waiting between the rise of a clock signal until the rise of the next clock signal (step S<b>725</b>: Yes), and if the master identifying information included in the acknowledge signal matches the master identifying information included in the received first command (step S<b>730</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>403</b> outputs, to the arbitration device <b>131</b> at the next level, the received second command as the first arbitration candidate memory use request command and a signal with all zeros, indicating non-existence of a memory use request command, as the second arbitration candidate memory use request command (step S<b>735</b>).

In step S<b>725</b>, if the arbitration result output control unit <b>403</b> does not receive an acknowledge signal from the memory control unit <b>118</b> while waiting between the rise of a clock signal until the rise of the next clock signal (step S<b>725</b>: No), or in step S<b>730</b>, if the master identifying information included in the acknowledge signal does not match the master identifying information included in the received first command (step S<b>730</b>: No), then when the next clock signal rises, the arbitration result output control unit <b>403</b> outputs, to the arbitration device <b>131</b> at the next level, the received first command as the first arbitration candidate memory use request command and the received second command as the second arbitration candidate memory use request command (step S<b>740</b>).

When processing in step S<b>735</b> or step S<b>740</b> is complete, the arbitration device <b>131</b> returns to step S<b>700</b> and again performs processing starting with step S<b>700</b>.

&lt;Final Arbitration&gt;

<figref idrefs="DRAWINGS">FIG. 8</figref> is a flowchart showing final arbitration performed by the arbitration device <b>130</b>.

Final arbitration is processing wherein the arbitration device <b>130</b> arbitrates memory use request commands at the highest level, to which the arbitration device <b>130</b> belongs, and as the result of arbitration, outputs a top priority memory use request command to the memory control unit <b>118</b>.

During final arbitration, processing from step S<b>800</b> through step S<b>830</b> is the same as processing from step S<b>700</b> through step S<b>730</b> during the arbitration by hierarchical level, replacing the arbitration result output control unit <b>403</b> with the arbitration result output control unit <b>603</b>. Accordingly, a description of the processing in these steps is omitted.

In step S<b>830</b>, if the master identifying information included in the received acknowledge signal matches the master identifying information included in the first command (step S<b>830</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>603</b> outputs the received second command to the memory control unit <b>118</b> as the top priority memory use request command (step S<b>835</b>).

In step S<b>825</b>, the arbitration result output control unit <b>603</b> may not receive an acknowledge signal from the memory control unit <b>118</b> while waiting until the rise of the next clock signal (step S<b>825</b>: No). In step S<b>830</b>, the master identifying information included in the acknowledge signal may not match the master identifying information included in the received first command (step S<b>830</b>: No). In either case of these two cases, when the next clock signal rises, the arbitration result output control unit <b>603</b> outputs the received first command to the memory control unit <b>118</b> as the top priority memory use request command (step S<b>840</b>).

When processing in step S<b>835</b> or step S<b>840</b> is complete, the arbitration device <b>130</b> returns to step S<b>800</b> and again performs processing starting with step S<b>800</b>.

&lt;Arbitration&gt;

The following is a description of arbitration performed by the hierarchical arbitration device <b>105</b>, with reference to the drawings and using a specific example.

<figref idrefs="DRAWINGS">FIG. 9</figref> is a timing chart of internal signals in the system LSI <b>100</b> for a specific example illustrating arbitration.

In this specific example, at time A, the third arbitration device <b>131</b>B outputs a command Ca <b>910</b> (read request command to read the external memory <b>101</b>) as the first arbitration candidate memory use request command and a command Cb <b>920</b> (read request command to read the external memory <b>101</b>) as the second arbitration candidate memory use request command. During the period from time A to time C, no master issues any new memory use request commands.

At time A, the third arbitration device <b>131</b>B outputs the command Ca <b>910</b> as the first arbitration candidate memory use request command and the command Cb <b>920</b> as the second arbitration candidate memory use request command to the second arbitration device <b>131</b>A. At time A<b>1</b>, i.e. when the next clock signal rises, the second arbitration device <b>131</b>A outputs a command Ca <b>911</b> as the first arbitration candidate memory use request command and a command Cb <b>921</b> as the second arbitration candidate memory use request command to the first arbitration device <b>130</b>.

At time A<b>2</b>, the first arbitration device <b>130</b> outputs a command Ca <b>912</b> to the memory control unit <b>118</b> as the top priority command.

At time B, the memory control unit <b>118</b> outputs an acknowledge signal ack_a <b>930</b>, which includes master identifying information included in the command Ca <b>912</b>, to all of the arbitration devices. Furthermore, over two cycles the memory control unit <b>118</b> reads data Da <b>940</b> stored in a 64-byte memory region in the external memory <b>101</b> at the starting address included in the command Ca <b>912</b> and outputs, over two cycles, the data Da <b>940</b> to the main bus <b>120</b>, which has a 32-byte bus width.

Between time B and time B<b>1</b>, all of the arbitration devices <b>130</b> receive the acknowledge signal ack_a <b>930</b> output by the memory control unit <b>118</b>.

Having received the acknowledge signal ack_a <b>930</b> from the memory control unit <b>118</b>, at time B<b>1</b> the first arbitration device <b>130</b> switches the top priority command from the command Ca <b>912</b> to a command Cb <b>924</b> and outputs the top priority command.

At time C, the memory control unit <b>118</b> outputs an acknowledge signal ack_b <b>931</b>, which includes master identifying information included in the command Cb <b>924</b>, to all of the arbitration devices. Furthermore, over two cycles the memory control unit <b>118</b> reads data Db <b>941</b> stored in a 64-byte memory region in the external memory <b>101</b> at the starting address included in the command Cb <b>924</b> and outputs, over two cycles, the data Db <b>941</b> to the main bus <b>120</b>, which has a 32-byte bus width.

The memory control unit <b>118</b> thus consecutively reads, from the external memory <b>101</b>, data Da <b>940</b> and data Db <b>941</b> and outputs the data to the main bus <b>120</b>. Therefore, the bubble phenomenon does not occur in the external memory <b>101</b> between output of the data Da <b>940</b> and output of the data Db <b>941</b>.

&lt;Conventional Arbitration&gt;

In order to explain the differences between arbitration performed by the hierarchical arbitration device <b>105</b> and conventional arbitration performed by a conventional hierarchical arbitration device, the following is a specific example of conventional arbitration performed by a conventional hierarchical arbitration device with reference to the drawings.

In this example, conventional arbitration performed by a conventional hierarchical arbitration device is defined as arbitration in which functionality of the arbitration device <b>130</b> and arbitration devices <b>131</b>A-<b>131</b>C that compose the hierarchical arbitration device <b>105</b> is limited. Specifically, these arbitration devices output, from among received memory use requests, only the memory use request having the highest priority to the arbitration device at the next higher level and do not output the memory use request having the second highest priority.

<figref idrefs="DRAWINGS">FIG. 10</figref> is a timing chart of internal signals in a system LSI <b>100</b> for a specific example illustrating arbitration. This system LSI <b>100</b> includes the arbitration device <b>130</b> and arbitration devices <b>131</b>A-<b>131</b>C that have limited functionality.

In this specific example, at time A, the third arbitration device <b>131</b>B with limited functionality outputs a command Ca <b>1010</b> (read request command to read the external memory <b>101</b>) as the first arbitration candidate memory use request command. During the period from time A to time C, no master issues any new memory use request commands.

While the third arbitration device <b>131</b>B with limited functionality stores, at time A, a command Cb that is lower priority than command Ca, due to its limited functionality the third arbitration device <b>131</b>B is unable to output the command Cb as the second arbitration memory use request command.

At time A, the third arbitration device <b>131</b>B with limited functionality outputs the command Ca <b>1010</b> as the first arbitration candidate command to the second arbitration device <b>131</b>A with limited functionality. At time A<b>1</b>, the second arbitration device <b>131</b>A with limited functionality outputs a command Ca <b>1011</b> as the first arbitration candidate command to the first arbitration device <b>130</b> with limited functionality.

At time A<b>2</b>, the first arbitration device <b>130</b> with limited functionality outputs a command Ca <b>1012</b> to the memory control unit <b>118</b> as the top priority command.

At time B, the memory control unit <b>118</b> outputs an acknowledge signal ack_a <b>1030</b>, which includes master identifying information included in the command Ca <b>1012</b>, to all of the arbitration devices with limited functionality. Furthermore, over two cycles the memory control unit <b>118</b> reads data Da <b>1040</b> stored in a 64-byte memory region in the external memory <b>101</b> at the starting address included in the command Ca <b>1012</b> and outputs the data Da <b>1040</b> to the main bus <b>120</b>.

Having received the acknowledge signal ack_a <b>1030</b> from the memory control unit <b>118</b>, at time B<b>1</b> the third arbitration device <b>131</b>B with limited functionality outputs a command Cb <b>1020</b>.

After the third arbitration device <b>131</b>B with limited functionality outputs the command Cb <b>1020</b> as the first arbitration candidate command to the second arbitration device <b>131</b>A with limited functionality, the second arbitration device <b>131</b>A with limited functionality outputs a command Cb <b>1021</b> at time C as the first arbitration candidate command to the first arbitration device <b>130</b> with limited functionality.

At time C<b>1</b>, the first arbitration device <b>130</b> with limited functionality outputs a command Cb <b>1022</b> to the memory control unit <b>118</b> as the top priority command.

At time D, the memory control unit <b>118</b> outputs an acknowledge signal ack_b <b>1031</b>, which includes master identifying information included in the command Cb <b>1022</b>, to all of the arbitration devices with limited functionality. Furthermore, over two cycles the memory control unit <b>118</b> reads data Db <b>1042</b> stored in a 64-byte memory region in the external memory <b>101</b> at the starting address included in the command Cb <b>1022</b> and outputs the data Db <b>1042</b> to the main bus <b>120</b>.

A period that is two cycles long and in which data is not output thus occurs between when the memory control unit <b>118</b> reads the data Da <b>1040</b> and the data Db <b>1042</b> from the external memory <b>101</b> (i.e. a two-cycle bubble phenomenon occurs).

In other words, a bubble phenomenon occurs for the two cycles that are the difference between (i) the four cycles from output of one arbitration result until output of the next arbitration result by the third arbitration device <b>131</b>B with limited functionality (i.e. the latency of the third arbitration device <b>131</b>B with limited functionality) and (ii) the two cycles during which the master uses the external memory <b>101</b>.

&lt;Summary&gt;

With the above system LSI <b>100</b>, if for example the period from output of one set of arbitration results until output of the next set of arbitration results by the third arbitration device <b>131</b>B (i.e. the latency of the third arbitration device <b>131</b>B) is four cycles as shown in the specific example, then even if the period during which a master uses the external memory <b>101</b> is two cycles, the bubble phenomenon occurring with a conventional configuration no longer occurs. Therefore, the above system LSI <b>100</b> reduces occurrence of the bubble phenomenon as compared to a conventional configuration.

While it is possible to increase the data size from 64 bytes to, for example, 128 bytes, such a measure would increase the capacity of the data buffer in the bus interface unit, thereby increasing necessary circuit area. Moreover, a data size of 128 bytes would mean that masters occupy the external memory for four cycles. Therefore, performance would be reduced for a master such as the processor, which has a high priority and whose performance is directly affected by a short data response time after the start of an access request.

Each master in the system LSI <b>100</b> thus uses the external memory <b>101</b> more efficiently than in a conventional configuration.

Since this system LSI <b>100</b> is provided with a master that has functions related to image processing and can efficiently use the external memory <b>101</b>, this system LSI <b>100</b> is useful in systems that perform image processing with the use of memory, such as a Blu-ray recorder system.

Embodiment 2

The following describes, as Embodiment 2 of an arbitration device according to the present invention, a first modified system LSI that is a partial modification of the system LSI <b>100</b> according to Embodiment 1.

If in an arbitration device in the first modified system LSI the time lag between (i) output of the first arbitration memory use request command and (ii) receipt of an acknowledge signal that is a response signal corresponding to the first arbitration memory use request command is equal to or greater than a predetermined time, the arbitration device outputs a signal with all zeros as the second arbitration memory use request command.

This structure is adopted because the above bubble phenomenon does not occur even if an arbitration device does not output a second arbitration memory use request command, as long as the number of clock cycles for which a master uses the memory is equal to or greater than the number of clock cycles from when the arbitration device outputs the first arbitration memory use request command until the arbitration device receives an acknowledge signal that is a response signal corresponding to the first arbitration memory use request command and outputs the next first arbitration memory use request command.

The following describes the configuration of the first modified system LSI according to Embodiment 2 with reference to the drawings, focusing on the differences with the system LSI <b>100</b> according to Embodiment 1.

&lt;Configuration&gt;

The differences between the first modified system LSI according to Embodiment 2 and the system LSI according to Embodiment 1 are (1) that the arbitration device <b>131</b> is changed to an arbitration device <b>1131</b>, and (2) that the size of data written to and read from a memory region by each master is changed from a fixed length of 64 bytes to a fixed length of 96 bytes.

Since the bus width of the main bus <b>120</b> is 32 bytes, the main bus <b>120</b> transfers 96 bytes of data over three cycles.

<figref idrefs="DRAWINGS">FIG. 11</figref> is a configuration diagram of the arbitration device <b>1131</b>.

The arbitration device <b>1131</b> is a partial modification of the arbitration device <b>131</b> in Embodiment 1, in which the arbiter <b>141</b> in the arbitration device <b>131</b> is replaced with an arbiter <b>1141</b>.

The arbiter <b>1141</b> is a partial modification of the arbiter <b>141</b> in Embodiment 1, in which a setting register <b>1104</b> is added to the arbiter <b>141</b>, and the arbitration result output control unit <b>403</b> is replaced with an arbitration result output control unit <b>1103</b>.

The setting register <b>1104</b> is connected to the processor <b>110</b> and arbitration result output control unit <b>1103</b> and has a function to store a number of clock cycles set by the processor <b>110</b>.

When the arbitration device <b>1131</b> to which the arbiter <b>1141</b> belongs outputs a first arbitration memory use request command and receives an acknowledge signal that is a response signal corresponding to the first arbitration memory use request command, the number of clock cycles set by the processor <b>110</b> refers to the number of clock cycles necessary from output of the first arbitration memory use request command until receipt of the acknowledge signal.

The arbitration result output control unit <b>1103</b> is connected to the first candidate arbiter <b>400</b>, second candidate arbiter <b>402</b>, memory control unit <b>118</b>, first arbitration candidate signal line A <b>411</b>A, second arbitration candidate signal line A <b>412</b>A, and setting register <b>1104</b>, operates in synchronization with the clock signal, and includes the following three functions.

Function 1: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1103</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, and furthermore when the number of clock cycles set in the setting register <b>1104</b> is equal to or greater than a predetermined value of four, then when the next clock signal rises, the arbitration result output control unit <b>1103</b> outputs the first command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs the second command to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

Function 2: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1103</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, and furthermore when the number of clock cycles set in the setting register <b>1104</b> is not equal to or greater than a predetermined value of four, then the arbitration result output control unit <b>1103</b> outputs the first command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs a signal with all zeros to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

Function 3: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1103</b> receives from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>1103</b> outputs the second command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs a signal with all zeros to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

The following is a description, with reference to the drawings, of the operations of the first modified system LSI with the above configuration.

&lt;Operations&gt;

Among the operations of the first modified system LSI, the following is a description of representative operations, namely first modified arbitration by hierarchical level by the arbitration device <b>1131</b> and first modified arbitration by the hierarchical arbitration device according to Embodiment 2.

&lt;First Modified Arbitration by Hierarchical Level&gt;

First modified arbitration by hierarchical level is a partial modification of the arbitration by hierarchical level performed by the arbitration device <b>131</b>.

<figref idrefs="DRAWINGS">FIGS. 12 and 13</figref> are a flowchart showing the first modified arbitration by hierarchical level performed by the arbitration device <b>1131</b>.

During the first modified arbitration by hierarchical level, processing from step S<b>1200</b> through step S<b>1230</b> is the same as processing from step S<b>700</b> through step S<b>730</b> during the arbitration by hierarchical level, replacing the arbitration result output control unit <b>403</b> with the arbitration result output control unit <b>1103</b>. Accordingly, a description of the processing in these steps is omitted.

In step S<b>1230</b>, if the master identifying information included in the received acknowledge signal matches the master identifying information included in the first command (step S<b>1230</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>1103</b> outputs, to the arbitration device <b>1131</b> at the next level, the received second command as the first arbitration candidate memory use request command and a signal with all zeros, indicating non-existence of a memory use request command, as the second arbitration candidate memory use request command (step S<b>1300</b>).

In step S<b>1225</b>, if the arbitration result output control unit <b>1103</b> does not receive an acknowledge signal from the memory control unit <b>118</b> while waiting until the rise of the next clock signal (step S<b>1225</b>: No), or in step S<b>1230</b>, if the master identifying information included in the acknowledge signal does not match the master identifying information included in the received first command (step S<b>1230</b>: No), then the arbitration result output control unit <b>1103</b> checks whether the number of clock cycles set in the setting register <b>1104</b> is equal to or greater than a predetermined value of four (step S<b>1235</b>).

In step S<b>1235</b>, if the number of clock cycles set in the setting register <b>1104</b> is equal to or greater than four (step S<b>1235</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>1103</b> outputs, to the arbitration device <b>1131</b> at the next level, the received first command as the first arbitration candidate memory use request command and the received second command as the second arbitration candidate memory use request command (step S<b>1305</b>).

In step S<b>1235</b>, if the number of clock cycles set in the setting register <b>1104</b> is not equal to or greater than four (step S<b>1235</b>: No), then when the next clock signal rises, the arbitration result output control unit <b>1103</b> outputs, to the arbitration device <b>1131</b> at the next level, the received first command as the first arbitration candidate memory use request command and a signal with all zeros, indicating non-existence of a memory use request command, as the second arbitration candidate memory use request command (step S<b>1310</b>).

&lt;First Modified Arbitration&gt;

The following is a description of the first modified arbitration performed by the hierarchical arbitration device according to Embodiment 2, with reference to the drawings and using a specific example.

<figref idrefs="DRAWINGS">FIG. 14</figref> is a timing chart of internal signals in the first modified system LSI for a specific example illustrating first modified arbitration.

In this specific example, at time A, the third arbitration device <b>1131</b>B outputs a command Ca <b>1410</b> (read request command to read the external memory <b>101</b>) as the first arbitration candidate memory use request command and a command Cb <b>1420</b> (read request command to read the external memory <b>101</b>) as the second arbitration candidate memory use request command During the period from time A to time C, no master issues any new memory use request commands.

At time A, the third arbitration device <b>1131</b>B outputs the command Ca <b>1410</b> as the first arbitration candidate memory use request command and the command Cb <b>1420</b> as the second arbitration candidate memory use request command to the second arbitration device <b>1131</b>A. At time A<b>1</b>, i.e. when the next clock signal rises, the second arbitration device <b>1131</b>A outputs a command Ca <b>1411</b> as the first arbitration candidate memory use request command and a signal with all zeros as the second arbitration candidate memory use request command to the first arbitration device <b>130</b>.

At time A<b>2</b>, the first arbitration device <b>130</b> outputs a command Ca <b>1412</b> to the memory control unit <b>118</b> as the top priority command.

At time B, the memory control unit <b>118</b> outputs an acknowledge signal ack_a <b>1430</b>, which includes master identifying information included in the command Ca <b>1412</b>, to all of the arbitration devices. Furthermore, over three cycles the memory control unit <b>118</b> reads data Da <b>1440</b> stored in a 96-byte memory region in the external memory <b>101</b> at the starting address included in the command Ca <b>1412</b> and outputs, over three cycles, the data Da <b>1440</b> to the main bus <b>120</b>, which has a 32-byte bus width.

Between time B and time B<b>1</b>, all of the arbitration devices <b>130</b> receive the acknowledge signal ack_a <b>1430</b> output by the memory control unit <b>118</b>.

Having received the acknowledge signal ack_a <b>1430</b> from the memory control unit <b>118</b>, at time B<b>1</b> the second arbitration device <b>1131</b>A switches the top priority command from the command Ca <b>1411</b> to a command Cb <b>1422</b> and outputs the top priority command.

At time B<b>2</b>, the first arbitration device <b>130</b> outputs a command Cb <b>1423</b> to the memory control unit <b>118</b> as the top priority command.

At time C, the memory control unit <b>118</b> outputs an acknowledge signal ack_b <b>1431</b>, which includes master identifying information included in the command Cb <b>1423</b>, to all of the arbitration devices. Furthermore, over three cycles the memory control unit <b>118</b> reads data Db <b>1441</b> stored in a 96-byte memory region in the external memory <b>101</b> at the starting address included in the command Cb <b>1424</b> and outputs, over three cycles, the data Db <b>1441</b> to the main bus <b>120</b>, which has a 32-byte bus width.

The memory control unit <b>118</b> thus consecutively reads, from the external memory <b>101</b>, data Da <b>1440</b> and data Db <b>1441</b> and outputs the data to the main bus <b>120</b>. Therefore, the bubble phenomenon does not occur in the external memory <b>101</b> between output of the data Da <b>1440</b> and output of the data Db <b>1441</b>.

&lt;Summary&gt;

With the first modified system LSI, if for example the period from output of one set of arbitration results until output of the next set of arbitration results by the third arbitration device <b>1131</b>B (i.e. the latency of the third arbitration device <b>1131</b>B) is four cycles as shown in the specific example, then even if the period during which a master uses the external memory <b>101</b> is three cycles, the bubble phenomenon does not occur.

All of the masters in the above configuration have been described as adopting the same fixed data length of 96 bytes. In an actual configuration, however, it is possible for each master to choose a different fixed data length. In such a case, one setting register exists for each master.

Furthermore, since the second arbitration device <b>1131</b>A in the first modified system LSI always outputs a signal with all zeros as the second arbitration memory use request command, less power is consumed than in a configuration in which the second arbitration device outputs a signal other than all zeros as the second arbitration memory use request command.

Embodiment 3

The following describes, as Embodiment 3 of an arbitration device according to the present invention, a second modified system LSI that is a partial modification of the first modified system LSI according to Embodiment 2.

If the number of clock cycles for which a master uses the memory is equal to or greater than the number of clock cycles from when each arbitration device in the second modified system LSI outputs the first arbitration memory use request command until the arbitration device receives an acknowledge signal that is a response signal corresponding to the first arbitration memory use request command and outputs the next first arbitration memory use request command, the arbitration device does not output a second arbitration memory use request command.

In the first modified system LSI, access to a memory region by each master is a fixed length of 96 bytes, but in the second modified system LSI, the size of access to a memory region by each master is a variable length.

The following describes the configuration of the second modified system LSI according to Embodiment 3 with reference to the drawings, focusing on the differences with the first modified system LSI according to Embodiment 2.

&lt;Configuration&gt;

The differences between the second modified system LSI according to Embodiment 3 and the first modified system LSI according to Embodiment 2 are (1) that the arbitration device <b>1131</b> is changed to an arbitration device <b>1631</b>, and (2) that data written to and read from a memory region by each master is changed to variable access with a length that is a multiple of 32 bytes.

<figref idrefs="DRAWINGS">FIG. 15</figref> is a data structure diagram of a memory use request command output by the masters.

As shown in <figref idrefs="DRAWINGS">FIG. 15</figref>, the memory use request command includes a starting address <b>1501</b>, burst length information <b>1502</b>, master identifying information <b>1503</b>, and command type information <b>1504</b>.

The starting address <b>1501</b> is the same as the starting address <b>1201</b> in Embodiment 1, the master identifying information <b>1503</b> is the same as the master identifying information <b>202</b> in Embodiment 1, and the command type information <b>1504</b> is the same as the command type information <b>203</b> in Embodiment 1. Accordingly, a description of these pieces of information is omitted.

The burst length information <b>1502</b> is a six-bit piece of data indicating the size, in multiples of 32 bytes, of a memory region that is accessed.

For example, if the size of a memory region that is accessed is 96 bytes, the burst length information <b>1502</b> is “000011”.

<figref idrefs="DRAWINGS">FIG. 16</figref> is a configuration diagram of the arbitration device <b>1631</b>.

The arbitration device <b>1631</b> is a partial modification of the arbitration device <b>1131</b> in Embodiment 2, in which the arbiter <b>1141</b> in the arbitration device <b>1131</b> is replaced with an arbiter <b>1641</b>.

The arbiter <b>1641</b> is a partial modification of the arbiter <b>1141</b> in Embodiment 2, in which the arbitration result output control unit <b>1103</b> in the arbiter <b>1141</b> is replaced with an arbitration result output control unit <b>1603</b>.

The arbitration result output control unit <b>1603</b> is connected to the first candidate arbiter <b>400</b>, second candidate arbiter <b>402</b>, memory control unit <b>118</b>, first arbitration candidate signal line A <b>411</b>A, second arbitration candidate signal line A <b>412</b>A, and setting register <b>1104</b>, operates in synchronization with the clock signal, and includes the following three functions.

Function 1: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1603</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, and furthermore when the value of the burst length information included in the first command is greater than the number of clock cycles set in the setting register <b>1104</b>, then when the next clock signal rises, the arbitration result output control unit <b>1603</b> outputs the first command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs the second command to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

Function 2: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1603</b> does not receive from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, and furthermore when the value of the burst length information included in the first command is not greater than the number of clock cycles set in the setting register <b>1104</b>, then the arbitration result output control unit <b>1603</b> outputs the first command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs a signal with all zeros to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

Function 3: after receiving the first command from the first candidate arbiter <b>400</b> and the second command from the second candidate arbiter <b>402</b>, when during the clock cycle in which these commands are received, the arbitration result output control unit <b>1603</b> receives from the memory control unit <b>118</b> an acknowledge signal that includes master identifying information included in the first command, then when the next clock signal rises, the arbitration result output control unit <b>1603</b> outputs the second command to the first arbitration candidate signal line A <b>411</b>A as the first arbitration candidate memory use request command and outputs a signal with all zeros to the second arbitration candidate signal line A <b>412</b>A as the second arbitration candidate memory use request command.

The following is a description, with reference to the drawings, of the operations of the second modified system LSI with the above configuration.

&lt;Operations&gt;

Among the operations of the second modified system LSI, the following is a description of representative operations, namely second modified arbitration by hierarchical level by the arbitration device <b>1631</b>.

&lt;Second Modified Arbitration by Hierarchical Level&gt;

Second modified arbitration by hierarchical level is a partial modification of the first arbitration by hierarchical level performed by the arbitration device <b>1131</b>.

<figref idrefs="DRAWINGS">FIGS. 17 and 18</figref> are a flowchart showing the second modified arbitration by hierarchical level performed by the arbitration device <b>1631</b>.

During the second modified arbitration by hierarchical level, processing from step S<b>1700</b> through step S<b>1730</b> is the same as processing from step S<b>1200</b> through step S<b>1230</b> during the first modified arbitration by hierarchical level, replacing the arbitration result output control unit <b>1103</b> with the arbitration result output control unit <b>1603</b>. Accordingly, a description of the processing in these steps is omitted.

In step S<b>1730</b>, if the master identifying information included in the received acknowledge signal matches the master identifying information included in the first command (step S<b>1730</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>1603</b> outputs, to the arbitration device <b>1631</b> at the next level, the received second command as the first arbitration candidate memory use request command and a signal with all zeros, indicating non-existence of a memory use request command, as the second arbitration candidate memory use request command (step S<b>1800</b>).

In step S<b>1725</b>, if the arbitration result output control unit <b>1103</b> does not receive an acknowledge signal from the memory control unit <b>118</b> while waiting until the rise of the next clock signal (step S<b>1725</b>: No), or in step S<b>1730</b>, if the master identifying information included in the acknowledge signal does not match the master identifying information included in the received first command (step S<b>1730</b>: No), then the arbitration result output control unit <b>1603</b> compares the value of the burst length information included in the first command with the number of clock cycles set in the setting register <b>1104</b> (step S<b>1735</b>).

In step S<b>1735</b>, if the value of the burst length information included in the first command is larger than the number of clock cycles set in the setting register <b>1104</b> (step S<b>1735</b>: Yes), then when the next clock signal rises, the arbitration result output control unit <b>1603</b> outputs, to the arbitration device <b>1631</b> at the next level, the received first command as the first arbitration candidate memory use request command and the received second command as the second arbitration candidate memory use request command (step S<b>1805</b>).

In step S<b>1735</b>, if the value of the burst length information included in the first command is not larger than the number of clock cycles set in the setting register <b>1104</b> (step S<b>1735</b>: No), then when the next clock signal rises, the arbitration result output control unit <b>1603</b> outputs, to the arbitration device <b>1631</b> at the next level, the received first command as the first arbitration candidate memory use request command and a signal with all zeros, indicating non-existence of a memory use request command, as the second arbitration candidate memory use request command (step S<b>1810</b>).

&lt;Summary&gt;

If the number of clock cycles for which a master uses the memory is equal to or greater than the number of clock cycles from when the arbitration device <b>1631</b> in the second modified system LSI outputs the first arbitration memory use request command until the arbitration device <b>1631</b> receives an acknowledge signal that is a response signal corresponding to the first arbitration memory use request command and outputs the next first arbitration memory use request command, the arbitration device <b>1631</b> outputs a signal with all zeros as the second arbitration memory use request command. Therefore, less power is consumed than in a configuration in which each arbitration device outputs a signal other than all zeros as the second arbitration memory use request command.

&lt;Supplementary Explanation&gt;

While this concludes the description of system LSIs provided with the hierarchical arbitration devices according to Embodiments 1-3 as embodiments of an arbitration device according to the present invention, the following modifications are also possible, and the present invention is certainly not limited to the arbitration devices exactly as described in the above embodiments.

(1) In Embodiment 1, the processor, video output engine, encryption engine, stream engine, decoder, encoder, and image enhancement engine are described as examples of masters, but masters are not limited in this way. Any component with a function to use a resource as a slave can be a master, such as an image playback device, digital tuner, etc.

(2) In Embodiment 1, an example in which the external memory is a slave is described, but the slave is not limited to the external memory. Any component with a function to be used by a master can be a slave, such as an internal memory, encryption engine, decoder, image playback device, digital tuner, Digital to Analog (DA) converter, Universal Serial Bus (USB), interface, multiplication circuit, etc.

(3) In Embodiment 1, the main bus <b>120</b> is a 32-byte bidirectional bus, but the main bus <b>120</b> is not limited to being bidirectional. Any bus with a function to transmit data may be the main bus, such as the following: a bus with two sets of signal lines, a set of signal lines to transmit data from a slave to a master, and a set of signal lines to transmit data from a master to a slave; a bus with a ring structure; a bus with a cross-bar structure; etc.

Furthermore, the bus width of the main bus <b>120</b> is not limited to 32 bytes, but may be four bytes, 256 bytes, etc.

(4) In Embodiment 1, an example is described in which four arbitration devices are connected in series in the hierarchical arbitration device <b>105</b>, but as long as the number of arbitration devices connected in series is two or greater, the number is not limited to four, but may for example be three or six.

(5) In Embodiment 1, an example is described in which the arbitration device <b>131</b> can output two memory use request commands, the memory use request command having the highest priority and the memory use request command having the second highest priority. As long as the arbitration device can output the memory use request command having the highest priority and the memory use request command having the second highest priority, a structure in which the arbitration device also outputs a memory use request command with the third highest priority is possible.

(6) In Embodiment 1, an example is described in which the algorithm for selecting the memory use request command having the highest priority in the first candidate arbiter <b>400</b> and second candidate arbiter <b>402</b> is based on information according to a predetermined priority ranking. However, the algorithm for selecting the memory use request command having the highest priority is not limited to being based on information according to a predetermined priority ranking, as long as the algorithm uniquely selects a memory use request command having the highest priority, as does an algorithm according to the Earliest Deadline First (EDF) method, for example.

(7) In Embodiment 1, an example is described in which the acknowledge signal output by the memory control unit <b>118</b> is received by all of the arbitration devices during the clock cycle in which the acknowledge signal is output. However, it is not necessary for all of the arbitration devices to receive the acknowledge signal during the same clock cycle, as long as all of the arbitration devices do receive the acknowledge signal.

For example, it is possible for the number of clock cycles from the output of the acknowledge signal until receipt of the acknowledge signal to increase as the physical distance from the arbitration device to the memory control unit <b>118</b> increases.

(8) In Embodiment 1, an example is described in which the constituent elements of the system LSI <b>100</b> are integrated on the system LSI <b>100</b>, which is one LSI, yet integration on one LSI is not necessary. Any system that can implement the same functions as the system LSI <b>100</b> is possible, such as a structure in which constituent elements are integrated on separate LSIs.

(9) The system LSI <b>100</b>, first modified system LSI, and second modified system LSI respectively described in Embodiments 1-3 are useful in a variety of systems, such as a Blu-ray recorder system, cellular phone, terminal for a vehicle, etc.

<figref idrefs="DRAWINGS">FIG. 19</figref> is a configuration diagram of a Blu-ray recorder system <b>1900</b> that uses a system LSI <b>100</b>.

(10) In the system LSI <b>100</b> described in Embodiments 1-3, an example is described in which the first arbitration device <b>130</b> and the second arbitration device <b>131</b>A through fourth arbitration device <b>131</b>C operate in synchronization with a shared clock signal, but the arbitration devices do not need to be limited to operating in synchronization with a shared clock signal.

For example, each arbitration device may operate in synchronization with a clock signal having an independent frequency. Furthermore, each constituent element in an arbitration device may operate in synchronization with a clock signal having an independent frequency.

(11) In the system LSI <b>100</b> described in Embodiments 1-3, an example is described in which the second arbitration device <b>131</b>A through fourth arbitration device <b>131</b>C output the first arbitration candidate memory use request command via the first arbitration candidate signal line and the second arbitration candidate memory use request command via the second arbitration candidate signal line, but these arbitration devices do not need to be limited to outputting the first arbitration candidate memory use request command and the second arbitration candidate memory use request command via two separate signal lines.

For example, each arbitration device may use one signal line to serially output the first arbitration candidate memory use request command and the second arbitration candidate memory use request command over two clock cycles.

INDUSTRIAL APPLICABILITY

The present invention may be widely used in systems in which a plurality of masters share a resource as a slave.

REFERENCE SIGNS LIST

<ul><li id="ul0002-0001" num="0291"><b>100</b> system LSI</li><li id="ul0002-0002" num="0292"><b>101</b> external memory</li><li id="ul0002-0003" num="0293"><b>105</b> hierarchical arbitration device</li><li id="ul0002-0004" num="0294"><b>110</b> processor</li><li id="ul0002-0005" num="0295"><b>111</b> video output engine</li><li id="ul0002-0006" num="0296"><b>112</b> encryption engine</li><li id="ul0002-0007" num="0297"><b>113</b> stream engine</li><li id="ul0002-0008" num="0298"><b>114</b> decoder A</li><li id="ul0002-0009" num="0299"><b>115</b> decoder B</li><li id="ul0002-0010" num="0300"><b>116</b> encoder</li><li id="ul0002-0011" num="0301"><b>117</b> image enhancement engine</li><li id="ul0002-0012" num="0302"><b>118</b> memory control unit</li><li id="ul0002-0013" num="0303"><b>120</b> main bus</li><li id="ul0002-0014" num="0304"><b>130</b> first arbitration device</li><li id="ul0002-0015" num="0305"><b>131</b>A second arbitration device</li><li id="ul0002-0016" num="0306"><b>131</b>B third arbitration device</li><li id="ul0002-0017" num="0307"><b>131</b>C fourth arbitration device</li><li id="ul0002-0018" num="0308"><b>140</b> arbiter</li><li id="ul0002-0019" num="0309"><b>141</b>A-<b>141</b>C arbiters</li><li id="ul0002-0020" num="0310"><b>150</b>A-<b>150</b>D bus interface units</li><li id="ul0002-0021" num="0311"><b>161</b>A-<b>161</b>C first arbitration candidate signal lines</li><li id="ul0002-0022" num="0312"><b>162</b>B-<b>162</b>B second arbitration candidate signal lines</li></ul>