Method for manufacturing a circuit board structure
Summary by NHIP
Circuit board manufacturing method
The method manufactures a circuit board by attaching a component to a conductor layer containing a pattern and contact openings before removing excess material. Distinctive steps include filling those openings with conductor material while selectively removing substrate material from outside the pattern to preserve specific thicknesses.
Claim Score by NHIP
Abstract
The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and at least some conductor material of the conductor layer is removed from outside the conductor pattern.

Term
1.5 yearsleft in the term
Expires 22 March 2028, including 646 days of term adjustment.
- Priority
- Filed
- Granted
- Today
- Expires
19 claims: 2 independent, 17 dependent
- 1Method for manufacturing a circuit-board structure including a component having contact areas, the method comprising making a conductor layer, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil, making contact openings or recesses, before attaching the component to the conductor layer, at least in the conductor pattern of the conductor layer, the positions of which contact openings or recesses correspond to locations of the contact areas of the component, aligning the component relative to the conductor pattern and the contact openings or recesses, attaching the component by gluing to the conductor layer, after gluing the component to the conductor layer, filling or surfacing the contact openings or recesses with a filling conductor material, and removing at least some conductor material of the conductor layer from outside the conductor pattern.
- 19Broadest claimClaim Score 68, broad(NHIP)Method for manufacturing a circuit-board structure including a component having contact areas, the method comprising making a conductor layer, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil, making contact openings or recesses, before attaching the component to the conductor layer, at least in the conductor pattern of the conductor layer, the positions of which contact openings or recesses correspond to locations of the contact areas of the component, attaching the component to the conductor layer, after attaching the component to the conductor layer, filling or surfacing the contact openings or recesses with a filling conductor material, and after attaching the component to the conductor layer, removing at least some conductor material of the conductor layer from outside the conductor pattern.
Independent claims2
67 paragraphs in 6 sections, as filed
CROSS-REFERENCE TO RELATED APPLICATION
0001This application is a U.S. nationalized patent application of PCT/FI2006/000207, filed Jun. 15, 2006, which claims priority to Finnish Patent Application No. 20050646 filed Jun. 16, 2005, the entire disclosures of each are hereby expressly incorporated by reference herein.
FIELD OF THE DISCLOSURE
0002The present invention relates to a method for manufacturing a circuit-board structure and a circuit-board structure.
0003The circuit-board structure manufactured can form, for example, part of a circuit board, a multilayer circuit board, a component packet, or an electronic module.
0004The circuit-board structure comprises at least one layer of conductor patterns and at least one component, which is connected electrically to the conductor patterns.
0005The invention also relates to methods, in which at least one component connected to a conductor pattern is surrounded by an insulation-material layer. Such solutions can be alternatively also referred to as circuit-board or module structures, which contain buried, embedded, or built-in components. The insulation-material layer surrounding the component is typically part of the basic structure of a circuit-board or module structure, which forms a support for the innermost conductor layers of the circuit board or module.
BACKGROUND OF THE DISCLOSURE
0006Application publication US 2005/0001331 discloses a circuit-board structure manufacturing method, in which first of all a circuit board is manufactured, which comprises an insulator layer and a conductor pattern on top of it. After this, a semiconductor component is connected to the conductor patterns by means of a suitable flip-chip method. The connection takes place through contact bumps on the surface of the semiconductor component. In the method of the US publication, after the connection of the component a patterned and unpatterned insulation-material layer is laminated on top of the circuit board and a conductor-pattern layer is further laminated on their surface.
0007Patent publications U.S. Pat. No. 6,038,133 and U.S. Pat. No. 6,489,685 as well as application publication US 2002/0117743 disclose a method, in which a conductor pattern is manufactured on the surface of a detachable membrane, and a semiconductor component is connected to the conductor pattern by means of a flip-chip attachment method. After this, the component is surrounded with a layer of insulation material and the detachable membrane is removed.
0008The aforementioned publication U.S. Pat. No. 6,038,133 and US 2002//0117743 also disclose methods, in which a component is connected by a flip-chip method not to conductor patterns but to a unified conductor foil, from which conductors patterns are formed in a later stage of the process. Corresponding method are also disclosed, for example, in the publications U.S. Pat. No. 5,042,145; WO 2004/077902; WO 2004/077903; and WO 2005/020651.
0009In addition to the aforementioned types of method, many other methods are known, which can be used to manufacture circuit-board structures containing components. The components can, for example, first of all be placed inside an insulating-material layer and connected electrically to the conductor layer only after this, as is disclosed in application publication WO 2004/089048. In the method of application publication WO 2004/089048, the component is glued to the surface of a conductor layer and, after the gluing of the component, an insulating-material layer, which surrounds the component attached to the conductor layer, is formed of attached to the conductor layer. After the gluing of the component, vias are also made, through which electrical contacts are formed between the conductor layer and the contact areas of the component. After this, conductor patterns are formed from the conductor layer, to the surface of which the component is glued.
0010The invention is intended to develop a new method for manufacturing a circuit-board structure.
SUMMARY OF THE DISCLOSURE
0011According to the invention, a method is implemented, in which a conductor layer is made, which comprises both a conductor pattern and a conductor foil. The component is attached to the conductor layer comprising the conductor pattern and conductor foil and, after the attaching of the component, the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
0012In this way, a new method for manufacturing a circuit-board structure is created.
0013The invention has several embodiments, a few of which are presented briefly in the following.
0014The manufacture of the conductor layer can be performed in several different ways: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0015">According to one embodiment, the conductor layer is manufactured by growing a conductor pattern on top of a conductor foil, using a growing method. Thus the conductor foil is grown directly into its correct shape.</li><li id="ul0002-0002" num="0016">According to a second embodiment, the conductor layer is manufactured by thinning areas of a thicker conductor foil, in such a way that a thinner conductor foil and a conductor pattern on top of this remain. The thinning of the areas can be implemented, for example, using a photo-lithographic method, or a laser-ablation method.</li></ul></li></ul>
0017The attachment of the component can also be performed using several techniques and in one or more stages. The attachment of the component is concerned with achieving a mechanical attachment between the component and the conductor pattern, in such a way that the component and the conductor pattern will remain in place in the circuit-board structure. The attachment of the component is also concerned with making an electrical contact between the component and the conductor pattern, in such a way that, through the conductor pattern, the desired voltages and currents can be led to the component and away from the component. The mechanical attachment and the electrical contact can be made simultaneously using a single connection method, or proceed in such a way that the mechanical attachment is made first and the electrical contact in some suitable later process stage. It is also possible to proceed in such a way that the electrical contact is made first along with a preliminary mechanical attachment, in which case the final mechanical attachment is made in some suitable later process stage.
0018The electrical contact of the component can be made using several techniques: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0019">In one embodiment, the component is connected to the conductor layer using an ultrasonic bonding method.</li><li id="ul0004-0002" num="0020">In a second embodiment, the component is connected to the conductor layer by soldering.</li><li id="ul0004-0003" num="0021">In a third embodiment, the component is connected to the conductor layer by a conductive adhesive.</li><li id="ul0004-0004" num="0022">In a fourth embodiment, the component is connected to the conductor layer using a via method.</li></ul></li></ul>
0023In the first, second, and third connection techniques for the component, contact openings need not necessarily be made in the conductor layer at the locations of the contact areas of the component. If, on the other hand, a via method is used, contact openings, the position of which corresponds to the locations of the contact areas of the component, are made in the conductor layer, or at least in the conductor-pattern part of it. The making of the contact openings too can also be performed according to several different embodiments: <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0024">In a first embodiment, the contact openings are made before the attachment of the component and through the entire conductor layer, i.e. the openings extend through both the conductor layer and the conductor pattern. The component can then be aligned with the contact openings.</li><li id="ul0006-0002" num="0025">In a second embodiment, the contact openings are made partly before the attachment of the component, in such a way that the partly made contact openings extend into the conductor layer, without extending through it. In such an embodiment, the contact openings are opened later to extend through the conductor pattern, or they are opened in connection with the thinning of the conductor layer.</li><li id="ul0006-0003" num="0026">In a third embodiment, the contact openings are made after the attachment of the component, but before the thinning of the conductor pattern. In such an embodiment, the contact openings are made in such a way that they extend through the entire conductor layer, or so that they partly penetrate it, in such a way that they open at the latest in connection with the thinning of the conductor layer.</li><li id="ul0006-0004" num="0027">In a fourth embodiment, the contact openings are made after the attachment of the component and the thinning of the conductor pattern. In such an embodiment, the contact openings extend through the conductor layer.</li><li id="ul0006-0005" num="0028">In a fifth embodiment, the contact openings are made in the conductor pattern in connection with the making of the conductor pattern.</li></ul></li></ul>
0029When using a via method, the contact openings are filled, in a suitable stage of the method, with a conductor material, for example, a metal, metal alloy, a conductive paste or conductive polymer, for example, a conductive adhesive. Alternatively, the edges of the contact openings are surfaced with a conductor material. The best electrical contact is achieved using an embodiment, in which the contact openings are filled by growing metal into the openings and on top of the contact areas of the component, for example, using a chemical and/or electrochemical surfacing method. It will then be possible to create in the contact openings a via structure that is of essentially pure metal. It will then also be possible to create in the contact openings a via structure, which is in metallurgical contact with the conductor material of the contact areas.
0030The mechanical attachment of the component can be made using several techniques: <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0000"><ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0031">In one embodiment, the component is attached to the conductor layer by soldering or using an ultrasonic bonding method. The mechanical attachment created is later reinforced with the aid of an insulating material, for example, by filling the gap between the component and the conductor layer with a hardening polymer, or by surrounding the component tightly with an insulating material that adheres to the surface of both the component and the conductor pattern.</li><li id="ul0008-0002" num="0032">In a second embodiment, the component is attached to the conductor layer using a conductive adhesive. The adhesive can already at the same time form itself a sufficient mechanical attachment. The mechanical attachment can also be reinforced in the manner described in connection with the previous embodiment. The adhesive can be an isotropically conductive adhesive, or an anisotropically conductive adhesive.</li><li id="ul0008-0003" num="0033">In a third embodiment, the component is attached to the conductor layer by an insulating adhesive. An electrical contact can be made later through the insulating adhesive.</li></ul></li></ul>
0034The thinning of the conductor layer can also be performed in several different ways. The thinning of the conductor layer is intended to removed conductor material from between the conductor patterns. <ul id="ul0009" list-style="none"><li id="ul0009-0001" num="0000"><ul id="ul0010" list-style="none"><li id="ul0010-0001" num="0035">According to one embodiment, the conductor layer is thinned throughout, in such a way that the thickness of the conductor layer diminishes both at the locations of the conductor patterns and in the areas remaining between the conductor patterns. The thinning can be performed, for example, by wet-etching.</li><li id="ul0010-0002" num="0036">According to a second embodiment, the conductor layer is thinned in areas, in such a way that the thickness of the conductor layer diminishes in the areas remaining between the conductor patterns, but remains essentially unchanged at the locations of the conductor patterns. This can be achieved, for example, by wet-etching, in which a suitable etching mask is used on the surface of the conductor patterns.</li></ul></li></ul>
0037In several embodiments, an insulating-material layer is made around the component and on the surface of the conductor pattern. The insulating-material layer can be made from one or more insulating-material sheets, or from an insulating material spread in a fluid form. The insulating-material layer can be made, for example, according to the following embodiments: <ul id="ul0011" list-style="none"><li id="ul0011-0001" num="0000"><ul id="ul0012" list-style="none"><li id="ul0012-0001" num="0038">In one embodiment, the insulating-material layer is taken and a conductor layer is made on its surface. Before this or after this a suitable opening for the component is made in the insulating-material layer.</li><li id="ul0012-0002" num="0039">In a second embodiment, an insulating-material layer is made on the surface of the conductor layer. After this, an opening for the component is opened in the insulating-material layer.</li><li id="ul0012-0003" num="0040">In a third embodiment, the component is first attached to the conductor layer (mechanical attachment or electrical contact and at least a preliminary mechanical attachment), and after this an insulating-material layer is made on the surface of the conductor layer and around the component.</li></ul></li></ul>
0041In the embodiments, the conductor foil of the conductor layer is typically a unified, or at least a substantially unified conductor foil. Thus, there can be, for example, small holes in the conductor layer, for example, for alignment purposes. The conductor layer can, however, be handled as a single piece. The thickness of the conductor foil is typically such that it will withstand the treatment required by the process without breaking or being damaged, also without support. In the embodiments, it is of course possible to use a thinner conductor foil, in which case the conductor foil will be supported with the aid of a support layer.
0042In the embodiments, the conductor pattern of the conductor layer includes conductors of the conductor-pattern layer being made in the circuit-board structure, or patterns corresponding to these conductors. The conductors can thus be connected to each other, or separate, according to the desired circuit-board design.
0043References to the contact areas of the component mean conductor areas on the surface of the component, through which an electrical contact can be formed to the component. In this meaning, the contact area can be formed by, for example, a contact bump or a conductor area on the surface of the component.
0044In the following, the invention is examined with the aid of examples and with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
0045<figref idref="DRAWINGS">FIGS. 1-8</figref> show a series of cross-sections of the intermediate stages of the circuit-board structures, in a manufacturing process according to a first embodiment.
0046<figref idref="DRAWINGS">FIGS. 9-16</figref> show a series of cross-sections of the intermediate stages of the circuit-board structures, in a manufacturing process according to a second embodiment.
0047<figref idref="DRAWINGS">FIGS. 17-22</figref> show a series of cross-sections of the intermediate stages of the circuit-board structures, in a manufacturing process according to a third embodiment.
0048<figref idref="DRAWINGS">FIGS. 23-26</figref> show a series of cross-sections of the intermediate stages of the circuit-board structures, in a manufacturing process according to a fourth embodiment.
0049<figref idref="DRAWINGS">FIGS. 27-32</figref> show a series of cross-sections of the intermediate stages of the circuit-board structures, in a manufacturing process according to a fifth embodiment.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE
0050In the first example, the circuit-board blank shown in <figref idref="DRAWINGS">FIG. 1</figref> is manufactured first of all. The circuit-board blank of <figref idref="DRAWINGS">FIG. 1</figref> comprises an insulating-material layer <b>1</b>, a conductor foil <b>3</b> on the first surface of this, and a conductor foil <b>2</b> on the second surface.
0051The circuit-board blank also comprises a recess <b>4</b>. In addition, the circuit-board blank comprises a thinner insulating-material layer <b>11</b> between the insulating-material layer <b>1</b> and the conductor foil <b>2</b>. The insulating-material layer <b>11</b> can be of material differing from that of the insulating-material layer <b>1</b>, or it can be part of the insulating-material layer <b>1</b>. In the former case, the circuit-board blank of <figref idref="DRAWINGS">FIG. 1</figref> may have been formed, for example, by laminating together or otherwise combining with each other the insulating-material layer <b>1</b>, the conductor foil <b>2</b>, the conductor foil <b>3</b>, and the insulating-material layer <b>11</b>. In the latter case, the circuit-board blank of <figref idref="DRAWINGS">FIG. 1</figref> may have been formed, for example, in such a way that a recess <b>4</b> has been made in the blank formed by the insulating-material <b>1</b>, the conductor foil <b>2</b>, and the conductor foil <b>3</b>. In that case, the recess <b>4</b> will not extent completely through the insulating-material layer <b>1</b>, but instead a corresponding part of the insulating-material layer <b>11</b> has been left on the ‘bottom’ of the recess.
0052The method of the example can, of course, be modified in such a way that the recess <b>4</b> extends to the conductor foil <b>2</b>, in which case there will not be an insulating-material layer <b>11</b> in the circuit-board blank, at least at the location of the recess. However, at least in some embodiments the reliability of the circuit-board structure can be improved by using an insulating-material layer <b>11</b>. This is due to the fact that the use of an insulating-material layer <b>11</b> for its part ensures that unnecessary openings will not remain in the insulating material between the component and the conductor foil <b>2</b>.
0053Manufacture continues from the situation shown in <figref idref="DRAWINGS">FIG. 1</figref>, by spreading resist layers <b>5</b>, typically photoresist layers, on the surfaces of the conductor foils <b>2</b> and <b>3</b>. This stage is shown in <figref idref="DRAWINGS">FIG. 2</figref>. The photoresist layers <b>5</b> are exposed through a patterned mask and after this the blank is developed. After developing, the exposed photoresist layers <b>5</b> are patterned in the desired manner to form conductor-pattern masks, which is shown in <figref idref="DRAWINGS">FIG. 3</figref>.
0054Manufacture is continued by electrolytically growing a conductor material, typically copper, in the areas from which the photoresist was removed. The desired conductor patterns <b>6</b> and <b>7</b> are then formed on the surfaces of the conductor foils <b>2</b> and <b>3</b>, which is shown in <figref idref="DRAWINGS">FIG. 4</figref>. The thickness of the conductor pattern can be, for example, 20 micrometers while the width of the line of the conductor patterns being made can be less than 20 micrometers. The method can thus also be used to manufacture small and precise conductor patterns.
0055The method can be modified in such a way that a layer of some other metal or metal alloy, for example tin, can be made on the surface of the conductor patterns <b>6</b> and <b>7</b>, or on the interface between the conductor foils <b>2</b> and <b>3</b> and the conductor patterns <b>6</b> and <b>7</b>. This layer can be used as an etching stop.
0056The method can also be modified in such a way that the recess <b>4</b> is made only after the spreading of the photoresist layer <b>5</b>, or at an even later process stage.
0057After the manufacture of the conductor patterns <b>6</b> and <b>7</b>, the resist layers <b>5</b> can be removed. In addition, contact openings <b>8</b> are made in the conductor pattern <b>6</b> of the circuit-board blank, at the locations of the contact areas of the component. The contact openings <b>8</b> can be made in such a way that they essentially extend through the conductor pattern <b>8</b>, or in such a way that they essentially extend through both the conductor pattern <b>8</b> and the conductor foil <b>2</b>, (i.e. through the entire conductor layer). It is also possible to make the contact openings from the other direction, in such a way that they extend through only the insulating-material layer <b>11</b> and the conductor foil <b>2</b>. In the example, the contact openings <b>8</b> are made in such a way that they extend through the conductor pattern <b>6</b>, the conductor foil <b>2</b>, and the insulating-material layer <b>11</b>. <figref idref="DRAWINGS">FIG. 4</figref> shows the circuit-board blank after this intermediate stage.
0058The contact openings <b>8</b> can be made, for example, by drilling with a laser. The contact openings <b>8</b> are aligned correctly in position relative to the conductor pattern <b>6</b>. The mutual position of the contact openings <b>8</b> corresponds to the mutual position of the contact areas of the component. Thus, at least one contact opening <b>8</b> is made for each contact area participating in the creation of an electrical contact. The surface area of the contact openings <b>8</b> being made can be more or less as large as the surface area of the corresponding contact areas. The surface area of a contact opening <b>8</b> can, of course, also be selected to be smaller, or in some embodiments slightly larger, than the surface area of the corresponding contact area.
0059In the example, the component <b>9</b> is attached to the circuit-board blank with the aid of an adhesive <b>10</b>. For the gluing, an adhesive layer <b>10</b> is spread on the surface of the insulating-material layer <b>11</b>, on the ‘bottom’ of the recess <b>4</b>. <figref idref="DRAWINGS">FIG. 5</figref> shows this intermediate stage. Alternatively, the adhesive layer can be spread on the attachment surface of the component <b>9</b>, or on both the attachment surface of the component <b>9</b> and on the surface of the insulating-material layer <b>11</b>. The adhesive <b>10</b> can also be spread in stages and in layers. After this, the components <b>9</b> can be aligned in the positions designed for the components <b>9</b>, with the aid of alignment marks. For example, the contact openings <b>8</b>, or the conductor patterns <b>6</b> or <b>7</b>, or separate alignment marks (not shown in the figures) can act as alignment marks. <figref idref="DRAWINGS">FIG. 6</figref> shows the circuit-board blank after the gluing of the component <b>9</b>.
0060The term attachment surface of the component <b>9</b> refers to that surface of the component <b>9</b> that will face the conductor pattern <b>6</b>. The attachment surface of the component <b>9</b> comprises contact areas, by means of which an electrical contact can be made to the component. The contact areas can be, for example, flat areas on the surface of the component <b>9</b>, or more usually contact protrusions, such as contact bumps, on the surface of the component <b>9</b>. There are usually at least two contact areas or contact protrusions in the component <b>9</b>. In complex microcircuits there can well be many contact areas.
0061In many embodiments, it is advantageous to spread so much adhesive on the attachment surface or attachment surfaces that the adhesive completely fills the space between the component <b>9</b> and the structure coming against the component. A separate filler agent will then not be required. Good filling will reinforce the mechanical connection between the component <b>9</b> and the circuit-board blank, so that a mechanically more durable construction will be achieved. A comprehensive adhesive layer <b>10</b> without gaps will also support the conductor pattern and protect the structure in later process stages. During gluing, adhesive also usually gets into the contact openings <b>8</b>, if these open towards the attachment surface.
0062The term adhesive refers to a material, by means of which a component can be attached to the circuit-board blank. One property of an adhesive is that the adhesive can be spread on the surface of the circuit-board blank and/or of the component in a relatively fluid form, or otherwise in a form that conforms to surface shapes, for example, in the form of a film. Another property of an adhesive is that after spreading the adhesive hardens or can be hardened, at least partly, so that the adhesive will be able to hold the component in place at least until the component is attached to the structure in some other way. The third property of the adhesive is its adhesive ability, i.e. its ability to bond to the surface being glued.
0063The term gluing refers to attaching the component and the circuit-board to each other with the aid of an adhesive. In gluing, adhesive is thus brought between the component and the circuit-board blank and the component is set in a suitable position relative to the circuit-board blank, in which the adhesive is in contact with the component and the circuit-board blank and at least partly fills the space between the component and the circuit-board blank. After this, the adhesive is allowed to (at least partly) harden or the adhesive is (at least partly) actively hardened, so that the component attaches to the circuit-board blank with the aid of the adhesive. In some embodiments, the contact protrusions of the component may, during gluing, extend through the adhesive layer to come in contact with the rest of the structure of the circuit-board blank.
0064The adhesive used in the embodiments is, for example, a thermally cured epoxy. The adhesive is selected in such a way that the adhesive used has sufficient adhesion with the circuit-board blank and the component. One advantageous property of the adhesive is a suitable coefficient of thermal expansion, so that the thermal expansion of the adhesive will not differ too much from the thermal expansion of the surrounding material during the process. The adhesive selected should also preferably have a short hardening time, preferably of a few seconds at most. In this time the adhesive should harden at least partly in such a way that it is able to hold the component in place. The final hardening can take clearly more time and the final hardening can indeed be designed to take place in connection with later process stages. The electrical conductivity of the adhesive is preferably in the order of the electrical conductivity of insulating materials.
0065The component <b>9</b> to be attached can be, for example, an integrated circuit, such as a memory chip, a processor, or an ASIC. The component to be attached can also be, for example, a MEMS, LED, or a passive component. The component to be attached can be cased or uncased, and it can comprise contact bumps in the contact areas or be without bumps. There can also be a conductor surfacing thinner than a contact bump on the surface of the contact areas of the component. The outer surface of the contact areas of the component can thus be on the level of the outer surface of the component, on the bottom of recesses on the surface of the component, or on the surface of protrusions extending from the surface of the component.
0066After the gluing of the component <b>9</b>, the recess is filled with a filler material <b>12</b>. The example can also be modified in such a way that manufacture is started from a circuit-board blank (the situation in <figref idref="DRAWINGS">FIG. 1</figref>), which comprises only a conductor foil <b>2</b> and possibly an insulating-material layer <b>11</b>. After this, process stages that are otherwise the same as those described above, except that naturally the method stages relating to the conductor foil <b>3</b>, the conductor pattern <b>7</b>, and the resist layer <b>5</b> relating to them are omitted. In this embodiment, the circuit-board blank comprises, after the gluing of the component (refer to <figref idref="DRAWINGS">FIG. 6</figref>): <ul id="ul0013" list-style="none"><li id="ul0013-0001" num="0000"><ul id="ul0014" list-style="none"><li id="ul0014-0001" num="0067">a conductor layer formed by a conductor foil <b>2</b> and a conductor pattern <b>6</b>,</li><li id="ul0014-0002" num="0068">an adhesive layer <b>10</b>,</li><li id="ul0014-0003" num="0069">optionally an insulating-material layer <b>11</b> between the conductor layer and the adhesive layer <b>10</b>,</li><li id="ul0014-0004" num="0070">contact openings <b>8</b>, and</li><li id="ul0014-0005" num="0071">at least one component <b>9</b>.</li></ul></li></ul>
0072In this modified embodiment, there is not recess <b>4</b> to be filled, instead in this stage an insulator layer <b>1</b>, which surrounds the component <b>9</b> and supports the conductor layers <b>2</b> and <b>6</b>, is made on the surface with the component <b>9</b> of the circuit-board blank. The insulator layer <b>1</b> can be formed, for example, by putting an insulating-material sheet, in which openings have been made at the location of the components <b>9</b>, on top on the circuit-board blank. In addition, a unified insulating-material sheet can be put on top of the insulating-material sheet <b>9</b>. Both sheets can be similar, or sheets than differ from each other can also be used, at least one of which is prehardened or unhardened. Examples of materials suitable for the insulator layer <b>1</b> are PI (polyimide), FR4, FR5, aramid, polytetrafluoroethylene, Teflon®, LCP (liquid crystal polymer), and a prehardened binder layer, i.e. prepreg. The insulating-material sheets put on top of the circuit-board blank are pressed, with the aid of heat and pressure, to form a unified insulator layer <b>1</b>. In the insulating-material sheets, on the upper surface of one can also be a ready conductor-pattern layer, so that after pressing the circuit-board blank comprises at least two conductor-pattern layers, as shown by the series of figures. In this embodiment, conductor patterns <b>7</b> can, however, also be designed at the location of the components <b>9</b>.
0073Both in the example shown in the figure series and in the above described modification, it is next possible to make vias <b>13</b>, with the aid of which electrical contacts are made between the contact areas of the components <b>9</b> and the conductor patterns <b>6</b>. For the making of vias, the contact openings <b>8</b> are cleaned of adhesive and other materials that may have been pushed into them. In connection with the cleaning of the contact openings <b>8</b>, it is also possible to clean the contact areas of the components <b>9</b>, thus further improving the preconditions for making a high-quality electrical contact. The cleaning can be performed using, for example, a plasma technique, chemically, or with the aid of a laser. If the contact openings <b>4</b> and the contact areas are already sufficiently clean, the cleaning can naturally be omitted.
0074If the contact openings <b>8</b> were made to only partly penetrate, the contact openings <b>8</b> are opened in this stage. It is also possible to proceed in such a way that the contact openings <b>8</b> are made entirely in this stage.
0075After cleaning, it is also possible to examine the success of the alignment of the component <b>9</b>, as the contact areas of a correctly aligned component will be visible through the contact openings <b>8</b>, when viewed from the direction of the conductor pattern.
0076After this, a conductor material is introduced to the contact openings <b>8</b>, in such a way that it forms an electrical contact between the component <b>9</b> and the conductor pattern <b>6</b>. The conductor material of the vias <b>13</b> can be made, for example, by filling the contact openings <b>8</b> with an electrically conductive paste. The conductor material can also be made using one of several growing methods known in the circuit-board industry. High-quality electrical contacts can be made, for example, by forming a metallurgical connection by growing a conductor material using a surfacing method, for example, a chemical or electrochemical method. One good alternative is the growing of a thin layer using a chemical method and continuing the growing using a more economical electrochemical method. The term filling refers to the fact that the contact openings are at least substantially filled with the conductor material. Instead of filling, surfacing can also be performed in such a way that only the edges of the contact openings are surfaced. In addition to these methods, it is of course possible to also use some other method, which will be beneficial in terms of the end result.
0077In the example of the figure series, the contact openings <b>8</b>, the contact areas of the component <b>9</b>, and the conductor patterns <b>6</b> are surfaced first of all with a thin conductor layer and then afterwards the thickness of the conductor layer is increased electrolytically until the contact openings <b>8</b> are filled with conductor material. <figref idref="DRAWINGS">FIG. 7</figref> shows the structure after the growing. After this, the circuit-board blank is etched, to remove the excess conductor material. If a protective membrane is used on the surface of the conductor patterns <b>6</b> and <b>7</b>, the conductor material is removed essentially only from those parts of the conductor foils <b>2</b> and <b>3</b> that remain outside the conductor patterns <b>6</b> and <b>7</b>. Alternatively, it is possible to etch the entire conductor layer, so that the material of the conductor foils <b>2</b> and <b>3</b> is removed from outside the conductor patterns <b>6</b> and <b>7</b>. In that case, material of the conductor patterns <b>6</b> and <b>7</b> too will be removed, but the conductor patterns <b>6</b> and <b>7</b> will be copied into the material of the conductor foils <b>2</b> and <b>3</b>.
0078The series of <figref idref="DRAWINGS">FIGS. 9-16</figref> shows one variation of the examples described above. In the variation, the suitable parts of the method stages described above are utilized and the procedure is as follows: <ul id="ul0015" list-style="none"><li id="ul0015-0001" num="0000"><ul id="ul0016" list-style="none"><li id="ul0016-0001" num="0079">A circuit-board blank is made, which comprises an insulator layer <b>1</b>, a recess <b>4</b>, and conductor foils <b>2</b> and <b>3</b> (<figref idref="DRAWINGS">FIG. 9</figref>).</li><li id="ul0016-0002" num="0080">Photoresists <b>5</b> are spread and exposure takes place through the masks (<figref idref="DRAWINGS">FIG. 10</figref>). The exposed areas <b>5</b>′ are shown darkened in the figure.</li><li id="ul0016-0003" num="0081">Contact openings <b>8</b> are made (<figref idref="DRAWINGS">FIG. 11</figref>).</li><li id="ul0016-0004" num="0082">Adhesive <b>10</b> is spread (<figref idref="DRAWINGS">FIG. 12</figref>).</li><li id="ul0016-0005" num="0083">The component <b>9</b> is attached to the circuit-board blank with the aid of an adhesive layer <b>10</b> (<figref idref="DRAWINGS">FIG. 13</figref>) and the recess <b>4</b> is filled with a filler agent <b>12</b>.</li><li id="ul0016-0006" num="0084">The resist is developed, so that all that remains are the unexposed areas of the resist <b>5</b>. The contact openings <b>8</b> are cleaned. The circuit-board blank after these stages is shown in <figref idref="DRAWINGS">FIG. 14</figref>.</li><li id="ul0016-0007" num="0085">Conductor material is grown using an electrolytic method. The conductor material then grows in the openings of the resist <b>5</b> and the contact openings <b>8</b> are filled, thus forming both conductor patterns <b>6</b> and <b>7</b> and vias <b>13</b> (<figref idref="DRAWINGS">FIG. 15</figref>).</li><li id="ul0016-0008" num="0086">The resist <b>5</b> is removed and the conductor material is etched, so that the desired conductor pattern is separated from the conductor layer when the conductor material is removed from the areas between the conductor patterns (<figref idref="DRAWINGS">FIG. 16</figref>).</li></ul></li></ul>
0087In the embodiment shown in the series of <figref idref="DRAWINGS">FIGS. 9-16</figref> the conductor foils <b>2</b> and <b>3</b> are preferably thin relative to the conductor patterns <b>6</b> and <b>7</b> to be grown on their surfaces. The conductor foils <b>2</b> and <b>3</b> are thus intended to conduct the current required by the electrolytic growing to the growing areas. If the conductor foils <b>2</b> and <b>3</b> are thin relative to the conductor patterns <b>6</b> and <b>7</b>, the etching of the conductor foils <b>2</b> and <b>3</b> away from outside the conductor patterns <b>6</b> and <b>7</b> will not substantially affect the relative dimensions of the conductor patterns <b>6</b> and <b>7</b>.
0088The series of <figref idref="DRAWINGS">FIGS. 17-22</figref> shows a third variation of the examples described above. In the variation, suitable parts of the method stages described above are utilized and the procedure is as follows: <ul id="ul0017" list-style="none"><li id="ul0017-0001" num="0000"><ul id="ul0018" list-style="none"><li id="ul0018-0001" num="0089">A circuit-board blank is made, which comprises a conductor foil <b>2</b> and a conductor pattern <b>6</b> (<figref idref="DRAWINGS">FIG. 17</figref>). This can be made, for example, in such a way that a resist <b>5</b>, which is exposed and developed, is spread on top of the conductor foil <b>2</b>. After this, metal is grown in the openings formed in the resist <b>5</b>, for example, using an electrochemical method. In this variation, contact openings are also defined in the exposure mask of the resist, so that the resist will remain at the locations of the contact openings <b>8</b>′. Thus, in connection with the growing of the conductor pattern <b>6</b>, contact openings <b>8</b> are also formed in the conductor patterns <b>6</b>, and are thus aligned directly and in a self-aligning manner in the correct places relative to the conductor pattern <b>6</b>.</li><li id="ul0018-0002" num="0090">The resist is removed and the contact openings <b>8</b> are opened to also extend through the conductor foil <b>2</b> (<figref idref="DRAWINGS">FIG. 18</figref>).</li><li id="ul0018-0003" num="0091">The component <b>9</b> is glued onto the surface of the conductor pattern <b>6</b> with the aid of an adhesive <b>10</b> (<figref idref="DRAWINGS">FIG. 19</figref>). The component is aligned in the correct position relative to the conductor pattern <b>6</b> and the contact openings <b>8</b>.</li><li id="ul0018-0004" num="0092">An insulating-material layer <b>1</b> is made on top of the circuit-board blank (<figref idref="DRAWINGS">FIG. 20</figref>).</li><li id="ul0018-0005" num="0093">The contact openings <b>8</b> are cleaned and vias <b>13</b> are made in the contact openings from a conductor material (<figref idref="DRAWINGS">FIG. 21</figref>). In the example of the figure, the vias <b>13</b> are made using a surfacing method. In that case, the vias are surfaced in such a way that the necessary electrical contact arises, i.e. generally a conductor layer is made at least on the edges of the contact openings <b>8</b>. In the example of the figure, the contact openings <b>8</b> are grown full of the conductor material. The more conductor material is put into a via <b>13</b>, the better will be the conductivity of the via <b>13</b>. The vias <b>13</b> are indeed preferably made to be at least substantially filled with conductor material.</li><li id="ul0018-0006" num="0094">The conductor foil <b>2</b> is removed, for example, by etching (<figref idref="DRAWINGS">FIG. 22</figref>).</li></ul></li></ul>
0095The series of <figref idref="DRAWINGS">FIGS. 23-26</figref> shown a fourth variation of the examples described above. In the variation, suitable parts of the method stages described above are utilized and the procedure is as follows: <ul id="ul0019" list-style="none"><li id="ul0019-0001" num="0000"><ul id="ul0020" list-style="none"><li id="ul0020-0001" num="0096">A circuit-board blank is made, which comprises a conductor foil <b>2</b> and a conductor pattern <b>6</b> (<figref idref="DRAWINGS">FIG. 23</figref>). This can be made, for example, in such a way that a resist <b>5</b>, which is exposed and developed, is spread on top of the conductor foil <b>2</b>. After this, metal is grown in the openings formed in the resist <b>5</b>, for example, using an electrochemical method.</li><li id="ul0020-0002" num="0097">A component <b>9</b> is glued on top of the conductor pattern <b>6</b>, with the aid of an anisotropically conductive adhesive <b>20</b> (<figref idref="DRAWINGS">FIG. 24</figref>). The anisotropically conductive adhesive <b>20</b> forms an electrical contact in the direction between the contact areas of the component and the conductor pattern <b>6</b>. The adhesive <b>20</b> is, however, electrically insulating in the transverse direction, so that an electrical contact is not formed between the contact areas of the component, nor between the separate conductors of the conductor pattern <b>6</b>.</li><li id="ul0020-0003" num="0098">An insulating-material layer <b>1</b> is made on top of the circuit-board blank and on the surface of that a conductor foil <b>3</b> (<figref idref="DRAWINGS">FIG. 25</figref>).</li><li id="ul0020-0004" num="0099">The conductor foil <b>2</b> is removed, for example, by etching. The conductor foil <b>3</b> is patterned to form a conductor pattern <b>7</b> (<figref idref="DRAWINGS">FIG. 26</figref>).</li></ul></li></ul>
0100The series of <figref idref="DRAWINGS">FIGS. 27-32</figref> shows a fifth variation of the examples described above. In the method, suitable parts of the method stages described above are utilized, and the procedure is as follows: <ul id="ul0021" list-style="none"><li id="ul0021-0001" num="0000"><ul id="ul0022" list-style="none"><li id="ul0022-0001" num="0101">A circuit-board blank is made, which comprises a conductor foil <b>2</b> and a conductor pattern <b>6</b> (<figref idref="DRAWINGS">FIG. 27</figref>). This can be made, for example, in such a way that a resist <b>5</b>, which is exposed and developed, is spread onto top of the conductor foil <b>2</b>. After this, metal is grown in the openings formed in the resist <b>5</b>, for example, using an electrochemical method.</li><li id="ul0022-0002" num="0102">A second resist <b>15</b>, which is exposed and developed, is spread on top of the resist <b>5</b> and conductor pattern <b>6</b>. A conductor material is made in the opening formed in the resist <b>15</b>, for example, using an electrochemical method. The made conductor areas form contact bumps <b>17</b> on the surface of the conductor pattern <b>6</b> (<figref idref="DRAWINGS">FIG. 28</figref>).</li><li id="ul0022-0003" num="0103">The resists <b>5</b> and <b>15</b> are removed (<figref idref="DRAWINGS">FIG. 29</figref>).</li><li id="ul0022-0004" num="0104">A component <b>9</b> is attached on top of the conductor pattern <b>6</b> and against the contact bumps <b>17</b>, using a suitable method (<figref idref="DRAWINGS">FIG. 30</figref>). In the example of the figure, the joint is made by an ultrasonic bonding method or alternatively by a thermo-compression bonding method. In the example of the figure, a component <b>9</b> is used, which does not itself contain contact bumps.</li><li id="ul0022-0005" num="0105">An insulating-material layer <b>1</b> is made on top of the circuit-board blank, and a conductor foil <b>3</b> of top of that (<figref idref="DRAWINGS">FIG. 31</figref>).</li><li id="ul0022-0006" num="0106">The conductor foil <b>2</b> is removed, for example, by etching. The conductor foil <b>3</b> is patterned to form a conductor pattern <b>7</b> (<figref idref="DRAWINGS">FIG. 32</figref>).</li></ul></li></ul>
0107In the embodiments, it is possible to also use a separate support layer to support the conductor foil, or the conductor layer formed by the conductor foil and the conductor pattern.
0108A suitable intermediate layer, which will not dissolve in the etching agent used, or will dissolve in it extremely slowly, can also be used between the conductor foil and the conductor pattern, or on the surface of either of them. Thus the etching stops at the intermediate layer and the desired surface can be defined precisely. An intermediate layer of this kind can be made, for example, from some other metal, such as tin. If necessary, the intermediate layer can be removed, for example, chemically with some other etching agent.
0109When using a manufacturing method, in which the contact openings <b>8</b> are aligned and made after the manufacture of the conductor pattern <b>6</b>, the sensitivity of the method to alignment errors can be reduced by dimensioning the diameter of the contact openings <b>8</b> to be greater than the width of the conductors of the conductor pattern <b>6</b>.
0110There are numerous variations of the methods according to the examples presented above while the methods depicted by the examples can also be combined with each other. The variations can relate to individual process stages, or to the mutual sequence of the process stages.
0111Many features, which do not appear in the previous examples, can also be manufactured into the circuit-board structure. For example, in addition to vias that participate in the creation of electrical contacts, thermal vias can also be made, which are intended to conduct heat more efficiently away from the component <b>9</b>. The increase in the efficiency of heat conducting is based on the thermal conductivity of the thermal via being greater than that of the insulating material surrounding the component. As electrical conductors are typically also good thermal conductors, the thermal vias can in most cases be made using the same technique and even in the same process stage as the electrical contacts to the components <b>9</b>.
0112On the basis of the previous examples, it is obvious that the method can also be used for manufacturing many different kinds of three-dimensional circuit structures. The method can be used, for example, in such a way that several components, for example, semiconductor chips, are placed on top of each other, thus forming a packet containing several components, in which the components are connected to each other to form a single functional totality. Such a packet can be termed a three-dimensional multi-chip module.
0113The examples of the figures depict some possible processes, with the aid of which our invention can be exploited. However, our invention is not restricted to only the processes described above, but instead the invention covers various other processes too and their end products, within the full scope of the Claims and taking equivalence interpretation into account. The invention is also not restricted to only the structures and methods described by the examples, but instead it will be obvious to one versed in the art that various applications of our invention can be used to manufacture very many different kinds of electronic modules and circuit boards, which may even differ greatly from the examples presented. Thus the components and circuits of the figures are presented only with the intention of illustrating the manufacturing process. Many alterations can be made to the processes of the examples described above, while nevertheless not deviating from the basic idea according to the invention. The alterations can related, for example, to the manufacturing techniques depicted in the various stages, or to the mutual sequence of the process stages.
0114With the aid of the invention, it is also possible to manufacture component packets for attachment to a circuit board. Such packets can also contain several components, which are connected electrically to each other.
0115The method can also be used to manufacture entire electrical modules. The module can also be a circuit board, to the outer surface of which components can be attached, in the same way as to a conventional circuit board.
Contents6
9 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US10201095B2 | Cited by | United States of America | Search report |
| US9622354B2 | Cited by | United States of America | Search report |
| DE102015016196A1 | Cited by | Germany | Applicant |
| US2014059851A1 | Cited by | United States of America | Pre-grant |
| US9999136B2 | Cited by | United States of America | Applicant |
| US2024145258A1 | Cited by | United States of America | Search report |
| US11784063B2 | Cited by | United States of America | Search report |
| US2022044942A1 | Cited by | United States of America | Search report |
| US11792941B2 | Cited by | United States of America | Applicant |
| US2014063748A1 | Cited by | United States of America | Pre-grant |
| US2015250059A1 | Cited by | United States of America | Pre-grant |
| US9706637B2 | Cited by | United States of America | Search report |
| US2021358883A1 | Cited by | United States of America | Search report |
| US11134572B2 | Cited by | United States of America | Applicant |
| EP0774888A2 | Cites | European Patent Office (EPO) | Applicant |
| EP1111662A2 | Cites | European Patent Office (EPO) | Applicant |
| EP1156525A1 | Cites | European Patent Office (EPO) | Applicant |
| EP1542519A1 | Cites | European Patent Office (EPO) | Applicant |
| JP2000311229A | Cites | Japan | Applicant |
| JP2000349437A | Cites | Japan | Applicant |
| JP2001053447A | Cites | Japan | Applicant |
| JP2001274034A | Cites | Japan | Applicant |
| JP2001345560A | Cites | Japan | Applicant |
| US2002017711A1 | Cites | United States of America | Applicant |
| US2002053465A1 | Cites | United States of America | Applicant |
| US2002117743A1 | Cites | United States of America | Applicant |
| US2002133943A1 | Cites | United States of America | Applicant |
| US2002185303A1 | Cites | United States of America | Applicant |
| US2003067074A1 | Cites | United States of America | Applicant |
| US2003068852A1 | Cites | United States of America | Applicant |
| US2003068877A1 | Cites | United States of America | Applicant |
| US2003100142A1 | Cites | United States of America | Applicant |
| US2003137045A1 | Cites | United States of America | Applicant |
| US2003159852A1 | Cites | United States of America | Applicant |
| US2003209796A1 | Cites | United States of America | Applicant |
| US2003218249A1 | Cites | United States of America | Search report |
| US2004000710A1 | Cites | United States of America | Applicant |
| US2004068852A1 | Cites | United States of America | Applicant |
| US2004097086A1 | Cites | United States of America | Applicant |
| US2004266067A1 | Cites | United States of America | Applicant |
| US2005000729A1 | Cites | United States of America | Applicant |
| US2005001331A1 | Cites | United States of America | Applicant |
| US2005285244A1 | Cites | United States of America | Applicant |
| US2006105500A1 | Cites | United States of America | Applicant |
| US2006124345A1 | Cites | United States of America | Search report |
| US2006163740A1 | Cites | United States of America | Applicant |
| US2006278967A1 | Cites | United States of America | Applicant |
| US2007166886A1 | Cites | United States of America | Applicant |
| US2007267136A1 | Cites | United States of America | Applicant |
| US2008202801A1 | Cites | United States of America | Applicant |
| US2008295326A1 | Cites | United States of America | Applicant |
| US2010202115A1 | Cites | United States of America | Applicant |
| GB2342995A | Cites | United Kingdom | Applicant |
| US4246595A | Cites | United States of America | Applicant |
| US4731645A | Cites | United States of America | Applicant |
| US4993148A | Cites | United States of America | Applicant |
| US5042145A | Cites | United States of America | Applicant |
| US5048179A | Cites | United States of America | Applicant |
| US5081562A | Cites | United States of America | Applicant |
| US5216806A | Cites | United States of America | Applicant |
| US5227338A | Cites | United States of America | Applicant |
| US5248852A | Cites | United States of America | Applicant |
| US5306670A | Cites | United States of America | Applicant |
| US5353195A | Cites | United States of America | Applicant |
| US5355102A | Cites | United States of America | Applicant |
| US5407864A | Cites | United States of America | Applicant |
| US5497033A | Cites | United States of America | Applicant |
| US5510580A | Cites | United States of America | Applicant |
| US5552633A | Cites | United States of America | Applicant |
| US5633204A | Cites | United States of America | Applicant |
| US5637919A | Cites | United States of America | Applicant |
| US5654220A | Cites | United States of America | Applicant |
| US5838545A | Cites | United States of America | Applicant |
| US5840593A | Cites | United States of America | Applicant |
| US5870289A | Cites | United States of America | Applicant |
| US5882957A | Cites | United States of America | Applicant |
| US5936847A | Cites | United States of America | Applicant |
| US5985693A | Cites | United States of America | Applicant |
| US6037665A | Cites | United States of America | Applicant |
| US6038133A | Cites | United States of America | Applicant |
| US6084781A | Cites | United States of America | Applicant |
| US6154366A | Cites | United States of America | Applicant |
| US6232666B1 | Cites | United States of America | Applicant |
| US6242282B1 | Cites | United States of America | Applicant |
| US6271469B1 | Cites | United States of America | Applicant |
| US6284564B1 | Cites | United States of America | Applicant |
| US6292366B1 | Cites | United States of America | Applicant |
| US6396148B1 | Cites | United States of America | Applicant |
| US6402970B1 | Cites | United States of America | Applicant |
| US6475877B1 | Cites | United States of America | Applicant |
| US6489685B2 | Cites | United States of America | Applicant |
| US6537848B2 | Cites | United States of America | Applicant |
| US6538210B2 | Cites | United States of America | Applicant |
| US6551861B1 | Cites | United States of America | Applicant |
| US6562660B1 | Cites | United States of America | Applicant |
| US6576493B1 | Cites | United States of America | Applicant |
| US6607943B1 | Cites | United States of America | Applicant |
| US6701614B2 | Cites | United States of America | Applicant |
| US6710458B2 | Cites | United States of America | Applicant |
| US6713859B1 | Cites | United States of America | Applicant |
36 members in 9 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 20050646 | Finland | – | |
| 20050646 | Finland | A | |
| 2006000207 | Finland | W |
Members36
| Document | Office | Kind | |
|---|---|---|---|
| FI20050643A0 | Finland | A0 | |
| FI20050646A0 | Finland | A0 | |
| FI20050643A | Finland | A | |
| FI20050643L | Finland | L | |
| FI20050646A | Finland | A | |
| FI20050646L | Finland | L | |
| WO2006134216A2 | World Intellectual Property Organization (WIPO) | A2 | |
| WO2006134220A1 | World Intellectual Property Organization (WIPO) | A1 | |
| WO2006134216A3 | World Intellectual Property Organization (WIPO) | A3 | |
| GB0724097D0 | United Kingdom | D0 | |
| EP1891845A2 | European Patent Office (EPO) | A2 | |
| GB2441265A | United Kingdom | A | |
| DE112006001506T5 | Germany | T5 | |
| KR20080038124A | Republic of Korea | A | |
| CN101199244A | China | A | |
| CN101199246A | China | A | |
| US2008202801A1 | United States of America | A1 | |
| JP2008544510A | Japan | A | |
| JP2008544512A | Japan | A | |
| US2009014872A1 | United States of America | A1 | |
| FI119714B | Finland | B | |
| CN100596258C | China | C | |
| FI121134B | Finland | B | |
| KR101090423B1 | Republic of Korea | B1 | |
| GB2441265B | United Kingdom | B | |
| CN101199244B | China | B | |
| US8225499B2 | United States of America | B2 | |
| JP5025644B2 | Japan | B2 | |
| US8581109B2This record | United States of America | B2 | |
| US2014059851A1 | United States of America | A1 | |
| EP1891845B1 | European Patent Office (EPO) | B1 | |
| US2017071061A1 | United States of America | A1 | |
| US9622354B2 | United States of America | B2 | |
| US11134572B2 | United States of America | B2 | |
| US2021392752A1 | United States of America | A1 | |
| US11792941B2 | United States of America | B2 |
77 transactions on the USPTO file
Allowed after 2 non-final rejections, 2 final rejections and 2 RCEs.
- Non-final rejections
- 2
- Final rejections
- 2
- RCEs
- 2
- Appeals
- 0
Over time
Point at a mark for the transactionTransactions
| Event | Code | |
|---|---|---|
| Payment of Maintenance Fee, 12th Year, Large EntityM1553 | M1553 | |
| Payment of Maintenance Fee, 8th Year, Large EntityM1552 | M1552 | |
| Change in Power of Attorney (May Include Associate POA)PA.. | PA.. | |
| Correspondence Address ChangeC.AD | C.AD | |
| Recordation of Patent Grant MailedPGM/ | PGM/ | |
| Patent Issue Date Used in PTA CalculationAllowedPTAC | PTAC | |
| Email NotificationEML_NTR | EML_NTR | |
| Issue Notification MailedAllowedWPIR | WPIR | |
| Dispatch to FDCD1935 | D1935 | |
| Application Is Considered Ready for IssuePILS | PILS | |
| Issue Fee Payment VerifiedN084 | N084 | |
| Issue Fee Payment ReceivedIFEE | IFEE | |
| Email NotificationEML_NTR | EML_NTR | |
| Filing Receipt - CorrectedFLRCPT.C | FLRCPT.C | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Notice of AllowanceAllowedMN/=. | MN/=. | |
| Notice of Allowance Data Verification CompletedAllowedN/=. | N/=. | |
| Reasons for AllowanceEX.R | EX.R | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Disposal for a RCE / CPA / R129AbandonedABN9 | ABN9 | |
| Request for Continued Examination (RCE)RCEX | RCEX | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Workflow - Request for RCE - BeginBRCE | BRCE | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Final Rejection (PTOL - 326)Final rejectionMCTFR | MCTFR | |
| Final RejectionFinal rejectionCTFR | CTFR | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Date Forwarded to ExaminerFWDX | FWDX | |
| Response after Non-Final ActionA... | A... | |
| Request for Extension of Time - GrantedXT/G | XT/G | |
| Electronic ReviewELC_RVW | ELC_RVW | |
| Email NotificationEML_NTF | EML_NTF | |
| Mail Non-Final RejectionNon-final rejectionMCTNF | MCTNF | |
| Non-Final RejectionNon-final rejectionCTNF | CTNF | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| Case Docketed to Examiner in GAUDOCK | DOCK | |
| IFW TSS Processing by Tech Center CompleteTSSCOMP | TSSCOMP | |
| PG-Pub Issue NotificationPG-ISSUE | PG-ISSUE | |
| Application Dispatched from OIPEOIPE | OIPE | |
| Sent to Classification ContractorPGPC | PGPC | |
| Filing ReceiptFLRCPT.O | FLRCPT.O | |
| Notice of DO/EO Acceptance MailedM903 | M903 | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Oath or Declaration Filed (Including Supplemental)C602 | C602 | |
| Reference capture on IDSRCAP | RCAP | |
| Information Disclosure Statement (IDS) FiledM844 | M844 | |
| 371 Completion Date371COMP | 371COMP | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Cleared by OIPE CSRL194 | L194 | |
| IFW Scan & PACR Auto Security ReviewSCAN | SCAN | |
| Information Disclosure Statement consideredIDSC | IDSC | |
| Request for Foreign Priority (Priority Papers May Be Included)RQPR | RQPR | |
| Preliminary AmendmentA.PE | A.PE | |
| Electronic Information Disclosure StatementEIDS. | EIDS. | |
| Information Disclosure Statement (IDS) FiledWIDS | WIDS | |
| Initial Exam Team nnIEXX | IEXX |
29 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Maintenance fee paymentMAFP | MAFP | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| AssignmentAS | AS | |
| Fee paymentFPAY | FPAY | |
| Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP | FEPP | |
| AssignmentAS | AS | |
| Information on status: patent grantGrantedPATENTED CASESTCF | STCF | |
| AssignmentAS | AS | |
| AssignmentAS | AS |
Numbers
- Publication
- 8581109
- Application
- 11917737
Titles
- English
- Method for manufacturing a circuit board structure
Patent term adjustment
- A delay
- +600 daysthe office missed an examination deadline
- B delay
- +443 dayspendency past three years
- Overlap
- −63 daysdelays counted once
- Applicant delay
- −334 days
- Net adjustment
- 646 days
Classification
- CPC, 55
- H10W70/05
- H05K3/108
- H05K3/20
- H05K3/064
- H05K1/187
- H05K1/188
- H05K3/205
- H05K3/284
- H05K3/305
- H05K3/32
- H05K3/321
- H05K3/4069
- H05K2201/0355
- H05K2201/09563
- H05K2201/0969
- H05K2201/10674
- H05K2201/10977
- H05K2203/0353
- H05K2203/063
- H05K2203/0723
- H05K1/183
- Y10T29/4913
- Y02P70/50
- H10W74/019
- H10W70/68
- H10W70/614
- H10W46/00
- H10W72/07251
- H10W72/20
- H10W90/00
- H10W72/325
- H10W72/352
- H10W72/354
- H10W72/07223
- H10W72/241
- H10W72/072
- H10W72/07232
- H10W72/07233
- H10W72/07323
- H10W72/07236
- H10W72/073
- H10W72/074
- H10W72/00
- H10W46/601
- H10W72/9413
- H10W70/685
- H10W70/682
- H10W70/099
- H10W74/01
- H10W46/301
- H10W70/60
- H10W72/07332
- H10W72/07333
- H10W99/00
- H05K3/303
- IPC, 12
- H05K1 16
- H01L23 13
- H01L23 538
- H01L23 544
- H05K
- H05K1 18
- H05K3 20
- H05K3 28
- H05K3 30
- H05K3 32
- H05K3 40
- H10W74 01