Redundant signal transmission

BACKGROUND

0001A continuing demand for more compact electronic devices has contributed to the development of three-dimensional multi-chip packages, such as the system in package (SiP) and the chip-stack multi-chip module. In general terms, the multi chip package may include two or more integrated circuit dice that are vertically stacked, and a signal transmission network that electrically couples the dice within the three-dimensional multi-chip package. Accordingly, the multi-chip package may be configured to perform many functions of an electronic system. The reliability of such configurations may suffer when the signal transmission network fails.

BRIEF DESCRIPTION OF THE DRAWINGS

0002Various embodiments are described in detail in the discussion below and with reference to the following drawings.

0003<figref idref="DRAWINGS">FIG. 1</figref> is a diagrammatic block view of a redundant signal transmission system, according to various embodiments.

0004<figref idref="DRAWINGS">FIG. 2</figref> is a partial schematic view of a driver steering network, according to various embodiments.

0005<figref idref="DRAWINGS">FIG. 3</figref> is a partial schematic view of a receiver steering network, according to various embodiments.

0006<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart that describes a method of reconfiguring a signal transmission system, according to various embodiments.

0007<figref idref="DRAWINGS">FIG. 5</figref> is a diagrammatic block view of a processing system, according to various embodiments.

DETAILED DESCRIPTION

0008Various embodiments include processing systems, semiconductor modules, memory systems and methods. Specific details of several embodiments are set forth in the following description and in <figref idref="DRAWINGS">FIGS. 1 through 5</figref> to provide an understanding of such embodiments. One of ordinary skill in the art, however, will understand that additional embodiments are possible, and that many embodiments may be practiced without several of the details disclosed in the following description. It is also understood that various embodiments may be implemented within a physical circuit that includes physical components (e.g., “hardware”), or they may be implemented using machine-readable instructions (e.g., “software”), or in some combination of physical components and machine readable instructions (e.g., “firmware”).

0009In general, three-dimensional multi-chip modules, such as system-in package (SiP) and chip stack multi-chip modules include vertical stacks of semiconductor dice that may be internally communicatively coupled by a signal transmission network that extends between the dice in the module. Accordingly, the signal transmission network may include individual conductive elements that form a signal transmission path extending between a driver component and a receiving component. The conductive elements may include conductive wiring that extends between the dice, conductive vias that are integrally formed within the multi-chip module, and other known interconnection means. In any case, during fabrication of the multi-chip module, the signal transmission function of a signal transmission path may become inoperable due to the failure of the driver component and/or a receiver component coupled to a conductive element.

0010More generally, however, the conductive element may be physically interrupted due to a break, which may occur during fabrication. Accordingly, a break in a conductive element (or any of the previously discussed failures) may render the three-dimensional multi-chip module inoperable. Since the module is a complex assembly that entails a number of separate processing steps, discarding the defective module is costly, and generally increases the per-unit cost of the multi-chip module. The inventor has made the discovery that redundant components may be introduced into the multi-chip module, permitting additional signal transmission paths to be utilized. Consequently, multi-chip modules having one or more signal transmission path defects may still be employed as functional devices when such redundant components are used.

0011<figref idref="DRAWINGS">FIG. 1</figref> is a diagrammatic block view of a redundant signal transmission system <b>10</b>, according to one or more of the embodiments. As a preliminary matter, the redundant signal transmission system <b>10</b> may be employed in a general or specialized processing system, a memory system, including one or more discrete memory devices, such as a static memory, a dynamic random access memory (DRAM), an extended data out dynamic random access memory (EDO DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a double data rate two synchronous dynamic random access memory (DDR2 SDRAM), a double data rate three synchronous dynamic random access memory (DDR3 SDRAM), a synchronous link dynamic random access memory (SLDRAM), a video random access memory (VRAM), a RAMBUS dynamic random access memory (RDRAM), a static random access memory (SRAM), a flash memory, as well as other known memory devices.

0012The system <b>10</b> is configured to communicate a data input <b>12</b> that includes data signals D<0> through D<7> to a data output <b>14</b>. The data signals D<0> through D<7> may be transmitted along a transmission network <b>16</b> that includes data lines L<0> through L<7>, and data lines LR and RR. In the various embodiments, the data lines L<0> through L<7>, and data lines LR and RR may comprise metallic wiring extending between dice within a vertically-stacked, multi-chip package. Alternatively, the data lines L<0> through L<7>, and data lines LR and RR may comprise conductive, silicon-based vias that extend at least partially through the vertically-stacked, multi-chip package. The system <b>10</b> also includes a driver network <b>18</b> that is operable to drive the data signals D<0> through D<7> onto the data lines L<0> through L<7>, LR and RR, and a receiver network <b>20</b> that is operable to receive the data signals D<0> through D<7> communicated along the data lines L<0> through L<7>, LR and RR.

0013The system <b>10</b> also includes a steering control network <b>22</b> that receives an error signal through an ERR<0:9> signal bus. In general terms, the error signals transmitted along the ERR<0:9> signal bus may be generated by a detection apparatus (not shown in <figref idref="DRAWINGS">FIG. 1</figref>) that is configured to detect a fault in the transmission network <b>16</b>. For example, in the various embodiments, the detection apparatus may be configured to detect a loss of electrical continuity (e.g., a break) in one or more of the data lines L<0> through L<7>, LR and RR, and generate the corresponding error signal that may be sent along the ERR<0:9> bus. In the various embodiments, the detection apparatus may be configured to detect repeated requests to resend a selected signal, and generate an error signal on the ERR<0:9> bus that reflects an inoperable transmission path when a selected number of requests has been exceeded. In some embodiments, the detection apparatus includes programmable elements that may be set during manufacture, such as anti-fuses, or other similar programmable elements.

0014As shown in <figref idref="DRAWINGS">FIG. 1</figref>, when a selected one of the bits on the ERR<0:9> bus is low (e.g., the bit on the corresponding line is ‘0’), the corresponding transmission path is operable. Correspondingly, if a selected one of the bits on the ERR<0:9> bus is high (e.g., the bit on the corresponding line is ‘1’), the corresponding transmission path is not operable. It is understood, however, that in the various embodiments, opposing logic may be employed, so that if a selected bit on the ERR<0:9> bus is high, the corresponding transmission path is operable, and if the selected bit on the ERR<0:9> bus is low, the corresponding transmission path is inoperable.

0015The steering control network <b>22</b> may be configured to translate the signals on the ERR<0:9> bus to one of several steering buses SL<0:7>, SC<0:7> and SR<0:7>, such that it causes all of the signals to be steered towards the available redundant and away from the inoperable path. Accordingly, the steering control network <b>22</b> may be operably implemented using known combinations of logic devices that may be configured to communicate the signals from the ERR<0:9> bus to the steering buses. For example, various known multiplexing circuits, such as, without limitation, 3×1 multiplexer, or other functionally similar devices may be used. The steering buses SL<0:7>, SC<0:7> and SR<0:7> are communicatively coupled to a steering network <b>24</b>, and are configured to communicate data steering information to the steering network <b>24</b>. Briefly, and in general terms, the steering bus SL<0:7> may be configured to direct data away from an inoperable data path and onto another data path that is immediately adjacent and to the left of the inoperable data path. It is understood that when the data is directed from the inoperable path and to the data path that is immediately adjacent and to the left of the inoperable path, all other data to the left of the inoperable path is shifted to the left, while data paths to the right of the inoperable path are not shifted. Additionally, the steering bus SR<0:7> may be configured to direct data away from an inoperable data path and onto a data path that is immediately adjacent and to the right of the inoperable data path. Consequently, when the data is directed from the inoperable path and onto the data path that is immediately adjacent and to the right of the inoperable path, all other data to the right of the inoperable path is shifted to the right. Data paths to the left of the inoperable path are not shifted. The steering bus SC<0:7>, in contrast, may permit data to be communicated along an originally intended path (e.g., without rerouting the data signal).

0016The steering network <b>24</b> includes logic elements that are responsive to the signals received from the steering control network <b>22</b>. Accordingly, when one of the data lines L<0> through L<7>, or an element within the driver network <b>18</b> and/or the receiver network <b>20</b> are determined to be inoperable, the steering network <b>24</b> directs a selected one of the data input <b>12</b> signals (e.g., D<0> through D<7>) onto an operative and adjacent one of the data lines L<0> through L<7>, LR, RR. For example, and in accordance with the various embodiments, if the steering network <b>24</b> is configured by default to direct data to the left adjacent data line, and if the bit on the ERR<0:9> corresponding to L<0> is high, the data<0> signal is directed to the LR data line, while all other data transmitted on lines to the right of the L<0> line are unaffected (e.g., not shifted). If the bit on the ERR<0:9> corresponding to L<1> is high, the data<1> signal is directed to the L<0> data line, and the data<0> is directed to the LR line. All of the data transmitted on lines to the right of the L<1> are unaffected. Alternatively, if the steering network <b>24</b> is configured by default to direct data to the right adjacent data line, and if the bit on the ERR<0:9> corresponding to L<7> is high, the data <7> signal is directed to the RR data line, and all other data transmitted on lines to the left of the L<7> are also shifted. If the bit on the ERR<0:9> corresponding to L<6> is high, the data<6> signal is directed to the L<7> data line, and the data<7> is shifted to the right, and onto RR. The data transmitted on lines to the left of the L<6> is not shifted. It is understood that the steering network <b>24</b> may be configured to steer signals by default to the left or to the right. It is also understood that if two of the data lines L<0> through L<7> are defective, either through a physical break in two of the L<0> through L<7> data lines, or due to other defects, then signals may be steered simultaneously to both the left and to the right. In this case, the signals may be directed towards the nearest one of the redundant lines (e.g., LR and RR). For example, if the L<1> and the L<5> lines are determined to be inoperative, data <1> is shifted onto the L<0> line, and the data <0> is shifted onto the LR line. Correspondingly, the data <5> may be shifted to the L<6> line, data <6> may be shifted to the L<7> line, and data <7> may be shifted to RR. Data communicated on other lines (e.g., L<2> through L<4>) is not shifted.

0017The system <b>10</b> may also include a steering control network <b>26</b> and a receiver steering network <b>28</b>. The receiver steering network <b>28</b> may be operably coupled to the receiver network <b>20</b> and configured to direct signals received from the transmission network <b>16</b> (e.g., from the data lines L<0> through L<7>, and the data lines LR and RR) to provide the data output <b>14</b>. The steering control network <b>26</b> is configured to communicate with the ERR<0:9> bus, and to communicate with steering buses SL<0:7>, SC<0:7> and SR<0:7>. Accordingly, if data has been shifted away from an inoperable line by the driver steering network <b>24</b>, as discussed in detail above, the receiver steering network <b>28</b> is configured to shift the data back to the intended data paths. For example, if the system <b>10</b> is configured to shift to the left, by default, and if the L<0> line is inoperable, the driver steering network <b>24</b> directs D<0> to the line LR. The receiver steering network <b>28</b> then directs data on the line LR back onto the intended data path. In the various embodiments, the steering control network <b>26</b> may be implemented using various known combinations of logic devices, such as a multiplexer or other functionally similar devices.

0018Although <figref idref="DRAWINGS">FIG. 1</figref> shows the steering control network <b>22</b>, the driver steering network <b>24</b> and the driver network <b>18</b> as separate elements, it is understood that in various embodiments, the steering control network <b>22</b>, the driver steering network <b>24</b> and the driver network <b>18</b> may be incorporated into one or more elements having the previously-described functionality. Correspondingly, the steering control network <b>26</b>, the receiver steering network <b>28</b> and the receiver network <b>20</b> may also be incorporated into one or more elements having the previously-described functionality. It is also understood that the signals SL<0:7>, SC<0:7> and SR<0:7> provided by the steering control network <b>22</b> and the steering control network <b>26</b> may be alternatively provided by a single unit.

0019With reference now to <figref idref="DRAWINGS">FIG. 2</figref>, the driver steering network <b>24</b>, according to the various embodiments, will now be described in greater detail. In general, the driver steering network <b>24</b> may include a first driver logic unit <b>32</b> that is configured to appropriately drive the LR data line. Accordingly, the first driver logic unit <b>32</b> may include AND logic gates <b>34</b> that are coupled to a three-input OR gate <b>36</b>. The output of the three-input OR gate <b>36</b> is in a logic high state if any one of the inputs (e.g., the outputs from the AND logic gates) is in a logic high state. Inputs to a first selected one of the AND logic gates <b>34</b> may be coupled to a ground potential (GND), which may correspond to a logic low state, so that the output of the first selected one of the AND logic gates <b>34</b> is a low logic state. Inputs to a second selected one of the AND logic gates <b>34</b> may be coupled to GND so that the second selected one of the AND logic gates is also in a logic low state. Inputs to a third selected one of the AND logic gates <b>34</b> may be coupled to the signals SL<0> and D<0>. Accordingly, if the SL<0> signal is asserted, the third selected one of the AND logic gates <b>34</b> transmits the D<0> logic state, so that the D<0> signal is output to the LR path through the OR gate <b>36</b>.

0020The driver steering network <b>24</b> may also include intermediate driver logic units <b>38</b> that are configured to appropriately drive the intermediate data lines (e.g., the L<0> through L<7> data lines). The intermediate driver logic unit <b>38</b> may include AND logic gates <b>34</b> and may also include a three-input OR gate <b>36</b> that is coupled to the AND logic gates <b>34</b>. The intermediate driver logic unit <b>38</b> may be configured to successively route the data signals D<i> onto the next adjacent data line, if an intended data line is inoperable. For example, if the data line L<1> is inoperable, then the data signal D<1> may be routed to a selected one of the operable adjacent data lines (e.g., to the data line L<0> or to the data line L<2>). In the various embodiments, the driver steering network <b>24</b> may be configured in a default-to-the-left configuration, so that if a data line is inoperable, the data line to the immediate left of the inoperable data line is selected. Alternatively, the driver steering network <b>24</b> may be configured in a default-to-the-right configuration, so that if a data line is inoperable, the data line to the immediate right of the inoperable data line is selected.

0021The driver steering network <b>24</b> may also include a second driver logic unit <b>40</b> that is configured to appropriately drive the RR data line. The second driver logic unit <b>40</b> may include AND logic gates <b>34</b> and may also include a three-input OR gate <b>36</b> that is coupled to the AND logic gates <b>34</b>. The second driver logic unit <b>40</b> may be configured to route the data signal D<7> onto the RR data line, and if the SR<7> signal is asserted, the D<7> data signal is output to the RR path. Accordingly, the first driver logic unit <b>32</b>, the intermediate driver logic units <b>38</b> and the second driver logic unit <b>40</b> collectively permit an inoperable data line to be avoided by shifting a selected data signal D<0:7> away from the inoperable line and onto the next immediately adjacent line. Since the affected data signal D<0:7> is routed to the adjacent line, the additional signal path length introduced by the signal rerouting is minimized, so that signal transmission speeds through the redundant signal transmission system <b>10</b> are not adversely affected.

0022While a specific configuration of signals and logic gates has been shown in <figref idref="DRAWINGS">FIG. 2</figref>, it should be noted that other configurations are possible. That is, gates with a different number and type of inputs may be used, and different combinations of signals may be presented to these gates. Any combination of gates and signals that enables steering signals away from inoperable transmission paths can be used in the various embodiments. In the foregoing discussion, it is understood that the first driver logic unit <b>32</b> and the second driver logic unit <b>40</b> are coupled to respective left and right portions of the transmission network <b>16</b> (e.g., LR and RR in <figref idref="DRAWINGS">FIG. 1</figref>, respectively) while intermediate driver logic units <b>38</b> are coupled to the intermediate portions of the transmission network <b>16</b> (e.g., L<0> through L<7> in <figref idref="DRAWINGS">FIG. 1</figref>).

0023Turning now to <figref idref="DRAWINGS">FIG. 3</figref>, the receiver steering network <b>42</b>, according to the various embodiments, will now be described in greater detail. The receiver steering network <b>42</b> is controllably coupled to the ER<0:9> signal bus through the steering control network <b>26</b> (as shown in <figref idref="DRAWINGS">FIG. 1</figref>). Accordingly, and in general terms, the receiver steering network <b>42</b> is operable to route all data signals that were redirected by the driver steering network <b>24</b> away from an inoperable signal path back to the intended signal paths. The receiver steering network <b>42</b> may therefore include a first receiver logic unit <b>44</b>, an intermediate receiver logic unit <b>50</b> and a second receiver logic unit <b>52</b>, which may further include AND logic gates <b>46</b> having outputs that are coupled to three-input OR gates <b>48</b>.

0024The first receiver logic unit <b>44</b> may be configured to pass the data signal carried on the L<0> data line to the D<0> data line in the data output <b>14</b> (<figref idref="DRAWINGS">FIG. 1</figref>) provided that the SC<0> signal is asserted. If the D<0> data has been redirected to the LR data line by the driver steering network <b>24</b>, then SL<0> is asserted also, and the D<0> data is output from the first receiver logic unit <b>44</b>. If the D<0> data has been redirected to the L<1> data line, then SR<0> is also asserted, and the D<0> data is output from the first receiver logic unit <b>44</b>.

0025The intermediate receiver logic unit <b>50</b> may be configured to pass the data signals carried on the L<i> data lines to the D<i> data lines in the data output <b>14</b>, where L<i> includes the L<1> through L<6> data lines (as shown in <figref idref="DRAWINGS">FIG. 1</figref>). Accordingly, if the SC<i> signal is asserted, the data on the L<i> data line is communicated to the three-input OR gate <b>48</b>, and output from the intermediate receiver logic unit <b>50</b>. If the D<i> data has been redirected to the L<i−1> data line, then SL<i> is asserted also, and the D<i> data is output from the first receiver logic unit <b>50</b>. If the D<i> data has been redirected to the L<i+1> data line, then when SR<i> is also asserted, then the D<i> data is output from the intermediate receiver logic unit <b>50</b>.

0026The second receiver logic unit <b>52</b> may be configured to pass the data signal carried on the L<7> data line to the D<7> data line in the data output <b>14</b> (<figref idref="DRAWINGS">FIG. 1</figref>). Accordingly, when the SC<7> is asserted, the data on the L<7> data line is communicated to the three-input OR gate <b>48</b>, and output from the second receiver logic unit <b>52</b>. If the D<7> data has been redirected to the L<6> data line, then SL<7> is asserted also, and the D<7> data is output from the second receiver logic unit <b>52</b>. If the D<7> data has been redirected to the RR data line, then SR<7> is also asserted, the D<7> data is output from the second receiver logic unit <b>52</b>.

0027While a specific configuration of signals and logic gates has been shown in <figref idref="DRAWINGS">FIG. 3</figref>, it should be noted that other configurations are possible. That is, gates with a different number and type of inputs may be used, and different combinations of signals may be presented to these gates. Any combination of gates and signals that enables steering signals toward operative transmission paths can be used in the various embodiments.

0028<figref idref="DRAWINGS">FIG. 4</figref> is a flowchart that will be used to describe a method <b>54</b> of configuring a signal transmission system according to the various embodiments. Referring now to <figref idref="DRAWINGS">FIGS. 1 and 4</figref>, it can be seen that at block <b>56</b>, a check of all signal paths may be made to determine if any signal path is inoperable. For example, the signal path may be inoperable due to a physical interruption (e.g., a ‘break’) in a line within the transmission network <b>16</b>. The signal path may also be inoperable due to a failure within one or both of the driver network <b>18</b> and the receiver network <b>20</b>, or within other elements associated with the transmission network <b>16</b>. In various embodiments, the signal paths may be checked using a diagnostic apparatus and/or software that tests the integrity of the signal paths when energy is applied to a system that includes the data transmission system <b>16</b>. Alternatively, and in accordance with the various embodiments, the check may be conducted continuously while the system <b>10</b> is in operation (e.g., “dynamically”). In still other of the various embodiments, the signal path check may be accomplished by counting resend requests received while sending data on the signal paths, and when a predetermined maximum number of resent requests have been generated, determining that the signal path is inoperable. Alternatively, the check of the signal paths may be conducted during a functional verification test that may occur during production of a device that includes the data transmission system <b>16</b>. In this case, at least one of the steering control network <b>22</b> and the driver steering network <b>24</b>, and at least one of the steering control network <b>26</b> and the receiver steering network <b>28</b> may be configured to permanently reconfigure the signal transmission system <b>16</b>, using antifuses or other similar devices operable to permanently reconfigure circuits, or at least to reconfigure them in a nonvolatile manner.

0029In any case, at block <b>58</b>, an error corresponding to the signal path determined to be defective is generated. The error may be transferred to the steering control network <b>22</b> coupled to the driver steering network <b>24</b>, and to the steering control network <b>26</b> that is coupled to the receiver steering network <b>28</b>. The error may be used to permanently program at least one of the steering control network <b>22</b> and the driver steering network <b>24</b>, and at least one of the steering control network <b>26</b> and the receiver steering network <b>28</b>, by programming antifuses in the foregoing networks, as discussed above. Alternatively, the error may be used to reconfigure the signal transmission system, perhaps in a nonvolatile manner, without permanently altering elements within the steering control network <b>22</b>, the driver steering network <b>24</b>, the steering control network <b>26</b> and the receiver steering network <b>28</b>.

0030At block <b>60</b>, an alternate signal path adjacent to the inoperative signal path is selected in response to the generated error. At the same time, all of the signal paths located on a selected side of the inoperative signal path are shifted also. For example, if a default left configuration is employed, then all signals to the left of the inoperative path are successively shifted to the next signal path to the left. If a default right configuration is used, then all signals to the right of the inoperative path are successively shifted to the next signal path to the right. Accordingly, when an inoperable signal path is detected, the data signal is routed away from the inoperable path and onto the transmission path adjacent to the inoperable path. In the various embodiments, the reconfiguration may default to the transmission path to the left of the inoperable signal path, or the reconfiguration may default to the signal path to the right of the inoperable signal path. In still other of the various embodiments, the transmission system <b>10</b> may select a signal path to the left or to the right of the inoperable signal path. Alternative paths above and below the inoperable path may be used as well. That is, the absolute physical location of the selected alternate path can be just about anywhere in space relative to the location of the inoperable path in most embodiments, as long as the alternate path is an operable one. If multiple alternate, operable paths exist, then the alternate, operable path having better signal transmission characteristics than the other existing alternate, operable paths (e.g., shorter length, better resonance, or higher density, etc.) may be selected. As earlier discussed, the various embodiments may also address situations where two of the data lines L<0> through L<7> are defective. Signals may be steered simultaneously to both the left and to the right, so that the signals may be directed towards the nearest one of the redundant lines (e.g., LR and RR).

0031At block <b>62</b>, the signal may be transferred along the alternate signal path while shifting all signals to the left or to the right of the inoperative signal path. At block <b>64</b>, the system may be directed to transfer all of the shifted signals to the originally intended signal paths. For example, if the D<0> signal is shifted to the LR signal path due to an inoperable L<0> path (<figref idref="DRAWINGS">FIG. 1</figref>), the transmission system is reconfigured to redirect the D<0> data signal back to the intended path. In addition, the signals that were shifted to the left or to the right of the inoperative signal path may be restored to the previously intended signal paths.

0032<figref idref="DRAWINGS">FIG. 5</figref> is a diagrammatic block view of a processing system <b>70</b> according to various embodiments. The processing system <b>70</b> may include a central processing unit (CPU) <b>72</b>, which may include any digital device capable of receiving data and programmed instructions, and processing the data according to the programmed instructions. Accordingly, the CPU <b>72</b> may include a microprocessor, such as a general purpose single-chip, or a multi-chip microprocessor. In particular, the multi-chip microprocessor may be structured as a three-dimensional multi-chip package, such as a system in package (SiP), or a chip stack multi-chip module (MCM) the chip-stack multi-chip module, and may include one or more of the redundant signal transmission systems, according to one or more of the embodiments, such as, for example, the redundant signal transmission system <b>10</b> of <figref idref="DRAWINGS">FIG. 1</figref>. The CPU <b>72</b> is generally configured to communicate with a memory unit <b>74</b> over a suitable communications bus <b>76</b>. The memory unit <b>74</b> may also be structured as a three-dimensional multi-chip package, and may include one or more of the redundant signal transmission systems, according to one or more of the embodiments. The processing system <b>70</b> may also include various other devices that are operably coupled to the bus <b>76</b>, which are configured to cooperatively interact with the CPU <b>72</b> and the memory unit <b>74</b>. For example, the processing system <b>70</b> may include one or more input/output (I/O) devices <b>78</b>, such as a printer, a display device, a keyboard, a mouse, or other known input/output devices. The processing system <b>70</b> may also include a mass storage device <b>80</b>, which may include a hard disk drive, a floppy disk drive, an optical disk device (CD-ROM), or other similar devices. It is understood that <figref idref="DRAWINGS">FIG. 5</figref> provides a simplified representation of the processing system <b>70</b>. Accordingly, it is understood that other devices not shown in <figref idref="DRAWINGS">FIG. 5</figref>, but known in the art (such as, for example, a memory controller, and other similar devices) may nevertheless be present in the processing system <b>70</b>. As the various figures have shown, there may be multiple local paths and global paths in a memory system.

0033The processing system <b>70</b> may also form a part of other larger systems, such as a wireless device, which may include devices such as a wireless telephone, a personal digital assistant (PDA), or another of a variety of known wireless devices.

0034While various embodiments have been illustrated and described, as noted above, changes can be made without departing from the disclosure. The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, various embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom. This Detailed Description, therefore, is not to be taken in a limiting sense.

0035Although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the various embodiments shown. Furthermore, although the various embodiments have described redundant signal transmission systems, it is understood that the various embodiments may be employed in a variety of known electronic systems and devices without modification. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those skilled in the art upon reviewing the above description.

0036The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features may be grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.