US8558522B2

Method for scaling a drive signal and circuit therefor

Summary by NHIP

Power supply drive signal scaling

The method scales a drive circuit supply signal based on measured input or output converter power. It generates a product signal by multiplying sensed current and voltage, then limits this signal before adjusting the supply voltage.

Claim Score by NHIP

Read claim 12, the broadest

Abstract

In accordance with an embodiment, a converter includes a circuit and method for scaling a drive signal. The converter determines the power at its input and scales a drive signal in accordance with the input power. In accordance with another embodiment the converter determines the power at its output and scales the drive signal in accordance with the output power.

US8558522B2, drawing sheet 1 — Sheet 1 of 3

Term

5 yearsleft in the term

Expires 6 October 2031, including 292 days of term adjustment.

20 claims: 3 independent, 17 dependent

1
A method for scaling a drive signal suitable for use in a power supply, comprising:providing a converter having an input and an output;determining an input power or an output power of the converter;and scaling a supply signal of a drive circuit in the converter in response to the input power or the output power to generate a scaled supply signal, the drive circuit comprising a first driver device having first and second supply terminals and a second driver device having first and second terminals, the scaled supply signal coupled to the first supply terminal of the first driver device and to the first supply terminal of the second driver device.
12
Broadest claimClaim Score 66, broad(NHIP)A method for adjusting a signal, comprising:providing a converter having an input and an output;determining power at the input or power at the output of the converter;generating a scaling signal in accordance with the power at the input or the power at the output of the converter;and using the scaling signal to adjust a drive signal of a circuit in the converter to generate an adjusted drive signal, the circuit comprising a first driver device having first and second supply terminals and a second driver device having first and second supply terminals, the adjusted drive signal coupled to the first supply terminal of the first driver and to the first supply terminal of the second driver.
17
A circuit, comprising:a drive circuit comprising first and second driver devices, each driver device having first and second supply input terminals and an output terminal;a scaling circuit having first and second input terminals and an output terminal, the scaling circuit configured to provide a scaled supply signal to the first and second driver devices and the output terminal coupled to the first supply input terminals of the first and second driver devices;a multiplier circuit having first and second input terminals and an output terminal, the output terminal of the multiplier circuit coupled to the first input terminal of the scaling circuit;a first buffer circuit having first and second input terminals and an output terminal, the output terminal of the first buffer circuit coupled to the first input terminal of the multiplier circuit;a second buffer circuit having an input terminal and an output terminal, the output terminal of the second buffer circuit coupled to the second input terminal of the multiplier circuit;and a resistor having first and second terminals, the first terminal of the resistor coupled to the first input terminal of the first buffer circuit and to the input terminal of the second input circuit, and the second terminal of the resistor coupled to the second input terminal of the first buffer circuit.

Independent claims3

27 paragraphs in 3 sections, as filed

BACKGROUND

The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure.

In the past, the semiconductor industry used power supplies that maintained a constant Direct Current (DC) output voltage even though the load current or the input voltage may have changed. For switching power supplies, this has led to switching and efficiency losses when operating at low and high load currents. Circuitry for improving the efficiencies under different current loads have been disclosed in U.S. Pat. No. 7,615,940 B2 issued to Weihong Qiu et al. on Nov. 10, 2009, and in U.S. Pat. No. 7,847,531 B2 issued to Weihong Qiu et al. on Dec. 7, 2010. A drawback with these techniques is that they only consider one aspect of the inefficiencies.

Accordingly, it would be advantageous to have a method and circuit that enables scaling a drive signal. It would be of further advantage for the method and circuit to be cost efficient to implement.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:

<figref idrefs="DRAWINGS">FIG. 1</figref> is a circuit schematic of a converter in accordance with an embodiment of the present invention; and

<figref idrefs="DRAWINGS">FIG. 2</figref> is circuit schematic of a converter in accordance with an embodiment of the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.

It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic zero voltage may be thirty percent of the power supply voltage level. In a five volt Translator-Translator Logic (TTL) system a logic zero voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.

DETAILED DESCRIPTION

Generally, the present invention provides a method for scaling a drive signal and a converter for scaling the drive signal. In accordance with an embodiment, a converter circuit having gate drive circuitry suitable for driving power transistors is provided. The supply voltage to the gate drive circuitry is scaled or adjusted in accordance with the power at the input of the converter. In response to a heavy load and in accordance with the power at the input of the converter the gate drive voltage is increased and in response to a light load and in accordance with the input power of the converter the gate drive voltage is decreased.

<figref idrefs="DRAWINGS">FIG. 1</figref> is a circuit schematic of a DC to DC converter 10 in accordance with an embodiment of the present invention. DC to DC converter 10 includes a controller 12 coupled to a drive circuit 14 which drives switching devices 16 and 18. Drive circuit 14 has upper supply terminals 14AU and 14BU coupled for receiving operating power from a voltage scaling circuit 20. More particularly, drive circuit 14 includes driver devices 14A and 14B, where driver device 14A drives switching device 16, driver device 14B drives switching device 18, and each driver device 14A and 14B receives a control signal from controller 12. Switching devices 16 and 18 may be field effect transistors such as, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), bipolar junction transistors, junction field effect transistors, or the like, where each device has a control conductor and current carrying conductors. In accordance with an embodiment in which switching devices 16 and 18 are power MOSFETs, the control conductor is a gate electrode or terminal, one of the current carrying conductors is a drain electrode or terminal, and the other current carrying conductor is a source electrode or terminal. Thus, an output terminal of driver device 14A is connected to the gate terminal of power MOSFET 16 and an output terminal of driver device 14B is connected to the gate terminal of power MOSFET 18. The drain terminal of power MOSFET 16 is connected to an output terminal 22 of voltage scaling circuit 20 and the source terminal of power MOSFET 16 is connected to the drain terminal of power MOSFET 18 to form a switching node 17. Lower supply terminal 14AL of switching device 14A is connected to switching node 17. The source terminal of power MOSFET 18 is coupled for receiving a source of operating potential such as, for example, VSS. Operating potential VSS may be, for example, a ground potential. An inductor 60 has a terminal 60A connected to switching node 17 and a terminal 60B. A load capacitor 62 is coupled in parallel with a load resistor between terminal 60B of inductor 60 and source of operating potential VSS.

In accordance with an embodiment, scaling circuit 20 comprises a resistor 24, buffer amplifiers 26 and 28, multiplier 30, a limiter 32, a voltage follower 36, and a diode 38. Optionally, scaling circuit 20 may include an offset voltage 40 and a filter capacitor 42. It should be noted that controller 12, drive circuit 14, and scaling circuit 20 may be monolithically integrated into the same semiconductor material. Buffer amplifier 26 has an inverting input terminal, a noninverting input terminal and an output terminal and buffer amplifier 28 has an input terminal and an output terminal. Resistor 24 has a terminal 24A connected to the inverting input terminal of buffer amplifier 26 and a terminal 24B connected to the noninverting input terminal of buffer amplifier 26. The connection of the inverting input terminal of buffer amplifier 26 and terminal 24A of resistor 24 form output terminal 22 of scaling circuit 20. The input terminal of buffer amplifier 28 is connected to the noninverting input terminal of buffer amplifier 26 and to terminal 24B of resistor 24.

Multiplier 30 has an input terminal connected to the output terminal of buffer amplifier 26 and an input terminal connected to the output terminal of buffer amplifier 28 through a voltage source 40, which voltage source 40 provides an offset in response to output voltage VOUT being zero. Voltage source 40 is an optional element. Limiter circuit 32 has an input terminal connected to the output terminal of multiplier 30 and an output terminal connected to an input terminal of voltage follower 36. It should be noted that limiter circuit 32 can introduce an offset voltage in the event that the product of multiplier 30 is zero. Because limiter circuit 32 can introduce the offset voltage, voltage source 40 can be optional.

Voltage follower 36 comprises an operational amplifier 50 connected to a field effect transistor 52. Operational amplifier 50 has a noninverting input terminal, an inverting input terminal and an output terminal, and field effect transistor 52 has a control electrode and current carrying electrodes. As discussed above, the control electrode may be referred to as a gate terminal, a gate electrode, or a gate conductor; one of the current carrying electrodes may be referred to as a drain terminal, a drain electrode, or a drain conductor; and the other current carrying electrode may be referred to as a source terminal, a source electrode, or a source conductor. The noninverting input terminal of operational amplifier 50 is connected to the output terminal of limiter 32 and the inverting input terminal is connected to the source terminal of field effect transistor 52. The gate terminal of field effect transistor 52 is connected to the output terminal of operational amplifier 50 and the drain terminal of field effect transistor 52 is connected to an input node 55, which node 55 is coupled for receiving a potential V1. It should be noted that potential V1 can be a system input voltage or a source of operating potential such as, for example, VCC. Connecting the inverting input terminal of operational amplifier 50 to the source terminal of field effect transistor 52 forms an output terminal 53. Output terminal 53 is connected to an upper supply terminal 14BU of driver device 14B and through diode 38 to the upper supply terminal 14AU of driver device 14A and to a terminal 42A of capacitor 42. More particularly, an anode terminal of diode 38 is connected to terminal 53 and the cathode terminal of diode 38 is connected to an upper supply terminal 14AU of driver device 14A and to a terminal 42A of capacitor 42. Lower supply terminal 14AL of driver device 14A and terminal 42B of capacitor 42 are connected to switching node 17. Lower supply terminal 14BL of driver device 14B is connected to the source terminal of power FET 18.

In operation, the drive voltages provided by driver devices 14A and 14B to power MOSFETs 16 and 18 are scaled or adjusted in accordance with the input power or the output power dissipated by converter 10. Thus, the drive voltages applied to the gate terminals of power MOSFETs 16 and 18 are varied in accordance with the input power of converter 10 or the load level and the converter output power. It is desirable to operate power MOSFETs 16 and 18 such that they have the lowest Rdson achievable to improve device reliability and to reduce the total system power dissipation at a light load using the gate drive voltage. Rdson is a function of current flowing in power MOSFETs 16 and 18 which varies in accordance with the load connected to converter 10. In response to a high load, a high gate driver voltage lowers Rdson, but in response to a light load the conduction losses due to Rdson are not significant, instead the gate drive losses become the dominant loss. Accordingly, at light load the gate driver voltage is lowered to decrease the current used to charge the gate capacitance and thus improve the total system power dissipation. By way of example, a load that results in a load current of less than 5 amperes may be considered a light load and a load that results in a load current greater than 10 amperes may be considered a heavy load. A higher gate drive voltage may be used to achieve a lower Rdson under a heavy load than is used to achieve a comparable Rdson under a light load. Converter 10 includes scaling circuit 20 which varies the gate drive voltages in accordance with the input or output power levels, thereby improving the efficiency of converter 10.

For example, a light load may be coupled to converter 10 and driver device 14A may receive a control signal from controller 12 to turn off power MOSFET 16 and driver device 14B may receive a control signal from controller 12 to turn on power MOSFET 18. Buffer amplifier 26 generates an output signal VCUR in response to the signal at its input terminals and buffer amplifier 28 generates an output signal VVOL in response to the signal at its input terminal. Output signal VCUR is a representative voltage signal or a sensed current signal that is generated in response to the input current to the converter 10 and output signal VVOL is a sensed voltage signal that is generated in response to the voltage at the input of converter 10. Voltage signals VCUR, VVOL, and VSVOL may be referred to as buffered voltage signals. Output signal VVOL is shifted by offset voltage VOS to generate a shifted voltage VSVOL. Although voltage VSVOL is a shifted value of voltage VVOL, it still represents a sensed voltage signal that is generated in response to the voltage at the input of converter 10. A product signal. PINL of output signal VCUR and shifted voltage signal VSVOL is generated by multiplier circuit 30 and is representative of the input power of converter 10 when power MOSFET 18 is on and power MOSFET 16 is off. If power signal PINL is outside of a specified operating window of voltage follower 36, limiter circuit 32 limits or clips the product signal to place it within the specified operating window and transmits the voltage signal to the noninverting input terminal of operational amplifier 50. Thus, limiter circuit 32 produces a limited product signal.

Because operational amplifier 50 is configured as a voltage follower, the voltage at its noninverting input terminal appears at its inverting input terminal and thus at node 53. The voltage that appears at node 53 serves as a scaling signal. When the load is light, the feedback loop maintains the voltage at node 53, and therefore the voltages at input terminals 14AL and 14AU at a level sufficient to drive power MOSFETs 16 and 18 while maintaining a sufficiently low Rdson to minimize the total power losses of converter 10. It should be noted that when power MOSFET 18 is on, the voltage at node 17 is approximately equal to operating potential VSS and that the drain-to-source current IDS52 of transistor 52 flows through node 53, diode 38, into node 17, and to ground through power MOSFET 18. Current IDS52 charges capacitor 42 so that it can serve as a supply voltage for high side driver device 14A.

In response to a control signal from controller 14 turning on power MOSFET 16 and turning off power MOSFET 18, the voltage at node 17 increases and causes a voltage VSUM to appear at input terminal 14AU of driver device 14A. Voltage VSUM is substantially equal to the sum of the voltage at node 17 and the voltage across capacitor 42 and serves as the supply voltage for driver device 14A. Capacitor 42 in combination with the voltage at node 17 form a floating power supply for driver device 14A and enable driver device 14A to drive power FET 16. Diode 38 inhibits capacitor 42 from discharging back into the regulated driver supply as the voltage on node 17 rises. Like the operation in response to power MOSFET 18 being on and power MOSFET 16 being off, buffer amplifier 26 generates an output signal VCUR in response to the signal at its input terminals and buffer amplifier 28 generates an output signal VVOL in response to the signal at its input terminal. Output signal VVOL is shifted by offset voltage VOS to generate a shifted voltage VSVOL. A product PINL of output signal VCUR and shifted voltage signal VSVOL is generated by multiplier circuit 30 that is representative of the input power of converter 10 when power MOSFET 18 is off and power MOSFET 16 is on. If power signal PINL is outside of a specified operating window of voltage follower 36, limiter circuit 32 limits or clips the signal to place it within the specified operating window and transmits the voltage signal to the noninverting input terminal of operational amplifier 50, wherein the voltage serves as a scaling signal.

Because operational amplifier 50 is configured as a voltage follower, the voltage at its noninverting input terminal appears at its inverting input terminal and thus at node 53. In response to a light load, the feedback loop minimizes the voltage at node 53, and therefore the voltages at input terminals 14AL and 14AU, at a level sufficient to drive power MOSFETs 16 and 18 while maintaining a sufficiently low Rdson to minimize the total losses of converter 10. Changing the voltages at input terminals 14AL and 14AU scales or adjusts the gate drive signal to the gate of power MOSFETs 16 and 18. In response to power MOSFET 16 switching on and power MOSFET 18 switching off, the voltage at node 17 and the voltage at input terminal 14AU increase. The voltage at input terminal 14AU increases to a voltage VSUM, where voltage VSUM is substantially equal to the sum of the voltage at node 17 and the voltage across capacitor 42. Thus, voltage VSUM serves as the supply voltage for driver device 14A. Capacitor 42 in combination with the voltage at node 17 form a floating power supply for driver device 14A enabling driver device 14A to drive power MOSFET 16 in response to power MOSFET 16 turning on. Changing the supply voltage of driver device 14A scales the gate drive signal to the gate of power MOSFET 16. Diode 38 inhibits capacitor 42 from discharging back into the regulated driver supply as the voltage on node 17 rises.

In response to a heavy load coupled to converter 10, driver device 14A may receive a control signal from controller 12 to turn off power MOSFET 16 and driver device 14B may receive a control signal from controller 12 to turn on power MOSFET 18. Buffer amplifier 26 generates an output signal VCUR in response to the signal at its input terminals and buffer amplifier 28 generates an output signal VVOL in response to the signal at its input terminal. Output signal VVOL is shifted by offset voltage VOS to generate a shifted voltage VSVOL. A product signal PINL of output signal VCUR and shifted voltage signal VSVOL is generated by multiplier circuit 30 and is representative of the input power of converter 10 when power MOSFET 18 is on and power MOSFET 16 is off. If product signal PINL is outside of a specified operating window of voltage follower 36, limiter circuit 32 limits or clips the signal to place it within the specified operating window and transmits the voltage signal to the noninverting input terminal of operational amplifier 50. Thus, limiter circuit 32 produces a limited product signal.

Because operational amplifier 50 is configured as a voltage follower, the voltage at its noninverting input terminal appears at its inverting input terminal and thus at node 53. The voltage that appears at node 53 serves as a scaling signal. It should be noted that the voltage at node 17 is approximately equal to supply voltage VSS and that a drain-to-source current IDS52 of transistor 52 flows through node 53, diode 38, into node 17, and to ground through power MOSFET 18. Current IDS52 charges capacitor 42 so that it can serve as the supply voltage for the high side driver device 14A.

In response to a control signal from controller 14 turning on power MOSFET 16 and turning off power MOSFET 18, the voltage at node 17 increases and causes a voltage VSUM to appear at input terminal 14AU of driver device 14A. Voltage VSUM is substantially equal to the sum of the voltage at node 17 and the voltage across capacitor 42 and serves as the supply voltage for driver device 14A. Capacitor 42 in combination with the voltage at node 17 form a floating power supply for driver device 14A and enable driver device 14A to drive power FET 16. Diode 38 inhibits capacitor 42 from discharging back into the regulated driver supply as the voltage on node 17 rises. Like the operation in response to power MOSFET 18 being on and power MOSFET 16 being off, buffer amplifier 26 generates an output signal VCUR in response to the signal at its input terminals, and buffer amplifier 28 generates an output signal VVOL in response to the signal at its input terminal. Output signal VVOL is shifted by offset voltage VOS to generate a shifted voltage VSVOL. A product PINL of output signal VCUR and shifted voltage signal VSVOL is generated by multiplier circuit 30 and is representative of the input power of converter 10 when power MOSFET 18 is off and power MOSFET 16 is on. If power signal PINL is outside of a specified operating window of voltage follower 36, limiter circuit 32 limits or clips the signal to place it within the specified operating window and transmits the voltage signal to the noninverting input terminal of operational amplifier 50.

Because operational amplifier 50 is configured as a voltage follower, the voltage at its noninverting input terminal appears at its inverting input terminal and thus at node 53. The voltage that appears at node 53 serves as a scaling signal. When power MOSFET 18 is off and power MOSFET 16 is on, the feedback loop maintains the voltage at node 53, and therefore the voltages at input terminals 14AL and 14AU, at a level sufficient to drive power MOSFETs 16 and 18 while maintaining a low Rdson. Changing the voltages at input terminals 14AL and 14AU scales or adjusts the gate drive signal to the gate of power MOSFETs 16 and 18. In response to power MOSFET 16 switching on and power MOSFET 18 switching off, the voltage at node 17 and the voltage at input terminal 14AU increase. The voltage at input terminal 14AU increases to a voltage VSUM, where voltage VSUM is substantially equal to the sum of the voltage at node 17 and the voltage across capacitor 42. Thus, voltage VSUM serves as the supply voltage for driver device 14A. Capacitor 42 in combination with the voltage at node 17 form a floating power supply for driver device 14A and enable driver device 14A to drive power MOSFET 16 in response to MOSFET 16 turning on. Diode 38 inhibits capacitor 42 from discharging back into the regulated driver supply as the voltage on node 17 rises.

It should be noted that scaling circuit 20 may be responsive to a digital control signal, i.e., controller 12 may be a digital controller or a controller that outputs one or more digital control signals.

<figref idrefs="DRAWINGS">FIG. 2</figref> is a circuit schematic of a DC to DC converter 100 in accordance with an embodiment of the present invention. Like DC to DC converter 10, converter 100 includes a controller 12 coupled to a drive circuit 14 that drives switching devices 16 and 18. Drive circuit 14 has upper supply terminals 14AU and 14BU coupled for receiving operating power from a voltage scaling circuit 102. More particularly, drive circuit 14 includes driver devices 14A and 14B, where driver device 14A drives switching device 16, driver device 14B drives switching device 18, and each driver device 14A and 14B receives a control signal from controller 12. Switching devices 16 and 18 may be field effect transistors such as, for example, MOSFETs, bipolar junction transistors, junction field effect transistors, or the like, where each has a control conductor and current carrying conductors. In accordance with an embodiment in which switching devices 16 and 18 are power MOSFETs, the control conductor is a gate electrode or terminal, one of the current carrying conductors is a drain electrode or terminal, and the other current carrying conductor is a source electrode or terminal. Thus, an output terminal of driver device 14A is connected to the gate terminal of power MOSFET 16 and an output terminal of driver device 14B is connected to the gate terminal of power MOSFET 18. The drain terminal of power MOSFET 16 is connected to an output terminal 22 of voltage scaling circuit 102 and the source terminal of power MOSFET 16 is connected to the drain terminal of power MOSFET 18 to form a switching node 17. Lower supply terminal 14AL of switching device 14A is connected to switching node 17. The source terminal of power MOSFET 18 is coupled for receiving a source of operating potential such as, for example, VSS. Operating potential VSS may be, for example, ground potential. An inductor 60 has a terminal 60A connected to switching node 17 and a terminal 60B. A load capacitor 62 is coupled in parallel with a load resistor between terminal 60B of inductor 60 and source of operating potential VSS.

In accordance with an embodiment, scaling circuit 102 comprises a resistor 104, buffer amplifiers 26 and 28, multiplier 30, a limiter 32, a voltage follower 36, and a diode 38. Optionally, scaling circuit 102 may include an offset voltage 40 and a filter capacitor 42. It should be noted that controller 12, drive circuit 14, and scaling circuit 102 may be monolithically integrated into the same semiconductor material. The configuration of buffer amplifiers 26 and 28, multiplier 30, limiter 32, voltage follower 36, diode 38, and capacitor 42 have been described with reference to <figref idrefs="DRAWINGS">FIG. 1</figref>. DC to DC converter 100 differs from DC to DC converter 10 in that resistor 24 is absent from DC to DC converter 100 and resistor 104 is connected between terminal 60B of inductor 60 and the parallel combination of capacitor 62 and resistor 64. Thus, resistor 104 has a terminal 104A connected to the inverting input terminal of buffer amplifier 26 and a terminal 104B connected to the noninverting input terminal of buffer amplifier 26. The input terminal of buffer amplifier 28 is connected to the noninverting input terminal of buffer amplifier 26 and to terminal 104B of resistor 104. Like scaling circuit 20, scaling circuit 102 may be responsive to a digital control signal.

The operation of DC to DC converter 100 is similar to that of DC to DC converter 10 except that DC to DC converter 100 monitors and adjusts the drive voltages in accordance with the output power rather than the input power, which is a product of the load current IL and voltage VOUT. Thus, resistor 104 rather than resistor 24 is coupled across the input terminals of amplifier 26 and voltage VOUT is coupled to the input of amplifier 28 rather than voltage V1. With this change, the operation of DC to DC converter 100 is similar to that of DC to DC converter 10.

Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.

Contents3

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97243610	United States of America	A	2010-12-18
US20100972436	–	–	–

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Document	Office	Kind
US2012153906A1	United States of America	A1	2012-06-21
TW201240311A	Taiwan Province of China	A	2012-10-01
US8558522B2This record	United States of America	B2	2013-10-15
TWI548189B	Taiwan Province of China	B	2016-09-01

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2011-01-07	Filing ReceiptFLRCPT.O	FLRCPT.O
2011-01-07	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2010-12-22	Cleared by OIPE CSR	–
2010-12-19	IFW Scan & PACR Auto Security Review	–
2010-12-18	Information Disclosure Statement consideredIDSC	IDSC
2010-12-18	Electronic Information Disclosure StatementEIDS.	EIDS.
2010-12-18	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2010-12-18	Initial Exam Team nnIEXX	IEXX
2010-02-18	Electronic Information Disclosure StatementEIDS.	EIDS.

10 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2025-03-21	Maintenance fee paymentMAFP	MAFP
2023-06-22	AssignmentAS	AS
2023-06-22	AssignmentAS	AS
2021-03-23	Maintenance fee paymentMAFP	MAFP
2017-03-21	Fee paymentFPAY	FPAY
2016-08-25	AssignmentAS	AS
2016-08-25	AssignmentAS	AS
2016-04-15	AssignmentAS	AS
2013-09-25	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2011-01-18	AssignmentAS	AS