Predictive thermal preconditioning and timing control for non-volatile memory cells

RELATED APPLICATIONS

0001This application is a continuation of copending U.S. patent application Ser. No. 13/016,390 filed on Jan. 28, 2011, which is a continuation of U.S. patent application Ser. No. 12/414,452 filed Mar. 30, 2009 and is not U.S. Pat. No. 7,916,528 issued Mar. 29, 2011.

BACKGROUND

0002Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices utilize a semiconductor array of solid-state memory cells to store individual bits of data. Such memory cells can be volatile or non-volatile.

0003Volatile memory cells generally retain data stored in memory only so long as operational power continues to be supplied to the device, while non-volatile memory cells generally retain data storage in memory even in the absence of the application of operational power.

0004In these and other types of data storage devices, it is often desirable to increase efficiency of memory cell operation, particularly with regard to the writing of data to the memory cells.

SUMMARY

0005Various embodiments of the present invention are generally directed to a method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell.

0006In accordance with some embodiments, a semiconductor memory comprises an array of non-volatile memory cells, and a control circuit adapted to store a first write command from a host to write data to said array. A write circuit is adapted to flow a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and to concurrently pass a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit is further adapted to pass a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.

0007These and other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0008<figref idref="DRAWINGS">FIG. 1</figref> is a generalized functional representation of an exemplary data storage device constructed and operated in accordance with various embodiments of the present invention.

0009<figref idref="DRAWINGS">FIG. 2</figref> shows an exemplary construction of a magnetic tunneling junction (MTJ) of a spin-torque transfer random access memory (STRAM) memory cell.

0010<figref idref="DRAWINGS">FIG. 3</figref> sets forth a schematic representation of portions of the array of <figref idref="DRAWINGS">FIG. 1</figref> using STRAM memory cells as configured in <figref idref="DRAWINGS">FIG. 2</figref>.

0011<figref idref="DRAWINGS">FIG. 4</figref> shows another schematic representation of portions of the array of <figref idref="DRAWINGS">FIG. 1</figref> with thermal preconditioning diodes.

0012<figref idref="DRAWINGS">FIG. 5</figref> is a schematic diagram of a timing circuit in accordance with various embodiments of the present invention.

0013<figref idref="DRAWINGS">FIG. 6</figref> sets forth a flow chart for a PREDICTIVE THERMAL PRECONDITIONING routine.

0014<figref idref="DRAWINGS">FIG. 7</figref> is a timing diagram for selectively preconditioning memory cells during a data write operation in accordance with some embodiments.

0015<figref idref="DRAWINGS">FIG. 8</figref> is a timing diagram for selectively preconditioning memory cells during a data write operation in accordance with further embodiments.

0016<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram representation of a cache memory structure of the device of <figref idref="DRAWINGS">FIG. 1</figref> configured as a content addressable memory (CAM).

0017<figref idref="DRAWINGS">FIG. 10</figref> shows a timing diagram for selectively preconditioning memory cells of the CAM of <figref idref="DRAWINGS">FIG. 9</figref> in accordance with some embodiments.

0018<figref idref="DRAWINGS">FIG. 11</figref> shows a timing diagram for selectively preconditioning memory cells of the CAM of <figref idref="DRAWINGS">FIG. 9</figref> in accordance with some embodiments.

DETAILED DESCRIPTION

0019<figref idref="DRAWINGS">FIG. 1</figref> provides a functional block representation of a data storage device <b>100</b> to illustrate an exemplary environment in which various embodiments of the present invention can be advantageously practiced. The device <b>100</b> includes a top level controller <b>102</b>, an interface (I/F) circuit <b>104</b> and a non-volatile data storage array <b>106</b>. The I/F circuit <b>104</b> operates under the direction of the controller <b>102</b> to transfer user data between the array <b>106</b> and a host device (not shown). In some embodiments, the device is characterized as a solid-state drive (SSD), the controller <b>102</b> is a programmable microcontroller, and the array <b>106</b> comprises an array of nonvolatile memory cells (unit cells).

0020An exemplary memory cell construction for the array <b>106</b> is shown in <figref idref="DRAWINGS">FIG. 2</figref>. The memory cell in <figref idref="DRAWINGS">FIG. 2</figref> has a spin-torque transfer random access memory (STRAM) configuration with a magnetic tunneling junction (MTJ) <b>110</b>, although other cell configurations can be used. The MTJ <b>110</b> includes a fixed reference layer <b>112</b> and a programmable free layer <b>114</b> (recording layer) separated by an intervening tunneling (barrier) layer <b>116</b>.

0021The reference layer <b>114</b> has a fixed magnetic orientation in a selected direction, as indicated by the associated arrow shown in <figref idref="DRAWINGS">FIG. 2</figref>. This fixed magnetic orientation can be established in a number of ways, such as via pinning to a separate magnet (not shown). The free layer <b>114</b> has a selectively programmable magnetic orientation that can be parallel (solid arrow) or anti-parallel (dotted arrow) with the selected direction of the reference layer <b>114</b>.

0022A low resistance state for the MTJ <b>110</b> is achieved when the magnetization of the free layer <b>114</b> is oriented to be substantially in the same direction (parallel) as the magnetization of the reference layer <b>112</b>. To orient the MTJ <b>110</b> in the parallel low resistance state, a write current passes through the MTJ <b>110</b> so that the magnetization direction of the reference layer <b>112</b> sets the magnetic orientation of the free layer <b>114</b>. Since electrons flow in the direction opposite to the direction of current, the write current direction passes from the free layer <b>114</b> to the reference layer <b>112</b>, and the electrons travel from the reference layer <b>112</b> to the free layer <b>114</b>.

0023A high resistance state for the MTJ <b>110</b> is established in the anti-parallel orientation in which the magnetization direction of the free layer <b>114</b> is substantially opposite that of the reference layer <b>112</b>. To orient the MTJ <b>110</b> in the anti-parallel resistance state, a write current passes through the MTJ <b>110</b> from the reference layer <b>112</b> to the free layer <b>114</b> so that spin-polarized electrons flow into the free layer <b>114</b> in the opposite direction.

0024A different logical state is assigned to each of the programmable resistances of the MTJ. In some embodiments, the low resistance, parallel state is used to represent a logical 0, and the high resistance, anti-parallel state is used to represent a logical 1. Additional programmed states can be used when the MTJ is configured to store multiple bits. For example, programmed resistances R<b>1</b>&lt;R<b>2</b>&lt;R<b>3</b>&lt;R<b>4</b> can be used to respectively store multi-bit values “00,” “01,” “10” and “11.”

0025<figref idref="DRAWINGS">FIG. 3</figref> shows a portion of the array <b>106</b> of <figref idref="DRAWINGS">FIG. 1</figref> with non-volatile memory cells <b>120</b>. Each memory cell <b>120</b> includes an MTJ <b>110</b> as set forth in <figref idref="DRAWINGS">FIG. 2</figref> coupled to a switching device <b>122</b>, characterized as a metal oxide semiconductor field effect transistor (MOSFET). The cells <b>120</b> are individually accessed by asserting word lines WL <b>124</b> to place the associated cell transistors <b>122</b> in a drain-to-source conductive state.

0026Programming (write) currents are respectively generated by write current drivers <b>126</b>, <b>128</b>. The write currents are passed between a bit line BL <b>130</b> and a source line SL <b>132</b> to program the selected MTJ <b>110</b> to the desired programmed state. To subsequently read the programmed state of a selected cell <b>120</b>, the associated WL <b>124</b> is asserted and a read current is passed by a read current driver (not separately shown) to establish a voltage drop across the cell <b>110</b>. This voltage drop is sensed by a sense amplifier <b>134</b> and compared to an input reference voltage V_REF. The output state of the sense amplifier <b>134</b> (e.g., high, low) will indicate the programmed state of the MTJ <b>120</b> of the selected cell <b>110</b>.

0027Large magnitudes of programming current can be required to switch the programmed states of the MTJs <b>120</b>, particularly to the anti-parallel (high resistance) state. This can require the use of relatively large cell transistors <b>122</b>, which limits achievable memory array densities. The use of large programming currents can also result in higher dynamic power consumption of the array, and can require a costly on-chip power delivery system.

0028The switching current for an STRAM MTJ such as <b>120</b> can be expressed as:

0029<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mrow><mfrac><mi>J</mi><msub><mi>J</mi><mi>c</mi></msub></mfrac><mo>=</mo><mrow><mn>1</mn><mo>-</mo><mrow><mfrac><mrow><msub><mi>K</mi><mi>b</mi></msub><mo>⁢</mo><mi>T</mi></mrow><mi>E</mi></mfrac><mo>⁢</mo><mi>ln</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mfrac><mi>τ</mi><msub><mi>τ</mi><mn>0</mn></msub></mfrac></mrow></mrow></mrow></mtd><mtd><mrow><mo>[</mo><mn>1</mn><mo>]</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8553454B2_D0001.tif" /><br /> Where J is the switching current density; J_cis the critical switching current density at 0 degrees K; E is the energy barrier for magnetic switching; τ is the switching time, τ₀is the attempt time for thermal switching and T is the temperature in degrees K. While a reduction in switching current can be accommodated by increasing the duration of the driving pulse width τ, this can reduce overall data throughput rates.

0030Another way to reduce switching current requirements is to increase the temperature T of the MTJ through thermal preconditioning, or localized heating of the MTJ prior to the switching event. The widescale application of thermal preconditioning to large numbers of cells, however, can increase overall power requirements and may result in the heating of many cells that are not actually written.

0031Accordingly, various embodiments of the present invention are generally directed to providing probabilistic (predictive) thermal preconditioning of memory cells in a non-volatile array. As explained below, an address of a first memory cell subjected to a write operation is used to predict a next address of a second memory cell that may be subjected to a write operation in the near future. Thermal preconditioning is applied to the second memory cell concurrently with the writing of the state to the first memory cell.

0032In this way, should the second memory cell be subsequently subjected to a write operation, the write operation upon the second memory cell will be thermally assisted, that is, take place while the second memory cell is at an elevated temperature, thereby reducing the magnitude of switching current required to switch the programmed state.

0033The address of the second memory cell can be used to predict a write operation to a third memory cell which is thermally preconditioned, and so on. In some embodiments, the use of thermal preconditioning in this manner can reduce both current requirements and write current pulse widths, leading to data throughput rate enhancements and decreased power consumption.

0034The predictive thermal preconditioning can be based on addresses of memory cells for which write data have been received. In some embodiments, a write command for the cells of a selected logical data block with an address N can result in the application of preconditioning for the cells in a data block N+1, based on a speculative prediction that a sequential write operation is underway in which blocks N, N+1, N+2 . . . may be successively written in the near future.

0035The logical data blocks N, N+1, N+2 . . . can be any suitable grouping of memory cells, such as an addressable sector of data (e.g., 512 bytes of user data) associated with a host level logical block address (LBA). The data blocks can constitute a row of memory cells in an array, such as 1024 bytes of data in a 32 KB memory unit (32 rows by 8192 columns, etc.), or portions of the same row of memory cells. The data blocks can also be defined as individual cells.

0036The preconditioned cells can be located at any selected location within one or more arrays, and may not necessarily be adjacent to the initial set of written cells that did not receive preconditioning (i.e., “unconditioned” or “non-preconditioned” cells). The set of memory cells being probabilistically preconditioned can comprise memory cells having successive logical addresses, logical addresses of dissimilar word lines, or a number of logical addresses that are less than the number of cells connected by a single word line. Although the first written block N will be unconditioned and will thus be written at a slower rate and/or at a higher current, each of the preconditioned blocks N+1 etc. will be subsequently written at a faster rate and/or lower current, resulting in overall higher data transfer rates and lower power consumption.

0037Referring again to <figref idref="DRAWINGS">FIG. 3</figref>, the thermal preconditioning can be applied in a number of ways, such as by the application of a relatively small driving current to the second (and subsequent) memory cells. For example, a write operation to a first MTJ <b>110</b> in <figref idref="DRAWINGS">FIG. 3</figref> can trigger the application of a relatively small current to a second MTJ <b>110</b>, such as by a partial assertion of the associated WL.

0038Alternatively, the thermal preconditioning can utilize a variety of components configured to raise the temperature of an MTJ <b>110</b> upon selection. <figref idref="DRAWINGS">FIG. 4</figref> shows a configuration for portions of the memory array <b>106</b> of <figref idref="DRAWINGS">FIG. 1</figref> in accordance with further embodiments. The circuitry of <figref idref="DRAWINGS">FIG. 4</figref> is generally similar to that set forth in <figref idref="DRAWINGS">FIG. 3</figref>, and like reference numerals are used for similar components.

0039In <figref idref="DRAWINGS">FIG. 4</figref>, thermal assist mechanisms such as diodes <b>136</b> are coupled to the respective MTJs <b>110</b> to facilitate the application of heating current thereto prior to a write operation. The diodes <b>136</b> can take any number of suitable forms, such as but not limited to Zener, Schottky, and Esaki diodes. When selected MTJs <b>110</b> are identified as candidates for preconditioning, low level currents are supplied by a suitable source (not shown) through the diodes to the cells <b>120</b>, providing localized heating of the MTJs <b>110</b>.

0040A number of different approaches can be implemented to limit the extent to which thermal preconditioning is applied. In some embodiments, an external signal can be generated by the system to terminate the thermal conditioning sequence. A controller such as <b>102</b> in <figref idref="DRAWINGS">FIG. 1</figref> can implement a thermal preconditioning algorithm (TPA) <b>138</b> that maintains a look ahead preconditioning sequence each time a write command and associated write data are received from the host.

0041For example, for each received block of write data, the controller <b>102</b> can identify to the array <b>106</b> some selected number of additional successive blocks to which thermal preconditioning should be subjected, and this will continue until no further write commands are received from the host. The controller <b>102</b> can further signal the array <b>106</b> that the writing operation is finished, thereby terminating any ongoing preconditioning operations.

0042In an alternative embodiment, a counter can be added for each memory block (or multiple adjacent memory blocks) for timing control, such as indicated by a counter circuit <b>140</b> in <figref idref="DRAWINGS">FIG. 1</figref>. Continued receipt of write commands can reinitiate the timer, or initiate counts using new timers. When a number of counted clock cycles reaches a predetermined elapsed time threshold, the applied thermal assistance can be removed.

0043Another timing control mechanism can be implemented via a timing circuit <b>142</b> in the array <b>106</b> of <figref idref="DRAWINGS">FIG. 1</figref>. As shown in <figref idref="DRAWINGS">FIG. 5</figref>, in some embodiments the timing circuit <b>142</b> can be characterized as an RC-based circuit that generally operates to detect voltage discharging due to an RC delay, and terminates further application of thermal preconditioning when the decaying RC voltage reaches a predetermined threshold.

0044The timing circuit <b>142</b> in <figref idref="DRAWINGS">FIG. 5</figref> includes a decay circuit <b>144</b> and a level converter <b>146</b>. An inverter <b>148</b> is coupled between the respective decay circuit <b>144</b> and level converter <b>146</b>. The decay circuit <b>144</b> includes transistors <b>150</b>, <b>152</b> and a capacitor <b>154</b>. The capacitor <b>154</b> stores a voltage V_CAPin relation to a rail voltage (in this case, 1.5V) and a word line WL <b>156</b>. A discharge line <b>158</b> facilitates RC discharge of the V_CAPvoltage to ground <b>160</b> via a V_DISCHARGEinput.

0045The level converter <b>146</b> includes transistors <b>162</b>, <b>164</b>, <b>166</b> and <b>168</b> and inverter <b>170</b> cross-connected as shown between rail voltages of 1.0V and −1.0V. Once the voltage V_CAPstored on the capacitor <b>154</b> falls below the threshold input of the inverter <b>150</b>, a change in output on path <b>172</b> signals a termination of the precharging operation. It will be appreciated in these and other related timing mechanisms as contemplated herein, an elapsed time interval can be predefined, and the preconditioning is terminated at the conclusion of the time interval for any and all preconditioned cells to which data have not been written. This further serves to reduce power consumption since the occurrence of unnecessary preconditioning currents can be reduced.

0046<figref idref="DRAWINGS">FIG. 6</figref> sets forth a PREDICTIVE THERMAL PRECONDITIONING routine <b>180</b> generally illustrative of steps carried out in accordance with various embodiments. It is contemplated that the routine of <figref idref="DRAWINGS">FIG. 6</figref> is carried out by a suitable control circuit, such as the controller <b>102</b> in <figref idref="DRAWINGS">FIG. 1</figref>. At step <b>182</b>, a write command is received by a device such as <b>100</b> in <figref idref="DRAWINGS">FIG. 1</figref> to write data to an array such as <b>106</b> at a selected block at a selected block address. The device proceeds to execute the write command at step <b>184</b>, and concurrently uses the selected block address to identify a subsequent block address (or addresses) to which a write operation may be received in the near future, step <b>186</b>. The device proceeds to concurrently apply thermal preconditioning to the subsequent block address (or addresses) at step <b>188</b> during the writing to the selected block at step <b>184</b>.

0047Decision step <b>190</b> determines whether an additional write command has been received by the host. This command may be for the subsequent block address, or for some other block address. If so, the routine may pass to step <b>192</b> where the additional write command is treated as a “selected block” at a “selected block address,” and the flow returns as shown. The routine will continue in this fashion until no additional write commands are received, at which point further preconditioning is terminated, step <b>194</b>.

0048<figref idref="DRAWINGS">FIG. 7</figref> provides a timing sequence corresponding to the routine <b>180</b> of <figref idref="DRAWINGS">FIG. 6</figref> for predictive preconditioning in an array in accordance with some embodiments. When writing data to a first memory block N, thermal preconditioning is concurrently applied to successive memory blocks N+1 and N+2. A subsequent write operation to block N+1 results in continued preconditioning of block N+2 plus concurrent preconditioning of a subsequent block N+3, and so on. This processing can continue, or time out as required.

0049<figref idref="DRAWINGS">FIG. 8</figref> shows an alternative timing sequence. A write operation to a first memory block N results in the application of predictive thermal preconditioning to a selected range of blocks N+1, N+2 and N+3. The thermal conditioning remains applied to each of these blocks until write operations are carried out thereto or a timeout condition is declared.

0050It is noted that the execution of subsequent writes to these other blocks does not trigger further preconditioning efforts; for example, the writing to preconditioned blocks N+1, N+2 or N+3 does not serve to trigger the further preconditioning of blocks N+4. N+5, etc. Rather, a set range of blocks is initially preconditioned based on the initial unconditioned block address, and writes are either carried out to these blocks or the preconditioning is terminated at the appropriate time out period conclusion. The actual writing to a given block undergoing preconditioning may serve to terminate further preconditioning of that block. Such is not necessarily required, however, particularly in cases where multiple updated writes are anticipated (or detected).

0051Receipt of a new write command to a different block X in <figref idref="DRAWINGS">FIG. 8</figref> similarly results in the application of continuous thermal preconditioning to blocks X+1, X+2 and X+3 until data are written thereto or a timeout condition is declared.

0052While it is contemplated that sequential writes in a memory array will often be based on an anticipated incrementally increasing write sequence (e.g., blocks N, N+1, N+2, N+3 . . . ) it will be appreciated that the above approach can be adapted to other conditions. A decreasing sequence of block addresses may be detected (e.g., blocks N, N−1, N−2, N−3), resulting in the predictive preconditioning of blocks with decreased addresses. The receipt of non-sequential write commands, given sufficient temporal and spatial locality of the associated blocks within a given range, can result in the selection of predictive preconditioning to other blocks within that range.

0053File allocation tables (FATs) or other data structures maintained by the device <b>100</b> may provide logical association information for blocks with otherwise non-local addresses. For example, a given data structure may provide a higher level association of a grouping of blocks such as blocks N, N+2, N+6, N+17, etc. Thus, a write operation to a selected block within the group, say N+2, may lead to a preconditioning decision for other blocks at other addresses as identified by such data structures (e.g., blocks N, N+6, N+17 . . . ).

0054While the foregoing discussion has contemplated the application of predictive write preconditioning to cells in a memory array such as <b>106</b>, such preconditioning can be readily applied to cells in other types of memory structures, such as caches. As will be appreciated, devices such as <b>100</b> can utilize such caches to provide intermediary storage of data during transfers between the host and the array <b>106</b>.

0055One such cache may be a data buffer in the I/F <b>104</b> that temporarily stores input user data pending encoding and storage to the array <b>106</b>, and which stores readback data retrieved from the array pending transfer to the host. Localized caches may also be provided at the controller level, such as L1, L2 and/or L3 caches to store data and/or control information such as programming instructions or status data.

0056<figref idref="DRAWINGS">FIG. 9</figref> provides a functional representation of an associative memory <b>200</b> (cache) having a content addressable memory (CAM) configuration. CAM based associative memories have found widespread use in a number of applications such as computer system cache, network routers, and various embedded applications.

0057The cache <b>200</b> is arranged to have a number of cache lines (rows) each with an index field <b>202</b> and a word data field <b>204</b>. The index field <b>202</b> stores tag data which serves as an identifier for the associated word data in field <b>204</b>. The tag data can take any number of desired forms, and can be expressed as a multi-bit value associated with some other address of the word data (such as a block address in another location in memory, such as the array <b>106</b>).

0058The cache <b>200</b> is generally accessed during a data retrieval operation by proving input search data which is quickly compared to the tag data in the respective index fields <b>202</b>. When a match is found, the corresponding word data from the associated word data field <b>204</b> is output. Depending on the size and arrangement of the cache <b>200</b>, the search can be executed over a single clock cycle, making the CAM structure faster than many other hardware or software based search systems.

0059Data in a cache such as <b>200</b> are often provided with temporal locality with respect to locations in the cache in which the data are stored. This is because data may be sequentially ordered within the cache in relation to the sequence in which the data were provided thereto. Moreover, multiple rows of data may be cached at the same time as groups of data are moved to the cache depending on loading requirements. Thus, a write operation to a particular cache line may be followed in the near future by subsequent write operations to cache lines that precede and/or come after the written cache line.

0060Preconditioning can be applied to caches such as <b>200</b> in accordance with the timing diagram of <figref idref="DRAWINGS">FIG. 10</figref>. In <figref idref="DRAWINGS">FIG. 10</figref>, a write command is executed to write new data to a selected word data line <b>204</b>. These data have an associated block address which will be referred to herein as address N. The address N may be a localized cache address (e.g., a row indicator via index fields <b>202</b>) or may be a global block address, such as an LBA at the host level, a row-block address at the array level, etc.

0061In <figref idref="DRAWINGS">FIG. 10</figref>, the writing of data to block N in the cache <b>200</b> results in a concurrent predictive thermal preconditioning operation upon blocks that both precede and follow the address of block N, that is, blocks N−2, N−1, N+1 and N+2. Other ranges can be used, including asymmetric ranges (e.g., blocks N−3 to N+4, etc.). It will be appreciated that the writing of data to the cache <b>200</b> may result in the overwriting of existing data, as in the case of the array <b>106</b>.

0062A subsequent writing of data for block N−2 initiates the concurrent preconditioning of block N−3, and a subsequent writing of data for block N+2 initiates preconditioning of block N+3. As before, the first block written (block N) is unconditioned and is therefore slower and/or requires higher write current, but the preconditioning allows greater efficiencies in the subsequent writing of the preconditioned blocks. A suitable timing mechanism is employed to halt further preconditioning efforts once the write operations cease, such as the various mechanisms <b>138</b>, <b>140</b> and/or <b>142</b> discussed above in <figref idref="DRAWINGS">FIGS. 1</figref>, <b>4</b> and <b>5</b>.

0063<figref idref="DRAWINGS">FIG. 11</figref> provides an alternative timing sequence for writing data to a cache such as <b>200</b>. In <figref idref="DRAWINGS">FIG. 11</figref>, the initial writing to an unconditioned block N results in the preconditioning of a larger range of blocks N−3 to N+3. Subsequent writes to these other blocks, however, do not trigger further preconditioning efforts. As before, the preconditioning continues until actively terminated.

0064As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantages in both memory cell efficiency and accuracy due to the writing of data to memory cells that have been preconditioned. Substantial power and time savings can be experienced by the intelligent selection of only those cells that should be preconditioned based on a prediction of future write operations. The use of a timing mechanism further provides power and time savings by providing a way to terminate further preconditioning responsive to changing data load conditions. The various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.

0065For purposes of the appended claims, the term “concurrently” and the like will be construed consistent with the foregoing discussion to describe operations that overlap in time, even if such operations individually commence or end at different times. The term “unconditioned” and the like will be construed consistent with the foregoing discussion to describe a memory cell to which thermal preconditioning has not been applied immediately prior to a write operation thereto.

0066It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.