Memory cell that includes a carbon-based memory element and methods of forming the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 12/418,855, filed Apr. 6, 2009, now U.S. Pat. No. 8,110,476, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/044,399, filed Apr. 11, 2008, and titled “Thin Deposited Carbon Switchable Resistor And Diode Matrix Cell For 3D Arrays,” each of which is hereby incorporated by reference herein in its entirety for all purposes.

FIELD OF THE INVENTION

This invention relates to non-volatile memories, and more particularly to a memory cell that includes a carbon-based memory element, and methods of forming the same.

BACKGROUND

Non-volatile memories formed from reversible resistance switching elements are known. For example, U.S. patent application Ser. No. 11/968,154, filed Dec. 31, 2007, titled “Memory Cell That Employs A Selectively Fabricated Carbon Nano-Tube Reversible Resistance Switching Element And Methods Of Forming The Same” (the “'154 Application”), which is hereby incorporated by reference herein in its entirety for all purposes, describes a rewriteable non-volatile memory cell that includes a diode coupled in series with a carbon-based reversible resistivity switching material.

However, fabricating memory devices from carbon-based materials is technically challenging, and improved methods of forming memory devices that employ carbon-based materials are desirable.

SUMMARY

In accordance with a first aspect of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material. The carbon-based material has a thickness of not more than ten atomic layers.

In accordance with a second aspect of the invention, a method of forming a metal-insulator-metal is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material. Forming the carbon-based material includes repeatedly performing the following steps: forming a layer of the carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same elements throughout, and in which:

<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of an exemplary memory cell in accordance with this invention;

<figref idref="DRAWINGS">FIG. 2A</figref> is a simplified perspective view of an exemplary memory cell in accordance with this invention;

<figref idref="DRAWINGS">FIG. 2B</figref> is a simplified perspective view of a portion of a first exemplary memory level formed from a plurality of the memory cells of <figref idref="DRAWINGS">FIG. 2A</figref>;

<figref idref="DRAWINGS">FIG. 2C</figref> is a simplified perspective view of a portion of a first exemplary three-dimensional memory array in accordance with this invention;

<figref idref="DRAWINGS">FIG. 2D</figref> is a simplified perspective view of a portion of a second exemplary three-dimensional memory array in accordance with this invention;

<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of an exemplary embodiment of a memory cell in accordance with this invention; and

<figref idref="DRAWINGS">FIGS. 4A-4E</figref> illustrate cross-sectional views of a portion of a substrate during an exemplary fabrication of a single memory level in accordance with this invention.

DETAILED DESCRIPTION

Certain carbon-based films, including but not limited to graphene, amorphous carbon (“aC”) containing microcrystalline or other regions of graphene, other graphitic carbon films, etc., may exhibit resistivity switching properties that may be used to form microelectronic non-volatile memories. Such films therefore are candidates for integration within a three-dimensional memory array.

Indeed, carbon-based materials have demonstrated memory switching properties on lab-scale devices with a 100×separation between ON and OFF states and mid-to-high range resistance changes. Such a separation between ON and OFF states renders carbon-based materials viable candidates for memory cells in which the carbon-based material is coupled in series with vertical diodes, thin film transistors or other steering elements. For example, a metal-insulator-metal (“MIM”) stack formed from a carbon-based material sandwiched between two metal or otherwise conducting layers may serve as a resistance-switching element for a memory cell.

Carbon-based materials are often deposited using plasma-enhanced chemical vapor deposition (“PECVD”) techniques. Such carbon-based material may have an “initial resistivity” (i.e., the resistivity of the material as formed) that may be low relative to the resistivities of the surrounding materials. As a result, a resistance-switching element that includes the carbon-based material may conduct a high initial current that is incompatible with a steering element used to control current flow through the resistance-switching element, such as an adjacent diode. Additionally or alternatively, the initial resistivity of the carbon-based material may require a high voltage and current to reset the material upon initial use.

In accordance with an exemplary embodiment of this invention, a memory cell is formed that includes a MIM stack that includes a carbon-based material, and that is coupled to a steering element such as a diode. The memory cell is formed by depositing a thin layer of carbon-based material having a thickness of about ten atomic layers or fewer.

In accordance with another exemplary embodiment of this invention, a memory cell is formed that includes a MIM stack that includes a carbon-based material, and that is coupled to a steering element such as a diode. The memory cell is formed by performing multiple depositions to form multiple monolayers or near-monolayers of a carbon-based material. As used herein, a monolayer of a carbon-based material is about one atomic layer of the carbon-based material. After each monolayer of carbon-based material is formed, the material is annealed at processing temperatures less than about 600° C. before forming the next and successive layer. Subjecting each respective layer to an anneal may facilitate formation of in-plane carbon bonds and limit the number of out-of-plane carbon bonds, thereby increasing the resistivity of the carbon-based material to current flowing in a direction perpendicular to the material's surface. Increasing the resistivity of the carbon-based material in this way may increase the resistance of the reversible-resistance switching element formed from the carbon-based material, thereby decreasing initial current flow through the reversible-resistance switching element.

Exemplary Inventive Memory Cell

<figref idref="DRAWINGS">FIG. 1</figref> is a schematic illustration of an exemplary memory cell <b>10</b> in accordance with this invention. Memory cell <b>10</b> includes a reversible resistance switching element <b>12</b> coupled to a steering element <b>14</b>. Reversible resistance switching element <b>12</b> includes a reversible resistivity switching material (not separately shown) having a resistivity that may be reversibly switched between two or more states.

For example, reversible resistivity switching material of element <b>12</b> may be in an initial, low-resistivity state upon fabrication. Upon application of a first voltage and/or current, the material is switchable to a high-resistivity state. Application of a second voltage and/or current may return reversible resistivity switching material to a low-resistivity state. Alternatively, reversible resistance switching element <b>12</b> may be in an initial, high-resistance state upon fabrication that is reversibly switchable to a low-resistance state upon application of the appropriate voltage(s) and/or current(s). When used in a memory cell, one resistance state may represent a binary “0,” whereas another resistance state may represent a binary “1”, although more than two data/resistance states may be used. Numerous reversible resistivity switching materials and operation of memory cells employing reversible resistance switching elements are described, for example, in U.S. patent application Ser. No. 11/125,939, filed May 9, 2005 and titled “Rewriteable Memory Cell Comprising A Diode And A Resistance Switching Material” (the “'939 Application”), which is hereby incorporated by reference herein in its entirety for all purposes.

Steering element <b>14</b> may include a thin film transistor, a diode, metal-insulator-metal tunneling current device, or another similar steering element that exhibits non-ohmic conduction by selectively limiting the voltage across and/or the current flow through reversible resistance switching element <b>12</b>. In this manner, memory cell <b>10</b> may be used as part of a two or three dimensional memory array and data may be written to and/or read from memory cell <b>10</b> without affecting the state of other memory cells in the array.

Exemplary embodiments of memory cell <b>10</b>, reversible resistance switching element <b>12</b> and steering element <b>14</b> are described below with reference to <figref idref="DRAWINGS">FIGS. 2A-2D</figref> and <figref idref="DRAWINGS">FIG. 3</figref>.

Exemplary Embodiments of Memory Cells and Memory Arrays

<figref idref="DRAWINGS">FIG. 2A</figref> is a simplified perspective view of an exemplary embodiment of a memory cell <b>10</b> in accordance with this invention that includes a steering element <b>14</b> and a carbon-based reversible resistance switching element <b>12</b>. Reversible resistance switching element <b>12</b> is coupled in series with steering element <b>14</b> between a first conductor <b>20</b> and a second conductor <b>22</b>. In some embodiments, a barrier layer <b>24</b> may be formed between reversible resistance switching element <b>12</b> and steering element <b>14</b>, and a barrier layer <b>33</b> may be formed between reversible resistance switching element <b>12</b> and second conductor <b>22</b>. An additional barrier layer <b>28</b> also may be formed between steering element <b>14</b> and first conductor <b>20</b>. For example, barrier layers <b>24</b>, <b>28</b> and <b>33</b> may include titanium nitride, tantalum nitride, tungsten nitride, or other similar barrier layer.

As discussed above, steering element <b>14</b> may include a thin film transistor, a diode, metal-insulator-metal tunneling current device, or another similar steering element that exhibits non-ohmic conduction by selectively limiting the voltage across and/or the current flow through reversible resistance switching element <b>12</b>. In the example of <figref idref="DRAWINGS">FIG. 2A</figref>, steering element <b>14</b> is a diode. Accordingly, steering element <b>14</b> is sometimes referred to herein as “diode <b>14</b>.”

Diode <b>14</b> may include any suitable diode such as a vertical polycrystalline p-n or p-i-n diode, whether upward pointing with an n-region above a p-region of the diode or downward pointing with a p-region above an n-region of the diode. For example, diode <b>14</b> may include a heavily doped n+ polysilicon region <b>14</b><i>a</i>, a lightly doped or an intrinsic (unintentionally doped) polysilicon region <b>14</b><i>b </i>above the n+ polysilicon region <b>14</b><i>a</i>, and a heavily doped p+ polysilicon region <b>14</b><i>c </i>above intrinsic region <b>14</b><i>b</i>. It will be understood that the locations of the n+ and p+ regions may be reversed. Exemplary embodiments of diode <b>14</b> are described below with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

Reversible resistance switching element <b>12</b> may include a carbon-based material (not separately shown) having a resistivity that may be reversibly switched between two or more states. For example, reversible resistance switching element <b>12</b> may include aC containing microcrystalline or other regions of graphene. For simplicity, reversible resistance switching element <b>12</b> will be referred to in the remaining discussion as “carbon element <b>12</b>.”

First conductor <b>20</b> and/or second conductor <b>22</b> may include any suitable conductive material such as tungsten, any appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like. In the embodiment of <figref idref="DRAWINGS">FIG. 2A</figref>, first and second conductors <b>20</b> and <b>22</b>, respectively, are rail-shaped and extend in different directions (e.g., substantially perpendicular to one another). Other conductor shapes and/or configurations may be used. In some embodiments, barrier layers, adhesion layers, antireflection coatings and/or the like (not shown) may be used with the first conductor <b>20</b> and/or second conductor <b>22</b> to improve device performance and/or aid in device fabrication.

<figref idref="DRAWINGS">FIG. 2B</figref> is a simplified perspective view of a portion of a first memory level <b>30</b> formed from a plurality of memory cells <b>10</b>, such as memory cell <b>10</b> of <figref idref="DRAWINGS">FIG. 2A</figref>. For simplicity, carbon element <b>12</b>, diode <b>14</b>, and barrier layers <b>24</b>, <b>28</b> and <b>33</b> are not separately shown. Memory array <b>30</b> is a “cross-point” array including a plurality of bit lines (second conductors <b>22</b>) and word lines (first conductors <b>20</b>) to which multiple memory cells are coupled (as shown). Other memory array configurations may be used, as may multiple levels of memory.

For example, <figref idref="DRAWINGS">FIG. 2C</figref> is a simplified perspective view of a portion of a monolithic three dimensional array <b>40</b><i>a </i>that includes a first memory level <b>42</b> positioned below a second memory level <b>44</b>. Memory levels <b>42</b> and <b>44</b> each include a plurality of memory cells <b>10</b> in a cross-point array. Persons of ordinary skill in the art will understand that additional layers (e.g., an interlevel dielectric) may be present between the first and second memory levels <b>42</b> and <b>44</b>, but are not shown in <figref idref="DRAWINGS">FIG. 2C</figref> for simplicity. Other memory array configurations may be used, as may additional levels of memory. In the embodiment of <figref idref="DRAWINGS">FIG. 2C</figref>, all diodes may “point” in the same direction, such as upward or downward depending on whether p-i-n diodes having a p-doped region on the bottom or top of the diodes are employed, simplifying diode fabrication.

For example, in some embodiments, the memory levels may be formed as described in U.S. Pat. No. 6,952,030, titled “High-Density Three-Dimensional Memory Cell” which is hereby incorporated by reference herein in its entirety for all purposes. For instance, the upper conductors of a first memory level may be used as the lower conductors of a second memory level that is positioned above the first memory level as shown in the alternative exemplary three dimensional array <b>40</b><i>b </i>illustrated in <figref idref="DRAWINGS">FIG. 2D</figref>. In such embodiments, the diodes on adjacent memory levels preferably point in opposite directions as described in U.S. patent application Ser. No. 11/692,151, filed Mar. 27, 2007 and titled “Large Array Of Upward Pointing P-I-N Diodes Having Large And Uniform Current” (hereinafter “the '151 Application”), which is hereby incorporated by reference herein in its entirety for all purposes. For example, as shown in <figref idref="DRAWINGS">FIG. 2D</figref>, the diodes of the first memory level <b>42</b> may be upward pointing diodes as indicated by arrow A<b>1</b> (e.g., with p regions at the bottom of the diodes), whereas the diodes of the second memory level <b>44</b> may be downward pointing diodes as indicated by arrow A<b>2</b> (e.g., with n regions at the bottom of the diodes), or vice versa.

A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.

As previously stated, any suitable carbon-based switching material may be used as carbon element <b>12</b>. In some embodiments, a preferred resistivity of the material used to form carbon element <b>12</b> is at least 1×10¹ohm-cm when carbon element <b>12</b> is in an ON-state, whereas a preferred resistivity of the material used to form carbon element <b>12</b> is at least 1×10³ohm-cm when carbon element <b>12</b> is in an OFF-state.

<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view of an exemplary embodiment of memory cell <b>10</b> of <figref idref="DRAWINGS">FIG. 1</figref>. In particular, <figref idref="DRAWINGS">FIG. 3</figref> shows an exemplary memory cell <b>10</b> which includes carbon element <b>12</b>, diode <b>14</b>, and first and second conductors <b>20</b> and <b>22</b>, respectively. Memory cell <b>10</b> may also include barrier layers <b>26</b>, <b>28</b>, and <b>33</b>, a silicide layer <b>50</b>, a silicide-forming metal layer <b>52</b>, and dielectric layer <b>58</b>, as well as adhesion layers, antireflective coating layers and/or the like (not shown) which may be used with first and/or second conductors <b>20</b> and <b>22</b>, respectively, to improve device performance and/or facilitate device fabrication.

In <figref idref="DRAWINGS">FIG. 3</figref>, diode <b>14</b> may be a vertical p-n or p-i-n diode, which may either point upward or downward. In the embodiment of <figref idref="DRAWINGS">FIG. 2D</figref> in which adjacent memory levels share conductors, adjacent memory levels preferably have diodes that point in opposite directions such as downward-pointing p-i-n diodes for a first memory level and upward-pointing p-i-n diodes for an adjacent, second memory level (or vice versa).

In some embodiments, diode <b>14</b> may be formed from a polycrystalline semiconductor material such as polysilicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. For example, diode <b>14</b> may include a heavily doped n+ polysilicon region <b>14</b><i>a</i>, a lightly doped or an intrinsic (unintentionally doped) polysilicon region <b>14</b><i>b </i>above the n+ polysilicon region <b>14</b><i>a</i>, and a heavily doped p+ polysilicon region <b>14</b><i>c </i>above intrinsic region <b>14</b><i>b</i>. It will be understood that the locations of the n+ and p+ regions may be reversed.

In some embodiments, a thin germanium and/or silicon-germanium alloy layer (not shown) may be formed on n+ polysilicon region <b>14</b><i>a </i>to prevent and/or reduce dopant migration from n+ polysilicon region <b>14</b><i>a </i>into intrinsic region <b>14</b><i>b</i>. Use of such a layer is described, for example, in U.S. patent application Ser. No. 11/298,331, filed Dec. 9, 2005 and titled “Deposited Semiconductor Structure To Minimize N-Type Dopant Diffusion And Method Of Making” (hereinafter “the '331 Application”), which is hereby incorporated by reference herein in its entirety for all purposes. In some embodiments, a few hundred angstroms or less of silicon-germanium alloy with about 10 at % or more of germanium may be employed.

A barrier layer <b>28</b>, such as titanium nitride, tantalum nitride, tungsten nitride, etc., may be formed between the first conductor <b>20</b> and the n+ region <b>14</b><i>a </i>(e.g., to prevent and/or reduce migration of metal atoms into the polysilicon regions).

If diode <b>14</b> is fabricated from deposited silicon (e.g., amorphous or polycrystalline), a silicide layer <b>50</b> may be formed on diode <b>14</b> to place the deposited silicon in a low resistivity state, as fabricated. Such a low resistivity state allows for easier programming of memory cell <b>10</b> as a large voltage is not required to switch the deposited silicon to a low resistivity state. For example, a silicide-forming metal layer <b>52</b> such as titanium or cobalt may be deposited on p+ polysilicon region <b>14</b><i>c</i>. During a subsequent anneal step (described below) employed to crystallize the deposited silicon that forms diode <b>14</b>, silicide-forming metal layer <b>52</b> and the deposited silicon of diode <b>14</b> interact to form silicide layer <b>50</b>, consuming all or a portion of the silicide-forming metal layer <b>52</b>. In some embodiments, a nitride layer (not shown) may be formed at a top surface of silicide-forming metal layer <b>52</b>. For example, if silicide-forming metal layer <b>52</b> is titanium, a TiN layer may be formed at a top surface of silicide-forming metal layer <b>52</b>.

A rapid thermal anneal (“RTA”) step may then be performed to form silicide regions by reaction of silicide-forming metal layer <b>52</b> with p+ region <b>14</b><i>c</i>. The RTA may be performed at about 540° C. for about 1 minute, and causes silicide-forming metal layer <b>52</b> and the deposited silicon of diode <b>14</b> to interact to form silicide layer <b>50</b>, consuming all or a portion of the silicide-forming metal layer <b>52</b>. As described in U.S. Pat. No. 7,176,064, titled “Memory Cell Comprising A Semiconductor Junction Diode Crystallized Adjacent To A Silicide,” which is hereby incorporated by reference herein in its entirety for all purposes, silicide-forming materials such as titanium and/or cobalt react with deposited silicon during annealing to form a silicide layer.

In embodiments in which a nitride layer was formed at a top surface of silicide-forming metal layer <b>52</b>, following the RTA step, the nitride layer may be stripped using a wet chemistry. For example, if silicide-forming metal layer <b>52</b> includes a TiN top layer, a wet chemistry (e.g., ammonium, peroxide, water in a 1:1:1 ratio) may be used to strip any residual TiN.

In at least some embodiments, described in more detail with respect to <figref idref="DRAWINGS">FIGS. 4A-4E</figref>, reversible resistance switching element <b>12</b> may be formed by depositing a thin layer of a carbon-based material, such as aC, having a thickness of about ten atomic layers or fewer.

In other embodiments, carbon element <b>12</b> may be formed by performing multiple depositions of a carbon-based material, such as aC, to form multiple monolayers or near-monolayers of the carbon-based material and annealing each layer before depositing a successive layer. Forming carbon-based material in this manner may increase the resistivity of the material to current flowing in a direction perpendicular to the material's surface.

Preferably between two and about ten monolayers or near-monolayers are deposited to form carbon element <b>12</b>. The total thickness of carbon element <b>12</b> is between about 1 angstrom and about 800 angstroms, preferably between about 5 angstrom and 100 angstroms.

In particular embodiments, carbon-based switching materials may be formed to exhibit sheet resistance (“Ω/□” or “ohms/square”) for a 1000 angstrom film from about 1×10⁵Ω/□ to about 1×10⁸Ω/□, and more preferably about 1×10⁴Ω/□ or greater. Similarly, some embodiments may comprise an aC film with nanocrystallites. Other film parameters and characteristics may be pursued as well (e.g., alternate values of deposition rate, film thickness, sheet resistance/resistivity, etc.).

A barrier layer <b>33</b>, such as titanium nitride, tantalum nitride, tungsten nitride, etc., may be formed between carbon element <b>12</b> and second conductor <b>22</b>. Second conductor <b>22</b> may be formed above barrier layer <b>33</b>, as shown in <figref idref="DRAWINGS">FIG. 3</figref>. Second conductor <b>22</b> may include one or more barrier and/or adhesion layers <b>26</b> and a conductive layer <b>140</b>.

Exemplary Fabrication Processes for Memory Cells

Referring now to <figref idref="DRAWINGS">FIGS. 4A-4E</figref>, a first exemplary method of forming an exemplary memory level in accordance with this invention is described. In particular, <figref idref="DRAWINGS">FIGS. 4A-4E</figref> illustrate an exemplary method of forming an exemplary memory level including memory cells <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref>. As will be described below, the first memory level includes a plurality of memory cells that each include a steering element and a carbon-based reversible resistance switching element coupled to the steering element. Additional memory levels may be fabricated above the first memory level (as described previously with reference to <figref idref="DRAWINGS">FIGS. 2C-2D</figref>).

With reference to <figref idref="DRAWINGS">FIG. 4A</figref>, substrate <b>100</b> is shown as having already undergone several processing steps. Substrate <b>100</b> may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (“SOI”) or other substrate with or without additional circuitry. For example, substrate <b>100</b> may include one or more n-well or p-well regions (not shown).

Isolation layer <b>102</b> is formed above substrate <b>100</b>. In some embodiments, isolation layer <b>102</b> may be a layer of silicon dioxide, silicon nitride, silicon oxynitride or any other suitable insulating layer.

Following formation of isolation layer <b>102</b>, an adhesion layer <b>104</b> is formed over isolation layer <b>102</b> (e.g., by physical vapor deposition or another method). For example, adhesion layer <b>104</b> may be about 20 to about 500 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable adhesion layer such as tantalum nitride, tungsten nitride, combinations of one or more adhesion layers, or the like. Other adhesion layer materials and/or thicknesses may be employed. In some embodiments, adhesion layer <b>104</b> may be optional.

After formation of adhesion layer <b>104</b>, a conductive layer <b>106</b> is deposited over adhesion layer <b>104</b>. Conductive layer <b>106</b> may include any suitable conductive material such as tungsten or another appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), etc.). In at least one embodiment, conductive layer <b>106</b> may comprise about 200 to about 2500 angstroms of tungsten. Other conductive layer materials and/or thicknesses may be used.

Following formation of conductive layer <b>106</b>, adhesion layer <b>104</b> and conductive layer <b>106</b> are patterned and etched. For example, adhesion layer <b>104</b> and conductive layer <b>106</b> may be patterned and etched using conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing. In at least one embodiment, adhesion layer <b>104</b> and conductive layer <b>106</b> are patterned and etched to form substantially parallel, substantially co-planar first conductors <b>20</b>. Exemplary widths for first conductors <b>20</b> and/or spacings between first conductors <b>20</b> range from about 200 to about 2500 angstroms, although other conductor widths and/or spacings may be used.

After first conductors <b>20</b> have been formed, a dielectric layer <b>58</b><i>a </i>is formed over substrate <b>100</b> to fill the voids between first conductors <b>20</b>. For example, approximately 3000-7000 angstroms of silicon dioxide may be deposited on the substrate <b>100</b> and planarized using chemical mechanical polishing or an etchback process to form a planar surface <b>110</b>. Planar surface <b>110</b> includes exposed top surfaces of first conductors <b>20</b> separated by dielectric material (as shown). Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used. Exemplary low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.

In other embodiments of the invention, first conductors <b>20</b> may be formed using a damascene process in which dielectric layer <b>58</b><i>a </i>is formed, patterned and etched to create openings or voids for first conductors <b>20</b>. The openings or voids then may be filled with adhesion layer <b>104</b> and conductive layer <b>106</b> (and/or a conductive seed, conductive fill and/or barrier layer if needed). Adhesion layer <b>104</b> and conductive layer <b>106</b> then may be planarized to form planar surface <b>110</b>. In such an embodiment, adhesion layer <b>104</b> will line the bottom and sidewalls of each opening or void.

Following planarization, the diode structures of each memory cell are formed. With reference to <figref idref="DRAWINGS">FIG. 4B</figref>, a barrier layer <b>28</b> is formed over planarized top surface <b>110</b> of substrate <b>100</b>. Barrier layer <b>28</b> may be about 20 to about 500 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten nitride, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titanium nitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layer materials and/or thicknesses may be employed.

After deposition of barrier layer <b>28</b>, deposition of the semiconductor material used to form the diode of each memory cell begins (e.g., diode <b>14</b> in <figref idref="DRAWINGS">FIGS. 1 and 3</figref>). Each diode may be a vertical p-n or p-i-n diode as previously described. In some embodiments, each diode is formed from a polycrystalline semiconductor material such as polysilicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. For convenience, formation of a polysilicon, downward-pointing diode is described herein. It will be understood that other materials and/or diode configurations may be used.

With reference to <figref idref="DRAWINGS">FIG. 4B</figref>, following formation of barrier layer <b>28</b>, a heavily doped n+ silicon layer <b>14</b><i>a </i>is deposited on barrier layer <b>28</b>. In some embodiments, n+ silicon layer <b>14</b><i>a </i>is in an amorphous state as deposited. In other embodiments, n+ silicon layer <b>14</b><i>a </i>is in a polycrystalline state as deposited. CVD or another suitable process may be employed to deposit n+ silicon layer <b>14</b><i>a</i>. In at least one embodiment, n+ silicon layer <b>14</b><i>a </i>may be formed, for example, from about 100 to about 1000 angstroms, preferably about 100 angstroms, of phosphorus or arsenic doped silicon having a doping concentration of about 10²¹cm⁻³. Other layer thicknesses, doping types and/or doping concentrations may be used. N+ silicon layer <b>14</b><i>a </i>may be doped in situ, for example, by flowing a donor gas during deposition. Other doping methods may be used (e.g., implantation).

After deposition of n+ silicon layer <b>14</b><i>a</i>, a lightly doped, intrinsic and/or unintentionally doped silicon layer <b>14</b><i>b </i>may be formed over n+ silicon layer <b>14</b><i>a</i>. In some embodiments, intrinsic silicon layer <b>14</b><i>b </i>may be in an amorphous state as deposited. In other embodiments, intrinsic silicon layer <b>14</b><i>b </i>may be in a polycrystalline state as deposited. CVD or another suitable deposition method may be employed to deposit intrinsic silicon layer <b>14</b><i>b</i>. In at least one embodiment, intrinsic silicon layer <b>14</b><i>b </i>may be about 500 to about 4800 angstroms, preferably about 2500 angstroms, in thickness. Other intrinsic layer thicknesses may be used.

A thin (e.g., a few hundred angstroms or less) germanium and/or silicon-germanium alloy layer (not shown) may be formed on n+ silicon layer <b>14</b><i>a </i>prior to depositing intrinsic silicon layer <b>14</b><i>b </i>to prevent and/or reduce dopant migration from n+silicon layer <b>14</b><i>a </i>into intrinsic silicon layer <b>14</b><i>b </i>(as described in the '331 Application, previously incorporated).

Heavily doped, p-type silicon may be either deposited and doped by ion implantation or may be doped in situ during deposition to form a p+ silicon layer <b>14</b><i>c. </i>For example, a blanket p+ implant may be employed to implant boron a predetermined depth within intrinsic silicon layer <b>14</b><i>b</i>. Exemplary implantable molecular ions include BF₂, BF₃, B and the like. In some embodiments, an implant dose of about 1×5×10¹⁵ions/cm²may be employed. Other implant species and/or doses may be used. Further, in some embodiments, a diffusion process may be employed. In at least one embodiment, the resultant p+ silicon layer <b>14</b><i>c </i>has a thickness of about 100-700 angstroms, although other p+ silicon layer sizes may be used.

Following formation of p+ silicon layer <b>14</b><i>c</i>, a silicide-forming metal layer <b>52</b> is deposited over p+ silicon layer <b>14</b><i>c</i>. Exemplary silicide-forming metals include sputter or otherwise deposited titanium or cobalt. In some embodiments, silicide-forming metal layer <b>52</b> has a thickness of about 10 to about 200 angstroms, preferably about 20 to about 50 angstroms and more preferably about 20 angstroms. Other silicide-forming metal layer materials and/or thicknesses may be used. A nitride layer (not shown) may be formed at the top of silicide-forming metal layer <b>52</b>.

Following formation of silicide-forming metal layer <b>52</b>, an RTA step may be performed at about 540° C. for about one minute to form silicide layer <b>50</b>, consuming all or a portion of the silicide-forming metal layer <b>52</b>. Following the RTA step, any residual nitride layer from silicide-forming metal layer <b>52</b> may be stripped using a wet chemistry, as described above, and as is known in the art.

Following the RTA step and the nitride strip step, carbon element <b>12</b> is formed above silicide-forming metal layer <b>52</b>. In at least some embodiments described herein, carbon element <b>12</b> is formed by depositing a carbon-based reversible resistivity switching material such as aC. In alternative embodiments, other carbon-based materials may be used, including, without limitation, graphene, graphite, etc. For each material, a ratio of sp²(double carbon-carbon bonds to sp³(single carbon-carbon bonds) may be determined via, e.g., Raman spectroscopy, by evaluating the D and G bands. The range of usable materials may be identified by a ratio such as M_yN_z, where M is the sp³material and N is the sp²material, and y and z are any fractional value from zero to one and y+z=1.

As discussed above, carbon element <b>12</b> may be formed by depositing a thin layer of aC having a thickness of only a few atomic layers (e.g., approximately ten atomic layers or fewer). Researchers have asserted that depositing a carbon-based material in this manner may facilitate the formation of carbon-carbon ring structures in the carbon-based material. For example, the formation of sp²carbon-carbon pi bonds typical in graphitic materials may be facilitated.

For example, carbon element <b>12</b> may be formed using a plasma enhanced decomposition and deposition procedure, such as PECVD, performed at processing temperatures between about 300° C. and 900° C., preferably below 600° C., more preferably below 450° C., using a mixture of hydrogen and hexane. In other embodiments, other deposition methods may be used, including, without limitation, sputter deposition from a target, CVD, arc discharge techniques and laser ablation.

In other embodiments, carbon element <b>12</b> may be formed by performing multiple depositions of an aC material to form multiple monolayers or near-monolayers of the aC material and annealing each respective monolayer or near-monolayer before depositing a successive layer. Forming a carbon-based material in this manner may increase the resistivity of the material to current flowing in a direction perpendicular to the material's surface.

Each monolayer or near-monolayer may be annealed at processing temperatures less than about 600° C. in a non-oxidizing ambient before deposition of the successive layer. Subjecting each respective layer to an anneal may facilitate formation of in-plane carbon bonds and limit the number of out-of-plane carbon bonds, thereby increasing the resistivity of the aC material in the direction perpendicular to the material's surface. Increasing the resistivity of the aC material in this manner may increase the resistance of reversible resistance switching element <b>12</b> formed from the aC material, thereby decreasing initial current flow through the reversible-resistance switching element <b>12</b>.

Preferably between two and about ten layers of aC material are deposited to form reversible resistance switching element <b>12</b>. The total thickness of reversible resistance switching element <b>12</b> is between about 1 angstrom and about 800 angstroms, preferably between about 5 angstrom and 100 angstroms.

A barrier layer <b>33</b> is formed over reversible resistance switching element <b>12</b>. Barrier layer <b>33</b> may be about 5 to about 800 angstroms, and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten nitride, combinations of one or more barrier layers, barrier layers in combination with other layers such as titanium/titanium nitride, tantalum/tantalum nitride or tungsten/tungsten nitride stacks, or the like. Other barrier layer materials and/or thicknesses may be employed.

As shown in <figref idref="DRAWINGS">FIG. 4C</figref>, barrier layer <b>33</b>, reversible resistance switching element <b>12</b>, silicide-forming metal layer <b>52</b>, diode layers <b>14</b><i>a</i>-<b>14</b><i>c </i>and barrier layer <b>28</b> are patterned and etched to form pillars <b>132</b>. Pillars <b>132</b> may have about the same pitch and about the same width as conductors <b>20</b> below, such that each pillar <b>132</b> is formed on top of a conductor <b>20</b>. Some misalignment may be tolerated.

For example, photoresist may be deposited, patterned using standard photolithography techniques, layers <b>28</b>, <b>14</b><i>a</i>-<b>14</b><i>c</i>, <b>52</b>, <b>12</b>, and <b>33</b> may be etched, and then the photoresist may be removed. Alternatively, a hard mask of some other material, for example silicon dioxide, may be formed on top of the barrier layer <b>33</b>, with bottom antireflective coating (“BARC”) on top, then patterned and etched. Similarly, dielectric antireflective coating (“DARC”) may be used as a hard mask.

Pillars <b>132</b> may be formed using any suitable masking and etching process. For example, layers <b>28</b>, <b>14</b><i>a</i>-<b>14</b><i>c</i>, <b>52</b>, <b>12</b>, and <b>33</b> may be patterned with about 1 to about 1.5 micron, more preferably about 1.2 to about 1.4 micron, of photoresist (“PR”) using standard photolithographic techniques. Thinner PR layers may be used with smaller critical dimensions and technology nodes. In some embodiments, an oxide hard mask may be used below the PR layer to improve pattern transfer and protect underlying layers during etching.

Any suitable etch chemistries, and any suitable etch parameters, flow rates, chamber pressures, power levels, process temperatures, and/or etch rates may be used. In some embodiments, barrier layer <b>33</b>, reversible resistance switching element <b>12</b>, silicide-forming metal layer <b>52</b>, diode layers <b>14</b><i>a</i>-<b>14</b><i>c </i>and barrier layer <b>28</b> may be patterned using a single etch step. In other embodiments, separate etch steps may be used. The etch proceeds down to dielectric layer <b>58</b><i>a</i>. Such etched pillars <b>132</b> have been observed to have nearly vertical sidewalls and little or no undercut of reversible resistance switching element <b>12</b>.

After etching pillars <b>132</b> may be cleaned using a dilute hydrofluoric/sulfuric acid clean. Such cleaning, whether or not PR asking is performed before etching, may be performed in any suitable cleaning tool, such as a Raider tool, available from Semitool of Kalispell, Mont. Exemplary post-etch cleaning may include using ultra-dilute sulfuric acid (e.g., about 1.5-1.8 wt %) for about 60 seconds and ultra-dilute hydrofluoric (“HF”) acid (e.g., about 0.4-0.6 wt %) for 60 seconds. Megasonics may or may not be used.

After pillars <b>132</b> have been cleaned, a dielectric layer <b>58</b><i>b </i>may be deposited over pillars <b>132</b> to fill the voids between pillars <b>132</b>. For example, approximately 200-7000 angstroms of silicon dioxide may be deposited and planarized using chemical mechanical polishing or an etchback process to remove excess dielectric material <b>58</b><i>b </i>and form a planar surface <b>134</b>, resulting in the structure illustrated in <figref idref="DRAWINGS">FIG. 4D</figref>. Planar surface <b>134</b> includes exposed top surfaces of pillars <b>132</b> separated by dielectric material <b>58</b><i>b </i>(as shown). Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric layer thicknesses may be used. Exemplary low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.

With reference to <figref idref="DRAWINGS">FIG. 4E</figref>, second conductors <b>22</b> may be formed above pillars <b>132</b> in a manner similar to the formation of first conductors <b>20</b>. For example, in some embodiments, one or more barrier layers and/or adhesion layers <b>26</b> may be deposited over pillars <b>132</b> prior to deposition of a conductive layer <b>140</b> used to form second conductors <b>22</b>.

Conductive layer <b>140</b> may be formed from any suitable conductive material such as tungsten, another suitable metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., CVD, PVD, etc.). Other conductive layer materials may be used. Barrier layers and/or adhesion layers <b>26</b> may include titanium nitride or another suitable layer such as tantalum nitride, tungsten nitride, combinations of one or more layers, or any other suitable material(s). The deposited conductive layer <b>140</b> and barrier and/or adhesion layer <b>26</b> may be patterned and etched to form second conductors <b>22</b>. In at least one embodiment, second conductors <b>22</b> are substantially parallel, substantially coplanar conductors that extend in a different direction than first conductors <b>20</b>.

In other embodiments of the invention, second conductors <b>22</b> may be formed using a damascene process in which a dielectric layer is formed, patterned and etched to create openings or voids for conductors <b>22</b>. The openings or voids may be filled with adhesion layer <b>26</b> and conductive layer <b>140</b> (and/or a conductive seed, conductive fill and/or barrier layer if needed). Adhesion layer <b>26</b> and conductive layer <b>140</b> then may be planarized to form a planar surface.

Following formation of second conductors <b>22</b>, the resultant structure may be annealed to crystallize the deposited semiconductor material of diodes <b>14</b> (and/or to form silicide regions by reaction of the silicide-forming metal layer <b>52</b> with p+ region <b>14</b><i>c</i>). The lattice spacing of titanium silicide and cobalt silicide are close to that of silicon, and it appears that silicide layers <b>50</b> may serve as “crystallization templates” or “seeds” for adjacent deposited silicon as the deposited silicon crystallizes (e.g., silicide layer <b>50</b> enhances the crystalline structure of silicon diode <b>14</b> during annealing at temps of about 600-800° C.). Lower resistivity diode material thereby is provided. Similar results may be achieved for silicon-germanium alloy and/or germanium diodes.

Thus in at least one embodiment, a crystallization anneal may be performed for about 10 seconds to about 2 minutes in nitrogen at a temperature of about 600 to 800° C., and more preferably between about 650 and 750° C. Other annealing times, temperatures and/or environments may be used.

Persons of ordinary skill in the art will understand that alternative memory cells in accordance with this invention may be fabricated in other similar techniques. For example, memory cells may be formed that include reversible resistance switching element <b>12</b> below diode <b>14</b>.

The foregoing description discloses only exemplary embodiments of the invention. Modifications of the above disclosed apparatus and methods which fall within the scope of the invention will be readily apparent to those of ordinary skill in the art. For instance, in any of the above embodiments, the carbon-based material may be located below the diodes <b>14</b>. As stated, although the invention has been described primarily with reference to amorphous carbon, other carbon-based materials may be similarly used. Further, each carbon-based layer is preferably formed between two conducting layers such as titanium nitride or other barrier/adhesion layers to form a MIM stack in series with a steering element.

Accordingly, although the present invention has been disclosed in connection with exemplary embodiments thereof, it should be understood that other embodiments may fall within the spirit and scope of the invention, as defined by the following claims.