US8525320B2

Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

Summary by NHIP

Stacked microelectronic die packages

The system stacks three die packages vertically, aligning their lateral metal contacts. Metal solder connectors join the upper and middle packages to the lower package through wetting across the gaps between dielectric casings.

Claim Score by NHIP

Read claim 12, the broadest

Abstract

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

US8525320B2, drawing sheet 1 — Sheet 1 of 11

Term

1.1 yearsleft in the term

Expires 24 October 2027.

18 claims: 3 independent, 15 dependent

1
A stacked system of microelectronic die packages, comprising:a first die package including a first die and a first dielectric casing at least partially covering the first die, first lateral sides along the first dielectric casing, and first metal contacts having first lateral contact surfaces along the first lateral sides of the first dielectric casing;a second die package including a second die and a second dielectric casing at least partially covering the second die, second lateral sides along the second dielectric casing, and second metal contacts having second lateral contact surfaces along the second lateral sides of the second dielectric casing, wherein the second die package is stacked on top of the first die package and the first metal contacts are at least generally aligned with corresponding second metal contacts;a third die package including a third die and a third dielectric casing at least partially covering the third die, third lateral sides along the third dielectric casing, and third metal contacts having third lateral contact surfaces along the third lateral sides of the third dielectric casing wherein the third metal contacts are at least generally aligned with corresponding first metal contacts;and metal solder connectors including first-set connectors and second-set connectors, wherein the first-set connectors are coupled to individual first metal contacts and individual second metal contacts, and wherein the second-set connectors are coupled to individual first metal contacts and individual third metal contacts, and wherein at least a portion of the first-set connectors contacts the first and second lateral contact surfaces, and wherein at least a portion of the second-set connectors contacts the first and third lateral contact surfaces, and wherein the first-set connectors are physically and electrically isolated from the individual third metal contacts while the second-set connectors are physically and electrically isolated from the individual second metal contacts.
7
A stacked system of microelectronic die packages, comprising:a first die package having a first lateral edge and first metal leads having first contact surfaces flush with the first lateral edge;a second die package having a second lateral edge and second metal leads having second contact surfaces flush with the second lateral edge, wherein the second contact surfaces are generally aligned with the first lateral contact surfaces;a third die package having a third lateral edge and third metal leads having third contact surfaces flush with the third lateral edge, wherein the third contact surfaces are generally aligned with the first lateral contact surfaces;and external electrically conductive inter-package connectors, including first-set connectors and second-set connectors, wherein the individual first-set connectors are connected to one of the first contact surfaces and a corresponding second contact surface, and wherein the first-set connectors comprise individual metal solder lines that bridge a first gap between the first die package and the second die package, and wherein the individual second-set connectors are connected to one of the first contact surfaces and a corresponding third contact surface, and wherein the second-set connectors comprise individual metal solder lines that bridge a second gap between the first die package and the third die package, and wherein the first-set connectors are physically and electrically isolated from the corresponding third contact surface while the second-set connectors are physically and electrically isolated from the corresponding second contact surface.
12
Broadest claimClaim Score 56, average(NHIP)A microelectronic device, comprising:a molded dielectric material having lateral-side, bottom-side, and top-side surfaces;a die at least partially encapsulated within the dielectric material and spaced laterally apart from the lateral surface of the dielectric material;and individual metal leads electrically coupled with the die and the individual metal leads having a wetting surface configured for attaching external inter-package solder lines, wherein the wetting surface includes an exposed metal portion that is flush with the lateral surface of the dielectric material and at least one of the top-side and bottom-side surfaces of the dielectric material, and wherein the external inter-package solder lines include first-set solder lines and second-set solder lines;wherein the first-set solder lines are coupled to a first external device while the second-set solder lines are coupled to a second external device, and wherein the first-set connectors are physically and electrically isolated from the second external device while the second-set connectors are physically and electrically isolated from the first external device.

Independent claims3

46 paragraphs in 5 sections, as filed

0001This application is a divisional of U.S. application Ser. No. 11/923,290 filed Oct. 24, 2007, now U.S. Pat. No. 7,947,529, which claims foreign priority benefits of Republic of Singapore Application No. 200706008-0 filed Aug. 16, 2007, each of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

0002The present disclosure is directed generally to microelectronic die packages with leadframes, and more particularly to leadframes configured for stacked die packages.

BACKGROUND

0003Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, and/or other microelectronic assemblies.

0004In one conventional arrangement, the die is mounted to a supporting substrate (e.g., a printed circuit board), and the die bond pads are electrically coupled to corresponding bond pads of the substrate with wirebonds. After encapsulation, the substrate can be electrically connected to external devices with solder balls or other suitable connections. Accordingly, the substrate supports the die and provides an electrical link between the die and the external devices.

0005In other conventional arrangements, the die can be mounted to a leadframe that has conductive lead fingers connected to a removable frame. The frame temporarily supports the lead fingers in position relative to the die during manufacture. Each lead finger is coupled to a corresponding bond pad of a die (e.g., via a wire bond or a metal redistribution layer), and the assembly is encapsulated in such a way that the frame and a portion of each of the lead fingers extend outside the encapsulating material. The frame is then trimmed off, and the exposed portions of each lead finger connect the die to external components. In general, individual lead fingers can be bent and then coupled to a corresponding external bond pad.

0006Die manufacturers have come under increasing pressure to reduce the size of dies and the volume occupied by the dies, and to increase the capacity of the resulting encapsulated assemblies. To meet these demands, die manufacturers often stack multiple dies on top of each other to increase the capacity or performance of the device within the limited surface area on the circuit board or other element to which the dies are mounted.

BRIEF DESCRIPTION OF THE DRAWINGS

0007<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> are cross-sectional side views of a stacked system that includes microelectronic die packages configured and stacked in accordance with an embodiment of the disclosure.

0008<figref idref="DRAWINGS">FIG. 2A</figref> is a top view of a microelectronic assembly that includes a frame, a release layer, and a support substrate.

0009<figref idref="DRAWINGS">FIGS. 2B and 2C</figref> are partially exploded cross-sectional side views of the assembly of <figref idref="DRAWINGS">FIG. 2A</figref>.

0010<figref idref="DRAWINGS">FIG. 3A</figref> is a top view of the assembly of <figref idref="DRAWINGS">FIG. 2A</figref> having microelectronic dies positioned within openings of the frame.

0011<figref idref="DRAWINGS">FIGS. 3B and 3C</figref> are cross-sectional side views of the assembly of <figref idref="DRAWINGS">FIG. 3A</figref>.

0012<figref idref="DRAWINGS">FIG. 4A</figref> is a top view of the assembly of <figref idref="DRAWINGS">FIG. 3A</figref> encapsulated in a dielectric material.

0013<figref idref="DRAWINGS">FIGS. 4B and 4C</figref> are cross-sectional side views of the assembly of <figref idref="DRAWINGS">FIG. 4A</figref>.

0014<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are cross-sectional side views of the assembly of <figref idref="DRAWINGS">FIG. 4A</figref> after partial removal of the dielectric material.

0015<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are cross-sectional side and bottom views of the assembly of <figref idref="DRAWINGS">FIGS. 5A and 5B</figref> after removing the support substrate.

0016<figref idref="DRAWINGS">FIG. 7A</figref> is a cross-sectional side view of the assembly of <figref idref="DRAWINGS">FIGS. 6A and 6B</figref> after forming a spacer layer.

0017<figref idref="DRAWINGS">FIG. 7B</figref> is a cross-sectional side view of the assembly of <figref idref="DRAWINGS">FIG. 7A</figref> after lead thinning in accordance with an alternative embodiment of the disclosure.

0018<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional side view of the assembly of <figref idref="DRAWINGS">FIG. 7A</figref> after singulation.

0019<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional side view of a stacked system that includes microelectronic die packages configured and stacked in accordance with an alternative embodiment of the disclosure.

0020<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional side view of a stacked system having microelectronic die packages that include dies of different sizes in accordance with an embodiment of the disclosure.

0021<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional side view of a stacked system having metal traces for selectively electrically coupling individual microelectronic die packages in accordance with an embodiment of the disclosure.

0022<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional side view of a stacked system having metal solder connectors configured for selectively electrically coupling individual microelectronic die packages in accordance with an embodiment of the disclosure.

0023<figref idref="DRAWINGS">FIG. 13</figref> is a schematic illustration of a system in which the microelectronic die packages and stacked systems may be incorporated.

DETAILED DESCRIPTION

0024Specific details of several embodiments of the disclosure are described below with reference to semiconductor devices and methods for fabricating semiconductor devices. The semiconductor components are manufactured on semiconductor wafers that can include substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, optics, read/write components, and other features are fabricated. For example, SRAM, DRAM (e.g., DDR/SDRAM), flash memory (e.g., NAND flash memory), processors, imagers, and other types of devices can be constructed on semiconductor wafers. Although many of the embodiments are described below with respect to semiconductor devices that have integrated circuits, other types of devices manufactured on other types of substrates may be within the scope of the invention. Moreover, several other embodiments of the invention can have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the invention may have other embodiments with additional elements, or the invention may have other embodiments without several of the features shown and described below with reference to <figref idref="DRAWINGS">FIGS. 1A-13</figref>.

0025<figref idref="DRAWINGS">FIGS. 1A and 1B</figref> are cross-sectional side views of one embodiment of a stacked system 102 having a plurality of die packages 100 (identified individually by reference numbers 100a-d). Individual die packages 100 can include a microelectronic die 107, a molded dielectric casing 106, and metal leads 108 (or metal contacts) that are spaced apart from lateral sides of the die 107. The casing 106 has lateral sides 103, a top side 104, and a bottoms side 105, and the casing 106 encapsulates at least a portion of the die 107 and the leads 108. The die packages 100 further include metal traces 110 that electrically couple the leads 108 to the die 107 and a dielectric spacer layer 112 encasing the traces 110 and a portion of an active side of the die 107. The die packages 100 can also include package bond pads 114 coupled to the traces 110. The stacked system 102, for example, has an interposer substrate 118 with metal bump pads 117 electrically connected to the bond pads 114 at the first die package 100a by bond pad connections 116.

0026The stacked system 102 shown in <figref idref="DRAWINGS">FIGS. 1A and 1B</figref> includes the four stacked die packages 100a-d physically coupled together, at least in part, by adhesive layers 119a-c, and the leads 108 of the die packages 100a-d electrically coupled together by external inter-package connectors 120. The connectors 120, for example, can be metal solder lines that wet to lateral contact surfaces of the leads 108 at the lateral sides 103 of the casing 106, but do not wet to the casing 106 itself. In this embodiment, the connectors 120 form along at least the lateral contact surfaces of sets of vertically aligned leads 108 and across die package gaps 115 between such vertically aligned leads 108 to electrically bridge the die packages 100a-d. Thus, the bonds 116 are electrically coupled to microelectronic dies within the die packages 100a-d through conduction paths that include the leads 108 and the connectors 120. As shown in <figref idref="DRAWINGS">FIGS. 1A and 1B</figref>, the external inter-package connectors 120 may also attach to top and bottom contact surfaces of the leads 108 at the top and bottom surfaces 104-105 of the casing 106, respectively. In alternative embodiments, the connectors 120 may attach only to the portion of the leads 108 flush with the lateral surfaces 103 of the casing 106, or combinations of the surfaces of the leads 108 at the lateral, top, and bottom surfaces 103-105 of the casing 106. Accordingly, several embodiments of the connectors 120 have a portion that projects at least laterally outward from the lateral edges of the die package 100a-d and another portion that extends between the top and bottom sides of individual die packages 100a-d.

0027The stacked system 102 may be formed by a method that includes stacking the die packages 100a-d, aligning the leads 108 of the die packages 100a-d, and forming the connectors 120 at individual leads 108 of the die packages 100a-d. Stacking and aligning the leads 108 may include stacking the die packages 100a-d in sequence so that the leads 108 are placed above and/or below leads on a corresponding die package. Forming the connectors 120 may be carried out, for example, using wave or reflow soldering processes. Using wave soldering, a pumped wave or cascade of liquid-phase metal solder can be applied across lateral sides of the die packages 100a-d. Using reflow soldering, solder paste having metal powder particles can be applied across the lateral sides of the die packages 100a-d and then heated to melt the metal particles. In these, or other soldering processes, the metal solder selectively wets (e.g., when heated) to the higher energy surfaces associated with the leads 108 and not to the lower energy surfaces associated with the casing 106. When the metal solder cools, the connectors 120 are formed across individual leads 108. A die package spacing distance t1 of 60 microns, for example, may ensure that the surface tension associated with the applied solder allows the connectors 120 to bridge between the leads 108.

0028In general, and in contrast to the stacked system 102, conventional methods of stacking packages or dies have been challenging and expensive, and even then misalignments occur. For example, conventional leads need to be accurately aligned, and thus attaching a conventional lead on one package to a conventional lead on a corresponding package is time-intensive. Also, because individual leads occupy only a small surface area, each conventional lead-to-lead interconnection needs to be carefully inspected. The process of stacking conventional packages is also difficult to standardize because dies are made in a variety of sizes, and packages likewise vary in size. Thus, the process of stacking and interconnecting conventional packages needs to be tailored to an arrangement of a particular package type.

0029By using the leads 108 as a framework for interconnecting devices, however, several embodiments of microelectronic die packages 100 can overcome these and other issues related to conventional die package stacking. For example, because the leads 108 are exposed at lateral surface portions of the casing 106, each set of leads can be electrically coupled together using a simple soldering process to intercouple the die packages 100a-d. Also, because the connectors 120 can selectively wet to the conductive leads 108 but not attach to the casing 106 between the leads 108, the lead-to-lead interconnections are reliable and do not require the same alignment tolerances as conventional lead-to-lead inspection. The leads 108 can further establish the exterior package dimensions such that a standardized package size may be used to house a variety of differently sized dies, an example of which is described further with reference to <figref idref="DRAWINGS">FIG. 10</figref>.

0030<figref idref="DRAWINGS">FIGS. 2A-8</figref> illustrate stages of forming the microelectronic die package 100a in accordance with one embodiment of the disclosure. <figref idref="DRAWINGS">FIG. 2A</figref> is a top view of a microelectronic assembly 121 that includes a metal frame 122 and a release layer 124. The frame 122 comprises openings 126, metal lead portions 127, and dicing lanes 128. The openings 126 expose a portion of the release layer 124 for attaching and positioning the die 107 adjacent to the lead portions 127, and the dicing lanes 128 provide a cutting or cleavage path for singulating the individual die package 100a from the frame 122 (described further with reference to <figref idref="DRAWINGS">FIG. 8</figref>). In one embodiment, the frame 122 may be made from copper and may include selective copper plating along the lead portions 127. In other embodiments, the frame 122 may comprise a variety of other metallic materials such as aluminum or an aluminum-copper alloy. The release layer 124 may be, for example, a thermal or UV release film.

0031<figref idref="DRAWINGS">FIGS. 2B and 2C</figref> are partially exploded cross-sectional side views of the assembly 121 showing the frame 122, the release layer 124, and a support substrate 130 (e.g., a silicon wafer or other type of structure having planar surface). <figref idref="DRAWINGS">FIGS. 2B and 2C</figref> also show individual dicing lane 128, first tier and second tier portions 132-133 of the lead portions 127, and gaps 136 between individual lead portions 127. The first and second tier portions 132-133, the gaps 136, and the support substrate 130 define bottom and lateral sides of a cavity, which will be subsequently filled with a dielectric material (described further with reference to <figref idref="DRAWINGS">FIGS. 4A-C</figref>).

0032<figref idref="DRAWINGS">FIG. 3A</figref> is a top view of the assembly 121 after microelectronic die placement. <figref idref="DRAWINGS">FIG. 3A</figref>, more specifically, shows the frame 122, the lead portions 127, and the openings 126, with individual dies 107 placed within the openings 126 and adjacent to the lead portions 127. <figref idref="DRAWINGS">FIGS. 3B and 3C</figref> are cross-sectional side views further showing the openings 126, the first tier and second tier portions 132-133 of the lead portions 127, and a top-side surface 139 of the dies 107. The first tier portions 132 are below the top-side surface 139 of the dies 107 and the second tier portions 133 extend above the top-side surface 139. In one embodiment, the second tier portions 133 may have a thickness t2 in the range of about 250 to 1000 microns. In another embodiment, t2 could be on the order of 650 microns or larger, which would eliminate a need for backgrinding the dies 107. In addition, it is also contemplated that the first and second tier portions 132-133 could have thicknesses that are configured to promote heat conduction away from the dies 107.

0033<figref idref="DRAWINGS">FIG. 4A</figref> is a top view of the assembly 121 after a dielectric material 140 has been formed on a top side of the metal frame 122 and a top side of the dies 107. The dielectric material 140, for example, may be a polymer or plastic that is heated and subsequently deposited on top of and within the gaps of the frame 122. The dielectric material 140, for example, can be molded over the frame 122 and the top sides of the dies 107. <figref idref="DRAWINGS">FIGS. 4B and 4C</figref> are cross-sectional side views showing the dielectric material 140 filling the openings 126 around the dies 107 and the gaps 136 between the lead portions 127. After curing and/or cooling, the hardened dielectric material 140 should form a protective and electrically isolative covering over the dies 107, within gaps between lateral sides 142 of the dies 107 and the lead portions 127, and within the gaps 136. To ensure that all of the leads and dies within the assembly 121 are encapsulated, the dielectric material 140 may optionally extend above the lead portions 127 by a thickness t3.

0034<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are cross-sectional side views of the assembly 121 after partial removal of the dielectric material 140 that show a top-side surface 146 of the dielectric material 140 flush with a top-side surface 148 of the lead portions 127. A backgrinding process, chemical etch, or chemical-mechanical polishing process may remove the upper portion of the dielectric material 140 to create the planar surface 146 for package-to-package stacking and to expose the top-side surface portions 148 of the lead portions 127 for electrical coupling between individual die packages.

0035<figref idref="DRAWINGS">FIGS. 6A and 6B</figref> are cross-sectional side and bottom views of the assembly 121 after removing the release layer 124 and the support substrate 130 to expose a bottom-side surface 150 (e.g., active side) of the dies 107 and expose bottom-side surfaces 152 of the lead portions 127. The bottom-side surfaces 150 of the dies 107 include bond pads 154 (or active features) electrically coupled to an integrated circuit within the dies 107 (not shown). The dielectric material 140 holds the dies 107 in place and separates the dies 107 from the lead portions 127.

0036<figref idref="DRAWINGS">FIG. 7A</figref> is a cross-sectional side view of the assembly 121 after forming an embodiment of the dielectric spacer layer 112 at the bottom-side surface 150 of the dies 107. The spacer layer 112 includes metal traces 110 electrically coupling the bond pads 154 to the lead portions 127 and the package bond pads 114. The spacer layer 112 may be made from a material such as a non-conductive oxide or polymer. The metal traces 110 and the package bond pads 114, for example, may be made from copper or aluminum. The spacer layer 112 can accordingly be a redistribution structure. It is also contemplated that in certain embodiments, the package bond pads 114 may be omitted. For example, in <figref idref="DRAWINGS">FIG. 1A</figref> the package bond pads of the die packages 100b-d could be omitted because these pads are not electrically connected to any external bond pads.

0037<figref idref="DRAWINGS">FIG. 7B</figref> is a cross-sectional side view that illustrates an additional or alternative stage in forming a microelectronic die package in accordance with another embodiment. In this embodiment, the lead portions 127 are thinned to a thickness so that the dielectric material 140 extends above the top-side surfaces 148 of the lead portions 127 and retains the planar surface 146 attained in the stage of <figref idref="DRAWINGS">FIGS. 5A-B</figref>. A chemical etch, for example, may thin the lead portions 127 without removing material from the dielectric material.

0038<figref idref="DRAWINGS">FIG. 8</figref> is a cross-sectional side view of the package 100a after singulation through the dicing lanes 128 (e.g., by a dicing saw or a chemical etch) to yield separated dies 107 housed in casings 106 and coupled to the leads 108. The singulation process forms exposed surface portions 157 of the leads 108 along the lateral edges of the casings. The top- and bottom-side surfaces 148 and 152 of the leads 108 can also be exposed or otherwise accessible. Accordingly, the die package 100a may be placed within a stacked system, such as the stacked system 102, and the connectors 120 can be formed along the die package 100a at any of the surfaces 148, 152, and 157.

0039Many variations may be made to the stacked system 102. For example, in lieu of the bond pad connections 116 shown in <figref idref="DRAWINGS">FIG. 1A</figref>, wire bonds may electrically couple the stacked system 102 to an interposer substrate. In other embodiments, the adhesive layers 119a-c interposed between the stacked packages may not be necessary. The connectors 120 alone, for example, could be used to hold the individual die packages 100a-d together by temporarily clamping the packages 100a-d until metal solder is applied and the connectors 120 are formed. Also, the stacked system may include any number of individual microelectronic die packages having more or fewer packages than those presented in the illustrated embodiments.

0040In another embodiment, the stacked system 102 includes packages that house the same type of die. For example, the stacked system 102 could be a memory, such as a static dynamic access memory (SRAM). In this embodiment, the leads 108 would provide word and bit line access to individual SRAM dies housed in the die packages 100a-d. Accordingly, the aggregated individual SRAM dies form a large SRAM, which has a reduced footprint relative to a conventional SRAM of the same size.

0041<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional side view showing an alternative embodiment of a stacked system 158 including microelectronic die packages formed in accordance with the additional, alternative stage described with reference to <figref idref="DRAWINGS">FIG. 7B</figref> and having a casing 159 that extends above the leads 108. Thus, this embodiment may be used, for example, to stack microelectronic die packages that house thick or non-backgrinded dies.

0042<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional side view showing a stacked system 160 that includes microelectronic die packages 162a-c having corresponding microelectronic dies 164a-c. The die packages 162a-c share a common lateral dimension d1, but the microelectronic dies 164a-c have different lateral dimensions d2, d3, and d4. In one embodiment, the stacked system 160 may be a memory module that includes an interface circuit at the die 164a; a control circuit at the die 164b; and a memory at the die 164c. Because the packages 162a-c share the common lateral dimension d1, a myriad of different types of stacked systems may be created by stacking preferred die packages or exchanging certain die packages. For example, an alternative embodiment of the DRAM-based memory module could be assembled by using smaller magnetoresistive RAM (MRAM) based dies housed in die packages having the lateral dimension d1. Accordingly, DRAM-based die packages 162b-c could be exchanged for MRAM-based die packages.

0043<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional side view showing a stacked system 170 that includes microelectronic die packages 172a-d separated by dielectric spacer layers 174a-d and having corresponding first metal leads 176a-d and second metal leads 178a-d respectively coupled together by first and second connectors 184a-b. In this view, the spacer layer 174a includes corresponding metal traces 180a-b, the spacer layer 174c includes corresponding metal traces 181a-b, the spacer layer 174d includes a single metal trace 182, and the spacer layer 174b includes no corresponding metal traces. The first connector 184a is applied across the first leads 176a-d to selectively electrically couple first, third, and fourth packages 172a, 172c, and 172d; and the second connector 184b is applied across the second leads 178a-d to selectively electrically couple the first and third packages 172a and 172c. Thus, one side of the die package 172d and both sides of the die package 172b are electrically isolated from the connectors 184a-b. The process of stacking the die packages 172a-d can be the same as the process described with reference to <figref idref="DRAWINGS">FIGS. 1A-B</figref>. The process of forming the die packages 172a-d can be similar to the method of manufacturing described with reference to <figref idref="DRAWINGS">FIGS. 2A-8</figref>, but instead of connecting a metal trace to every metal lead, individual metal trace-lead couplings have been omitted.

0044<figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional side view showing a stacked system 190 having microelectronic die packages 192a-d and individual external inter-package connectors 194a-c intercoupling the die packages 192a-d at corresponding sets of leads 196a-c. The connector 194a intercouples the first, second, and third die packages 192a-c at the first set of leads 196a; the connector 194b intercouples the third and fourth die packages 192c-d at the second set of leads 196b; and the connector 194c intercouples the first, second, third, and fourth die packages 192a-d at the third set of leads 196c. The connectors 194a-c can be configured to selectively route individual sets of the leads by applying metal solder across a limited lateral surface portion of packaging casing. Leads that are not soldered to remain electrically isolated from the stacked system 190. Combinations of the techniques illustrated in <figref idref="DRAWINGS">FIGS. 10-11</figref> may be employed to create a desired stacked system that includes a variety of die packages that perform an aggregated circuit function in other embodiments (i.e., by omitting certain metal traces within the dielectric spacer layers and not forming metal solder connectors at certain metal leads).

0045Any one of the microelectronic devices described above with reference to <figref idref="DRAWINGS">FIGS. 1A-12</figref> can be incorporated into any of a myriad of larger and/or more complex systems 490, a representative one of which is shown schematically in <figref idref="DRAWINGS">FIG. 13</figref>. The system 490 can include a processor 491, a memory 492 (e.g., SRAM, DRAM, Flash, and/or other memory device), input/output devices 493, and/or other subsystems or components 494. Microelectronic devices may be included in any of the components shown in <figref idref="DRAWINGS">FIG. 13</figref>. The resulting system 490 can perform any of a wide variety of computing, processing, storage, sensor, imaging, and/or other functions. Accordingly, representative systems 490 include, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants), multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Other representative systems 490 include cameras, light or other radiation sensors, servers and associated server subsystems, display devices, and/or memory devices. In such systems, individual dies can include imager arrays, such as CMOS imagers. Components of the system 490 may be housed in a single unit or distributed over multiple, interconnected units, e.g., through a communications network. Components can accordingly include local and/or remote memory storage devices and any of a wide variety of computer-readable media.

0046From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising” is inclusive and is used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. It will also be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the inventions. For example, many of the elements of one of embodiment can be combined with other embodiments in addition to, or in lieu of, the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims.

Contents5

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Showing 100 of 168

9 members in 4 offices

This recordMember, by publication date

Members9

Family members, oldest first
Document	Office	Kind
US2009045489A1	United States of America	A1	2009-02-19
WO2009025974A2	World Intellectual Property Organization (WIPO)	A2	2009-02-26
SG150396A1	Singapore	A1	2009-03-30
WO2009025974A3	World Intellectual Property Organization (WIPO)	A3	2009-05-07
TW200933760A	Taiwan Province of China	A	2009-08-01
US7947529B2	United States of America	B2	2011-05-24
US2011215453A1	United States of America	A1	2011-09-08
TWI402921B	Taiwan Province of China	B	2013-07-21
US8525320B2This record	United States of America	B2	2013-09-03

58 transactions on the USPTO file

Allowed after 1 non-final rejection, 1 final rejection and 1 RCE.

Non-final rejections: 1
Final rejections: 1
RCEs: 1
Appeals: 0

Over time

Point at a mark for the transaction

Transactions

Prosecution transactions, newest first
	Event	Code
2025-01-16	Payment of Maintenance Fee, 12th Year, Large EntityM1553	M1553
2021-02-23	Payment of Maintenance Fee, 8th Year, Large EntityM1552	M1552
2013-09-03	Recordation of Patent Grant MailedPGM/	PGM/
2013-09-03	Patent Issue Date Used in PTA CalculationAllowedPTAC	PTAC
2013-08-15	Email NotificationEML_NTR	EML_NTR
2013-08-14	Issue Notification MailedAllowedWPIR	WPIR
2013-08-02	Dispatch to FDCD1935	D1935
2013-08-02	Application Is Considered Ready for IssuePILS	PILS
2013-07-31	Response to Reasons for AllowanceREAS	REAS
2013-07-31	Issue Fee Payment VerifiedN084	N084
2013-07-31	Issue Fee Payment ReceivedIFEE	IFEE
2013-05-15	Electronic ReviewELC_RVW	ELC_RVW
2013-05-15	Email NotificationEML_NTF	EML_NTF
2013-05-15	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2013-05-08	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2013-05-04	Reasons for Allowance	–
2013-01-26	Date Forwarded to ExaminerFWDX	FWDX
2013-01-26	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2013-01-23	Request for Continued Examination (RCE)RCEX	RCEX
2013-01-23	Workflow - Request for RCE - BeginBRCE	BRCE
2012-12-11	Information Disclosure Statement consideredIDSC	IDSC
2012-12-11	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-12-11	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-10-23	Electronic ReviewELC_RVW	ELC_RVW
2012-10-23	Email NotificationEML_NTF	EML_NTF
2012-10-23	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2012-10-16	Final RejectionFinal rejectionCTFR	CTFR
2012-09-13	Date Forwarded to ExaminerFWDX	FWDX
2012-09-10	Response after Non-Final ActionA...	A...
2012-08-27	Information Disclosure Statement consideredIDSC	IDSC
2012-08-27	Electronic Information Disclosure StatementEIDS.	EIDS.
2012-08-27	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2012-06-12	Electronic ReviewELC_RVW	ELC_RVW
2012-06-12	Email NotificationEML_NTF	EML_NTF
2012-06-12	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2012-06-04	Non-Final RejectionNon-final rejectionCTNF	CTNF
2012-05-12	Date Forwarded to ExaminerFWDX	FWDX
2012-05-10	Response to Election / Restriction FiledELC.	ELC.
2012-05-10	Request for Extension of Time - GrantedXT/G	XT/G
2012-01-10	Electronic ReviewELC_RVW	ELC_RVW
2012-01-10	Email NotificationEML_NTF	EML_NTF
2012-01-10	Mail Restriction RequirementMCTRS	MCTRS
2012-01-04	Restriction/Election RequirementCTRS	CTRS
2011-09-09	Email NotificationEML_NTR	EML_NTR
2011-09-08	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2011-08-24	Case Docketed to Examiner in GAUDOCK	DOCK
2011-06-01	Application Is Now CompleteCOMP	COMP
2011-06-01	Email Notification	–
2011-06-01	Email Notification	–
2011-06-01	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2011-06-01	Filing ReceiptFLRCPT.O	FLRCPT.O
2011-05-31	Application Dispatched from OIPEOIPE	OIPE
2011-05-22	Cleared by OIPE CSR	–
2011-05-18	Information Disclosure Statement consideredIDSC	IDSC
2011-05-18	Electronic Information Disclosure StatementEIDS.	EIDS.
2011-05-18	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2011-05-18	IFW Scan & PACR Auto Security Review	–
2011-05-18	Initial Exam Team nnIEXX	IEXX

17 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2025-01-16	Maintenance fee paymentMAFP	MAFP
2021-02-23	Maintenance fee paymentMAFP	MAFP
2019-11-12	AssignmentAS	AS
2019-11-12	AssignmentAS	AS
2019-10-09	AssignmentAS	AS
2018-08-23	AssignmentAS	AS
2018-07-13	AssignmentAS	AS
2018-07-13	AssignmentAS	AS
2017-06-08	AssignmentAS	AS
2017-06-08	AssignmentAS	AS
2017-02-16	Fee paymentFPAY	FPAY
2016-06-02	AssignmentAS	AS
2016-06-02	AssignmentAS	AS
2016-05-12	AssignmentAS	AS
2016-05-12	AssignmentAS	AS
2013-08-14	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2012-12-08	Fee payment procedurePAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITYFEPP	FEPP

Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

Summary by NHIP

Claim Score by NHIP

Abstract