Multi-chip package having semiconductor chips of different thicknesses from each other and related device

CROSS-REFERENCE TO RELATED APPLICATION

0001This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-11117 filed on Feb. 5, 2010, in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference.

BACKGROUND

00021. Field

0003Example embodiments relate to a semiconductor device and a method of fabricating the same, and more particularly, to a multi-chip package having semiconductor chips of different thicknesses from each other, a semiconductor device employing the same, and a method of fabricating the same.

00042. Description of Related Art

0005As electronic devices become lighter, thinner, and more compact, technology for realizing a multi-chip package has been studied in various ways. However, stacking of a plurality of semiconductor chips has faced challenges due to the difference of coefficients of thermal expansion (CTE) and thermal budget.

SUMMARY

0006Example embodiments provide a semiconductor device employing a stacked structure of semiconductor chips and having excellent reliability.

0007Example embodiments also provide a method of fabricating a semiconductor device employing a stacked structure of semiconductor chips and having excellent reliability.

0008In accordance with example embodiments, a semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, and at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.

0009In accordance with example embodiments, a method of fabricating a semiconductor device, may include preparing a first semiconductor chip, stacking at least one second semiconductor chip on the first semiconductor chip, the at least one second semiconductor chip including a plurality of through silicon vias, forming at least one external contact terminal on the at least one second semiconductor chip, the at least one second external contact terminal being in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the through silicon vias, and attaching a sub-board on the first semiconductor chip, wherein the at least one second semiconductor chip is thinner that the first semiconductor chip.

0010In accordance with example embodiments, a semiconductor device may have semiconductor chips of different thicknesses from each other. The semiconductor device may include one or more thin semiconductor chips stacked on the semiconductor chip. The thin semiconductor chips may include a plurality of through silicon vias and have thicknesses less than the semiconductor chip. A plurality of external contact terminals may be formed on a surface of one of the thin semiconductor chips. The external contact terminals may be in electrical contact with the semiconductor chip and the thin semiconductor chips via the through silicon vias.

0011In example embodiments, the semiconductor chip may have a thickness twice to 300 times greater than the maximum length of each through silicon via. The semiconductor chip may not include the through silicon vias.

0012In example embodiments, a plurality of internal contact terminals formed on a surface of the semiconductor chip may be provided. The through silicon vias may be arranged with the internal contact terminals, and the internal contact terminals may be smaller than the external contact terminals. The internal contact terminals may be formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof.

0013In example embodiments, the external contact terminals may be formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, a pin grid array (PGA), a lead grid array (LGA), and a combination thereof.

0014In example embodiments, an encapsulant covering the semiconductor chip and the thin semiconductor chips may be provided. The encapsulant may cover sidewalls of the semiconductor chip and the thin semiconductor chips. In example embodiments, one surface of the semiconductor chip may be exposed.

0015In example embodiments, a main board facing one of the thin semiconductor chips may be provided. The external contact terminals may be in electrical contact with the main board.

0016In example embodiments, a sub-board attached to a surface of the semiconductor chip may be provided.

0017In accordance with example embodiments, a semiconductor device may include a main board and a sub-board, which may face each other. A semiconductor chip formed between the main board and the sub-board may be provided. One or more semiconductor chips formed between the semiconductor chip and the main board and including a plurality of through silicon vias may also be provided. A plurality of external contact terminals formed between one of the thin semiconductor chips and the main board may be provided. The main board may be in electrical contact with the semiconductor chip and the thin semiconductor chips via the through silicon vias.

0018In example embodiments, the semiconductor chip may be thicker than the thin semiconductor chips.

0019In example embodiments, an encapsulant covering the semiconductor chip and the thin semiconductor chips may be provided. The encapsulant may cover sidewalls of the semiconductor chip and the thin semiconductor chips and may extend between one of the thin semiconductor chips and the main board. An underfill formed between the main board and the encapsulant may be provided. The encapsulant may cover the sub-board.

0020In example embodiments, a plurality of internal contact terminals formed on a surface of the semiconductor chip may be provided. The through silicon vias may be arranged with the internal contact terminals. The internal contact terminals may be smaller than the external contact terminals.

0021In accordance with example embodiments, a method of fabricating a semiconductor device may include preparing a semiconductor chip and stacking one or more thin semiconductor chips having thicknesses less than the semiconductor chip on the semiconductor chip. The thin semiconductor chips may include a plurality of through silicon vias. A plurality of external contact terminals may be formed of on a surface of one of the thin semiconductor chips. The external contact terminals may be in electrical contact with the semiconductor chip and the thin semiconductor chips via the through silicon vias.

0022In example embodiments, an encapsulant covering the semiconductor chip and the thin semiconductor chips may be formed.

0023In example embodiments, after the thin semiconductor chips are stacked on the semiconductor chip, the semiconductor chip may be partially removed to reduce a thickness.

0024In example embodiments, a sub-board may be attached to a surface of the semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

0025The foregoing and other features and advantages of example embodiments will be apparent from the more particular description of example embodiments, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of example embodiments. In the drawings:

0026<figref idref="DRAWINGS">FIGS. 1 and 3</figref> through <b>5</b> are cross-sectional views of a multi-chip package according to example embodiments;

0027<figref idref="DRAWINGS">FIG. 2</figref> is an enlarged view of a part K of <figref idref="DRAWINGS">FIG. 1</figref>;

0028<figref idref="DRAWINGS">FIG. 6</figref> is a plan view of a semiconductor module employing a multi-chip package according to example embodiments;

0029<figref idref="DRAWINGS">FIG. 7</figref> is a diagram of an electronic system employing a multi-chip package according to example embodiments;

0030<figref idref="DRAWINGS">FIGS. 8 through 11</figref> are cross-sectional views illustrating a method of fabricating a multi-chip package according to example embodiments; and

0031<figref idref="DRAWINGS">FIGS. 12 through 14</figref> are cross-sectional views illustrating a method of fabricating a multi-chip package according to example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

0032Example embodiments will now be described more fully with reference to the accompanying drawings in which example embodiments are shown. Example embodiments may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concepts to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

0033It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

0034It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

0035Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

0036The terminology used herein is for the purpose of describing example embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0037Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

0038Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

0039<figref idref="DRAWINGS">FIGS. 1 and 3</figref> through <b>5</b> are cross-sectional views of a multi-chip package according to example embodiments, and <figref idref="DRAWINGS">FIG. 2</figref> is an enlarged view of a part K of <figref idref="DRAWINGS">FIG. 1</figref>.

0040Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, a multi-chip package according to example embodiments may include second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> stacked on a first semiconductor chip <b>21</b>. The first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b> may be covered with an encapsulant <b>45</b>. The first semiconductor chip <b>21</b> may be attached to a sub-board <b>11</b>. A main board <b>13</b> adjacent to the fourth semiconductor chip <b>27</b> may be provided. An underfill <b>47</b> may be interposed between the main board <b>13</b> and the encapsulant <b>45</b>. The first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b> may be in electrical contact with the main board <b>13</b> via contact terminals <b>31</b>, <b>35</b> and <b>49</b> and through silicon vias (TSVs) <b>33</b>. Adhesive layers <b>41</b> may be interposed between the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, and another adhesive layer <b>41</b> may be interposed between the first semiconductor chip <b>21</b> and the sub-board <b>11</b>.

0041The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be sequentially stacked on the first semiconductor chip <b>21</b>. The first semiconductor chip <b>21</b> may have a first thickness T<b>1</b>. Each of the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may have a second thickness T<b>2</b>. The second thickness T<b>2</b> may be less than the first thickness T<b>1</b>. Specifically, the first thickness T<b>1</b> may be twice to 300 times greater than the second thickness T<b>2</b>. In some embodiments, the first thickness T<b>1</b> may be greater than a length of the TSV <b>33</b>. For example, the first thickness T<b>1</b> may be twice to 300 times greater than the maximum length of the TSV <b>33</b>.

0042As illustrated in <figref idref="DRAWINGS">FIG. 2</figref>, the fourth semiconductor chip <b>27</b> may include a redistribution layer <b>133</b> and the TSV <b>33</b>. A chip pad <b>131</b> may be provided on a front side of the fourth semiconductor chip <b>27</b>. The front side of the fourth semiconductor chip <b>27</b> may be covered with a first insulating layer <b>141</b>, and a back side of the fourth semiconductor chip <b>27</b> may be covered with a second insulating layer <b>145</b>. The redistribution layer <b>133</b> may be formed on the first insulating layer <b>141</b>. The redistribution layer <b>133</b> may be in electrical contact with active devices (not shown) in the fourth semiconductor chip <b>27</b> via the chip pad <b>131</b>. A barrier metal layer <b>135</b> may be interposed between the redistribution layer <b>133</b> and the first insulating layer <b>141</b>. The barrier metal layer <b>135</b> may be in contact with the redistribution layer <b>133</b> and the chip pad <b>131</b>.

0043The TSV <b>33</b> may be exposed on the front and back sides through the fourth semiconductor chip <b>27</b>. A third insulating layer <b>143</b> may be interposed between the TSV <b>33</b> and the fourth semiconductor chip <b>27</b>. The TSV <b>33</b> may be insulated from the fourth semiconductor chip <b>27</b>. The barrier metal layer <b>135</b> may be interposed between the TSV <b>33</b> and the third insulating layer <b>143</b>. The barrier metal layer <b>135</b> may be in contact with the TSV <b>33</b>. The TSV <b>33</b> may project from the front surface of the fourth semiconductor chip <b>27</b>. The TSV <b>33</b> may be at substantially the same plane as the back side of the fourth semiconductor chip <b>27</b>, however, example embodiments are not limited thereto as the TSV <b>33</b> may protrude beyond the back side of the fourth semiconductor chip <b>27</b>.

0044The chip pad <b>131</b> may include at least one selected from the group consisting of aluminum (Al), copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and a combination thereof. The barrier metal layer <b>135</b> may be formed of at least one selected from the group consisting of Ti, TiN, and a combination thereof. The TSV <b>33</b> and the redistribution layer <b>133</b> may include at least one selected from the group consisting of W, WN, Ti, TiN, Ta, TaN, Al, Cu, or a combination thereof. The first to third insulating layers <b>141</b>, <b>143</b> and <b>145</b> may include at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a low-k dielectric layer, and a combination thereof. Although the chip pad <b>131</b> has been described as comprising aluminum (Al), copper (Cu), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and a combination thereof, example embodiments are not limited thereto. In other words, the list of materials provided for the chip pad is illustrative only and is not meant to limit example embodiments. Similarly, the list of materials provided for the barrier metal layer <b>135</b>, the TSV <b>33</b>, the redistribution layer <b>133</b>, and the first to third insulating layers <b>141</b>, <b>143</b> and <b>145</b>, are illustrative only and are not meant to limit example embodiments.

0045In example embodiments, the TSV <b>33</b> may be exposed on substantially the same plane as the front side or may be located at a lower plane than the front side. In addition, the TSV <b>33</b> may project from the back side or may be located at a lower plane than the back side.

0046In example embodiments, the TSV <b>33</b> may be in contact with the redistribution layer <b>133</b>. In this case, the TSV <b>33</b> may be in electrical contact with active devices (not shown) in the fourth semiconductor chip <b>27</b> via the redistribution layer <b>133</b> and the chip pad <b>131</b>.

0047As shown in <figref idref="DRAWINGS">FIG. 1</figref>, a plurality of TSVs <b>33</b> may be disposed in the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> at intervals that may or may not be predetermined. However, the first semiconductor chip <b>21</b> may not include the TSV <b>33</b>. The first semiconductor chip <b>21</b> may have a thickness greater than a length of the TSV <b>33</b>. Internal contact terminals <b>31</b> may be provided on the first semiconductor chip <b>21</b>. The internal contact terminals <b>31</b> may be in electrical contact with active devices (not shown) in the first semiconductor chip <b>21</b>. Each of the internal contact terminals <b>31</b> may be one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof.

0048In example embodiments, the first semiconductor chip <b>21</b> may include components similar to the redistribution layer <b>133</b> of <figref idref="DRAWINGS">FIG. 2</figref> and the chip pad <b>131</b> of <figref idref="DRAWINGS">FIG. 2</figref>. In this case, the internal contact terminals <b>31</b> may be formed on a redistribution layer similar to the redistribution layer <b>133</b> of <figref idref="DRAWINGS">FIG. 2</figref>.

0049The second semiconductor chip <b>23</b> may include the plurality of TSVs <b>33</b>. Ends of the TSVs <b>33</b> may be in contact with the internal contact terminals <b>31</b>, respectively. The adhesive layer <b>41</b> may be interposed between the first and second semiconductor chips <b>21</b> and <b>23</b>. Interlayer contact terminals <b>35</b> may be attached to the other ends of the TSVs <b>33</b>, respectively. Each of the interlayer contact terminals <b>35</b> may be one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof. Although each of the interlayer contact terminals <b>35</b> has been described as being one of a conductive bump, a solder ball, a conductive spacer, and a combination thereof, example embodiments are not limited thereto as this list is merely exemplary.

0050The third semiconductor chip <b>25</b> may also include the plurality of TSVs <b>33</b>. Ends of the TSVs <b>33</b> may be in contact with the interlayer contact terminals <b>35</b>, respectively. The adhesive layer <b>41</b> may be interposed between the second and third semiconductor chips <b>23</b> and <b>25</b>. Interlayer contact terminals <b>35</b> may be attached to the other ends of the TSVs <b>33</b>, respectively.

0051The fourth semiconductor chip <b>27</b> may also include the plurality of TSVs <b>33</b>. Ends of the TSVs <b>33</b> may be in contact with the internal contact terminals <b>35</b>, respectively. The adhesive layer <b>41</b> may be interposed between the third and fourth semiconductor chips <b>25</b> and <b>27</b>. The other ends of the TSVs <b>33</b> may be in contact with external contact terminals <b>49</b>, respectively. Each of the external contact terminals <b>49</b> may be one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, a pin grid array (PGA), a lead grid array (LGA), and a combination thereof. Although each of the external contact terminals <b>49</b> has been described as being one of a conductive bump, a solder ball, a conductive spacer, and a combination thereof, example embodiments are not limited thereto as this list is merely exemplary.

0052The first semiconductor chip <b>21</b> may be attached to a surface of the sub-board <b>11</b> using the adhesive layer <b>41</b>. The encapsulant <b>45</b> may be formed to cover the sub-board <b>11</b> and surround the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. In example embodiments, the external contact terminals <b>49</b> may be exposed through the encapsulant <b>45</b>. The encapsulant <b>45</b> may be formed of an epoxy molding compound (EMC).

0053The main board <b>13</b> facing the sub-board <b>11</b> may be provided. The main board <b>13</b> may include a board pad <b>15</b>. The underfill <b>47</b> may be formed between the main board <b>13</b> and the encapsulant <b>45</b>. The external contact terminals <b>49</b> may be in contact with the board pad <b>15</b> through the encapsulant <b>45</b> and the underfill <b>47</b>.

0054As a result, the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b> may be in electrical contact with the main board <b>13</b> via the internal contact terminals <b>31</b>, the TSVs <b>33</b>, the interlayer contact terminals <b>35</b>, and the external contact terminals <b>49</b>.

0055In example embodiments, the external contact terminals <b>49</b> may be larger than the internal contact terminals <b>31</b> and the interlayer contact terminals <b>35</b>. For example, the external contact terminals <b>49</b> may be twice to 10 times larger than the internal contact terminals <b>31</b> and the interlayer contact terminals <b>35</b>.

0056In example embodiments, the sub-board <b>11</b> may be a dummy substrate. The sub-board <b>11</b> may be formed as a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. In this case, the sub-board <b>11</b> may be insulated from the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. In example embodiments, the main board <b>13</b> may have a first surface adjacent to the external contact terminals <b>49</b> and a second surface facing the first surface. Other external contact terminals may be formed on the second surface, but this will be omitted for simple description. Further, the main board <b>13</b> may correspond to a motherboard of an electronic system.

0057Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a multi-chip package according to example embodiments may include first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, an encapsulant <b>45</b>, a main board <b>13</b>, a board pad <b>15</b>, an underfill <b>47</b>, contact terminals <b>31</b>, <b>35</b> and <b>49</b>, TSVs <b>33</b>, and adhesive layers <b>41</b>. Only a difference from those described with reference to <figref idref="DRAWINGS">FIG. 2</figref> will be briefly described below.

0058The first semiconductor chip <b>21</b> may have a third thickness T<b>3</b>. The third thickness T<b>3</b> may be greater than the second thickness T<b>2</b> and less than the first thickness T<b>1</b>.

0059To be specific, the multi-chip package according to example embodiments described with reference to <figref idref="DRAWINGS">FIG. 1</figref> may be processed, thereby removing the sub-board <b>11</b> and the adhesive layer <b>41</b> between the sub-board <b>11</b> and the first semiconductor chip <b>21</b>. Subsequently, one surface of the first semiconductor chip <b>21</b> may be partially removed, thereby reducing a thickness. In example embodiments, the encapsulant <b>45</b> may also be partially removed. The first semiconductor chip <b>21</b> and the encapsulant <b>45</b> may be exposed on the same plane.

0060Referring to <figref idref="DRAWINGS">FIG. 4</figref>, a multi-chip package according to example embodiments may include first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, an encapsulant <b>45</b>, a sub-board <b>11</b>, a main board <b>13</b>, a board pad <b>15</b>, contact terminals <b>31</b>, <b>35</b> and <b>49</b>, TSVs <b>33</b>, and adhesive layers <b>41</b>. Only a difference from those described with reference to <figref idref="DRAWINGS">FIGS. 2 and 3</figref> will be briefly described below.

0061The encapsulant <b>45</b> may cover the main board <b>13</b>, the sub-board <b>11</b>, and the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. An adhesive layer <b>41</b> may be interposed between the fourth semiconductor chip <b>27</b> and the main board <b>13</b>. That is, the adhesive layer <b>41</b> may be in contact with the main board <b>13</b> and the fourth semiconductor chip <b>27</b>. In example embodiments, external contact terminals <b>49</b> may be in contact with the board pad <b>15</b> through the adhesive layer <b>41</b>.

0062Referring to <figref idref="DRAWINGS">FIG. 5</figref>, a multi-chip package according to example embodiments may include first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, an encapsulant <b>45</b>, a sub-board <b>11</b>, a main board <b>13</b>, a board pad <b>15</b>, contact terminals <b>31</b>, <b>35</b> and <b>49</b>, TSVs <b>33</b>, and adhesive layers <b>41</b>. Only a difference from those described with reference to <figref idref="DRAWINGS">FIGS. 2 through 4</figref> will be briefly described below

0063The encapsulant <b>45</b> may cover the main board <b>13</b>, and the sub-board <b>11</b> and the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. The encapsulant <b>45</b> may be interposed between the fourth semiconductor chip <b>27</b> and the main board <b>13</b>. That is, the encapsulant <b>45</b> may be in contact with the main board <b>13</b> and the fourth semiconductor chip <b>27</b>. In this case, external contact terminals <b>49</b> may be in contact with the board pad <b>15</b> through the encapsulant <b>45</b>.

0064In example embodiments, the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be referred to as thin semiconductor chips. Further, one or more thin semiconductor chips may be stacked on the first semiconductor chip <b>21</b>.

0065According to example embodiments, due to the configuration of the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, the internal contact terminals <b>31</b>, the TSVs <b>33</b>, the interlayer contact terminals <b>35</b>, and the external contact terminals <b>49</b>, a reliability defect caused by the difference of coefficients of thermal expansion (CTE) may be fundamentally improved. Further, due to the configuration of the sub-board <b>11</b>, the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>, the internal contact terminals <b>31</b>, the TSVs <b>33</b>, the internal contact terminals <b>35</b>, the external contact terminals <b>49</b> and the main board <b>13</b>, a reliability defect caused by the difference of CTE and thermal budget may be significantly reduced.

0066<figref idref="DRAWINGS">FIG. 6</figref> is a plan view of a semiconductor module employing a multi-chip package according to example embodiments.

0067Referring to <figref idref="DRAWINGS">FIG. 6</figref>, a semiconductor module employing a multi-chip package according to example embodiments may include a module substrate <b>210</b>, a plurality of multi-chip packages <b>207</b>, and a control chip package <b>203</b>. Input/output terminals <b>205</b> may be formed on the module substrate <b>210</b>. The multi-chip packages <b>207</b> may have similar configurations to those described with reference to <figref idref="DRAWINGS">FIGS. 1 through 5</figref>. For example, the module substrate <b>210</b> may have a similar function to the main board <b>13</b> of <figref idref="DRAWINGS">FIG. 1</figref>.

0068The multi-chip packages <b>207</b> and the control chip package <b>203</b> may be installed on the module substrate <b>210</b>. The multi-chip packages <b>207</b> and the control chip package <b>203</b> may be in electrical contact with the input/output terminals <b>205</b> in series/parallel.

0069The control chip package <b>203</b> may be omitted. The multi-chip packages <b>207</b> may include a volatile memory chip (for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM)), a non-volatile memory chip (for example, a flash memory, a phase change memory, a magnetic random access memory (MRAM) or a resistive random access memory (RRAM)), or a combination thereof.

0070<figref idref="DRAWINGS">FIG. 7</figref> is a diagram of an electronic system employing a multi-chip package according to example embodiments.

0071Referring to <figref idref="DRAWINGS">FIG. 7</figref>, an electronic system <b>1100</b> according to example embodiments may include a controller <b>1110</b>, an input/output device <b>1120</b>, a memory device <b>1130</b>, an interface <b>1140</b>, and a bus structure <b>1150</b>. The memory device <b>1130</b> may include a multi-chip package similar to one described with reference to <figref idref="DRAWINGS">FIGS. 1 through 5</figref>. The bus structure <b>1150</b> may provide a pathway transferring data between the controller <b>1110</b>, the input/output device <b>1120</b>, the memory device <b>1130</b>, and the interface <b>1140</b>.

0072The controller <b>1110</b> may include at least one microprocessor, a digital signal processor, a microcontroller, and at least one of logic devices performing similar functions thereto. The input/output device <b>1120</b> may include at least one selected from a keypad, a keyboard, and a display device. The memory device <b>1130</b> may serve to store data and/or a command executed by the controller <b>1110</b>. Although the controller <b>1110</b> is described as including at least one of a microprocessor, a digital signal processor, a microcontroller, and at least one of logic devices performing similar functions thereto, example embodiments are not limited thereto as this list is merely exemplary rather than exhaustive. Similarly, although the input/output device <b>1120</b> is described as including at least one selected from a keypad, a keyboard, and a display device, example embodiments are not limited thereto as this list is merely exemplary rather than exhaustive.

0073The memory device <b>1130</b> may include a volatile memory chip (for example, a DRAM or a SRAM), a non-volatile memory chip (for example, a flash memory, a phase change memory, an MRAM or an RRAM), or a combination thereof. For example, the electronic system <b>1100</b> may be a solid-state disk (SSD).

0074The interface <b>1140</b> may serve to send data to a communication network or receive data from a communication network. The interface <b>1140</b> may be a wired/wireless type. For example, the interface <b>1140</b> may include an antenna or a wired/wireless transceiver. An application chipset, a camera image processor (CIS), and an input/output device may be further provided to the electronic system <b>1100</b>.

0075The electronic system <b>1100</b> may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be one of a personal digital assistant (PDA), a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music system, and a data transceiver system. When the electronic system <b>1100</b> is a device capable of performing wireless communication, the electronic system <b>1100</b> may be used for a communication system such as code division multiple access (CDMA), global system for mobile communication (GSM), north American digital cellular (NADC), enhanced-time division multiple access (E-TDMA), wideband code division multiple access (WCDAM), or CDMA2000.

0076<figref idref="DRAWINGS">FIGS. 8 through 11</figref> are cross-sectional views illustrating a method of fabricating a multi-chip package according to example embodiments.

0077Referring to <figref idref="DRAWINGS">FIG. 8</figref>, first semiconductor chips <b>21</b> may be attached to a surface of a sub-board <b>11</b> at predetermined intervals using an adhesive layer <b>41</b>. Internal contact terminals <b>31</b> may be formed on surfaces of the first semiconductor chips <b>21</b>. The internal contact terminals <b>31</b> may be formed before or after the first semiconductor chips <b>21</b> are attached to the sub-board <b>11</b>.

0078The sub-board <b>11</b> may be formed as a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The first semiconductor chips <b>21</b> may be formed using a silicon wafer or a silicon on insulator (SOI) wafer. The first semiconductor chips <b>21</b> may include a volatile memory chip (for example, a DRAM or an SRAM), a non-volatile memory chip (for example, a flash memory, a phase change memory, an MRAM or an RRAM, or a combination thereof). In example embodiments, the first semiconductor chips <b>21</b> may include a logic device and/or non-memory devices, for example, a microprocessor.

0079The first semiconductor chip <b>21</b> may include components similar to the redistribution layer <b>133</b> of <figref idref="DRAWINGS">FIG. 2</figref> and the chip pad <b>131</b> of <figref idref="DRAWINGS">FIG. 2</figref>. In this case, the internal contact terminals <b>31</b> may be formed on the redistribution layer similar to the redistribution layer <b>133</b> of <figref idref="DRAWINGS">FIG. 2</figref>. The internal contact terminals <b>31</b> may be formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof. For example, the internal contact terminals <b>41</b> may be formed using a micro bump having a relatively small size. Although the internal contact terminals <b>31</b> are described as being one of a conductive bump, a solder ball, a conductive spacer, and a combination thereof, example embodiments are not limited thereto as this list is merely exemplary rather than exhaustive.

0080In example embodiments, the sub-board <b>11</b> and the adhesive layer <b>41</b> may be omitted.

0081Referring to <figref idref="DRAWINGS">FIG. 9</figref>, second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be attached to surfaces of the first semiconductor chips <b>21</b> using adhesive layers <b>41</b>. In example embodiments, the second to fourth semiconductor chips <b>23</b>, <b>25</b>, and <b>27</b> may be attached to surfaces of the first semiconductor chips <b>21</b> sequentially or simultaneously as a group. The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may include a plurality of TSVs <b>33</b>. The TSVs <b>33</b> may be arranged with the internal contact terminals <b>31</b>, respectively. Interlayer contact terminals <b>35</b> may be formed between the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b>. The interlayer contact terminals <b>35</b> may be in contact with the TSVs <b>33</b>. The interlayer contact terminals <b>35</b> may be formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof. Although the interlayer contact terminals <b>35</b> are described as being formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, and a combination thereof, example embodiments are not limited thereto as this least is merely exemplary rather than exhaustive.

0082The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be the same or different types of chips from each other. Further, the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be the same or different types of chips from the first semiconductor chips <b>21</b>. The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may include a volatile memory chip (for example, a DRAM or an SRAM), a non-volatile memory chip (for example, a flash memory, a phase change memory, an MRAM or an RRAM), or a combination thereof. The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may include a logic device and/or non-memory devices such as a microprocessor.

0083Referring to <figref idref="DRAWINGS">FIG. 10</figref>, an encapsulant <b>45</b> covering the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b> may be formed on the sub-board <b>11</b>. The encapsulant <b>45</b> may be formed of an epoxy molding compound (EMC) containing a resin and a filler. The encapsulant <b>45</b> may cover sidewalls and top surfaces of the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. Openings <b>45</b>H exposing the TSVs <b>33</b> through the encapsulant <b>45</b> may be formed. The openings <b>45</b>H may be formed using a laser drilling technique.

0084Referring to <figref idref="DRAWINGS">FIG. 11</figref>, external contact terminals <b>49</b> may be formed on the TSVs <b>33</b> exposed through the openings <b>45</b>H. Further, the encapsulant <b>45</b> and the sub-boar <b>11</b> may be divided into appropriate sizes using singulation.

0085The external contact terminals <b>49</b> may be formed of one selected from the group consisting of a conductive bump, a solder ball, a conductive spacer, a pin grid array (PGA), a lead grid array (LGA), and a combination thereof. The external contact terminals <b>49</b> may be larger than the internal contact terminals <b>31</b> and the interlayer contact terminals <b>35</b>. For example, the external contact terminals <b>49</b> may be twice to 10 times larger than the internal contact terminals <b>31</b> and the interlayer contact terminals <b>35</b>.

0086In example embodiments, similar to that shown in <figref idref="DRAWINGS">FIG. 3</figref>, a process of removing the sub-board <b>11</b> and the adhesive layer <b>41</b> may be further performed. The process of removing the sub-board <b>11</b> and the adhesive layer <b>41</b> may be performed after the encapsulant <b>45</b> is formed. For example, the process of removing the sub-board <b>11</b> and the adhesive layer <b>41</b> may be performed before the openings <b>45</b>H are formed. Further, the process of removing the sub-board <b>11</b> and the adhesive layer <b>41</b> may be performed before or after the singulation is performed. Subsequently, one surface of the first semiconductor chip <b>21</b> may be partially removed, thereby reducing a thickness. In this case, the encapsulant <b>45</b> may also be partially removed. The first semiconductor chip <b>21</b> and the encapsulant <b>45</b> may be exposed on the same plane. Here, the partial removal of the side of the first semiconductor chip <b>21</b> to reduce the thickness may be performed using chemical-mechanical polishing (CMP) and/or etch-back.

0087In example embodiments, similar to that shown in <figref idref="DRAWINGS">FIG. 1</figref>, the multi-chip package fabricated above may be attached to the main-board <b>13</b>, and applied in various ways as described in example embodiments with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

0088<figref idref="DRAWINGS">FIGS. 12 through 14</figref> are cross-sectional views illustrating a method of fabricating a multi-chip package according to example embodiments.

0089Referring to <figref idref="DRAWINGS">FIG. 12</figref>, first semiconductor chips <b>21</b> may be attached to a surface of a sub-board <b>11</b> at intervals using an adhesive layer <b>41</b>. In example embodiments, the intervals may or may not be predetermined. Internal contact terminals <b>31</b> may be formed on surfaces of the first semiconductor chips <b>21</b>. Second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may be attached to the surfaces of the first semiconductor chips <b>21</b> using adhesive layers <b>41</b>. In example embodiments, the second to fourth semiconductor chips <b>23</b>, <b>25</b>, and <b>27</b> may be attached to the surfaces of the first semiconductor chips sequentially or as a group. The second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b> may include a plurality of TSVs <b>33</b>. The TSVs <b>33</b> may be arranged with the internal contact terminals <b>31</b>, respectively. Interlayer contact terminals <b>35</b> may be formed between the second to fourth semiconductor chips <b>23</b>, <b>25</b> and <b>27</b>.

0090External contact terminals <b>49</b> may be foamed on the fourth semiconductor chips <b>27</b>. The external contact terminals <b>49</b> may be attached to the TSVs <b>33</b>. In addition, the sub-board <b>11</b> may be divided into appropriate sizes using singulation.

0091Referring to <figref idref="DRAWINGS">FIG. 13</figref>, a main board <b>13</b> may be attached to surfaces of the fourth semiconductor chips <b>27</b> using adhesive layers <b>41</b>. The external contact terminals <b>49</b> may be in electrical contact with the main board <b>13</b>. The main board <b>13</b> may be formed as a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The main board <b>13</b> may include board pads (not shown). In this case, the external contact terminals <b>49</b> may be in contact with the board pads (not shown) through the adhesive layers <b>41</b>.

0092An encapsulant <b>45</b> covering the sub-board <b>11</b> and the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b> may be formed on the main board <b>13</b>. The encapsulant <b>45</b> may cover sidewalls and a lower surface of the sub-board <b>11</b> and sidewalls of the first to fourth semiconductor chips <b>21</b>, <b>23</b>, <b>25</b> and <b>27</b>. The encapsulant <b>45</b> and the main board <b>13</b> may be divided into appropriate sizes using singulation.

0093Example embodiments may realize a similar configuration to that shown in <figref idref="DRAWINGS">FIG. 4</figref>.

0094Referring to <figref idref="DRAWINGS">FIG. 14</figref>, according to example embodiments, the encapsulant <b>45</b> may extend between the main board <b>13</b> and the fourth semiconductor chips <b>27</b>. In this case, the external contact terminals <b>49</b> may be in electrical contact with the main board <b>13</b> through the encapsulant <b>45</b>. Example embodiments may realize a similar configuration to that shown in <figref idref="DRAWINGS">FIG. 5</figref>.

0095According to example embodiments, a semiconductor device including one or more thin semiconductor chips stacked on a semiconductor chip is provided. The thin semiconductor chips include a plurality of TSVs. A plurality of external contact terminals are formed on a surface of one of the thin semiconductor chips. A plurality of internal contact terminals formed on a surface of the semiconductor chip are provided. The TSVs are arranged with the internal contact terminals, respectively. Accordingly, a reliability defect caused by the difference of CTE and thermal budget can be significantly reduced.

0096The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of example embodiments and is not to be construed as limited to the example embodiments disclosed, and that modifications to example embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.