Manufacturing method of package carrier

CROSS-REFERENCE TO RELATED APPLICATION

p-0002This application claims the priority benefit of Taiwan application serial no. 98145638, filed on Dec. 29, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

p-00031. Field of the Invention

p-0004The present invention relates to a method of manufacturing a semiconductor structure, and more particularly to a method of manufacturing a package carrier.

p-00052. Description of Related Art

p-0006In the fabrication of semiconductors, chip package carrier is one of the most common used package components. The chip package carrier, for example, is a multi-layered circuit board, in which a plurality of circuit layers and a plurality of dielectric layers are alternately stacked. Each of the dielectric layers is disposed between two adjacent circuit layers, and the circuit layers are electrically connected through the plating through hole (PTH) or via. Since a chip package carrier has the advantages of dense wiring, compact assembly and good electrical performance, it is most widely used in the chip package structure.

p-0007Typically, the structure of the multi-layered circuit board commonly formed by the build-up method or the laminating method so that it has the features of high wiring density and small pitch. Since the rigidity of the ultra-thin substrate is poor, it is necessary to provide a metal (such as aluminum substrate or copper substrate) as a supporting carrier. Then, mass of gel are coated on the metal, and then the plurality of circuit layers and the plurality of dielectric layer are alternatively arranged on the two opposite surfaces of the metal. Finally, the gel is removed so that the circuit layers and the dielectric layers are separated from the metal to form two multi-layered circuit boards separated from each other. Moreover, as for forming the plating through hole or via in the multi-layered circuit board, after a dielectric layer is formed, a blind via is formed to expose the circuit layer underneath the dielectric layer. Then, by using copper plating method, a copper layer is plated in the blind via and on the dielectric layer to form connecting layers and the plating through hole or via.

p-0008Since, conventionally, the metal is provided to be the supporting carrier of the copper foil and the cost of the metal is relatively high, the cost for manufacturing the multi-layered circuit board is high. Also, the mass of gel is used to fix the copper foil on the metal so that it is difficult to remove the gel and the manufacturing yield is hardly improved. Moreover, as for the circuit layer formed by the copper plating method, the thickness uniformity of the copper layer is poor so that when the required thickness of the circuit layer is small, it is necessary to perform the thinning process (such as etching process) to decrease the thickness of the circuit layer. Thus, the number of the process steps for manufacturing the multi-layered circuit board is increased and the manufacturing yield of the multi-layered circuit board is decreased.

SUMMARY OF THE INVENTION

p-0009The present invention provides a method for forming a package carrier capable of simplifying the manufacturing steps, decreasing the manufacturing cost, increasing the manufacturing yield and further increasing the product reliability.

p-0010The present invention provides a method for forming a thin copper laminate without carrier and be handled on process. A first copper foil layer, a second copper foil layer on the first copper foil layer, a third copper foil layer and a fourth copper foil layer on the third copper foil layer are provided. The second foil layer is partially glued to the fourth copper foil layer by an adhesive gel or is partially attached to the fourth copper foil layer by welding copper foil. A plurality of first through holes extending from the first copper foil layer to the third copper foil layer are formed. A first dielectric layer and a first conductive layer disposed thereon are compressed on the first copper foil layer, and a second dielectric layer and a second conductive layer disposed thereon are compressed on the third copper foil layer. The first dielectric layer and the second dielectric layer face to the first copper foil layer and the third copper foil layer respectively, and portions of the first dielectric layer and the second dielectric layer fill in the first through holes. The first conductive layer and the second conductive layer are patterned to form a first circuit layer and a second circuit layer. Then, a third dielectric layer and a fifth copper foil layer disposed thereon are compressed on the first circuit layer and the adhesive gel is removed to from a first carrier unit. A plurality of first conductive blind via structures connecting the fifth copper foil layer and the first circuit layer are formed, and a plurality of second conductive blind via structures connecting the first copper foil layer and the first circuit layer are formed. Thin coppers laminate without carrier and can be handled on process.

p-0011In one embodiment of the present invention, the thickness of the second copper foil layer is substantially larger than the thickness of the first copper foil layer. Thickness of the first copper foil layer is substantially equal to the thickness of the third copper foil layer. The thickness of the second copper foil layer is substantially equal to the thickness of the fourth copper foil layer.

p-0012In one embodiment of the present invention, the adhesive gel includes cyanoacrylate (usually referred as an instant glue) or polypropylene resin (i.e. PP gel).

p-0013In one embodiment of the present invention, a method of forming the through holes includes mechanical drilling.

p-0014In one embodiment of the present invention, a sum of the thickness of the first dielectric layer and the thickness of the first conductive layer is substantially larger than a sum of the thickness of the first copper foil layer and the thickness of the second foil layer. A sum of the thickness of the second dielectric layer and the thickness of the second conductive layer is substantially larger than a sum of the thickness of the third copper foil layer and the thickness of the fourth copper foil layer.

p-0015In one embodiment of the present invention, before the step of patterning the first conductive layer and the second conductive layer, the method of forming the package carrier further comprises forming a plurality of second through holes extending from the first conductive layer to the second conductive layer.

p-0016In one embodiment of the present invention, the third dielectric layer and the fifth copper foil layer disposed on the third dielectric layer are compressed on the first circuit layer after the adhesive gel is removed.

p-0017In one embodiment of the present invention, the third dielectric layer and the fifth copper foil layer disposed on the third dielectric layer are compressed on the first circuit layer before the adhesive gel is removed.

p-0018In one embodiment of the present invention, the step of compressing the third dielectric layer and the fifth copper foil layer disposed on the third dielectric layer on the first circuit layer further comprises compressing a fourth dielectric layer and a sixth copper foil layer disposed thereon on the second circuit layer.

p-0019In one embodiment of the present invention, a method of removing the adhesive gel includes a mechanical drilling or a milling machine process.

p-0020In one embodiment of the present invention, after the step of removing the adhesive gel, the method for forming the package carrier further comprises removing the second copper foil layer.

p-0021In an embodiment of the present invention, a method of removing the second copper foil layer includes a lift-off method.

p-0022In one embodiment of the present invention, the first carrier unit comprises the fifth copper foil layer, the third dielectric layer, the first circuit layer, the first dielectric layer and the first copper foil layer, and the method for forming the first conductive blind via structures and the second conductive blind via structures is described as follows. A mechanical drilling is performed on the fifth copper foil layer and the first copper foil layer so as to form a plurality of first blind via extending from the fifth copper foil layer to the first circuit layer and a plurality of second blind vias extending from the first copper foil layer to the first circuit layer. The first blind vias and the second blind vias expose a portion of the first circuit layer. A chemical copper layer is formed in the first blind vias and the second blind vias, wherein the chemical copper layer connects the fifth copper foil layer and the first circuit layer and connects the first copper foil layer and the first circuit layer. A first patterned dry film photoresist layer is formed on the fifth copper foil layer and a second patterned dry film photoresist layer is formed on the first copper foil layer. The first patterned dry film photoresist layer at least exposes the first blind vias and the second patterned dry film photoresist layer at least exposes the second blind vias. An copper plating copper layer is formed at least in the first blind vias and the second blind vias, wherein the copper plating copper layer fills up the first blind vias and the second blind vias and covers a portion of the chemical copper layer. The first patterned dry film photoresist layer and a portion of the fifth copper foil layer under the first patterned dry film photoresist layer, and the second patterned dry film photoresist layer and a portion of the first copper foil layer under the second patterned dry film photoresist layer are removed to expose a portion of the third dielectric layer and a portion of the first dielectric layer so as to form the first conductive blind via structures in the first blind vias and the second conductive blind via structures in the second blind vias.

p-0023In one embodiment of the present invention, the mechanical drilling includes a laser drilling.

p-0024In one embodiment of the present invention, the method for forming the chemical copper layer includes an electroless plating process.

p-0025In one embodiment of the present invention, the method for removing the first patterned dry film photoresist layer and a portion of the fifth copper foil layer under the first patterned dry film photoresist layer, and the second patterned dry film photoresist layer and a portion of the first copper foil layer under the second patterned dry film photoresist layer includes an etching process.

p-0026In one embodiment of the present invention, after the first patterned dry film photoresist layer and a portion of the fifth copper foil layer under the first patterned dry film photoresist layer, and the second patterned dry film photoresist layer and a portion of the first copper foil layer under the second patterned dry film photoresist layer are removed, the method for forming the package carrier further comprises the steps described as follows. A first protecting layer is formed on the third dielectric layer and a second protecting layer is formed on the first dielectric layer. The first protecting layer covers the third dielectric layer and the first conductive blind via structures exposed by the third dielectric layer, and the second protecting layer covers the first dielectric layer and the second conductive blind via structures exposed by the first dielectric layer.

p-0027In one embodiment of the present invention, the method of forming the first protecting layer and the second protecting layer includes a screen printing.

p-0028In one embodiment of the present invention, after the step of forming the first protecting layer and the second protecting layer, the method of forming the package carrier further comprises performing a polishing process to remove a portion of the first protecting layer until the first conductive blind via structures are exposed and to remove a portion of the second protecting layer until the second conductive blind via structures are exposed. The rest portion of the first protecting layer and the rest portion of the second protecting layer are removed.

p-0029In one embodiment of the present invention, after the step of forming the first conductive blind via structures and the second conductive blind via structures, the method for forming the package carrier further comprises forming a first solder mask layer on the third dielectric layer, wherein the first solder mask layer has a plurality of first openings exposing the first conductive blind via structures. A second solder mask layer is formed on the first dielectric layer, wherein the second solder mask layer has a plurality of second openings exposing the second conductive blind via structures.

p-0030Accordingly, in the present invention, the second copper foil layer is partially bonded the fourth copper foil layer, so that the first copper foil layer, the second copper foil layer, the third copper foil layer and the fourth copper foil layer are bonded to each other. Comparing with the conventional technique, in the package carrier formation method of the present invention, it is not necessary to adopt the metal as the supporting carrier so that the cost for manufacturing the package carrier is decreased. Moreover, the first conductive layer and the second conductive layer are laminated by the compressing process, and then the first circuit layer and the second circuit layer are formed by the patterning method. Therefore, by comparing with the conventional technique that the circuit layers are formed by the copper plating method, the first circuit layer and the second circuit layer have relatively better copper thickness uniformities.

p-0031In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

p-0032The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

p-0033<figref idrefs="DRAWINGS">FIGS. 1A through 1P</figref> are schematic cross-sectional views illustrating a manufacturing method of a package carrier according to one embodiment of the present invention.

p-0034<figref idrefs="DRAWINGS">FIGS. 2A through 2B</figref> are schematic cross-sectional views illustrating the steps of compressing the third dielectric layer and the fifth copper foil layer and removing the adhesive gel according to another embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

p-0035<figref idrefs="DRAWINGS">FIGS. 1A through 1P</figref> are schematic cross-sectional views illustrating a manufacturing method of a package carrier according to one embodiment of the present invention. As shown in <figref idrefs="DRAWINGS">FIG. 1A</figref>, a first copper foil layer <b>110</b><i>a</i>, a second copper foil layer <b>110</b><i>b </i>on the first copper foil layer <b>110</b><i>a</i>, a third copper foil layer <b>110</b><i>c </i>and a fourth copper foil layer <b>110</b><i>d </i>on the third copper foil layer <b>110</b><i>c </i>are provided. The second foil layer <b>110</b><i>b </i>is partially bonded the fourth copper foil layer <b>100</b><i>d </i>by an adhesive gel <b>120</b>. That is, the adhesive gel <b>120</b> is disposed between the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d</i>, and the second copper foil layer <b>110</b><i>b </i>is partially glued to the fourth copper foil layer <b>110</b><i>d</i>. Moreover, the first copper foil layer <b>110</b><i>a </i>and the second copper foil layer <b>110</b><i>b </i>on the first copper foil layer <b>110</b><i>a </i>can be regarded as a coreless structure layer. Similarly, the third copper foil layer <b>110</b><i>c </i>and the fourth copper foil layer <b>110</b><i>d </i>on the third copper foil layer <b>110</b><i>c </i>can be regarded as a coreless structure layer.

p-0036In the present embodiment, the thickness of the second copper foil layer <b>110</b><i>b </i>is substantially larger than the thickness of the first copper foil layer <b>110</b><i>a</i>, and the thickness of the first copper foil layer <b>110</b><i>a </i>can be, for example, 3 micrometers, and the thickness of the second copper foil layer <b>110</b><i>b </i>can be, for example, 12 micrometers. The thickness of the first copper foil layer <b>110</b><i>a </i>is substantially equal to the thickness of the third copper foil layer <b>110</b><i>c</i>. In other words, the thickness of the third copper foil layer <b>110</b><i>c </i>can also be, for example, 3 micrometers. The thickness of the second copper foil layer <b>110</b><i>b </i>is substantially equal to the thickness of the fourth copper foil layer <b>110</b><i>d</i>. In other words, the thickness of the fourth copper foil layer <b>110</b><i>d </i>can also be, for example, 12 micrometers. Moreover, the second copper foil layer <b>110</b><i>b </i>of the present embodiment can be used to support the first copper foil layer <b>110</b><i>a</i>. Similarly, the fourth copper foil layer <b>110</b><i>d </i>can also be used to support the third copper foil layer <b>110</b><i>c</i>. Therefore, in the present embodiment, it is not necessary to use the conventional metal as the supporting carrier and the manufacturing cost can be decreased. In addition, in the present embodiment, the adhesive gel <b>120</b> includes, for example, cyanoacrylate (usually referred as an instant glue) or polypropylene resin (i.e. PP gel). It should be noticed that, although the second copper foil layer <b>110</b><i>b </i>is bonded the fourth copper foil layer <b>110</b><i>d </i>through the adhesive gel <b>120</b> in the present embodiment, the second copper foil layer <b>110</b><i>b </i>can be also bonded the fourth copper foil layer <b>110</b><i>d </i>through the welding copper foil method in other embodiments not shown in the drawings. That is, in the other embodiments, the adhesive gel <b>120</b> is the welded copper foil. Thus, the aforementioned welding copper foil method for bonding the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d </i>still within the scope of the present invention.

p-0037Thereafter, as shown in <figref idrefs="DRAWINGS">FIG. 1B</figref>, a plurality of first through holes <b>132</b> extending from the first copper foil layer <b>110</b><i>a </i>to the third copper foil layer <b>110</b><i>c </i>are formed. That is, the first through holes <b>132</b> at least penetrate through the first copper foil layer <b>110</b><i>a</i>, the second copper foil layer <b>110</b><i>b</i>, the fourth copper foil layer <b>110</b><i>d </i>and the third copper foil layer <b>110</b><i>c</i>. In the present embodiment, the method of forming the first through holes <b>132</b> includes mechanical drilling.

p-0038As shown in <figref idrefs="DRAWINGS">FIG. 1C</figref>, a first dielectric layer <b>150</b><i>a </i>and a first conductive layer <b>142</b> disposed on the first dielectric layer <b>150</b><i>a </i>are compressed on the first copper foil layer <b>110</b><i>a</i>, and, meanwhile, a second dielectric layer <b>150</b><i>b </i>and a second conductive layer <b>144</b> disposed on the second dielectric layer <b>150</b><i>b </i>are compressed on the third copper foil layer <b>110</b><i>c</i>. In the present embodiment, the first dielectric layer <b>150</b><i>a </i>and the second dielectric layer <b>150</b><i>b </i>face to the first copper foil layer <b>110</b><i>a </i>and the third copper foil layer <b>110</b><i>c </i>respectively, and portions of the first dielectric layer <b>150</b><i>a </i>and the second dielectric layer <b>150</b><i>b </i>fill in the first through holes <b>132</b>. In addition, the material of the first conductive layer <b>142</b> and the second conductive layer <b>144</b> can be, for example, copper.

p-0039Particularly, in the present embodiment, a sum of the thickness of the first dielectric layer <b>150</b><i>a </i>and the thickness of the first conductive layer <b>142</b> is substantially larger than a sum of the thickness of the first copper foil layer <b>110</b><i>a </i>and the thickness of the second foil layer <b>110</b><i>b</i>. Further, the thickness of the first dielectric layer <b>150</b><i>a </i>can be, for example, 40 micrometers, and the thickness of the first conductive layer <b>142</b> can be, for example, 18 micrometers. Similarly, a sum of the thickness of the second dielectric layer <b>150</b><i>b </i>and the thickness of the second conductive layer <b>144</b> is substantially larger than a sum of the thickness of the third copper foil layer <b>110</b><i>c </i>and the thickness of the fourth copper foil layer <b>110</b><i>d</i>. Further, the thickness of the second dielectric layer <b>150</b><i>b </i>is substantially equal to the thickness of the first dielectric layer <b>150</b><i>a </i>so that the thickness of the second dielectric layer <b>150</b><i>b </i>can be, for example, 40 micrometers. Also, the thickness of the second conductive layer <b>144</b> is substantially equal to the thickness of the first conductive layer <b>142</b> so that the thickness of the second conductive layer <b>144</b> can be, for example, 18 micrometers.

p-0040Furthermore, as shown in <figref idrefs="DRAWINGS">FIG. 1D</figref>, a plurality of second through holes <b>134</b> extending from the first conductive layer <b>142</b> to the second conductive layer <b>144</b> are formed. The second through holes <b>134</b> at least penetrate through the first conductive layer <b>142</b>, the first dielectric layer <b>150</b><i>a</i>, the first copper foil layer <b>110</b><i>a</i>, the second copper foil layer <b>110</b><i>b</i>, the fourth copper foil layer <b>110</b><i>c</i>, the third copper foil layer <b>110</b><i>c</i>, the second dielectric layer <b>150</b><i>b </i>and the second conductive layer <b>144</b>. Moreover, the second through holes <b>134</b> can be used to assist the removal of the adhesive gel <b>120</b> in later process step (i.e. the removal of the bonding region of the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d</i>). Usually, the first conductive layer <b>142</b> and the second conductive layer <b>144</b> have several metal patterns (not shown) thereon, and the metal patterns are used as the positioning and aligning standard points in the manufacturing process. That is, the metal patterns on the first conductive layer <b>142</b> and the second conductive layer <b>144</b> can be used as the positioning and aligning standards of the first copper foil layer <b>110</b><i>a </i>and the third copper foil layer <b>110</b><i>c</i>. Further, the metal patterns on the first conductive layer <b>142</b> and the second conductive layer <b>144</b> can also used as the positioning and aligning standards of the later formed fifth copper foil layer <b>110</b><i>e </i>(as shown in <figref idrefs="DRAWINGS">FIG. 1G</figref>).

p-0041Next, as shown in <figref idrefs="DRAWINGS">FIG. 1E</figref>, the first conductive layer <b>142</b> and the second conductive layer <b>144</b> are respectively patterned, so as to form a first circuit layer <b>142</b><i>a </i>and a second circuit layer <b>144</b><i>a</i>. The method for patterning the first conductive layer <b>142</b> and the second conductive layer <b>144</b> includes a photolithography and etching process. Particularly, the first conductive layer <b>142</b> and the second conductive layer <b>144</b> of the present embodiment are compressed on the first dielectric layer <b>150</b><i>a </i>and the second dielectric layer <b>150</b><i>b </i>respectively by the compressing process and are transformed in the first circuit layer <b>142</b><i>a </i>and the second circuit layer <b>144</b><i>a </i>respectively by the patterning process. Therefore, by comparing with the conventional technique that the circuit layers are formed by the copper plating method, the first circuit layer <b>142</b><i>a </i>and the second circuit layer <b>144</b><i>a </i>of the present embodiment have relatively better copper thickness uniformities.

p-0042Then, as shown in <figref idrefs="DRAWINGS">FIG. 1F</figref>, the adhesive gel <b>120</b> is removed to form a first circuit structure <b>160</b><i>a </i>and a second circuit structure <b>160</b><i>b </i>which are separated from each other. In the present embodiment, the second through holes <b>134</b> can be used to assist the removal of the adhesive gel <b>120</b>. That is, because of the formation of the second through holes <b>134</b>, the adhesion of the adhesive gel <b>120</b> between the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d </i>is damaged. Thus, it is easy to remove the adhesive gel <b>120</b>. Moreover, a method for removing the adhesive gel can be, for example, a mechanical drilling or a milling machine process. It should be noticed that, in the present embodiment, since the adhesive gel <b>120</b> only partially located between the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d</i>, the step of the present embodiment for removing the adhesive gel <b>120</b> is more simple and easy by comparing with the conventional technique for removing the mass of the gel between the circuit layer and the metal. Thus, the manufacturing yield can be increased.

p-0043In the present embodiment, the first circuit structure <b>160</b><i>a </i>and the second circuit structure <b>160</b><i>b </i>formed after the adhesive gel <b>120</b> is removed are the symmetrical structures. Further, the first circuit structure <b>160</b><i>a </i>comprises the first circuit layer <b>142</b><i>a</i>, the first dielectric layer <b>150</b><i>a</i>, the first copper foil layer <b>110</b><i>a </i>and the second copper foil layer <b>110</b><i>b </i>which are stacked sequentially. The second circuit structure <b>160</b><i>b </i>comprises the second circuit layer <b>144</b><i>a</i>, the second dielectric layer <b>150</b><i>b</i>, the third copper foil layer <b>110</b><i>c </i>and the fourth copper foil layer <b>110</b><i>d </i>which are stacked sequentially. To simplify the explanation, the first circuit structure <b>160</b><i>a </i>is used as an example in the following description of the formation of the package carrier.

p-0044As shown in <figref idrefs="DRAWINGS">FIG. 1G</figref>, the second copper foil layer <b>110</b><i>b </i>is removed, and a third dielectric layer <b>150</b><i>c </i>and a fifth copper foil layer <b>110</b><i>e </i>on the third dielectric layer <b>150</b><i>c </i>are compressed on the first circuit layer <b>142</b><i>a</i>. In the present embodiment, the method for removing the second copper foil layer <b>110</b><i>b </i>can be, for example, a lift-off process. That is, by using the lift-off process, the second copper foil layer <b>110</b><i>b </i>is lifted off the first copper foil layer <b>110</b><i>a</i>. Moreover, since the third dielectric layer <b>150</b><i>c </i>and the fifth copper foil layer <b>110</b><i>e </i>are compressed on the first circuit layer <b>142</b><i>a</i>, the first circuit layer <b>142</b><i>a </i>becomes an inner circuit layer. In other words, the first circuit layer <b>142</b><i>a </i>is a circuit layer buried between the third dielectric layer <b>150</b><i>c </i>and the first dielectric layer <b>150</b><i>a</i>. Moreover, the metal patterns (not shown) on the first circuit layer <b>142</b><i>a </i>(which is formed by patterning the first conductive layer <b>142</b>) are used as the standards in the step for compressing the fifth copper foil layer <b>110</b><i>e </i>on the first circuit layer <b>142</b><i>a </i>so that the alignment precision between the first copper foil layer <b>110</b><i>a</i>, the first circuit layer <b>142</b><i>a </i>and the fifth copper foil layer <b>110</b><i>e </i>can be ensured.

p-0045Usually, the thickness of the fifth copper foil layer <b>110</b><i>e </i>is relatively small and can be, for example, 3 micrometers. Hence, when the compressing process is applied on the fifth copper foil layer <b>110</b><i>e</i>, a thick copper foil layer (not shown) with a thickness about 12 micrometers is usually disposed on the fifth copper foil layer <b>110</b><i>e</i>. Thus, the fifth copper foil layer <b>110</b><i>e </i>can be prevented from being bent after the compressing process. Therefore, the surface flatness of the fifth copper foil layer <b>110</b><i>e </i>after the compressing process can be well maintained. Thereafter, after the compressing process, the thick copper foil layer is lifted off to leave the thin fifth copper foil layer <b>110</b><i>e </i>for the later performed processes.

p-0046In other words, in the present embodiment, the third dielectric layer <b>150</b><i>c </i>and the fifth copper foil layer <b>110</b><i>e </i>disposed on the third dielectric layer <b>150</b><i>c </i>are compressed on the first circuit layer <b>142</b><i>a </i>after the adhesive gel <b>120</b> is removed. However, the present invention is not limited to the step order that the third rein layer <b>150</b><i>c </i>and the fifth copper foil layer <b>110</b><i>e </i>are compressed on the first circuit layer <b>142</b><i>a </i>after the adhesive gel <b>120</b> is removed. In other embodiments, the third dielectric layer <b>150</b><i>c </i>and the fifth copper foil layer <b>110</b><i>e </i>disposed on the third dielectric layer <b>150</b><i>c </i>can be compressed on the first circuit layer <b>142</b><i>a </i>before the adhesive gel <b>120</b> is removed.

p-0047More specifically, as shown in <figref idrefs="DRAWINGS">FIG. 2A</figref>, the third dielectric layer <b>150</b><i>c </i>and the fifth copper foil layer <b>110</b><i>e </i>on the third dielectric layer <b>150</b><i>c </i>are compressed on the first circuit layer <b>142</b><i>a</i>, and, meanwhile, a fourth dielectric layer <b>150</b><i>d </i>and a sixth copper foil layer <b>110</b><i>f </i>on the fourth dielectric layer <b>150</b><i>d </i>are compressed on the second circuit layer <b>144</b><i>a</i>. Then, as shown in <figref idrefs="DRAWINGS">FIG. 2B</figref>, the adhesive gel <b>120</b>, the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d </i>are removed to form a third carrier unit <b>200</b><i>c </i>and a fourth carrier unit <b>200</b><i>d </i>which are separated from each other. Moreover, the third carrier unit <b>200</b><i>c </i>and the fourth carrier unit <b>200</b><i>d </i>formed by removing the adhesive gel <b>120</b>, the second copper foil layer <b>110</b><i>b </i>and the fourth copper foil layer <b>110</b><i>d </i>are the symmetrical structures. The third carrier unit <b>200</b><i>c </i>comprises the fifth copper foil layer <b>110</b><i>e</i>, the third dielectric layer <b>150</b><i>c</i>, the first circuit layer <b>142</b><i>a</i>, the first dielectric layer <b>150</b><i>a </i>and the first copper foil layer <b>110</b><i>a </i>which are stacked sequentially. Similarly, the fourth carrier unit <b>200</b><i>d </i>comprises the sixth copper foil layer <b>110</b><i>f</i>, the fourth dielectric layer <b>150</b><i>d</i>, the second circuit layer <b>144</b><i>a</i>, the second dielectric layer <b>150</b><i>b </i>and the third copper foil layer <b>110</b><i>c </i>which are stacked sequentially. In other words, the order of the steps for compressing the dielectric layer and the copper foil layer on the dielectric layer on the circuit layer and removing the adhesive gel <b>120</b> can be selectively adjusted according to the process requirement. Hence, the embodiment shown in <figref idrefs="DRAWINGS">FIGS. 1F through 1G</figref> is only an exemplary of the present invention and the present invention is not limited to this embodiment.

p-0048Thus, the manufacture of the first carrier unit <b>200</b><i>a </i>is completed. The first carrier unit <b>200</b><i>a </i>comprises the fifth copper foil layer <b>110</b><i>e</i>, the third dielectric layer <b>150</b><i>c</i>, the first circuit layer <b>142</b><i>a</i>, the first dielectric layer <b>150</b><i>a </i>and the first copper foil layer <b>110</b><i>a </i>which are stacked sequentially.

p-0049Further, as shown in <figref idrefs="DRAWINGS">FIG. 1H</figref>, a mechanical drilling is performed on the fifth copper foil layer <b>110</b><i>e </i>and the first copper foil layer <b>110</b><i>a </i>so as to form a plurality of first blind via <b>212</b> extending from the fifth copper foil layer <b>110</b><i>e </i>to the first circuit layer <b>142</b><i>a </i>and a plurality of second blind vias <b>214</b> extending from the first copper foil layer <b>110</b><i>a </i>to the first circuit layer <b>142</b><i>a</i>. The first blind vias <b>212</b> and the second blind vias <b>214</b> expose a portion of the first circuit layer <b>142</b><i>a</i>. In the present embodiment, the mechanical drilling can be, for example, a laser drilling. That is, the first blind vias <b>212</b> and the second blind vias <b>214</b> are formed by using the laser drilling.

p-0050As shown in <figref idrefs="DRAWINGS">FIG. 1I</figref>, a chemical copper layer <b>220</b> is formed in the first blind vias <b>212</b> and the second blind vias <b>214</b>, wherein the chemical copper layer <b>220</b> connects the fifth copper foil layer <b>110</b><i>e </i>and the first circuit layer <b>142</b><i>a </i>and connects the first copper foil layer <b>110</b><i>a </i>and the first circuit layer <b>142</b><i>a</i>. Specifically, in the present embodiment, the chemical copper layer <b>220</b> covers the fifth copper foil layer <b>110</b><i>e</i>, the first blind vias <b>212</b>, the first copper foil layer <b>110</b><i>a </i>and the second blind vias <b>214</b>. Further, the fifth copper foil layer <b>110</b><i>e </i>is electrically connected to the first circuit layer <b>142</b><i>a </i>through the chemical copper layer <b>220</b>, and the first copper foil layer <b>110</b><i>a </i>is electrically connected to the first circuit layer <b>142</b><i>a </i>through the chemical copper layer <b>220</b>. Moreover, the method for forming the chemical copper layer <b>220</b> can be, for example, an electroless plating process.

p-0051As shown in <figref idrefs="DRAWINGS">FIG. 1J</figref>, a first patterned dry film photoresist layer <b>232</b> is formed on the fifth copper foil layer <b>110</b><i>e</i>, and a second patterned dry film photoresist layer <b>234</b> is formed on the first copper foil layer <b>110</b><i>a</i>. The first pattern dry film photoresist layer <b>232</b> at least exposes the first blind vias <b>212</b> and the second patterned dry film photoresist layer <b>234</b> at least exposes the second blind vias <b>214</b>. Specifically, in the present embodiment, the first patterned dry film photoresist layer <b>232</b> exposes the chemical copper layer <b>220</b> in the first blind vias <b>212</b> and exposes a portion of the chemical copper layer <b>220</b> over the fifth copper foil layer <b>110</b><i>e</i>. The second patterned dry film photoresist layer <b>234</b> exposes the chemical copper layer <b>220</b> in the second blind vias <b>214</b> and exposes a portion of the chemical copper layer <b>220</b> over the first copper foil layer <b>110</b><i>a. </i>

p-0052As shown in <figref idrefs="DRAWINGS">FIG. 1K</figref>, an copper plating copper layer <b>240</b> is formed at least in the first blind vias <b>212</b> and the second blind vias <b>214</b>, wherein the copper plating copper layer <b>240</b> fills up the first blind vias <b>212</b> and the second blind vias <b>214</b> and covers a portion of the chemical copper layer <b>220</b>. In the present embodiment, the copper plating copper layer <b>240</b> is formed within the first blind vias <b>212</b>, the second blind vias <b>214</b> and on a portion of the chemical copper layer <b>220</b> exposed by the first patterned dry film photoresist layer <b>232</b> and the second patterned dry film photoresist layer <b>234</b> by using a via filling plating process with the first patterned dry film photoresist layer <b>232</b> and the second patterned dry film photoresist layer <b>234</b> as the masks.

p-0053As shown in <figref idrefs="DRAWINGS">FIG. 1L</figref>, the first patterned dry film photoresist layer <b>232</b>, and a portion of the chemical copper layer <b>220</b> and the fifth copper foil layer <b>110</b><i>e </i>under the first patterned dry film photoresist layer <b>232</b> are removed. Also, the second patterned dry film photoresist layer <b>234</b>, and a portion of the chemical copper layer <b>220</b> and the first copper foil layer <b>110</b><i>a </i>under the second patterned dry film photoresist layer <b>234</b> are removed. Therefore, the third dielectric layer <b>150</b><i>c </i>and a portion of the first dielectric layer <b>150</b><i>a </i>are exposed, and a first conductive blind via structure <b>212</b><i>a </i>is formed in each of the first bind holes <b>212</b> and a second conductive blind via structure <b>214</b><i>a </i>is formed in each of the second bind holes <b>214</b>. In the present embodiment, the method for removing the first patterned dry film photoresist layer <b>232</b>, and a portion of the chemical copper layer <b>220</b> and the fifth copper foil layer <b>110</b><i>e </i>under the first patterned dry film photoresist layer <b>232</b>, and the second patterned dry film photoresist layer <b>234</b>, and a portion of the chemical copper layer <b>220</b> and the first copper foil layer <b>110</b><i>a </i>under the second patterned dry film photoresist layer <b>234</b> can be, for example, an etching process. Thus, the first conductive blind via structures <b>212</b><i>a </i>and the second conductive blind via structures <b>214</b><i>a</i>, both of which are electrically connected to the first circuit layer <b>142</b><i>a</i>, are formed.

p-0054As shown in <figref idrefs="DRAWINGS">FIG. 1M</figref>, a first protecting layer <b>252</b> is formed on the third dielectric layer <b>150</b><i>c </i>and a second protecting layer <b>254</b> is formed on the first dielectric layer <b>150</b><i>a</i>. In the present embodiment, the first protecting layer <b>252</b> covers the third dielectric layer <b>150</b><i>c </i>and the first conductive blind via structures <b>212</b><i>a </i>exposed by the third dielectric layer <b>150</b><i>c </i>so that the integrity of the pattern of the first conductive blind via structures <b>212</b><i>a </i>can be well protected. Similarly, the second protecting layer <b>254</b> covers the first dielectric layer <b>150</b><i>a </i>and the second conductive blind via structures <b>214</b><i>a </i>exposed by the first dielectric layer <b>150</b><i>a </i>so that the integrity of the pattern of the second conductive blind via structures <b>214</b><i>a </i>can be well protected. Moreover, the method for forming the first protecting layer <b>252</b> and the second protecting layer <b>254</b> can be, for example, a screen printing. The material of the first protecting layer <b>252</b> and the second protecting layer <b>254</b> can be, for example, ink.

p-0055As shown in <figref idrefs="DRAWINGS">FIG. 1N</figref>, a polishing process is performed to remove a portion of the first protecting layer <b>252</b> until the surface of the first conductive blind via structures <b>212</b><i>a </i>are exposed and to remove a portion of the second protecting layer <b>254</b> until the surface of the second conductive blind via structures <b>214</b><i>a </i>are exposed. Meanwhile, the surface of the first protecting layer <b>252</b> is substantially aligned with the surfaces of the first conductive blind via structures <b>212</b><i>a</i>, and the surface of the second protecting layer <b>254</b> is aligned with the surfaces of the second conductive blind via structures <b>214</b><i>a. </i>

p-0056Furthermore, as shown in <figref idrefs="DRAWINGS">FIG. 1O</figref>, the rest portion of the first protecting layer <b>252</b> and the rest portion of the second protecting layer <b>254</b> are removed to expose a portion of the third dielectric layer <b>150</b><i>c</i>, the first conductive blind vias <b>212</b><i>a </i>exposed by the third dielectric layer <b>150</b><i>c</i>, a portion of the first dielectric layer <b>150</b><i>a </i>and the second conductive blind vias <b>214</b><i>a </i>exposed by the first dielectric layer <b>150</b><i>a</i>. In the present embodiment, the purpose of the process comprises, in sequence, forming the first protecting layer <b>252</b> and the second protecting layer <b>254</b>, performing the polishing process and removing the first protecting layer <b>252</b> and the second protecting layer <b>254</b> is to improve the surface flatness of the surfaces of the first conductive blind via structures <b>212</b><i>a </i>and the second conductive blind via structures <b>214</b><i>a. </i>

p-0057As shown in <figref idrefs="DRAWINGS">FIG. 1P</figref>, a first solder mask layer <b>262</b> is formed on the third dielectric layer <b>150</b><i>c </i>and a second solder mask layer <b>264</b> is formed on the first dielectric layer <b>150</b><i>a</i>. In the present embodiment, the first solder mask layer <b>262</b> has a plurality of first openings <b>262</b><i>a</i>, wherein a portion of the first conductive blind via structures <b>212</b><i>a </i>exposed by the first openings <b>262</b><i>a </i>are used as the bonding pads. The second solder mask layer <b>264</b> has a plurality of second openings <b>264</b><i>a</i>, wherein a portion of the second conductive blind via structures <b>214</b><i>a </i>exposed by the second openings <b>264</b><i>a </i>are used as the bonding pads. Herein, the fabricating of the package carrier <b>100</b> is completed.

p-0058The first conductive blind via structures <b>212</b><i>a </i>exposed by the first openings <b>262</b><i>a </i>of the first solder mask layer <b>262</b> are used as the bonding pads, and the second conductive blind via structures <b>214</b><i>a </i>exposed by the second openings <b>264</b><i>a </i>of the second solder mask layer <b>264</b> are used as the bonding pads. Thus, after the chip (not shown) is electrically connected to the bonding pads by the wire bonding or flip-chip process and the chip is encapsulated in a compound (not shown), the chip package process is completed. That is, the package carrier <b>100</b> of the present embodiment is suitable to be a chip package carrier.

p-0059In other words, in the present embodiment, because it is not necessary to use the metal for supporting the first copper foil layer <b>110</b><i>a </i>and the second copper foil layer <b>110</b><i>c</i>, the method for manufacturing the package carrier is capable of effectively decreasing the manufacturing cost by comparing with the conventional technique. In addition, in the present embodiment, the first circuit layer <b>142</b><i>a </i>and the second circuit layer <b>144</b><i>a </i>are formed by compressing the first conductive layer <b>142</b> and the second conductive layer <b>144</b>, and then patterning the first conductive layer <b>142</b> and the second conductive layer <b>144</b>. By comparing with the conventional technique that the circuit layers are formed by the copper plating method, the first circuit layer <b>142</b><i>a </i>and the second circuit layer <b>144</b><i>a </i>of the present embodiment have relatively better copper thickness uniformities. Further, in the present embodiment, by using the first circuit layer <b>142</b><i>a </i>(which is made from the first conductive layer <b>142</b>) as the positioning and aligning standard of the first copper foil layer <b>110</b><i>a </i>and the fifth copper foil layer <b>110</b><i>e</i>. Hence, the alignment precision of the package carrier <b>100</b> can be effectively increased so that the manufacturing yield and the reliability of the package carrier <b>100</b> are improved.

p-0060According to the above description, in the present invention, the copper foil layers are bonded each other by using the adhesive gel. Comparing with the conventional technique in which the metal is used as the carrier for supporting the circuit layer, in the present invention, the method for forming the package carrier is capable of effectively decreasing the cost for manufacturing the package carrier. Also, in the present invention, it is not necessary to use mass of gel to fix the circuit layer on the metal as taught by the conventional technique so that the method for forming the package carrier may not confront the difficulty in removing the mass of gel layer. Therefore, the manufacturing process of the present invention is more simple and easy. Moreover, the conductive layers are laminated by the compressing process, and then the circuit layers are formed by the patterning the conductive layers. Therefore, by comparing with the conventional technique that the circuit layers are formed by the copper plating method, the circuit layers have relatively better copper thickness uniformities. Furthermore, in the present invention, by using one circuit layer as the positioning standard, the alignment precision between the copper foil layers and the circuit layers can be effectively increased. In general, the package carrier formation method of the present invention is capable of simplifying the manufacturing steps, decreasing the manufacturing cost, increasing the manufacturing yield and further increasing the product reliability.

p-0061Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.