Nova Patents
US8448002B2

Clock-gated series-coupled data processing modules

Summary by NHIP

Series-coupled clock-gated power management

The system couples a clock module in parallel to series-connected data processing modules that individually determine idle eligibility. A controller asserts a second signal only if an upstream module will not send data before the first module enters idle state, preventing premature clock gating.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data.

US8448002B2, drawing sheet 1
Sheet 1 of 5

Term

3.3 yearsleft in the term

Expires 16 January 2030, including 646 days of term adjustment.

  1. Priority and filed
  2. Granted
  3. Today
  4. Expires

18 claims: 3 independent, 15 dependent

  1. 1
    Broadest claimClaim Score 39, average(NHIP)A power management system comprising:a plurality of data processing modules coupled in series, wherein each of said data processing modules is operable for individually determining whether it is eligible to be placed into an idle state;a clock module coupled in parallel to each of said data processing modules, wherein said clock module is operable to turn off clock signals to any subset of said data processing modules eligible for said idle state while continuing to provide clock signals to any other of said data processing modules;and a controller module operable for detecting signals from said plurality of data processing modules, wherein said signals comprise a first signal asserted by a first data processing module, said first signal indicating that said first data processing module has determined it is eligible to be placed in said idle state, wherein further said controller module optionally asserts a second signal in response to said first signal, wherein said second signal is asserted if said controller module determines that said first data processing module is allowed to enter said idle state, and wherein said controller module does not assert said second signal if said controller module determines that said first data processing module will receive data from an upstream data processing module before said first data processing module can be placed in said idle state and then awakened.
  2. 9
    A method comprising:operating a data processing pipeline comprising a plurality of data processing modules coupled in series and including a first data processing module, wherein each of said data processing modules is operable for receiving a clock signal from a shared clock module and wherein each of said data processing modules monitors a measure of its idleness, wherein further said clock module is operable to turn off clock signals to any subset of said data processing modules eligible for an idle state while continuing to provide clock signals to any other of said data processing modules, wherein said first data processing module asserts an idle detect with threshold signal to indicate that said first data processing module has determined it is eligible to be placed in said idle state, wherein a controller module receives said idle detect with threshold signal and, in response, optionally asserts a clock disable signal, wherein said clock disable signal is asserted if said controller module determines that said first data processing module is allowed to enter said idle state, and wherein said controller module does not assert said clock disable signal if said controller module determines that said first data processing module will receive data from an upstream data processing module before said first data processing module can be placed in said idle state and then awakened;and selectively turning off said a clock signal to said first data processing module, wherein said clock signal to said first data processing module is turned off if said clock disable signal is asserted by said controller module and is not turned off if said clock disable signal is not asserted by said controller module.
  3. 14
    A method comprising:monitoring a plurality of data processing modules coupled in a pipeline, wherein outputs of an upstream module in said pipeline comprise inputs to a downstream module in said pipeline, said plurality of data processing modules comprising a first data processing module and a second data processing module coupled to a controller module;detecting a first signal asserted by said first data processing module, said first data processing module determining that it is eligible to be placed into an idle state and then asserting said first signal in response to said determining;and in response to said first signal, optionally placing said first data processing module in said idle state by clock-gating said first data processing module at a clock module that is coupled to each of said data processing modules, wherein said second data processing module continues to receive clock signals from said clock module if said first data processing module is clock-gated, wherein said first data processing module is clock-gated if said controller module determines that said first data processing module is allowed to enter said idle state, and wherein said first data processing module is not clock-gated if said controller module determines that said first data processing module will receive data from an upstream data processing module before said first data processing module can be placed in said idle state and then awakened.
Independent claims3