Methods of uniformly removing silicon oxide and an intermediate semiconductor device

CROSS-REFERENCE TO RELATED APPLICATION

0001This application is a continuation of U.S. patent application Ser. No. 11/652,218, filed Jan. 11, 2007, now U.S. Pat. No. 7,786,016, issued Aug. 31, 2010, the disclosure of which is hereby incorporated herein by this reference in its entirety.

FIELD OF THE INVENTION

0002Embodiments of the invention relate to fabricating an intermediate semiconductor device structure. Specifically, embodiments of the invention relate to uniformly removing silicon oxide from intermediate semiconductor device structures, to removing a sacrificial oxide without substantially removing an isolation oxide, and an intermediate semiconductor device structure including same.

BACKGROUND OF THE INVENTION

0003Chemical Oxide Removal (“COR”) is a gaseous process known in the art to selectively etch oxides. In COR, gaseous ammonia (“NH₃”) and hydrogen fluoride (“HF”) are reacted to produce NH₄F_x, which reacts with silicon oxide on a semiconductor wafer to form ammonium hexafluorosilicate (“(NH₄)₂SiF₆”). The semiconductor wafer is then heated, producing nitrogen (“N₂”), water (“H₂O”), silicon tetrafluoride (“SiF₄”), and NH₃, which are volatile and evaporate from the surface of the semiconductor wafer. Alternatively, the (NH₄)₂SiF₆is removed using a deionized (“DI”) water rinse. COR is marketed under the tradename CERTAS® by Tokyo Electron Limited. Additional NH₃/HF-based chemistries for etching oxides are marketed by ULVAC Technologies, Inc. (Methuen, Mass.) and Applied Materials, Inc. (Santa Clara, Calif.). U.S. Pat. No. 6,951,821 discloses a method of trimming an oxide hard mask using a chemical treatment and a thermal treatment. The chemical treatment includes exposing the oxide hard mask to NH₃and HF. The thermal treatment includes heating the oxide hard mask to a temperature that ranges from 20° C. 200° C. 20° C.-200° C. The combination of the chemical treatment and the thermal treatment etches a thermal oxide at greater than 10 nm per 60 seconds of chemical treatment and tetraethyl orthosilicate (“TEOS”) at greater than 10 nm per 180 seconds of chemical treatment.

0004COR has also been used to selectively remove small amounts (1 nm-30 nm) of silicon oxides, such as a native oxide or a thermal oxide, relative to polysilicon. Unites States Patent Application Publication No. 2006/0196527 discloses using COR to remove SiO₂in a pre-metal-silicon contact formation cleaning, to remove SiO₂before a silicon epitaxial process, or to remove SiO₂from a polysilicon wafer before depositing a silicide metal.

0005U.S. Pat. No. 7,091,069 discloses using a plasma or vapor of HF and NH₃to remove a sacrificial oxide layer on a silicon-on-insulator (“SOI”) metal oxide semiconductor field effect transistor (“MOSFET”). U.S. Pat. No. 6,656,824 discloses using a plasma or vapor of HF and NH₃to remove a sacrificial oxide layer in a MOSFET. The plasma or vapor of HF and NH₃produces undercuts beneath silicon spacers formed on sidewalls of a dielectric layer of the MOSFET. U.S. Pat. No. 6,838,347 discloses etching concave portions of an oxide hardmask at a reduced rate relative to convex portions using a plasma or vapor of HF and NH₃.

0006Shallow trench isolation (“STI”) has been commonly used in semiconductor fabrication to provide field isolation. As semiconductor devices are scaled ever smaller, and trenches become narrower, filling the trenches with a dielectric material becomes increasingly difficult. As trench sizes become smaller, seams, voids, gaps, or microbubbles are unavoidably formed in the trenches as the dielectric material is deposited. These seams, voids, gaps, or microbubbles affect the ability to uniformly etch the dielectric material. In addition, if the semiconductor device includes trenches having different widths, uniformly removing the dielectric material from the trenches is difficult. Furthermore, if the semiconductor device includes other exposed layers, removing the dielectric material without removing the other exposed layers is difficult.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

0007While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention may be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

0008<figref idref="DRAWINGS">FIGS. 1A-1F</figref> are cross-sectional views of an embodiment of an intermediate semiconductor device structure during various stages of fabrication;

0009<figref idref="DRAWINGS">FIGS. 2A-2C</figref> are cross-sectional views of a second embodiment of an intermediate semiconductor device structure during various stages of fabrication; and

0010<figref idref="DRAWINGS">FIGS. 3A-3C</figref> are cross-sectional views of a third embodiment of an intermediate semiconductor device structure during various stages of fabrication.

DETAILED DESCRIPTION OF THE INVENTION

0011An embodiment of a method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein. The presence of the at least one cavity affects substantially uniform removal of the silicon oxide. As used herein, the term “silicon oxide” refers to silicon dioxide or other silicon oxide based material. The silicon oxide having the cavity therein may be exposed to a gaseous mixture of NH₃and HF, forming a solid reaction product on a surface of the silicon oxide. Heat may be applied to the silicon oxide and the solid reaction product, producing volatile reaction products. As such, at least a portion of the silicon oxide is substantially uniformly removed.

0012An embodiment of a second method of uniformly removing silicon oxide is disclosed. The silicon oxide includes at least two portions, wherein a first portion of the silicon oxide has a first property and a second portion of the silicon oxide has a second property. The presence of the at least two portions of the silicon oxide affects substantially uniform removal of the silicon oxide. The silicon oxide may be exposed to the gaseous mixture of NH₃and HF, forming a solid reaction product on a surface of the silicon oxide. Heat may be applied to the silicon oxide and the solid reaction product such that the at least two portions of the silicon oxide are substantially uniformly removed.

0013An embodiment of a method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH₃and HF and heat is also disclosed.

0014An embodiment of an intermediate semiconductor device structure that comprises a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions is also disclosed. The sacrificial layer is in contact with the exposed isolation regions.

0015The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the present invention. However, a person of ordinary skill in the art would understand that the embodiments of the present invention may be practiced without employing these specific details. Indeed, the embodiments of the present invention may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device. The intermediate semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the present invention are described in detail below. Additional acts to form the complete semiconductor device from the intermediate semiconductor device structures may be performed by conventional fabrication techniques.

0016For the sake of example only, the methods are described below in reference to fabricating an STI region on a device, such as a NAND FLASH device, a dynamic random access memory (“DRAM”) device, a logic device, or other device. However, the methods may also be used in other situations where silicon oxide is to be uniformly removed. The memory device may be used in wireless devices, personal computers, or other electronic devices, without limitation.

0017<figref idref="DRAWINGS">FIGS. 1A-1F</figref> illustrate the fabrication of a portion of a memory array that includes the STI region. <figref idref="DRAWINGS">FIG. 1A</figref> illustrates an intermediate semiconductor device structure <b>100</b> after several processing acts have already been conducted. The intermediate semiconductor device structure <b>100</b> may include a semiconductor substrate <b>102</b> having a first dielectric layer <b>104</b> thereon. As used herein, the term “semiconductor substrate” refers to a conventional silicon substrate or other bulk substrate having a layer of semiconductor material. As used herein, the term “bulk substrate” includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, silicon-on-sapphire (“SOS”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor, optoelectronics, or biotechnology materials, such as silicon-germanium, germanium, gallium arsenide, or indium phosphide. A first conductive layer <b>106</b> may be formed on the first dielectric layer <b>104</b>. For the sake of example only, the first dielectric layer <b>104</b> may be formed from silicon oxide and the first conductive layer <b>106</b> may be formed from doped polysilicon.

0018A hard mask layer <b>108</b> may be formed on the first conductive layer <b>106</b>. The hard mask layer <b>108</b> may be formed from a dielectric material, such as a nitride. The nitride may include, but is not limited to, silicon nitride (“Si₃N₄”). STI region <b>110</b> may be formed by patterning the hard mask layer <b>108</b> and etching an opening (not shown) through the hard mask layer <b>108</b>, the first conductive layer <b>106</b>, and the first dielectric layer <b>104</b>. The opening may be extended into the semiconductor substrate <b>102</b>, forming a trench (not shown). Patterning and etching of these layers are performed by conventional techniques. As such, the patterning and etching is not described in detail herein. The trench defines an active region <b>112</b> on the semiconductor substrate <b>102</b>. Silicon oxide may be deposited in the trench and over the hard mask layer <b>108</b>. The silicon oxide used to fill the trench may ultimately form the STI region <b>110</b> between active regions <b>112</b>. The silicon oxide may be conformally deposited in the trench by a conventional deposition technique, such as by a spin-on process, atomic layer deposition (“ALD”), or an ozone TEOS process. In one embodiment, the silicon oxide may be a spin-on dielectric (“SOD”) material. SOD materials are known in the art and are commercially available. The silicon oxide may be a silsesquioxane material (“SSQ”) including, but not limited to, hydrogen silsesquioxane (“HSQ”), methyl silsesquioxane (“MSQ”), polyhydrogen silsesquioxane (“pHSQ”), hydrio polysilsesquioxane (“H-PSSQ”) methyl polysilsesquioxane (“M-PSSQ”), and phenyl polysilsesquioxane (“P-PSSQ”). The SOD material may also include carbon, such as the dielectric materials sold under the SILECS® tradename. The SOD material may also include nitrogen, such as a polysilazane. As used herein, the term “polysilazane” refers to an oligomer, cyclic, polycyclic, linear polymer or resinous polymer having multiple Si—N repeating units.

0019As the silicon oxide is deposited in the trench, seams, voids, gaps, microbubbles, or other cavities may undesirably form in the STI region <b>110</b>. The seams, voids, gaps, microbubbles, or cavities may introduce empty space into at least one portion of the STI region <b>110</b>. For convenience, such seams, voids, gaps, microbubbles, or cavities are collectively referred to herein as a “cavity.” For the sake of example only, the cavity may form as the silicon oxide is deposited by a conformal deposition technique, such as ALD, a spin-on process, or an ozone TEOS process. <figref idref="DRAWINGS">FIG. 1A</figref> illustrates a cavity <b>114</b> in the STI region <b>110</b>. For the sake of clarity, the size of cavity <b>114</b> is exaggerated. While one cavity <b>114</b> in one STI region <b>110</b> is illustrated in <figref idref="DRAWINGS">FIG. 1A</figref>, each of the STI regions <b>110</b> may include none, one, or more than one cavity <b>114</b> as long as one of the STI regions <b>110</b> includes at least one cavity <b>114</b>. The presence of cavity <b>114</b> may affect uniform etching, device isolation, and overall structural integrity of the STI region <b>110</b>. In other words, the cavity <b>114</b> may prevent substantially uniform etching of the STI regions <b>110</b>. For instance, if the intermediate semiconductor device structure <b>100</b> (shown in <figref idref="DRAWINGS">FIG. 1A</figref>) were etched using a conventional wet etch process, such as HF, the cavity <b>114</b> would be etched at a faster, uncontrollable rate than the remainder of the STI region <b>110</b>. Portions of the silicon oxide may be removed, such as by chemical mechanical polishing (“CMP”), so that an upper surface of the STI region <b>110</b> is substantially level with an upper surface of the hard mask layer <b>108</b>. The intermediate semiconductor device structure <b>100</b> having the STI regions <b>110</b> with cavity <b>114</b> is shown in <figref idref="DRAWINGS">FIG. 1A</figref>.

0020The hard mask layer <b>108</b> may be removed by conventional techniques, exposing an upper surface of the first conductive layer <b>106</b> of each of the active regions <b>112</b>, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>. <figref idref="DRAWINGS">FIG. 1B</figref> illustrates intermediate semiconductor device structure <b>100</b>′. The STI regions <b>110</b> of the intermediate semiconductor device structure <b>100</b>′ may be substantially uniformly removed, even though the cavity <b>114</b> is present, so that the upper surface of the STI regions <b>110</b> lies below the upper surface of the first conductive layer <b>106</b>. The STI regions <b>110</b> may be anisotropically etched without substantially removing other exposed layers, such as first conductive layer <b>106</b>. The STI regions <b>110</b> may be substantially uniformly removed by exposing the silicon oxide to a gaseous mixture of NH₃and HF. The NH₃and HF may react with each other and with the silicon oxide to produce (NH₄)₂SiF₆on a surface of the silicon oxide. The (NH₄)₂SiF₆forms a diffusion barrier <b>116</b> on the STI regions <b>110</b>, as shown in <figref idref="DRAWINGS">FIG. 1B</figref>. As the reaction proceeds, a thickness of the diffusion barrier <b>116</b> increases, reducing access of the gaseous NH₃and HF to the surface of the silicon oxide. When NH₃and HF are no longer able to penetrate the diffusion barrier <b>116</b>, the rate of the reaction slows and, ultimately, stops. As such, the reaction of NH₃and HF with the silicon oxide to produce the (NH₄)₂SiF₆is substantially self-limiting.

0021To form the diffusion barrier <b>116</b>, the gaseous mixture of NH₃and HF may be supplied to a first chamber, such as a reaction chamber, in which the intermediate semiconductor device structure <b>100</b>′ is placed. The gaseous mixture may, optionally, include a diluent gas, such as argon, xenon, or helium. To prevent NH₃and HF from prematurely reacting, the NH₃and HF may be supplied separately to the first chamber. Processing conditions, including but not limited to, temperature, pressure, and flow rates within the first chamber may be controlled. For instance, the temperature of the intermediate semiconductor device structure <b>100</b> may be maintained within a range from approximately 10° C. to 30° C., such as at approximately room temperature (approximately 25° C.). The pressure within the first chamber may be maintained within a range of from approximately 6.7×10⁻²PA to approximately 4.0 Pa (from approximately 0.5 mTorr to approximately 30 mTorr). The gaseous mixture may include an equal volume of HF and NH₃or a greater volume of the HF relative to the NH₃. For instance, a volumetric flow ratio of the HF to the NH₃in the gaseous mixture may be within a range of from approximately 1/1 to 2/1.

0022After the reaction is complete, the intermediate semiconductor device structure <b>100</b>′ may be heated in a second chamber to remove the diffusion barrier <b>116</b>. Alternatively, the diffusion barrier <b>116</b> may be removed using a DI water rinse, if exposed material layers on the intermediate semiconductor device structure <b>100</b>′ are not adversely affected by water. The heat may cause the diffusion barrier <b>116</b> to thermally decompose into the volatile reaction products (N₂, H₂O, SiF₄, and NH₃), which are exhausted from the second chamber. The intermediate semiconductor device structure <b>100</b>′ may be heated to a temperature within a range of from approximately 80° C. to approximately 200° C., such as from approximately 100° C. to approximately 200° C. or from approximately 125° C. to approximately 150° C. The intermediate semiconductor device structure <b>100</b>′ may be heated for an amount of time within a range of from approximately 60 seconds to approximately 180 seconds. N₂may be flowed through the second chamber to provide a viscous flow to remove the volatile reaction products. The second chamber may be maintained at a pressure within a range of from approximately 66.6 Pa to approximately 133 Pa (from approximately 500 mTorr to approximately 1 Torr), and the gas flow rate of N₂may be within a range of from approximately 500 sccm to approximately 3000 sccm.

0023After removing the diffusion barrier <b>116</b>, the exposed portion of the STI regions <b>110</b> may be reacted with additional NH₃and HF, as previously described, forming another diffusion barrier <b>116</b> over the remaining portion of the STI regions <b>110</b>. The diffusion barrier <b>116</b> may be heated, as previously described, to remove the diffusion barrier <b>116</b>. By exposing the intermediate semiconductor device structure <b>100</b> to multiple reaction and heating cycles, a controlled amount of the silicon oxide may be removed from the STI regions <b>110</b>. However, for the sake of convenience and clarity, only one reaction and heat cycle is illustrated in <figref idref="DRAWINGS">FIGS. 1A-1C</figref>. For the sake of example only, with each reaction and heating cycle, up to approximately 200 Å of the silicon oxide may be removed. By conducting multiple reaction and heat cycles, a desired amount of the STI regions <b>110</b> may be removed. <figref idref="DRAWINGS">FIG. 1C</figref> shows intermediate semiconductor device structure <b>100</b>″ after removing the desired amount of the STI regions <b>110</b>. For instance, up to approximately 600 Å of the STI regions <b>110</b> may be removed by performing multiple reaction and heat cycles. By repeating the reaction and heat cycles, larger amounts of silicon oxide may be removed using the gaseous mixture of NH₃and HF than was previously thought possible. While <figref idref="DRAWINGS">FIG. 1C</figref> shows a portion of the STI regions <b>110</b> as being uniformly removed, the reaction and heat cycles may be repeated to remove the desired amount of the STI regions <b>110</b>, ranging from a portion of the STI regions <b>110</b> to substantially all of the STI regions <b>110</b>.

0024If the intermediate semiconductor device structure <b>100</b> includes exposed layers (not shown) formed from other silicon oxide materials, the intermediate semiconductor device structure <b>100</b> may be exposed to the gaseous mixture of NH₃and HF and heated, as described above, to uniformly remove the STI regions <b>110</b> without substantially removing these other silicon oxide materials. For the sake of example only, these other silicon oxide materials may include, but are not limited to, tetraethylorthosilicate (“TEOS”), phosphosilicate glass (“PSG”), or borophosphosilicate glass (“BPSG”).

0025Without being bound by a particular theory, it is believed that the diffusion barrier <b>116</b> inhibits diffusion of the gaseous mixture of NH₃and HF into the cavity <b>114</b>. As such, the diffusion barrier <b>116</b> may enable the STI regions <b>110</b> to be substantially uniformly etched even in the presence of the cavity <b>114</b>. Diffusion length differences of the NH₃and HF across the cavity <b>114</b> relative to other portions of the STI regions <b>110</b> may be substantially similar. For instance, the NH₃and HF may diffuse across the cavity <b>114</b> and across other portions of the STI regions <b>110</b> at a substantially similar rate when the diffusion barrier <b>116</b> is present. Without the diffusion barrier <b>116</b>, the NH₃and HF may diffuse across the cavity <b>114</b> at a faster rate compared to other portions of the STI regions <b>110</b>, leading to uncontrolled removal of the STI regions <b>110</b> having the cavity <b>114</b>. It is also believed that the thickness, type, and density of the diffusion barrier <b>116</b> formed over the cavity <b>114</b> may be different than that formed over the remainder of the STI regions <b>110</b>. By controlling these parameters of the diffusion barrier <b>116</b>, such as by adjusting the processing conditions, the STI regions <b>110</b> may be uniformly removed. The amount or thickness of the (NH₄)₂SiF₆forming the diffusion barrier <b>116</b> may depend on the ability of the gaseous NH₃and HF to diffuse to the surface of the silicon oxide, which is controlled by adjusting the processing conditions. The density of the diffusion barrier <b>116</b> may also affect the diffusion of the NH₃and HF. The density of the diffusion barrier <b>116</b> is affected by the type and density of the silicon oxide used as the fill material of the STI regions <b>110</b>. In addition to density, other physical properties of the silicon oxide, such as the strain of the silicon oxide, may affect the density of the diffusion barrier <b>116</b>.

0026After the desired amount of the STI regions <b>110</b> is removed, additional material layers may be formed on the intermediate semiconductor device structure <b>100</b>″, as known in the art, to produce the memory device, such as the NAND FLASH memory device. For the sake of example only, a second conductive layer <b>118</b> may be formed overlying the STI regions <b>110</b> and the first conductive layer <b>106</b>, as shown in <figref idref="DRAWINGS">FIG. 1D</figref>. The second conductive layer <b>118</b> may be formed from doped polysilicon. Portions of the second conductive layer <b>118</b> may be anisotropically etched so that remaining portions of the second conductive layer <b>118</b> self align with, and form, conductive spacers <b>118</b>′ on sidewalls of the first conductive layer <b>106</b>, as shown in <figref idref="DRAWINGS">FIG. 1E</figref>. The conductive spacers <b>118</b>′ increase the surface area of the first conductive layer <b>106</b>. The first conductive layer <b>106</b> with the conductive spacers <b>118</b>′ thereon form floating gates of floating gate memory cells. A second dielectric layer <b>120</b> may be formed overlying STI regions <b>110</b>, the first conductive layer <b>106</b>, and the conductive spacers <b>118</b>′, as shown in <figref idref="DRAWINGS">FIG. 1F</figref>. The second dielectric layer <b>120</b> may be formed from silicon oxide, nitride, oxynitride, oxide-nitride-oxide (ONO), or other dielectric material. A third conductive layer <b>122</b>, such as a layer of doped polysilicon, may be formed on the second dielectric layer <b>120</b>. The first dielectric layer <b>104</b>, the first conductive layer <b>106</b>, the conductive spacers <b>118</b>′, the second dielectric layer <b>120</b>, and the third conductive layer <b>122</b> form gate stacks <b>124</b>. Portions of the gate stacks <b>124</b> may form a portion of floating gate memory cells, where the first dielectric layer <b>104</b> forms a tunnel dielectric layer, the first conductive layer <b>106</b> and the second conductive layer <b>118</b> form a form a floating gate, the second dielectric layer <b>120</b> is an intergate dielectric layer, and the third dielectric layer <b>122</b> forms a control gate (or word line).

0027The gaseous mixture of NH₃and HF and heat may also be used to uniformly remove silicon oxide in which portions of the silicon oxide have different physical properties, such as at least one of a different density and a different strain. A first portion of the silicon oxide may have a first physical property, such as a first density or first strain, and a second portion of the silicon oxide may have a second physical property, such as a second density or second strain. For the sake of example only, the first portion of the silicon oxide and the second portion of the silicon oxide may have different densities. For convenience, such a silicon oxide is referred to herein as a “mixed density oxide.” The first portion of the silicon oxide may be a low density oxide and the second portion of the silicon oxide may be a high density silicon oxide. For the sake of example only, the mixed density oxide may be present in trenches of different widths, as shown in <figref idref="DRAWINGS">FIGS. 2A-2C</figref>. The silicon oxide may be removed from these trenches without removing other exposed layers, such as first conductive layer <b>106</b>. As described below, the trenches may be filled with silicon oxide, producing an intermediate semiconductor device structure <b>200</b> having STI regions <b>110</b>, <b>110</b>′ of different widths, as shown in <figref idref="DRAWINGS">FIG. 2A</figref>. The silicon oxide may include at least one portion of a low density oxide and at least one portion of a high density oxide. For the sake of example only, the mixed densities in the silicon oxide may be caused by unequal densification of the STI regions <b>110</b>, <b>110</b>′ during subsequent processing. The trenches may be formed on the semiconductor substrate <b>102</b> as previously described, except that the resulting semiconductor substrate <b>102</b> may have multiple trenches with different widths. In other words, a first trench may have a first width and a second trench may have a second, different width. The width differential between the trenches may be such that it would difficult to uniformly remove the silicon oxide using a conventional wet etchant, such as HF. For the sake of example only, the semiconductor substrate <b>102</b> may include a first trench having a width of less than or equal to approximately 90 nm, such as a width of approximately 50 nm, and a second trench having a width greater than or equal to approximately 250 nm, such as a width of approximately 500 nm.

0028The first trench and the second trench may be filled with silicon oxide, such as a SOD material, as previously described, and densified. The densification causes the silicon oxide on a top surface of the semiconductor substrate <b>102</b> and the silicon oxide filling the second trench to be substantially densified, while the silicon oxide in the first trench is less densified. As such, the silicon oxide in the first trench may be less dense (more porous) than that in the second trench. Without being bound by a particular theory, the difference in densification is believed to be caused by strain issues. As such, the silicon oxide in the first trench may be low density oxide (STI region <b>110</b>′), while the silicon oxide in the second trench may be high density oxide (STI region <b>110</b>). The silicon oxide may be planarized, such as by CMP, removing the silicon oxide from the top surface of the semiconductor substrate <b>102</b>, while the silicon oxide remains in the first trench and the second trench. In <figref idref="DRAWINGS">FIGS. 2A-2C</figref>, the trenches are shown filled with silicon oxide, producing STI regions <b>110</b>, <b>110</b>′.

0029The intermediate semiconductor device structure <b>200</b> shown in <figref idref="DRAWINGS">FIG. 2A</figref> may be exposed to the gaseous mixture of NH₃and HF, forming diffusion barrier <b>116</b>, as described above. The diffusion barrier is shown in <figref idref="DRAWINGS">FIG. 2B</figref>, which illustrates intermediate semiconductor device structure <b>200</b>′. Since the silicon oxide in the larger, STI region <b>110</b> is substantially densified while the silicon oxide in the narrower, STI region <b>110</b>′ is more porous (less dense), the thickness, type, and density of the diffusion barrier <b>116</b> formed over the STI region <b>110</b> may differ from that formed over the STI region <b>110</b>′. The intermediate semiconductor device structure <b>200</b>′ may then be heated, as previously described, to form the volatile reaction products (N₂, H₂O, SiF₄, and NH₃). By controlling the parameters of the diffusion barrier <b>116</b> formed over the STI regions <b>110</b>, <b>110</b>′ and the rate at which the volatile reaction products are evaporated, the etch differential between the silicon oxide filling the STI region <b>110</b> and the STI region <b>110</b>′ may be reduced. As such, the silicon oxide may be more uniformly removed from STI regions <b>110</b>, <b>110</b>′, which have different widths. Alternatively, the diffusion barrier <b>116</b> may be removed using a DI water rinse, if exposed material layers on the intermediate semiconductor device structure <b>200</b>′ are not adversely affected by water. By conducting multiple reaction and heat cycles, a desired amount of the silicon oxide of the STI regions <b>110</b>, <b>110</b>′ may be removed, forming intermediate semiconductor device structure <b>200</b>″, as shown in <figref idref="DRAWINGS">FIG. 2C</figref>. After removing the desired amount of the STI regions <b>110</b>, <b>110</b>′ additional material layers may be formed over the STI regions <b>110</b>, <b>110</b>′ as previously described and as known in the art, to produce the memory device, such as the NAND FLASH memory device.

0030If the intermediate semiconductor device structure <b>200</b> includes exposed layers (not shown) formed from other silicon oxide materials, the intermediate semiconductor device structure <b>200</b> may be exposed to the gaseous mixture of NH₃and HF and heated, as described above, to uniformly remove the STI regions <b>110</b>, <b>110</b>′ without removing these other silicon oxide materials. For the sake of example only, these other silicon oxide materials may include, but are not limited to, TEOS, PSG, or BPSG.

0031If the intermediate semiconductor device structure <b>200</b> shown in <figref idref="DRAWINGS">FIG. 2A</figref> was exposed to a conventional etchant, such as HF, the STI region <b>110</b>′ would be etched at a faster rate that the STI regions <b>110</b>.

0032The gaseous mixture of NH₃and HF may also be used to substantially remove a sacrificial oxide without substantially removing an isolation oxide, as shown in <figref idref="DRAWINGS">FIGS. 3A-3C</figref>. <figref idref="DRAWINGS">FIG. 3A</figref> shows intermediate semiconductor device structure <b>300</b> in a reverse flow process for fabricating a memory device, such as a NAND FLASH memory device. The intermediate semiconductor device structure <b>300</b> may include an exposed sacrificial layer <b>302</b>, at least one exposed STI region <b>304</b>, and a semiconductor substrate <b>102</b>. The sacrificial layer <b>302</b> may be formed from silicon oxide, such as a sacrificial oxide. The STI region <b>304</b> may be formed from silicon oxide, such as an isolation oxide. The sacrificial layer <b>302</b> may be in contact with the STI regions <b>304</b>. The sacrificial layer <b>302</b> may function as a mask to protect the underlying semiconductor substrate <b>102</b>.

0033The sacrificial layer <b>302</b> may be substantially removed without substantially removing the STI region <b>304</b>. For instance, the sacrificial layer <b>302</b> may be removed without forming divots or “j-hooks” in the STI region <b>304</b>. In other words, sidewalls <b>306</b> of the STI region <b>304</b> may remain substantially vertical, with no etching occurring at interfaces of the sacrificial layer <b>302</b> with the STI region <b>304</b>. The sacrificial layer <b>302</b> may be exposed to the gaseous mixture of NH₃and HF, as previously described, forming the diffusion barrier <b>116</b> on the sacrificial layer <b>302</b>. <figref idref="DRAWINGS">FIG. 3B</figref> shows an intermediate semiconductor device structure <b>300</b>′ having the diffusion barrier <b>116</b> on the sacrificial layer <b>302</b>. Without being bound by a particular theory, it is believed that the diffusion barrier <b>116</b> prevents or inhibits etching of the sidewalls <b>306</b> of the STI region <b>304</b>. The diffusion barrier <b>116</b> may be removed by heating, as previously described. Alternatively, the diffusion barrier <b>116</b> may be removed using a DI water rinse, if exposed material layers on the intermediate semiconductor device structure <b>300</b>′ are not adversely affected by water. The gaseous mixture of NH₃and HF may react with the sacrificial layer <b>302</b>, forming the reaction products previously described, which are volatilized by applying heat.

0034Depending on the thickness of the sacrificial layer <b>302</b>, substantially all of the sacrificial layer <b>302</b> may be removed by a single reaction and heat cycle. Alternatively, multiple reaction and heat cycles may be performed. After removing the sacrificial layer <b>302</b>, a gate oxide layer <b>308</b> may be formed over the semiconductor substrate <b>102</b> by techniques known in the art, such as by thermally growing the oxide. The intermediate semiconductor device structure <b>300</b>″, shown in <figref idref="DRAWINGS">FIG. 3C</figref>, may be subjected to additional processing, as known in the art, to form an active area over the gate oxide layer <b>308</b> on the semiconductor substrate <b>102</b>.

0035If the intermediate semiconductor device structure <b>300</b> includes exposed layers (not shown) formed from other silicon oxide materials, the intermediate semiconductor device structure <b>300</b> may be exposed to the gaseous mixture of NH₃and HF and heated, as described above, to remove the sacrificial layer <b>302</b> without removing these other silicon oxide materials. For the sake of example only, these other silicon oxide materials may include, but are not limited to, TEOS, PSG, or BPSG.

0036If the intermediate structure <b>300</b> (shown in <figref idref="DRAWINGS">FIG. 3A</figref>) was exposed to a conventional etchant, such as HF, the STI region <b>304</b> would be etched, in addition to the sacrificial layer <b>302</b>. For instance, divots or “j-hooks” would be formed in the STI region <b>304</b>.

0037While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.