Semiconductor device and method of forming the same

CROSS-REFERENCE TO RELATED APPLICATION

0001This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2009-0083124, filed on Sep. 3, 2009, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

0002The present disclosure herein relates to semiconductor devices and methods of forming the same, and more particularly, to semiconductor devices including a metal pattern and methods of forming the same.

0003Due to various demands for consumer electronic devices, semiconductor devices embedded therein also need to be more compact and reliable. Accordingly, research continues to be performed that is directed to increasing the degree of integration and/or performance of semiconductor devices.

0004Techniques for storing more data in the same physical space may help to achieve a higher degree of integration and/or performance of semiconductor devices. To accomplish this, various attempts have been made to maintain the original properties of semiconductor devices while reducing the sizes of components in the semiconductor devices. However, reducing the size of semiconductor components is made more difficult by limitations in semiconductor device manufacturing equipment.

SUMMARY

0005The present disclosure relates to semiconductor devices with improved reliability and methods of forming the same.

0006Methods of forming a semiconductor device according to some embodiments include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer.

0007The first metal layer and the second metal layer include a gate pattern, and the methods may further include forming an insulation pattern between the semiconductor structure and the gate pattern.

0008The methods may further include forming a plurality of openings in the insulation layer to define a plurality of gate interlayer insulation layers and forming a plurality of first and second metal layers in the respective plurality of openings to thereby define a plurality of gate patterns. Forming the gate interlayer insulation layers and the insulation pattern may include alternately stacking gate interlayer insulation layers and sacrificial layers on a substrate, forming the hole that penetrates the gate interlayer insulation layers and the sacrificial layers, removing the sacrificial layers, and forming the insulation pattern conformally in a space, where the sacrificial layers are removed, and the hole.

0009In still other embodiments, the methods may further include forming a barrier layer between the insulation pattern and the first metal layer, wherein the barrier layer is etched together with the first metal layer during the wet etching process.

0010In other embodiments, the insulation pattern may include a compound bonded by an ionic bond.

0011In yet other embodiments, the first metal layer and the second metal layer may include the same metal.

0012In further embodiments, a formation speed of the first metal layer may be faster than that of the second metal layer.

0013In still further embodiments, the forming of the first metal layer and the forming of the second metal layer may include supplying a first metal source and a first reducing gas in the opening and supplying a second metal source and a second reducing gas in the opening, respectively, the first metal source and the second metal source being formed of the same metal element.

0014In even further embodiments, the first metal source and the second metal source may be WF₆.

0015In yet further embodiments, the first reducing gas and the second reducing gas may include hydrogen atoms, hydrogen radicals, and/or hydrogen ions.

0016In yet further embodiments, the first reducing gas may be silane or diborane and the second reducing gas may be hydrogen gas.

0017In yet further embodiments, the forming of the insulation pattern and the opening may include forming an insulation layer on the semiconductor structure and performing an anisotropic-etching process on the insulation layer until the top surface of the semiconductor structure is exposed.

0018In yet further embodiments, the semiconductor structure may further include a conductive region exposed through the bottom of the opening and the first metal layer is electrically connected to the conductive region.

0019In yet further embodiments, the methods may further include: forming a variable resistance pattern that contacts the second metal layer and forming a third metal layer on the variable resistance pattern.

0020In other embodiments of the inventive concept, semiconductor devices include a substrate, gate interlayer insulation layers and gate patterns, which are stacked on the substrate alternately; a semiconductor structure extending upwardly from the substrate along sidewalls of the gate interlayer insulation layers and the gate patterns, and an insulation pattern between the gate patterns and the semiconductor structure, wherein the gate patterns comprise a first metal pattern and a second metal pattern, the first metal pattern being adjacent to the semiconductor structure, the second metal pattern being spaced apart from the semiconductor structure by the first metal pattern.

0021In some embodiments, an average grain size of the first metal pattern may be smaller than an average grain size of the second metal pattern.

0022In other embodiments, the insulation pattern may extend on the top and bottom surfaces of the gate patterns.

0023In still other embodiments, the second metal pattern may extend on a second sidewall facing a first sidewall of the gate patterns adjacent to the semiconductor structure; the second metal pattern protruding more than the insulation patterns on the second sidewall of the gate patterns.

0024In even other embodiments, the semiconductor devices may further include a barrier layer between the first metal pattern and the insulation pattern, where one side of the barrier layer is coplanar with one side of the first metal pattern.

0025In yet other embodiments, the insulation pattern may include Oxide-Nitride-Oxide-AluminumOxide (ONOA).

BRIEF DESCRIPTION OF THE DRAWINGS

0026The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:

0027<figref idref="DRAWINGS">FIG. 1</figref> is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept;

0028<figref idref="DRAWINGS">FIGS. 2A through 2F</figref> are manufacturing sectional views taken along the line I-II of <figref idref="DRAWINGS">FIG. 1</figref> illustrating methods of forming semiconductor devices according to some embodiments of the inventive concept;

0029<figref idref="DRAWINGS">FIG. 3</figref> is a sectional view taken along the line I-II of <figref idref="DRAWINGS">FIG. 1</figref> illustrating a semiconductor device according to some embodiments of the inventive concept;

0030<figref idref="DRAWINGS">FIGS. 4A and 4B</figref> are enlarged views of an area A of <figref idref="DRAWINGS">FIG. 3</figref>;

0031<figref idref="DRAWINGS">FIGS. 5A through 5C</figref> are manufacturing sectional views illustrating a semiconductor device according to further embodiments of the inventive concept;

0032<figref idref="DRAWINGS">FIGS. 6 and 7</figref> are views illustrating application examples of semiconductor devices according to further embodiments of the inventive concept; and

0033<figref idref="DRAWINGS">FIGS. 8 and 9</figref> are views illustrating application examples of the embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

0034Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

0035It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

0036The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

0037Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly form formal sense unless expressly so defined herein.

0038It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

0039Relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” “lateral,” “vertical,” “beneath,” “over,” “on,” etc., may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

0040Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a discrete change from implanted to non-implanted regions. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

0041Referring to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A through <b>2</b>F, and <b>3</b>, methods of forming semiconductor devices according to some embodiments of the inventive concept will be described. <figref idref="DRAWINGS">FIG. 1</figref> is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. <figref idref="DRAWINGS">FIGS. 2A through 2F</figref> and <figref idref="DRAWINGS">FIG. 3</figref> are manufacturing sectional views of a semiconductor device taken along the line I-II of <figref idref="DRAWINGS">FIG. 1</figref> according to some embodiments of the inventive concept.

0042Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, a semiconductor substrate <b>100</b> (hereinafter, referred to as a substrate) is provided. The semiconductor substrate <b>100</b> may include a bulk semiconductor, an epitaxial semiconductor layer, a silicon on insulator (SOI) layer or other semiconductor structure. The substrate <b>100</b> may include a well region doped with dopants. An insulation layer <b>121</b> is formed on the substrate <b>100</b>.

0043Sacrificial layers SC and gate interlayer insulation layers <b>123</b> are alternately stacked on the underlying insulation layer <b>121</b>. The gate interlayer insulation layers <b>123</b> may be formed of the same material as the underlying insulation layer <b>121</b>. The gate interlayer insulation layers <b>123</b> and the sacrificial layers SC may include materials having respectively different etch selectivities with respect to an etch solution. For example, when the gate interlayer insulation layers <b>123</b> include an oxide, the sacrificial layers SC may include a nitride. An upper insulation layer <b>125</b> may be formed on the uppermost sacrificial layer SC. The upper insulation layer <b>125</b> may include the same insulation material as the gate interlayer insulation layers <b>123</b>.

0044The insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC are anisotropically etched to form a hole <b>130</b> that penetrates the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC. The hole <b>130</b> penetrates the above layers, and may be formed vertically from the plane surface of the substrate <b>100</b>. In other embodiments, instead of the hole <b>130</b>, a groove that penetrates the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC and extends along a first direction of the substrate <b>100</b> may be formed.

0045A semiconductor structure <b>133</b> may be formed in the hole <b>130</b>. The semiconductor structure <b>133</b> may include a semiconductor element such as, for example, a semiconductor material that includes group IV elements of the periodic table, although it will be appreciated that other types of semiconductor materials can be used. The semiconductor structure <b>133</b> may include a semiconductor element of a single crystal or polycrystalline state. In particular embodiments, the semiconductor structure <b>133</b> may include an active pattern in which a channel region of a transistor is formed.

0046The semiconductor structure <b>133</b> may be a pillar type structure that fills the hole <b>130</b>. In other embodiments, the semiconductor structure <b>133</b> may have a shell form with an inner space. In that case, the inner space may be filled by an insulation layer. When a groove is formed instead of the hole <b>130</b>, a semiconductor layer for filling the groove is formed, and then is patterned, such that the semiconductor structure <b>133</b> having a pillar form may be formed.

0047An impurity region <b>135</b> may be formed on a top portion of the semiconductor structure <b>133</b>. The impurity region <b>135</b> may be formed, for example, by implanting dopants into the top portion of the semiconductor structure <b>133</b>. In other embodiments, the impurity region <b>135</b> may be formed by performing an in-situ process, such as a diffusion doping process.

0048Referring to <figref idref="DRAWINGS">FIG. 2B</figref>, an optional groove <b>140</b> that penetrates the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC may be formed by patterning the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC. The groove <b>140</b> may extend in a first direction that is parallel to the top (plane) surface of the substrate <b>100</b>. The top surface of the substrate <b>100</b> and the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC may be exposed by the groove <b>140</b>.

0049The groove <b>140</b> and the hole <b>130</b> may have slanted sidewalls. This is because the total thickness of layers, which are etched by an anisotropic etching process for forming the groove <b>140</b> and the hole <b>130</b>, is thick. In other embodiments, if the total thickness of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the sacrificial layers SC is appropriately adjusted, the sidewalls of the groove <b>140</b> and the hole <b>130</b> may be substantially vertical to the top surface of the substrate <b>100</b>.

0050Referring to <figref idref="DRAWINGS">FIG. 2C</figref>, the sacrificial layers SC are removed. When the sacrificial layers SC include a nitride, they may be removed, for example, by a wet etching process using H3PO4 solution as an etching solution. Openings <b>150</b> may be formed between the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> by removing the sacrificial layers SC. Portions of the sidewall of the semiconductor structure <b>133</b> may be exposed by the openings <b>150</b>. In addition, the top surface of the underlying insulation layer <b>121</b> and the top surfaces and the bottom surfaces of the gate interlayer insulation layers <b>123</b> and the upper insulation layer <b>125</b> may be exposed by the openings <b>150</b>.

0051An insulation pattern <b>142</b> is formed in the groove <b>140</b> and the openings <b>150</b>. The insulation pattern <b>142</b> may conformally cover the sidewalls of the groove <b>140</b> and the openings <b>150</b>. The insulation pattern <b>142</b> may be formed on the sidewall portions of the semiconductor structure <b>133</b> exposed by the openings <b>150</b>. The insulation pattern <b>142</b> may cover the top surfaces and bottom surfaces of the gate interlayer insulation layers <b>123</b> and the upper insulation layer <b>125</b> and the top surface of the underlying insulation layer <b>121</b>. The insulation pattern <b>142</b> may be formed on the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The insulation pattern <b>142</b> on the top surfaces and the bottom surfaces of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> may define the sidewalls of the openings <b>150</b>.

0052The insulation pattern <b>142</b> may include a plurality of insulation layers. In some embodiments, the insulation pattern <b>142</b> may include a charge storage layer. For example, the insulation pattern <b>142</b> may include an oxide-nitride-oxide (ONO) layer or an oxide-nitride-oxide-aluminum oxide (ONOA) layer. In some embodiments, the nitride layer may serve as a charge storage layer in a nonvolatile semiconductor memory device.

0053A barrier layer <b>144</b> may be formed on the insulation pattern <b>142</b>. The barrier layer <b>144</b> may be conformally formed on the bottoms and sidewalls of the groove <b>140</b> and the openings <b>150</b>. The barrier layer <b>144</b> may be formed to have a thickness of less than about 100 Å. For example, the barrier layer <b>144</b> may be formed to have a thickness of less than about 50 Å. The barrier layer <b>144</b> may include a metal nitride. For example, the barrier layer <b>144</b> may include tungsten nitride (WN) or titanium nitride (TiN).

0054Referring to <figref idref="DRAWINGS">FIG. 2D</figref>, a first metal layer <b>153</b> may be formed in the openings <b>150</b> and the groove <b>140</b>. The first metal layer <b>153</b> may fill a portion of the groove <b>140</b>.

0055Forming the first metal layer <b>153</b> may include providing a first metal source and a first reducing gas in the openings <b>150</b> and the groove <b>140</b>. The first metal source may include a first metal. For example, the first metal source may be a compound including a transition metal. The first reducing gas reduces the metal included in the first metal source. For example, the first reducing gas may include a chemical species that supplies hydrogen gas, hydrogen radicals, and/or hydrogen ions.

0056In some embodiments, the first metal source may include WF₆and the first reducing gas may include SiH₄and/or B₂H₆. When the first metal source and the first reducing gas are supplied to a reaction chamber into which the substrate <b>100</b> including the structure of <figref idref="DRAWINGS">FIG. 2C</figref> is loaded, a reaction corresponding to a chemical formula 1 below may occur. <br />2WF₆+3SiH₄->2W+3SiF₄+6H₂  (chemical formula 1)

0057WF₆corresponds to the first metal source and SiH₄corresponds to the first reducing gas in the chemical formula 1. The reaction of the first metal source and the first reducing gas may be relatively fast. Accordingly, the first metal layer <b>153</b> may be deposited with a fast speed in the openings <b>150</b> and the groove <b>140</b>. As a consequence, the grain size of the first metal layer <b>153</b>, which is deposited at a fast speed, may be relatively small.

0058Referring to <figref idref="DRAWINGS">FIG. 2E</figref>, a portion of the first metal layer <b>153</b> is etched to form first metal patterns <b>154</b> in the openings <b>150</b>. The first metal layer <b>153</b> may be wet-etched. For example, the first metal layer <b>153</b> may be etched by an etching solution including at least one of H₂O₂, H₃PO₄, HNO₃, CH₃COOH, HF, HCl, H₂SO₄, EKC, SF₆, Cl₂, and/or NF₃. One first metal pattern <b>154</b> is formed in each opening by etching the first metal layer <b>153</b>. Accordingly, node isolation of the first metal layer <b>153</b> may occur due to the wet etching. That is, first metal patterns <b>154</b> in adjacent openings <b>150</b> may be insulated from one another.

0059Since the first metal layer <b>153</b> is etched by the wet etching, etching byproducts, which are generated during the etching process of the first metal layer <b>153</b>, may be reduced and/or prevented from polluting the surface of the insulation pattern <b>142</b>. In addition, as the first metal layer <b>153</b> has a relatively small grain size, etching damage caused by the wet etching can be reduced. A cleaning process may be additionally performed after the wet etching. Dangling bonds on the insulation pattern <b>142</b> may be removed by the wet etching process and/or the cleaning process.

0060During the etching of the first metal layer <b>153</b>, the barrier layer <b>144</b> may be etched along with the first metal layer <b>153</b> to form a barrier pattern <b>145</b>. Portions of the insulation pattern <b>142</b> that define upper and lower sidewalls of the openings <b>150</b> may be exposed by the etching of the barrier pattern <b>145</b>. The etched surface of the barrier pattern <b>145</b> and the etched surface of the first metal pattern <b>154</b> may be coplanar.

0061The etched surfaces of the first metal pattern <b>154</b> and the barrier pattern <b>145</b> may be disposed further inside the openings <b>150</b> than a surface of the insulation pattern <b>142</b> that contacts the sidewalls of the gate interlayer insulation layer <b>123</b>.

0062Referring to <figref idref="DRAWINGS">FIG. 2F</figref>, a second metal pattern <b>156</b> is formed from the etched surface of the first metal pattern <b>154</b>. In particular, the second metal pattern <b>156</b> may be selectively formed from the etched surface of the first metal pattern <b>154</b>. The first metal pattern <b>154</b> and the second metal pattern <b>156</b> formed in one opening may constitute one gate pattern LSG, CG, or USG. The gate pattern LSG that is nearest to the substrate <b>100</b> is a lower selection gate pattern, and the uppermost gate pattern USG among the gate patterns LSG, CG, and USG may be an upper selection gate pattern. Gate patterns between the lower selection gate LSG and the upper selection gate pattern USG may include memory cell gate patterns CG.

0063Selectively forming the second metal pattern <b>156</b> on the etched surface of the first metal pattern <b>154</b> may include supplying a second metal source and supplying a second reducing gas in a reaction chamber.

0064The second metal source may include a second metal. In some embodiments, the second metal source may include the same metal as the first metal source. For example, when the second metal source is WF₆and the second reducing gas is H₂, reaction occurring in the reaction chamber may be the following chemical formula 2. <br />2WF₆+3H₂->W+6HF  (chemical formula 2)

0065The chemical reaction corresponding to the chemical formula 2 may preferentially occur on the etched surface of the first metal pattern <b>154</b>. While not wishing to be bound by a particular theory of operation, the second metal source and the second reducing gas may be absorbed on the etched surface of the first metal pattern <b>154</b>. The second reducing gas may be decomposed into an atomic state, and then the decomposed second reducing gas of an atomic state reacts to the absorbed second metal source, such that the second metal may be deposited on the etched surface of the first metal pattern <b>154</b>.

0066The reaction for forming the second metal pattern <b>156</b> may be relatively slow. For example, the reaction for forming the second metal pattern <b>156</b> may progress slower than the reaction for forming the first metal layer <b>153</b>. The second metal pattern <b>156</b> may have a lager grain size than the first metal pattern <b>154</b>.

0067The forming process of the second metal pattern <b>156</b> may be performed under low temperature and low pressure conditions. For example, during the forming of the second metal pattern <b>156</b>, a temperature in the reaction chamber may be below about 500° C. and a pressure in the reaction chamber may be below about 50 Torr. In some embodiments, during the forming of the second metal pattern <b>156</b>, a temperature in the reaction chamber may be about 350° C. and a pressure in the reaction chamber may be about 40 Torr

0068For starting the deposition of a metal atom, a metal source is provided at a deposition target layer and then accepts electrons from the deposition target layer. Because the metal source accepts electrons, a portion of atoms attached to the metal of the metal source may be separated from the metal source. For example, when WF₆is used as the metal source, it may be separated into WF_nand F₆-n (n is an integer less than 6) by electrons provided from the deposition target layer. The separated F may be bonded by sharing one atom, constituting the etching target layer, and the provided electron. The bonded one atom and F atom are removed from the deposition target layer in a gas state such that the metal is deposited on the deposition target layer.

0069During the deposition process of the metal atom, one factor that causes the metal atom to be deposited on the deposition target layer is that electrons are provided from the deposition target layer to the metal source. Accordingly, if the deposition target layer provides electrons easily, the deposition of the metal atom may progress smoothly. The degree that the deposition target layer provides electrons may be affected by the type of chemical bonding in the deposition target layer. The compounds constituting the deposition target layer may be combined through metallic bonds, covalent bonds, and/or ionic bonds. The compounds may be bonded by a plurality of bonding factors, but one of the plurality of combinations may be predominant. For example, the metallic bond may be predominant during bonding of metal atoms, and the covalent bond may be predominant during bonding of non-metal atoms. For convenience of description, atoms of a particular material are considered to be bonded by the most dominant bonding type among the various types of atomic bonds. If a compound constituting the deposition target layer is bonded by predominantly by ionic bonds, the deposition target layer may provide a relatively small amount of electrons to the metal source. In particular, if a compound constituting the deposition target layer has strong ionic bonds, the deposition target layer may not easily provide electrons to the metal source. In contrast, if a compound constituting the deposition target layer has strong metallic bonds, the deposition target layer may easily provide relatively more electrons to the metal source. Accordingly, if the metal layer is formed by providing the metal source to the deposition target layer, the formation of the metal layer can be controlled by the types of bonding found in the deposition target layer.

0070Accordingly, the deposition of the metal atoms for forming the second metal pattern may be performed selectively. The compound constituting the insulation pattern <b>142</b> may be bonded predominantly by strong ionic bonds. For example, the surface of the insulation pattern <b>142</b> exposed by the openings <b>150</b> may include an oxide. A compound including strong ionic bonds may provide less electrons to the second metal source. Accordingly, the second metal source and the second reducing gas may not be easily absorbed on the insulation pattern <b>142</b>. In more detail, the reaction for deposition of the second metal layer <b>156</b> may include absorption of the second metal source and the second reducing gas. Accordingly, since the second metal source and the second reducing gas may not be easily absorbed on the insulation pattern <b>142</b>, the second metal pattern <b>156</b> may not be easily formed on the insulation pattern <b>142</b>.

0071On the contrary, since the first metal pattern <b>154</b> includes compounds formed predominantly by metallic bonds, the first metal pattern <b>154</b> may provide relatively more electrons to the second metal source. Accordingly, the second metal source and the second reducing gas may be preferentially absorbed on the first metal pattern <b>154</b>. Thus, the second metals may be more easily deposited on the first metal pattern <b>154</b>. By the degree difference of metal deposition speed, the second metal pattern <b>156</b> may be formed preferentially on the first metal pattern <b>154</b>. Since the second metal pattern <b>156</b> grows selectively, it may not be necessary to perform a node isolation process for isolating the second metal patterns <b>156</b> in adjacent openings <b>150</b>. Accordingly, defects of the second metal pattern <b>156</b>, which may occur due to a node isolation process, may be avoided. In more detail, the second metal pattern <b>156</b> may have a relatively large grain size compared to the first metal pattern <b>154</b>. Accordingly, a node isolation process could cause a large portion of the second metal pattern to be torn out, which may have a bad influence on a resistance property of the second metal pattern <b>156</b>. However, according to embodiments of the inventive concept, the node isolation process may be omitted, such that defects of the second metal pattern <b>156</b>, which would otherwise occur during the node isolation process, can be reduced or avoided. In addition, since the second metal patterns <b>156</b> may be electrically separated in the adjacent openings <b>150</b>, it may be more completely insulated than adjacent gate patterns.

0072As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the second metal pattern <b>156</b> may grow up to be substantially even with the sidewall of the insulation pattern <b>142</b> on the sidewalls of the gate interlayer insulation layers <b>123</b>. In other embodiments, as shown in <figref idref="DRAWINGS">FIG. 4B</figref>, the second metal pattern <b>156</b> may protrude beyond the sidewalls of the insulation pattern <b>142</b> on the sidewalls of the gate interlayer insulation layers <b>123</b>. That is, the second metal pattern <b>156</b> may have overgrowth. Thereby, a resistance of the gate pattern including the second metal pattern <b>156</b> can be reduced. A resistance of the gate pattern can be adjusted by controlling the degree of growth of the second metal pattern <b>156</b>.

0073Methods of forming the first metal pattern <b>154</b> and the second metal pattern <b>156</b> according to some embodiments of the inventive concept may reduce physical defects, such as void and seams, which may otherwise occur during the pattern formation process. As mentioned above, since the first metal pattern <b>154</b> is etched by wet etching, etching byproducts of the first metal pattern <b>154</b> (for example, metal atoms in the first metal source) that could pollute the insulation pattern <b>142</b> may be reduced. For example, etching byproducts that would otherwise become attached to the insulation pattern <b>142</b> and the second metal pattern <b>154</b> may be reduced. Since a second metal using the etching byproduct as a nucleus grows in a different direction than a second metal that grows from the first metal pattern <b>154</b>, the second metal pattern <b>154</b> formed according thereto may have physical defects. Moreover, since the etching byproducts are formed irregularly on the insulation pattern <b>142</b>, it may be difficult to control the second metal pattern <b>154</b> growing from the etching byproducts. However, according to some embodiments of the inventive concept, if the second metal pattern <b>156</b> is selectively formed from the first metal pattern <b>154</b>, the second metal pattern <b>156</b> having reduced physical defects may be formed. Accordingly, the reliability of a semiconductor device including the second metal pattern <b>156</b> can be improved.

0074Referring to <figref idref="DRAWINGS">FIG. 3</figref>, a filling insulation layer <b>158</b> is formed to fill the groove <b>140</b>. Due to the filling insulation layer <b>158</b>, the first and second metal patterns <b>154</b> and <b>156</b> stacked sharing the one semiconductor structure <b>133</b> and the first and second metal patterns <b>154</b> and <b>156</b> stacked sharing adjacent another semiconductor structure <b>133</b> are separated. The top surface of the filling insulation layer <b>158</b> may be planarized. When it is planarized, portions of the upper insulation layer <b>125</b> and the insulation pattern <b>142</b> on the semiconductor structure <b>133</b> may be removed together. The planarization may be performed until the top surface of the upper insulation layer <b>125</b> and the top surface of the impurity region <b>135</b> in the semiconductor structure <b>133</b> are exposed.

0075An interlayer insulation layer <b>161</b> is formed on the semiconductor structure <b>133</b> and the upper insulation layer <b>125</b>. A bit line contact hole penetrating the interlayer insulation layer <b>161</b> is formed. The bit line contact hole may expose the top surface of the impurity region <b>135</b>. A bit line contact <b>163</b> is formed to fill the bit line contact hole. The bit line contact <b>163</b> may include a metal, a doped semiconductor, or a metal compound. A bit line <b>165</b> is formed on the interlayer insulation layer <b>161</b> and the bit line contact <b>163</b>. The bit line <b>165</b> may extend in a second direction intersecting the first direction. The bit line contact <b>163</b> and the bit line <b>165</b> may be formed simultaneously or separately.

0076Referring to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>3</b>, <b>4</b>A, and <b>4</b>B, a semiconductor device according to an embodiment of the inventive concept will be described. The above contents described with reference to <figref idref="DRAWINGS">FIGS. 1</figref>, <b>2</b>A through <b>2</b>F, <b>3</b>, <b>4</b>A, and <b>4</b>B may be omitted.

0077Referring to <figref idref="DRAWINGS">FIGS. 1 and 3</figref>, the semiconductor structure <b>133</b> is disposed on the substrate <b>100</b>. The semiconductor structure <b>133</b> may have a pillar form that extends upwardly from the substrate <b>100</b>. The semiconductor structure <b>133</b> may include a single crystal or polycrystalline semiconductor material. An impurity region <b>135</b> may be formed on the uppermost portion of the semiconductor structure <b>133</b>. The impurity region <b>135</b> may be formed with a higher dopant concentration than other portions of the semiconductor structure <b>133</b>.

0078The insulation layers <b>121</b>, <b>123</b>, and <b>125</b> may be stacked along the sidewall of the semiconductor structure <b>133</b>. The insulation layers <b>121</b>, <b>123</b>, and <b>125</b> may include the underlying insulation layer <b>121</b> that is the most adjacent to the substrate <b>100</b>, a plurality of gate interlayer insulation layers <b>123</b> on the underlying insulation layer <b>121</b>, and the upper insulation layer <b>125</b> on the uppermost gate insulation layer <b>123</b>. The insulation layers <b>121</b>, <b>123</b>, and <b>125</b> are separated from each other and may be disposed on the sidewall of the semiconductor structure <b>133</b>.

0079An insulation pattern <b>142</b> is provided on sidewalls of the semiconductor structure <b>133</b> and the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The insulation pattern <b>142</b> may cover the sidewall of the semiconductor structure <b>133</b> between the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and the top surfaces, bottom surfaces and the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The insulation pattern <b>142</b> may include a plurality of layers. The insulation pattern <b>142</b> may include an oxide layer, a nitride layer, or a combination thereof. For example, the insulation pattern <b>142</b> may be an ONO layer or an ONOA layer.

0080Openings <b>150</b> may be defined between adjacent insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The openings <b>150</b> may be a space that is defined by the insulation pattern <b>142</b> between the adjacent insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The openings <b>150</b> include the bottoms defined by the insulation pattern <b>142</b> on the sidewall of the semiconductor structure <b>133</b> and the sidewalls defined by the insulation pattern <b>142</b> on the top surfaces and bottom surfaces of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>.

0081The openings <b>150</b> may be filled with a gate pattern. The gate pattern may include a first metal pattern <b>154</b> adjacent to the bottom of the openings <b>150</b> and a second metal pattern <b>156</b> on the sidewall of the first metal pattern <b>154</b>.

0082Referring to <figref idref="DRAWINGS">FIG. 4A</figref>, one sidewall of the second metal pattern <b>156</b> may be coplanar with the sidewall of the insulation pattern <b>142</b> on the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> that are not adjacent to the semiconductor structure <b>133</b>. In other embodiments, as shown in <figref idref="DRAWINGS">FIG. 4B</figref>, one sidewall of the second metal pattern <b>156</b> may protrude farther laterally than the sidewall of the insulation pattern <b>142</b> on the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. In still other embodiments, one sidewall of the second metal pattern <b>156</b> may be disposed within the openings <b>150</b>. For example, the second metal pattern <b>156</b> may be more depressed than the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>. The form of the second metal pattern <b>156</b> may be appropriately selected according to an applied device.

0083The first metal pattern <b>154</b> and the second metal pattern <b>156</b> may include the same metal. For example, the first metal pattern <b>154</b> and the second metal pattern <b>156</b> may include tungsten. The first metal pattern <b>154</b> may have a different grain size than the second metal pattern <b>156</b>. For example, the grain size of the first metal pattern <b>154</b> may be smaller than that of the second metal pattern <b>156</b>. Thereby, the first metal pattern <b>154</b> may have greater resistivity than the second metal pattern <b>156</b>.

0084The barrier pattern <b>145</b> may be provided on the top surface and bottom surface of the first metal pattern <b>154</b>. The barrier pattern <b>145</b> may extend between and separate the first metal pattern <b>154</b> and the semiconductor structure <b>133</b>. The barrier pattern <b>145</b> may include at least one selected from metal compounds including TiN and WN.

0085One stacked layer structure including the semiconductor structure <b>133</b>, the gate patterns, the insulation layers <b>121</b>, <b>123</b>, and <b>125</b>, and the insulation patterns and a different stacked layer structure that is substantially similar to the one stacked layer structure may be disposed on the substrate <b>100</b>. The filling insulation layer <b>158</b> may be disposed between the stacked layer structures. The filling insulation layer <b>158</b> may contact the insulation pattern <b>142</b> on the sidewalls of the insulation layers <b>121</b>, <b>123</b>, and <b>125</b> and one sidewall of the second metal pattern <b>156</b>.

0086A bit line <b>165</b> is provided on the filling insulation layer <b>158</b>, the upper insulation layer <b>125</b>, and the semiconductor structure <b>133</b>. The bit line <b>165</b> may be connected to the semiconductor structure <b>133</b> by the bit line contact <b>163</b>. An interlayer insulation layer <b>161</b> may be further disposed between the bit line <b>165</b>, and the upper insulation layer <b>125</b> and the filling insulation layer <b>158</b>.

0087Referring to <figref idref="DRAWINGS">FIGS. 5A through 5C</figref>, a method of forming a semiconductor device according to further embodiments of the inventive concept will be described.

0088Referring to <figref idref="DRAWINGS">FIG. 5A</figref>, a semiconductor structure <b>200</b> is provided. The semiconductor structure <b>200</b> may be a semiconductor substrate, an epitaxial semiconductor layer, a silicon on insulator (SOI) layer or other semiconductor structure. The semiconductor structure <b>200</b> may include a conductive region and/or an insulating region. An insulation pattern <b>242</b> for defining an opening <b>250</b> is formed on the semiconductor structure <b>200</b>. The insulation pattern <b>242</b> may include atoms bonded by an ionic bond. The insulation pattern <b>242</b> may include an oxide, for example. The opening <b>250</b> may expose the top surface of the semiconductor structure <b>200</b>. For example, the opening <b>250</b> may expose the top surface of the conductive region of the semiconductor structure <b>200</b>. The opening <b>250</b> may include the bottom defined by the top surface of the semiconductor structure <b>200</b> and the sidewall defined by the sidewall of the insulation pattern <b>242</b>.

0089A barrier layer <b>244</b> may be formed in the opening <b>250</b>. The barrier layer <b>244</b> may be conformally formed on the top surface of the exposed semiconductor structure <b>200</b> (the bottom of the opening <b>250</b>), the sidewall of the opening <b>250</b>, and the top surface of the insulation pattern <b>242</b>. The barrier layer <b>244</b> may include a metal compound. For example, the barrier layer <b>244</b> may include TiN or WN.

0090A first metal layer <b>253</b> may be formed in the opening <b>250</b>. The forming of the first metal layer <b>253</b> includes providing a first metal source and providing a first reducing gas in the reaction chamber. The first metal source may include a first metal. The first reducing gas may include hydrogen atoms, hydrogen radicals, and/or hydrogen ions. The first metal source and the first reducing gas may include materials having a relatively fast reaction. For example, the first metal source may be WF6 and the first reducing gas may be SiH4 or B2H6. Next, an embodiment that WF6 is used as the first metal source and SiH4 is used as the first reducing gas will be described. Reaction between the first metal source and the first reducing gas may be expressed with a reaction formula (a chemical formula 1 below). <br />2WF₆+3SiH₄->2W+3SiF₄+6H₂  (chemical formula 1)

0091WF₆corresponds to the first metal source and SiH₄corresponds to the first reducing gas in the chemical formula 1. The reaction of the first metal source and the first reducing gas may be relatively fast. Accordingly, the first metal layer <b>253</b> may be deposited at a fast speed. Likewise, the grain size of the first metal layer <b>253</b>, which is deposited at a fast speed, may be relatively small.

0092Referring to <figref idref="DRAWINGS">FIG. 5B</figref>, the first metal layer <b>253</b> and the barrier layer <b>244</b> may be wet-etched. The first metal layer <b>253</b> and the barrier layer <b>244</b> may be etched by an etching solution including at least one of H₂O₂, H₃PO₄, HNO₃, CH₃COOH, HF, HCl, H₂SO₄, EKC, SF₆, Cl₂, and NF₃. The first metal pattern <b>254</b> and the barrier pattern <b>245</b> may be formed by the wet etching. The first metal pattern <b>254</b> and the barrier pattern <b>245</b> may have a lower top surface than the insulation pattern <b>242</b>. The sidewall of the opening <b>250</b> may be partially exposed by the wet etching. That is, the sidewall of the insulation pattern <b>242</b> may be partially exposed.

0093Referring to <figref idref="DRAWINGS">FIG. 5C</figref>, the second metal pattern <b>256</b> may be selectively formed. The second metal pattern <b>256</b> may grow anisotropically on the first metal pattern <b>254</b>.

0094Selectively forming the second metal pattern <b>256</b> on the etched surface of the first metal pattern <b>254</b> may include supplying a second metal source and supplying a second reducing gas in the reaction chamber.

0095In an embodiment, the second metal source may include the same metal as the first metal source. For example, if the second metal source is WF₆and the second reducing is H₂, reaction occurring in the reaction chamber may be the following chemical formula 2. <br />2WF₆+3H₂->W+6HF  (chemical formula 2)

0096The chemical reaction corresponding to the chemical formula 2 may occur on the etched surface of the first metal pattern <b>254</b>. The second metal source and the second reducing gas may be absorbed on the etched surface of the first metal pattern <b>254</b>. The second reducing gas is decomposed into an atomic state, and the decomposed second reducing gas of an atomic state reacts to the second metal source such that the second metal may be deposited on the etched surface of the first metal pattern <b>254</b>.

0097The reaction for forming the second metal pattern <b>256</b> may be relatively slow. For example, the reaction for forming the second metal pattern <b>256</b> may progress more slowly than the reaction for forming the first metal layer <b>253</b>.

0098In these embodiments, in order to slow down the reaction speed of the second material source and the second reducing gas, the second metal source may be provided in greater amounts than the reducing gas. The forming process of the second metal pattern <b>256</b> may be performed under low temperature and low pressure conditions. For example, during the forming of the second metal pattern <b>256</b>, a temperature in the reaction chamber may be below about 500° C. and a pressure in the reaction chamber may be below about 50 Torr. In an embodiment, during the forming of the second metal pattern <b>256</b>, a temperature in the reaction chamber may be about 350° C. and a pressure in the reaction chamber may be about 40 Torr.

0099Referring to <figref idref="DRAWINGS">FIG. 5C</figref> again, a semiconductor device according to further embodiments of the inventive concept will be described. The contents described with reference to <figref idref="DRAWINGS">FIGS. 5A through 5C</figref> will be partially omitted.

0100An insulation pattern <b>242</b> may be disposed on the semiconductor structure <b>200</b>. The semiconductor structure <b>200</b> may include a conductive region and/or an insulating region. The insulation pattern <b>242</b> may define an opening <b>250</b> that exposes at least portion of the conductive region of the semiconductor structure <b>200</b>.

0101The first metal pattern <b>254</b> and the second metal pattern <b>256</b> may be disposed in the opening <b>250</b>. The first metal pattern <b>254</b> is disposed at the bottom of the opening <b>250</b> adjacent to the semiconductor structure <b>200</b> and the second metal pattern <b>256</b> may be disposed on the first metal pattern <b>254</b> in the opening <b>250</b>.

0102The first metal pattern <b>254</b> and the second metal pattern <b>256</b> may include the same metal element. For example, the first metal pattern <b>254</b> and the second metal pattern <b>256</b> may include tungsten. The first metal pattern <b>254</b> and the second metal pattern <b>256</b> may have different average grain sizes. For example, the grain size of the first metal pattern <b>254</b> may be smaller than that of the second metal pattern <b>256</b>. Thereby, the first metal pattern <b>254</b> may have greater resistivity than the second metal pattern <b>256</b>.

0103A barrier pattern <b>245</b> may be interposed between the first metal pattern <b>254</b> and the insulation pattern <b>242</b>. The top surface of the barrier pattern <b>245</b> and the top surface of the first metal pattern <b>254</b> may be coplanar.

0104Referring to <figref idref="DRAWINGS">FIGS. 6 and 7</figref>, application examples of a semiconductor device according to other embodiments of the inventive concept will be described.

0105Referring to <figref idref="DRAWINGS">FIG. 6</figref>, a variable resistance layer <b>263</b> is disposed on the second metal pattern <b>256</b> of <figref idref="DRAWINGS">FIG. 5C</figref>. The variable resistance layer <b>263</b> may include a phase change material, a transition metal oxide, or a plurality of magnetic layers. In this case, the first metal pattern <b>254</b> and the second metal pattern <b>256</b> may serve as a first contact plug.

0106A top electrode <b>265</b> and a bottom electrode <b>261</b> may be respectively disposed on the top and bottom of the variable resistance layer <b>263</b>. The bottom electrode <b>261</b> may be interposed between the variable resistance layer <b>263</b> and the second metal pattern <b>256</b>. The bottom electrode <b>261</b> may be omitted according to a property of the variable resistance layer <b>263</b>.

0107Referring to <figref idref="DRAWINGS">FIG. 7</figref>, the first metal pattern <b>254</b>, the second metal pattern <b>256</b>, and the barrier pattern <b>245</b> of <figref idref="DRAWINGS">FIG. 5C</figref> may electrically contact the top surfaces of the gate <b>212</b> and the impurity region <b>203</b> constituting a transistor. In this case, the first metal pattern <b>254</b> and the second metal pattern <b>256</b> may serve as a contact plug. An ohmic layer <b>216</b> may be further interposed between the barrier pattern <b>245</b> and the impurity region <b>203</b> and/or between the barrier pattern <b>245</b> and the gate <b>212</b>.

0108Referring to <figref idref="DRAWINGS">FIG. 8</figref>, an electronic system <b>1100</b> may include a controller <b>1110</b>, an input/output (I/O) <b>1120</b>, a memory device <b>1130</b>, an interface <b>1140</b>, and a bus <b>1150</b>. The controller <b>1110</b>, the I/O <b>1120</b>, the memory device <b>1130</b>, and/or the interface <b>1140</b> may be electrically connected through the bus <b>1150</b>. The bus <b>1150</b> corresponds to a path through which data may be transferred. The controller <b>1110</b> may include at least one of a microprocessor, a digital signal processor, a microcontroller, and/or logic devices performing equivalent functions thereof. The I/O <b>1120</b> may include a keypad, a keyboard, and a display device. The memory device <b>1130</b> may store data and/or commands. The memory device <b>1130</b> may include at least one of the semiconductor memory devices disclosed in the above first and second embodiments. In addition, the memory device <b>1130</b> may further include a semiconductor memory device of a different form (for example, a flash memory device, a DRAM, and/or SRAM) The interface <b>1140</b> may perform a function for transmitting data to a communication network or receiving data from a communication network. The interface <b>1140</b> may be a wire or wireless interface. For example, the interface <b>1140</b> may include an antenna or a wire/wireless transceiver. Although not illustrated, the electronic system <b>1100</b> may further include a high-speed DRAM and/or SRAM as an operating memory to improve an operation of the controller <b>1110</b>

0109The electronic system <b>1100</b> may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or all kinds of electronic products for transmitting and/or receiving information via a wireless environment.

0110<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram illustrating a memory card including a semiconductor memory device according to an embodiment of the inventive concept.

0111Referring to <figref idref="DRAWINGS">FIG. 9</figref>, a memory card <b>1200</b> according to an embodiment of the inventive concept includes a memory device <b>1210</b>. The memory device <b>1210</b> may include at least one of the semiconductor memory devices of the first and second embodiments. The memory device <b>1210</b> may further include another form of a semiconductor memory device (for example, a flash memory device, a DRAM, and/or SRAM). The memory card <b>1200</b> may include a memory controller <b>1220</b> for controlling data exchange between a host and the memory device <b>1210</b>.

0112The memory controller <b>1220</b> may include a central processing unit (CPU) <b>1222</b> for controlling general operations of the memory card <b>1200</b>. Or, the memory controller <b>1220</b> may include a SRAM <b>1221</b> that serves as an operating memory of the CPU <b>1222</b>. Furthermore, the memory controller <b>1220</b> may further include a host interface (I/F) <b>1223</b> and a memory I/F <b>1225</b>. The host I/F <b>1223</b> may include a data exchange protocol between the memory card <b>1200</b> and a host. The memory I/O <b>1225</b> may connect the memory controller <b>1220</b> with the memory device <b>1210</b>. Furthermore, the memory controller <b>1220</b> may further include an error correction circuit (ECC) <b>1224</b>. The ECC <b>1224</b> detects and corrects an error of data read from the memory device <b>1210</b>. Although not illustrated in the drawings, the memory card <b>1200</b> may further include a ROM device for storing code data to interface with a host. The memory card <b>1200</b> may used as a portable data storage card. Alternatively, the memory card <b>1200</b> may be realized with a solid state disk (SSD) that may replace a hard disk of a computer system.

0113According to some embodiments of the inventive concept, a first metal layer is formed in an opening and then is wet-etched. A second metal pattern is selectively grown from the wet-etched first metal layer. If the first metal layer is etched by the wet etching, an etching impurity is applied to the sidewall of the opening, such that the second metal pattern is grown preferentially from the first metal layer rather than sidewalls of the opening. Accordingly, metal patterns having reduced defects may be formed in the opening. Additionally, the second metal pattern is selectively grown such that it is formed being separated from an adjacent second metal pattern. Therefore, two respectively adjacent second metal patterns may be formed in a manner that they remain insulated from each other. Accordingly, a semiconductor device having an improved reliability can be formed.

0114The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.