Optical network

CROSS-REFERENCE TO RELATED APPLICATIONS

0001This application is a continuation of PCT International Application No. PCT/US06/060577 filed Nov. 6, 2006 which claims the benefit of U.S. Provisional Patent Application Ser. Nos. 60/733,842, filed on Nov. 4, 2005, entitled “A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network” and 60/734,890, filed on Nov. 9, 2005, entitled “Utilizing Path Diversity in Optical Packet Switched Interconnection Networks,” which are hereby incorporated by reference in their entirety herein.

BACKGROUND OF THE INVENTION

00021. Technical Field

0003The disclosed subject matter relates to an optical network having one or more photonic switching nodes.

00042. Background Information

0005Contemporary high performance computing (HPC) systems typically use the distributed shared memory (DSM) paradigm, wherein the entire memory is logically shared among all the processors but may be physically implemented using memory modules distributed across many computing nodes. This approach simplifies programming, provides portability of software, and exhibits improved scalability over traditional shared memory systems. Large scale DSM systems, however, suffer from a fundamental communication problem that significantly affects scalability: increased latency of remote memory accesses. The remote access latency problem is becoming critically more pronounced with faster processor speeds as each memory access consumes a correspondingly larger number of clock cycles.

0006Interconnection networks with low latency and high bandwidth have therefore become an important component in the design of HPC systems. Cutting-edge electronic transmission technologies, such as Hyper-transport and PCI-Express, as well as high performance cross-point switching fabrics are currently used to construct such networks. However, a performance gap is beginning to emerge between the processors, whose performance scales quickly according to Moore's law, and the interconnecting medium which fails to advance at a commensurate rate due to fundamental physical limitations. Dynamic power consumption, wiring density, and signal distortion are fundamental impediments to the scaling of electronic interconnection networks. Additionally, transmission of signals at high data rates (e.g., in excess of 1 Gb/s) over long electronic transmission lines (e.g., longer than 1 m) results in signal distortion which makes decoding these signals difficult or requires great amounts of power, large chip area, and high cost to ensure correct detection. Sophisticated signal processing techniques, such as pre-emphasis and equalization, can mitigate these effects to some extent, but they add to the overall latency and are expensive both in power and area. An alternative approach is to use relatively short transmission lines and an indirect topology such as a mesh or a torus, based on low-radix routers, but this approach leads to further increases in the overall latency as each packet has to traverse a larger number of hops.

0007Photonic interconnection networks are a potentially transformative technology with the capability to overcome these limitations and provide commensurate performance scaling. The enormous bandwidth of optical fibers, approximately 32 THz, facilitates the transmission of multiple data streams on a single fiber at very high data-rates using wavelength division multiplexing (WDM). The low loss in fibers, nearly zero for the distances relevant to interconnection networks, alleviates the need for regeneration and effectively removes the signal transmission limitation. The photonic medium also allows for bidirectional transmission and switching of high-rate data using optical switching elements completely transparent to the modulated data, a property known as bit-rate transparency. Semiconductor optical amplifiers (SOAs) are used in several experimental optical packet switching systems as on-off photonic gates, providing a substantial gain over a wide switching band, and sub-ns switching times.

0008Photonic technology presents, however, some fundamental design challenges specifically in its lack of efficient buffering and processing capabilities. Although some promising technologies such as photonic crystals are being investigated and may prove useful in constructing photonic memories and logic gates, they have failed to reach commercialization thus far. Optical buffers based on recirculating fiber delay lines have been demonstrated as have interferometeric optical logic gates but their dimensions and “bulkiness” prohibit them from becoming cost-effective solutions.

0009An impediment to the construction of photonic interconnection networks lies in the high cost and large footprints associated with using discrete optical elements such as lasers, modulators, switches and passive optics. Photonic integration, the fabrication of circuits implementing multiple photonic functions in a single package, is promising to eliminate these final barriers. Since the elements comprising the prohibitive cost of optical networks mainly lie in the assembly and packaging of very large systems, and a significant share of the power consumption rises from coupling losses between individually packaged devices, integration of large parts of the network on a single photonic integrated circuit (PIC) alleviates these factors. Monolithic Indium-Phosphide PICs containing 50 photonic functions have been reported in scientific literature and are now commercially available. Additionally, silicon-based optical and electro-optical components such as modulators, photodetectors, and waveguides, all compatible with standard (CMOS) processing techniques have recently become available, promising an unprecedented potential for low cost electronic-optical interfacing.

0010When photonic integration is harnessed to construct interconnection networks, however, buffering becomes very difficult. The optical packet typically occupies a fixed length of a waveguiding medium which is the product of the speed of light in the medium and the duration of the packet. The size of optical packets known in the art occupy a certain amount of space, such that it is difficult, if not impossible, to fit on an integrated circuit. For example, a typical 100-ns packet will occupy 20 meters of silica fiber or 6 meters of a semiconductor waveguide. Consequently, buffering optical packets within a PIC is not currently practical.

0011Accordingly, there is a need in the art to provide a scalable interconnection network based on photonic integration that offers a bufferless means of contention resolution.

SUMMARY OF THE INVENTION

0012An optical network is disclosed comprising one or more photonic switching nodes, each of which, comprises a plurality of input ports; at least one output port; and a switch configured to route messages between the plurality of input ports and the at least one output port and provide bufferless resolution of contention between messages for a common output port.

0013In some embodiments, the switch selects a first message in the case where two or more messages contend for a common output port. In some embodiments, the switch drops a second message in the case where two or more messages contend for a common output port. In some embodiments, the switch selects said first message randomly, according to an alternating scheme, or according to priority information encoded in said messages.

0014In some embodiments, the optical network may further include a source terminal and a destination terminal, wherein the photonic switching nodes transmit a first message on a path from said source terminal to said destination terminal. The destination terminal may transmit an acknowledgment signal to the source terminal of a message upon receipt of said message at its requested output port. In some embodiments, the photonic switching nodes transmit said acknowledgement signal on said path from said destination terminal to said source terminal. The optical network may retransmit the message in the case where an acknowledgment signal is not received. In some embodiments, the optical network retransmits the message in the case where an acknowledgment signal is not received prior to the end of a slot.

0015In some embodiments, the switch comprises a programmable logic device. The photonic switching nodes may be interconnected in a Banyan topology. The photonic switching nodes may be interconnected in an Omega topology.

0016In some embodiments, the message comprises routing information at a first wavelength and data at a second wavelength. The switch may comprise wavelength filters associated with said first wavelength and said second wavelength.

0017In some embodiments, the optical network may comprise one or more scattering nodes. The one or more photonic switching nodes and one or more scattering nodes may transmit the first message on a path from the source terminal to the destination terminal. The destination terminal may transmit an acknowledgment signal to the source terminal of a message upon receipt of the message at its requested output port. The one or more photonic switching nodes and one or more scattering nodes may pass said acknowledgement signal on said path from said destination terminal to said source terminal.

0018The optical network may further include a distribution network comprising one or more distribution stages for routing messages comprising a distribution address. The source terminal changes the distribution address of a message prior to retransmission. In some embodiments, transmission in the optical network is synchronous. In some embodiments, the optical network is slotted.

0019A method is provided for transmitting messages through an optical network. A network comprising one or more photonic switching nodes for transmitting messages therethrough is provided. One or more messages is received at one or more input ports of a photonic switching node, each message comprising routing information relating to a requested output port. In the case of two or more messages contending for a common output port, bufferless contention resolution of contention between messages for a common output port is provided. The messages are transmitted through the network.

BRIEF DESCRIPTION OF THE DRAWINGS

0020Further features and advantages of the disclosed subject matter will become apparent from the following detailed description taken in conjunction with the accompanying figures showing illustrative embodiments of the disclosed subject matter, in which:

0021<figref idref="DRAWINGS">FIG. 1</figref> is a diagram representing a network of switching nodes in accordance with an exemplary embodiment of the disclosed subject matter.

0022<figref idref="DRAWINGS">FIG. 2</figref> is a diagram representing a switching node in accordance with an exemplary embodiment of the disclosed subject matter.

0023<figref idref="DRAWINGS">FIGS. 3A to 3F</figref> are diagrams representing switching states of a switching node in accordance with an exemplary embodiment of the disclosed subject matter.

0024<figref idref="DRAWINGS">FIG. 4</figref> is a diagram representing a message transmitted through the network in accordance with an exemplary embodiment of the disclosed subject matter.

0025<figref idref="DRAWINGS">FIG. 5</figref> is a diagram representing a message dropped by a switch in the network in accordance with an exemplary embodiment of the disclosed subject matter.

0026<figref idref="DRAWINGS">FIG. 6</figref> is a diagram representing the wavelength distribution of a message in accordance with an exemplary embodiment of the disclosed subject matter.

0027<figref idref="DRAWINGS">FIG. 7</figref> is a diagram representing a node in the network in accordance with an exemplary embodiment of the disclosed subject matter.

0028<figref idref="DRAWINGS">FIG. 8</figref> is a diagram representing a switching network in accordance with another embodiment of the disclosed subject matter.

0029<figref idref="DRAWINGS">FIGS. 9-10</figref> are diagrams representing nodes in a network illustrated in <figref idref="DRAWINGS">FIG. 8</figref> in accordance with an exemplary embodiment of the disclosed subject matter.

0030<figref idref="DRAWINGS">FIG. 11</figref> is a diagram representing a switching network in accordance with an exemplary embodiment of the disclosed subject matter.

0031<figref idref="DRAWINGS">FIG. 12</figref> is a diagram representing a switching network in accordance with an exemplary embodiment of the disclosed subject matter.

0032<figref idref="DRAWINGS">FIG. 13</figref> is a diagram representing a switching network in accordance with an exemplary embodiment of the disclosed subject matter.

0033Throughout the figures, the same reference numerals and characters are used to denote like features, elements, components or portions of the illustrated embodiments, unless otherwise stated.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

0034In an exemplary embodiment of a scalable photonic integrated network, port-to-port optical packets (messages) can be self-routed through an optical multistage interconnection network. The network may be constructed from 2×2 photonic switching nodes, while the payload is maintained in the optical domain across the network. The messages may be constructed in a manner according to wavelength division multiplexing to achieve high bandwidth and simplify the node design.

0035<figref idref="DRAWINGS">FIG. 1</figref> illustrates a scalable photonic integrated network <b>100</b>. In an exemplary embodiment, the network is a binary butterfly-class multistage interconnection network, comprised of 2×2 photonic wideband switching nodes <b>10</b>. <figref idref="DRAWINGS">FIG. 1</figref> shows a scalable photonic integrated network <b>100</b> implemented in an Omega topology, but the specific topology can encompass other implementations, such as Banyan, Butterfly, 4-cube, and Baseline.

0036The system shown in <figref idref="DRAWINGS">FIG. 1</figref> may be synchronous and slotted. The messages are constructed in the source terminals <b>110</b> and are transmitted on optical fibers or optical waveguides <b>114</b> into the network <b>100</b>.

0037For a slot, messages start propagating substantially simultaneously in the network <b>100</b>. According to an exemplary embodiment, messages may be self-routed. Such messages include information regarding an intended destination terminal. The intended destination terminal may or may not be the message's ultimate destination. At a switching node <b>10</b>, when a leading edge of a message is received, a routing decision is made, and the message continues to propagate to its requested output port <b>14</b>. Output port contention may occur, for example, when two messages arrive at a node and request the same output port. In such case, one of the contending messages is transmitted, and one (or more) contending messages is dropped. The choice of which message to drop may be, for example, random, alternating or priority-based. For example, in a priority-based scheme, priority information may be encoded on a specific wavelength in the message. The switching node may decode such information and use it to make the routing decision so that the message with the higher priority is transmitted and the message with the lower priority is dropped. In an exemplary embodiment, the propagation delay through every stage may be substantially identical, such that the leading edges of the transmitted messages reach all the nodes <b>10</b> of each stage at the same time.

0038<figref idref="DRAWINGS">FIG. 2</figref> illustrates a 2×2 photonic wideband switching node <b>10</b> with input ports <b>12</b> and output ports <b>14</b>. A switch path <b>16</b> is established between an input port <b>12</b> and an output port <b>14</b>.

0039<figref idref="DRAWINGS">FIGS. 3A to 3F</figref> illustrate the 6 states of a switching node <b>10</b>. <figref idref="DRAWINGS">FIG. 3A</figref> illustrates an interchange state <b>20</b> in which an upper-to-lower switch path <b>16</b><i>a </i>is established between the upper input port <b>12</b><i>a </i>and the lower output port <b>14</b><i>b </i>and a lower-to-upper switch path <b>16</b><i>b </i>is established between the lower input port <b>12</b><i>b </i>and the upper output port <b>14</b><i>a</i>. <figref idref="DRAWINGS">FIG. 3B</figref> illustrates a straight state <b>22</b> in which an upper straight switch path <b>16</b><i>c </i>is established between the upper input port <b>12</b><i>a </i>and the upper output port <b>14</b><i>a </i>and a lower straight switch path <b>16</b><i>d </i>is established between the lower input port <b>12</b><i>b </i>and the lower output port <b>14</b><i>b</i>. <figref idref="DRAWINGS">FIG. 3C</figref> illustrates an upper straight state <b>24</b> in which only an upper straight switch path <b>16</b><i>c </i>is established between the upper input port <b>12</b><i>a </i>and the upper output port <b>14</b><i>a</i>. <figref idref="DRAWINGS">FIG. 3D</figref> illustrates an upper exchange state <b>26</b> in which only an upper-to-lower switch path <b>16</b><i>a </i>is established between the upper input port <b>12</b><i>a </i>and the lower output port <b>14</b><i>b</i>. <figref idref="DRAWINGS">FIG. 3E</figref> illustrates a lower straight state <b>28</b> in which only a lower straight switch path <b>16</b><i>d </i>is established between the lower input port <b>12</b><i>b </i>and the lower output port <b>14</b><i>b</i>. <figref idref="DRAWINGS">FIG. 3F</figref> illustrates a lower exchange state <b>30</b> in which only a lower-to-upper switch path <b>16</b><i>b </i>is established between the lower input port <b>12</b><i>b </i>and the upper output port <b>14</b><i>a</i>. As will be understood by one of ordinary skill in the art, additional and/or different states may be provided for nodes having a different number of input or output ports. Further, the terms “upper” and “lower” as used in <figref idref="DRAWINGS">FIGS. 3A-3F</figref> to describe input and output ports are used for convenience of description only, and will generally be understood to refer to a “first” and a “second” port.

0040<figref idref="DRAWINGS">FIG. 4</figref> illustrates that the switching states (e.g., states <b>20</b>-<b>30</b> illustrated in <figref idref="DRAWINGS">FIGS. 3A-3F</figref>) of the switching nodes <b>10</b>, as determined by leading edges, remain constant throughout the duration of the message, e.g., throughout a slot, so the entire message follows each switch path <b>16</b> acquired by the leading edge, effectively creating a transparent lightpath <b>200</b> between the source terminal <b>110</b> and destination terminal <b>112</b>. When the messages reach their destinations, an acknowledgement optical pulse (“ack pulse”) is generated at the destination terminal and sent on the same transparent lightpath <b>200</b> in the opposite direction. Owing to the bidirectionality of the switching nodes <b>10</b>, the acknowledgement pulses are transmitted along the lightpath <b>200</b> to the appropriate source terminals <b>110</b>.

0041When the slot time is over, all source terminals <b>110</b> and destination terminals <b>112</b> may cease transmission simultaneously, the switching nodes <b>10</b> reset their switching states <b>20</b>-<b>30</b>, and the system is ready for a new slot. The slot duration may be set so that the ack pulses are received at the source terminal <b>110</b> before the slot ends, allowing every source terminal <b>110</b> to determine whether its message was successfully transmitted and make a timely decision regarding its retransmission in the case that the message was dropped. This physical-layer acknowledgement mechanism allows the source terminals <b>110</b> to regard the dropped messages as blocked messages and avoid the penalty associated with packet recovery at higher layers.

0042<figref idref="DRAWINGS">FIG. 5</figref> illustrates a condition in which two messages contend for the same output port <b>14</b><i>a </i>of node <b>10</b><i>a</i>. The message originating from source terminal (<b>0</b>) <b>110</b><i>a</i>, traveling on lightpath <b>200</b><i>a</i>, is transmitted to destination terminal <b>112</b><i>a</i>. The message originating from source terminal (<b>6</b>) <b>110</b><i>b</i>, traveling on lightpath <b>200</b><i>b</i>, is dropped. Destination terminal (<b>0</b>) <b>112</b><i>a </i>transmits an acknowledgement signal on lightpath <b>200</b><i>a </i>to source terminal (<b>0</b>) <b>110</b><i>a</i>. Source terminal (<b>6</b>) <b>110</b><i>b </i>receives no acknowledgement signal and prepares to retransmit its message.

0043According to an exemplary embodiment, the wavelength domain is used to facilitate a routing mechanism in the switching nodes <b>10</b> that can instantaneously determine and execute the routing decision upon receiving the messages' leading edges, and maintain a constant switching state <b>20</b>-<b>30</b> throughout duration of the messages. As shown in <figref idref="DRAWINGS">FIG. 6</figref>, the messages <b>300</b> are constructed in a wavelength-parallel manner, i.e., the routing header bits <b>310</b> and the payload <b>320</b> may be encoded on separate wavelengths and are received substantially concurrently by the switching nodes <b>10</b>. The header bits <b>310</b> comprise a frame bit <b>312</b>, denoting the existence of the message, and a destination address tag <b>314</b>, which is comprised of address bits <b>316</b>. Each of the header bits, encoded on a dedicated wavelength, remains constant throughout the message. According to an exemplary embodiment, a single address bit <b>316</b> is processed at every stage, so the number of wavelengths required for address encoding is log₂of the number of output ports. Segmenting the payload <b>320</b> and encoding on multiple wavelengths utilize the large bandwidth offered by wavelength division multiplexing.

0044Butterfly networks may be used in the scalable photonic integrated network <b>100</b> because their binary nature facilitates the usage of destination tag routing and simple decision rules that are desirable for ultra-low latency optical switching. When messages originating from different input ports may contend for the same output ports, the process of implicit arbitration through self-routing also eliminates the need for a central arbitration mechanism thus allowing the system to scale to large port-counts. However, these blocking networks will have a lower throughput than non-blocking networks, in which a disjoint path exists between each pair of input/output terminals. Contention avoidance techniques and topological modifications as well as input speedup can be utilized to increase the message acceptance rate.

0045According to an exemplary embodiment, a large number of switching nodes <b>10</b> may be implemented on a single PIC. Commercially available optoelectronic elements such as semiconductor optical amplifier (SOA) gates and photodetectors may be used. For example, SOAs offer the uniform gain curve, sub-ns switching time and low latency required from electronically controlled optical switching gates in a switching node <b>10</b>.

0046<figref idref="DRAWINGS">FIG. 7</figref> illustrates one exemplary embodiment of the switching node. Switching node <b>10</b> includes a switch which routes messages received at input ports <b>12</b><i>a </i>and/or <b>12</b><i>b </i>to output ports <b>14</b><i>a </i>and <b>14</b><i>b</i>. Further, the switch selects a message for transmission to its requested output port as will be described in greater detail below. The switch may be comprised of semiconductor optical amplifier gates (SOAs) <b>502</b>, optical couplers <b>400</b> and <b>402</b>, wavelength filters <b>404</b> and <b>406</b>, p-i-n receivers <b>504</b>, optical fibers <b>410</b>, and a programmable logic device <b>506</b>. These elements may be connected together using optical fiber or waveguides <b>410</b>, depending on the implementation. Any of these elements may be substituted with other elements or rearranged as is known to one of skill in the art. When messages enter the switching node <b>10</b> at input ports <b>12</b><i>a </i>and/or <b>12</b><i>b</i>, the relevant header bits <b>310</b> (frame bit <b>312</b>, denoting message existence, and a relevant address bit <b>316</b>) are optically extracted from both messages using frame wavelength filters <b>404</b> and address wavelength filters <b>406</b>, detected, and forwarded to an electronic control circuit <b>506</b>. The control circuit <b>506</b>, e.g., a Xilinx complex programmable logic device (CPLD) in the exemplary embodiment, makes the routing decision and activates the appropriate SOAs (or SOA) <b>502</b> to create the required input-output path. The messages, delayed on optical fibers <b>410</b>, reach the SOAs <b>502</b> exactly when they are activated and are routed appropriately. The routing decision as to whether to transmit contending messages is determined by the control circuit <b>506</b>.

0047Topological modifications in the network can be used to increase the acceptance rate. <figref idref="DRAWINGS">FIG. 8</figref> illustrates another exemplary embodiment of a network, which is substantially identical to network <b>100</b>, with the relevant differences noted herein. Network <b>600</b> may include one or more scattering nodes <b>602</b>, which have an input port <b>12</b> and an output port <b>14</b>, as illustrated in <figref idref="DRAWINGS">FIG. 9</figref>. The Enhanced Omega <b>600</b> network shown in <figref idref="DRAWINGS">FIG. 8</figref> mitigates internal contentions by adding scattering stages <b>610</b> before the routing stages <b>620</b>. Scattering stages <b>610</b> are formed by the insertion of scattering nodes <b>602</b> before the Omega switching nodes <b>620</b>. The scattering nodes <b>602</b> identify messages that will contend for the same output port in the subsequent switching stage and scatter them to different switching nodes. Scattering nodes misroute contending messages rather then drop them, letting the subsequent switching node route them correctly. By adding additional possible routes, the addition of scattering nodes allows more messages to be successfully transmitted, and fewer messages dropped.

0048<figref idref="DRAWINGS">FIG. 10</figref> illustrates how the connection patterns between the scattering stage <b>610</b> and the routing stage <b>620</b> complete the scattering action while ensuring that even misrouted messages reach their original destinations. Messages are only scattered between switching nodes <b>10</b> that lead to the same part of the network in subsequent stages.

0049The scattering nodes <b>602</b> cannot be placed before the last stage of the Omega network <b>600</b>, because in this stage scattering will cause routing errors. Therefore, a maximum of N_S−1 scattering stages can be added to a network of N_Srouting stages, increasing its number of stages to 2N_S−1.

0050According to another exemplary embodiment, a network of scattering nodes may be inserted before a routing network to serve as a distribution network. A distribution network routes messages to different input ports of a routing network in a manner that minimizes contentions. Additional address bits carry the distribution address, which determines the path taken through the distribution network. The routing network follows the distribution network to ensure correct routing functionality is intact.

0051The exemplary embodiment may provide several advantages. First, a random route may be chosen in the distribution network by encoding a random distribution address, balancing the load on the routing network regardless of the real traffic pattern. Second, exploiting the physical layer acknowledgement protocol and path diversity, path adjustment may be made by changing the distribution address if the message is dropped in the first attempt. These path adjustments may be made in several iterations within the same timeslot, during the guardband that precedes the payload transmission. Each iteration takes as long as the sum of the roundtrip time across the network and the response time of the acknowledgment generation modules, so the number of iterations may be a design parameter balancing the added utilization gained from multiple iterations and time that can be allocated to path adjustments.

0052<figref idref="DRAWINGS">FIGS. 11-13</figref> illustrate the advantages of a distribution network in accordance with an exemplary embodiment. In <figref idref="DRAWINGS">FIGS. 11-13</figref>, four messages are transmitted: messages <b>300</b><i>a </i>(from source terminal <b>110</b><i>a </i>to destination terminal <b>112</b><i>a</i>), <b>300</b><i>b </i>(<b>110</b><i>b </i>to <b>112</b><i>b</i>), <b>300</b><i>c </i>(<b>110</b><i>c </i>to <b>112</b><i>c</i>), and <b>300</b><i>d </i>(from <b>110</b><i>d </i>to <b>112</b><i>d</i>). <figref idref="DRAWINGS">FIG. 11</figref> illustrates two messages <b>300</b><i>c </i>and <b>300</b><i>d </i>are dropped due to internal path contentions in an Omega network <b>100</b>. <figref idref="DRAWINGS">FIG. 12</figref> illustrates one embodiment of a network that comprises a distribution network <b>700</b>. By adding a distribution network <b>700</b> and routing the messages <b>300</b> through it according to a random distribution of addresses, message <b>300</b><i>d </i>takes a different path <b>200</b><i>d </i>and is transmitted successfully. Message <b>300</b><i>c </i>is still dropped, so when the acknowledgment pulse does not arrive on time, source terminal <b>110</b><i>c </i>encodes a new distribution address on message <b>300</b><i>c</i>. <figref idref="DRAWINGS">FIG. 13</figref> illustrates how a new distribution address forces message <b>300</b><i>c </i>to take a different path <b>200</b><i>c </i>at node <b>602</b><i>a </i>that resolves the contention. In this manner, the path adjustment technique may use the ultra-low latency of the integrated interconnection network and the distributed computing power of the switching nodes, to increase the network utilization by resolving contentions in the space domain.

0053The acceptance rate of the path-diversified scalable photonic network has been investigated on a representative 64×64 Omega network with a distribution network. Simulations were run using Bernoulli iid traffic with a varying p parameter (offered load). In the first performance study, the immunity for adversarial traffic patterns was shown by simulating bit-reversal traffic patterns, chosen as adversarial patterns for the Omega network. As expected, adding distribution stages increased the path diversity and performance, but with a diminishing rate.

0054The effect of the path adjustments was investigated in a network simulated with 0 to 4 path adjustment iterations, under uniform traffic. The performance improvement was substantial, effectively pushing the performance curve closer to the upper boundary represented by a non-blocking network (that would require 4096 switching nodes). The performance improvement beyond two iterations diminished so that two iterations seem to be a good trade-off point, considering the time limitation.

0055Whereas a non-distribution network switching node may include a gate array as the logic circuit, the node in a distribution network, such as network <b>700</b>, toggles between several states to avoid interference between messages whose paths are being adjusted and messages that are already successfully routed, i.e., the switching nodes ensure that messages whose transmission has begun will not suffer from interference from messages whose paths are being adjusted. According to an exemplary embodiment, nodes in a distribution network may be implemented as state machines that encode three states for path protection: idle, bar, and cross. When no message is routed through the node, it is in the “idle” path-protection state. When one or more messages is routed through an “idle” node, its path-protection state changes from “idle” to either “cross” or “bar,” according to the selected switching state encoded on a message. For example, if interchange switching state <b>20</b> is selected, then the node's path-protection state will change to “cross,” and if straight switching state <b>22</b> is selected, the node's path-protection state will change to “bar.” When the node is in the “cross” or “bar” path-protection state (i.e. currently handling a message) and a subsequent message is received (e.g., after has its path has been adjusted), the subsequent message will be passed only if its requested output port matches the current path-protection state (i.e. does not require a state change). If the new message requires a state change, it will be dropped. Once a node is in the “cross” or “bar” path-protection state, it may remain in that state until the message that triggered the state is over. During that time, the node may route messages that are not contending with the original message, while messages that are contending are blocked or dropped. When the slot is over and all messages have been transmitted, the node switches back to the “idle” state and is ready to receive new messages. Error-free transmission of 16×10 Gb/s wavelength-parallel messages has been confirmed for a switching node with three path-protection states.

0056The average bandwidth routed by a scalable photonic integrated network can be calculated from simulation results. For example, a 64-port Enhanced Omega network, operated at 0.8 offered load, may attain 0.52 acceptance rate. The normalized throughput is therefore 0.8·0.52=0.42. Operation with a 160 Gb/s wavelength-parallel payload (16×10 Gb/s) yields an average throughput of 67 Gb/s per port and 4.26 Tb/s system total average throughput.

0057The functionality of the switching node and scalable photonic integrated network have been experimentally verified using an optical testbed. Wavelength-parallel messages, consisting of 16 wavelengths modulated at 10 Gb/s, were constructed to create a total payload bandwidth of 160 Gb/s. The payload wavelengths spanned across 29 nm in the C-band, with a minimum spacing of 0.8 nm between adjacent channels, to show that more payload wavelengths could be straightforwardly added to increase the system's bandwidth. The messages were 97.6 ns long, spaced by a 4.8 ns dead time. Once constructed, the messages were multiplexed with the appropriate header wavelengths and injected into the experimental switching node through both input ports. At the node output ports correct routing was verified using an oscilloscope and bit error rate (BER) measurements were conducted on each wavelength individually. Ack pulses (9.6 ns long) were modulated externally on a dedicated wavelength and were injected into the output ports when messages are received. Full routing functionality of all nine possible input combinations (no-packet, packet-to-out0, packet-to-out1 per input port) has been verified in one experiment.

0058Error-free routing of the messages has been verified and a BER of 10⁻¹²or better has been confirmed on all 16 payload wavelengths. It has been shown for SOA-based multi-hop networks that after 58 hops, a 10⁻⁹bit error rate can still be maintained for 8 wavelengths, spanned across a functional bandwidth of 24.2 nm. As even large scalable photonic integrated networks are expected to have a significantly lower number of stages, (N_Sv log₂N), a larger functional bandwidth can be attained.

0059It will be understood that the foregoing is only illustrative of the principles of the disclosed subject matter, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the disclosed subject matter as defined by the appended claims. Exemplary embodiments may be combined with other exemplary embodiments or modified to create new embodiments.