Photoelectric conversion apparatus, imaging system, and photoelectric conversion apparatus manufacturing method

CROSS REFERENCE TO RELATED APPLICATIONS

0001The present application is a continuation of U.S. patent application Ser. No. 12/496,114, filed Jul. 1, 2009, now U.S. Pat. No. 8,084,729, and claims the benefit of the filing date of that application, and priority benefit of the filing date of Japan Patent Application No. 2008-179468, filed Jul. 9, 2008. The entire disclosure of each of the prior applications mentioned above is incorporated by reference, as if fully set forth herein.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a photoelectric conversion apparatus, imaging system, and photoelectric conversion apparatus manufacturing method.

00042. Description of the Related Art

0005Photoelectric conversion apparatuses are roughly divided into a CCD (Charge Coupled Device) sensor and a CMOS (Complementary MOS) sensor. Early CMOS sensors generated large noise and were poorer in image quality than CCD sensors. However, today's advanced noise reduction technology allows CMOS sensors to attain image qualities equivalent to those of CCD sensors.

0006Japanese Patent Laid-Open No. 2004-153682 achieves high readout speeds by arranging two pairs of optical signal output lines (to be referred to as S output lines hereinafter) and noise signal output lines (to be referred to as N output lines hereinafter), and arranging two S/N readout circuits for amplifying and reading out difference signals from the two output lines. These output lines are arranged in order of the first S output line, first N output line, second N output line, and second S output line. This arrangement order makes the first S output line spaced apart from the second S and N output lines, reducing the coupling capacitance formed between the first S output line and the second S and N output lines. Similarly, the order makes the second S output line spaced apart from the first S and N output lines, decreasing the coupling capacitance formed between the second S output line and the first S and N output lines. The technique disclosed in Japanese Patent Laid-Open No. 2004-153682 can reduce crosstalk arising from capacitive coupling between two pairs of S output lines and N output lines.

0007Japanese Patent Laid-Open No. 11-330444 discloses a technique of forming a dummy pattern in a predetermined non-filter region except the array of color filters. The technique disclosed in Japanese Patent Laid-Open No. 11-330444 can assure the flatness of a planarization layer on the color filters to prevent defocusing and an image blur, and avoid degradation of the image quality caused by ambient scattered light. The technique can therefore improve the image quality of an image obtained by a CMOS sensor.

0008According to the technique disclosed in Japanese Patent Laid-Open No. 11-330444, a dummy pattern is formed of the same substance as a color filter to ensure the flatness of a planarization layer on the color filter. It is estimated that the dummy pattern is arranged in a large region except the pixel array region.

0009It is also estimated that, if the technique of Japanese Patent Laid-Open No. 11-330444 is applied to that of Japanese Patent Laid-Open No. 2004-153682, a dummy pattern is arranged even on two pairs of N output lines and S output lines. In this case, the dummy pattern raises the dielectric constant between output lines, compared to a case in which no dummy pattern for a color filter is formed on a plurality of output lines. The high dielectric constant between output lines owing to the dummy pattern increases the coupling capacitance between them. The coupling capacitance between the output lines may increase crosstalk.

0010As the distance between output lines is shortened at a high dielectric constant between them for reduction of the chip size, the coupling capacitance becomes larger in accordance with the shorter distance between them. This hinders shortening the distance between output lines by a predetermined amount or more, failing to downsize the chip.

SUMMARY OF THE INVENTION

0011The present invention provides for reducing crosstalk between output lines.

0012According to the first aspect of the present invention, there is provided a photoelectric conversion apparatus having a pixel array region and a peripheral region positioned at a periphery of the pixel array region, the apparatus comprising: a pixel array which is arranged in the pixel array region and has a plurality of pixels arrayed; a readout unit which is arranged in the peripheral region to read out a signal from the pixel array; an output unit which is arranged in the peripheral region; a plurality of output lines which are arranged in the peripheral region to transfer signals from the readout unit to the output unit; and a color filter layer which is arranged in the pixel array region and the peripheral region and includes a color filter arranged above the plurality of pixels, wherein the color filter layer extends to surround the plurality of output lines when viewed from above the plurality of output lines, and has an opening arranged above the plurality of output lines, and the opening of the color filter layer is filled with either of gas and an insulator lower in dielectric constant than the color filter.

0013According to the second aspect of the present invention, there is provided an imaging system comprising: a photoelectric conversion apparatus according to the first aspect of the present invention; an optical system which guides light to a pixel array of the photoelectric conversion apparatus; and a signal processing unit which processes a signal output from the photoelectric conversion apparatus to generate image data.

0014According to the third aspect of the present invention, there is provided a method of manufacturing a photoelectric conversion apparatus having a pixel array region and a peripheral region positioned at a periphery of the pixel array region, the method comprising steps of: forming, in the pixel array region, a pixel array having a plurality of pixels arrayed, and forming, in the peripheral region, a readout unit which reads out a signal from the pixel array, an output unit, and a plurality of output lines which transfer signals transferred from the readout unit to the output unit; forming a first resin layer including a color filter in the pixel array region and the peripheral region; forming a second resin layer on the first resin layer in the pixel array region and the peripheral region; planarizing an upper face of the second resin layer; and removing portions of the first resin layer and second resin layer that are positioned above the plurality of output lines, thereby forming openings in the first resin layer and the second resin layer, wherein the openings of the first resin layer and the second resin layer are filled with either of gas and an insulator lower in dielectric constant than the color filter.

0015The present invention can reduce crosstalk between output lines.

0016Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0017<figref idref="DRAWINGS">FIG. 1</figref> is a diagram of the arrangement of a photoelectric conversion apparatus <b>100</b> according to the first embodiment of the present invention;

0018<figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram showing the structure of a pixel in the photoelectric conversion apparatus <b>100</b>;

0019<figref idref="DRAWINGS">FIG. 3</figref> is a plan view showing the structure of a color filter layer in the photoelectric conversion apparatus <b>100</b>;

0020<figref idref="DRAWINGS">FIG. 4</figref> is a schematic sectional view taken along a line A-A′ in <figref idref="DRAWINGS">FIG. 3</figref>;

0021<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are equivalent circuit diagrams showing the relationship between the output line and the capacitance in <figref idref="DRAWINGS">FIG. 1</figref>;

0022<figref idref="DRAWINGS">FIG. 6</figref> is a schematic sectional view of a region surrounded by a dotted frame B in <figref idref="DRAWINGS">FIG. 1</figref>;

0023<figref idref="DRAWINGS">FIG. 7</figref> is a sectional view of the structure of a photoelectric conversion apparatus according to a modification to the first embodiment of the present invention;

0024<figref idref="DRAWINGS">FIG. 8</figref> is a sectional view of the structure of a photoelectric conversion apparatus according to another modification to the first embodiment of the present invention;

0025<figref idref="DRAWINGS">FIG. 9</figref> is a block diagram showing the configuration of an imaging system to which the photoelectric conversion apparatus according to the first embodiment is applied; and

0026<figref idref="DRAWINGS">FIG. 10</figref> is a sectional view of the structure of a photoelectric conversion apparatus according to the second embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

0027The arrangement of a photoelectric conversion apparatus <b>100</b> according to the first embodiment of the present invention will be described with reference to <figref idref="DRAWINGS">FIGS. 1 to 3</figref>. <figref idref="DRAWINGS">FIG. 1</figref> is a diagram of the arrangement of the photoelectric conversion apparatus <b>100</b> according to the first embodiment of the present invention. <figref idref="DRAWINGS">FIG. 2</figref> is a circuit diagram showing the structure of a pixel in the photoelectric conversion apparatus <b>100</b>. <figref idref="DRAWINGS">FIG. 3</figref> is a plan view showing the structure of a color filter layer in the photoelectric conversion apparatus <b>100</b>.

0028The photoelectric conversion apparatus <b>100</b> includes a pixel array region IA and peripheral region PR. The pixel array region IA is, for example, a region where an object image is formed and sensed. The peripheral region PR is positioned at the periphery of the pixel array region IA.

0029A pixel array PA is arranged in the pixel array region IA. The peripheral region PR includes a vertical scanning circuit <b>120</b>, readout circuit (readout unit) <b>130</b>, horizontal scanning circuit <b>140</b>, output line group (a plurality of output lines) <b>160</b>, and output unit <b>150</b>. A color filter layer <b>310</b> (see <figref idref="DRAWINGS">FIGS. 3 and 4</figref>) is arranged in the pixel array region IA and peripheral region PR.

0030In the pixel array PA, a plurality of pixels <b>110</b> are arrayed two-dimensionally (directions along a row and a column). As shown in <figref idref="DRAWINGS">FIG. 2</figref>, each pixel <b>110</b> includes a reset transistor <b>25</b>, photoelectric conversion unit <b>27</b>, transfer gate <b>9</b>, floating diffusion (to be referred to as an FD hereinafter) <b>7</b>, and amplification transistor <b>29</b>. The reset transistor <b>25</b> resets the FD <b>7</b>. The photoelectric conversion unit <b>27</b> generates charges (signal) corresponding to incident light by photoelectric conversion, and accumulates them. The photoelectric conversion unit <b>27</b> is, for example, a photodiode. The transfer gate <b>9</b> transfers charges (signal) accumulated in the photoelectric conversion unit <b>27</b> to the FD <b>7</b>. The FD <b>7</b> converts the transferred charges (signal) into a voltage (signal). The amplification transistor <b>29</b> amplifies a signal input from the FD <b>7</b> and outputs the amplified signal to a column signal line RL. The amplification transistor <b>29</b> outputs a noise signal to the column signal line RL while the FD <b>7</b> has been reset. The amplification transistor <b>29</b> outputs an optical signal to the column signal line RL while the charges have been transferred from the photoelectric conversion unit <b>27</b> to the FD <b>7</b>.

0031Note that the noise signal is output from a pixel while the FD <b>7</b> has been reset, so it can also be referred to as a reset signal. The noise signal can be a reference signal for the optical signal such as a signal including an offset of a readout path.

0032The vertical scanning circuit <b>120</b> scans the pixel array PA vertically to select the pixels <b>110</b> of each row. Upon receiving control signals VD and VCLK, the vertical scanning circuit <b>120</b> supplies the pixel array PA with a signal for selecting the pixel <b>110</b> and a signal for driving it.

0033The readout circuit <b>130</b> reads out a signal from the pixel array PA. The readout circuit <b>130</b> includes a readout switch, holding capacitances Cts and Ctn, and a horizontal transfer switch for every column of the pixel array PA. The holding capacitance Cts receives an optical signal output via the column signal line RL and readout switch from the pixel <b>110</b> selected by the vertical scanning circuit <b>120</b>, and holds it. The holding capacitance Ctn receives a noise signal output via the column signal line RL and readout switch from the pixel <b>110</b> selected by the vertical scanning circuit <b>120</b>, and holds it. A horizontal transfer switch <b>250</b> connects/disconnects the holding capacitances Cts and Ctn to/from the output line group <b>160</b>. In the connected state, the horizontal transfer switch <b>250</b> transfers signals held in the holding capacitances Cts and Ctn to the output line group <b>160</b>.

0034The readout circuit <b>130</b> functions as a memory for temporarily accumulating signals of one row, so it can also be referred to as a line memory.

0035The horizontal scanning circuit <b>140</b> scans the readout circuit <b>130</b> horizontally to sequentially transfer optical signals held in the holding capacitances Cts of two columns to the output line group <b>160</b>. Also, the horizontal scanning circuit <b>140</b> sequentially transfers noise signals held in the holding capacitances Ctn of two columns to the output line group <b>160</b>. Upon receiving control signals HD and HCLK, the horizontal scanning circuit <b>140</b> supplies the readout circuit <b>130</b> with a control signal for transferring signals held in the holding capacitances Cts and Ctn of every two columns to the output line group <b>160</b>.

0036The output line group <b>160</b> transfers optical and noise signals of two columns received from the readout circuit <b>130</b> to the output unit <b>150</b>.

0037The output line group <b>160</b> includes a plurality of first output lines and a plurality of second output lines. The first output line transfers an optical signal (first signal) output from the readout circuit <b>130</b>. The second output line transfers a noise signal (second signal) output from the readout circuit <b>130</b>. More specifically, as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the output line group <b>160</b> includes a first S output line (first output line) <b>170</b><i>a</i>, first N output line (second output line) <b>170</b><i>b</i>, second S output line (first output line) <b>170</b><i>d</i>, and second N output line (second output line) <b>170</b><i>c. </i>The first S output line <b>170</b><i>a </i>and first N output line <b>170</b><i>b </i>are paired while the second S output line <b>170</b><i>d </i>and second N output line <b>170</b><i>c </i>are paired.

0038The output unit <b>150</b> includes a plurality of differential amplifiers (differential circuits) <b>150</b><i>a </i>and <b>150</b><i>b. </i>The differential amplifiers <b>150</b><i>a </i>and <b>150</b><i>b </i>generate difference signals between optical signals and noise signals respectively transferred via the pairs of first and second output lines. The differential amplifiers <b>150</b><i>a </i>and <b>150</b><i>b </i>output the generated difference signals via output terminals <b>180</b><i>a </i>and <b>180</b><i>b. </i>It should be noted that each of the differential amplifiers <b>150</b><i>a </i>and <b>150</b><i>b </i>can amplify the optical signal and noise signal respectively so that the following stage (e.g. the sensed signal processing circuit <b>95</b>) can generate the difference signal between the optical signal and noise signal.

0039As shown in <figref idref="DRAWINGS">FIG. 3</figref>, the color filter layer <b>310</b> includes a plurality of color filters above the pixels <b>110</b>. Each of the color filters selectively transmits light of a predetermined wavelength (e.g., R G, or B wavelength) in a visible region so that the light of the predetermined wavelength enters a pixel. The color filter layer <b>310</b> extends from a pixel array region IA to the peripheral region PR. The color filter layer <b>310</b> has an opening <b>310</b><i>a </i>above the output line group <b>160</b> (in an output line formation region <b>401</b>). The color filter layer <b>310</b> is formed to cover the entire region except the output line formation region <b>401</b>. In other words, the color filter layer <b>310</b> extends to surround the output lines <b>170</b><i>a </i>to <b>170</b><i>d </i>when viewed from a direction perpendicular to a surface SBa of a semiconductor substrate SB (when viewed from above the output lines <b>170</b><i>a </i>to <b>170</b><i>d</i>) and has the opening <b>310</b><i>a </i>above the output lines <b>170</b><i>a </i>to <b>170</b><i>d. </i>With this structure, it is easy to ensure the flatness of upper face of the color filter layer <b>310</b>.

0040Note that the color filter layer may include a single-layered color filter (i.e. a single panel) of a single color. Whether the color filter includes the plurality of color filters or the single-layered color filter is arbitrarily settable. The color filter layer may also be removed from an end of the output line formation region <b>401</b> on the side of the pixel array region IA. In other words, the opening <b>310</b><i>a </i>may extend near the side of the pixel array region IA.

0041The relationship between the crosstalk amount and coupling capacitance between output lines will be explained with reference to <figref idref="DRAWINGS">FIG. 4</figref>. <figref idref="DRAWINGS">FIG. 4</figref> is a schematic sectional view taken along a line A-A′ in <figref idref="DRAWINGS">FIG. 3</figref>.

0042The photoelectric conversion unit <b>27</b> is formed as a semiconductor region in the semiconductor substrate SB.

0043The horizontal transfer switch <b>250</b> is formed as a MOS transistor having a source and drain formed as two semiconductor regions in the semiconductor substrate SB, and a gate formed as an electrode on the semiconductor substrate SB.

0044An interlayer insulation film <b>330</b> is arranged on the semiconductor substrate SB. An uppermost wiring layer including the output line group <b>160</b> is arranged on the interlayer insulation film <b>330</b>.

0045A passivation layer <b>320</b> is arranged to cover the uppermost wiring layer including the output line group <b>160</b>. The passivation layer <b>320</b> is made of, for example, SiN. The passivation layer <b>320</b> ensures the durability of the wiring layer and semiconductor element.

0046The color filter layer <b>310</b> is arranged on the passivation layer <b>320</b>. The opening <b>310</b><i>a </i>of the color filter layer <b>310</b> exposes a portion of the surface of the passivation layer <b>320</b> that covers the output line group <b>160</b>. Gas (e.g., air) fills the opening <b>310</b><i>a </i>of the color filter layer <b>310</b>.

0047As shown in <figref idref="DRAWINGS">FIG. 4</figref>, coupling capacitances Cp<b>1</b> to Cp<b>4</b> are formed between the output lines of the output line group <b>160</b>. More specifically, the coupling capacitance Cp<b>2</b> is formed between the first S output line <b>170</b><i>a </i>and the second N output line <b>170</b><i>c. </i>The coupling capacitance Cp<b>1</b> is formed between the first S output line <b>170</b><i>a </i>and the second S output line <b>170</b><i>d. </i>The coupling capacitance Cp<b>4</b> is formed between the first N output line <b>170</b><i>b </i>and the second N output line <b>170</b><i>c. </i>The coupling capacitance Cp<b>3</b> is formed between the first N output line <b>170</b><i>b </i>and the second S output line <b>170</b><i>d. </i>In the following description of <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>, the coupling capacitance Cp<b>3</b> will be explained as a coupling capacitance Cp for descriptive convenience.

0048Variation of voltage of the second S output line <b>170</b><i>d </i>and the first N output line <b>170</b><i>b </i>arising from the coupling capacitance Cp will be described with reference to equivalent circuits in <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>. <figref idref="DRAWINGS">FIG. 5A</figref> shows an equivalent circuit of the first N output line <b>170</b><i>b </i>and second S output line <b>170</b><i>d </i>before holding capacitances Ct<b>1</b><i>n </i>and Ct<b>2</b><i>s </i>transfer signals to the output lines (t=0). <figref idref="DRAWINGS">FIG. 5B</figref> shows an equivalent circuit of the first N output line <b>170</b><i>b </i>and second S output line <b>170</b><i>d </i>when the holding capacitances Ct<b>1</b><i>n </i>and Ct<b>2</b><i>s </i>transfer signals to the output lines (t=t<b>1</b>). In the equivalent circuits of <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>, Ch<b>1</b><i>n </i>represents the parasitic capacitance of the first N output line <b>170</b><i>b</i>, and Ch<b>2</b><i>s </i>represents that of the second S output line <b>170</b><i>d. </i>

0049Sampling of a noise signal to the holding capacitance Ct<b>1</b><i>n </i>and that of an optical signal to the holding capacitance Ct<b>2</b><i>s </i>are assumed to have ended at t=0. The voltage of each node is defined as follows.

0050In <figref idref="DRAWINGS">FIG. 5A</figref>, the holding capacitance Ct<b>1</b><i>n </i>is a sample/hold capacitance for sampling a noise signal from a pixel pix_out<b>1</b>. For descriptive convenience, a voltage Va at a node “<u style="single">a</u>” in <figref idref="DRAWINGS">FIG. 5A</figref> is 0, and no charge is accumulated in the holding capacitance Ct<b>1</b><i>n </i>at t=0. The holding capacitance Ct<b>2</b><i>s </i>is a sample/hold capacitance for sampling an optical signal from a pixel pix_out<b>2</b> different from the pixel for the holding capacitance Ct<b>1</b><i>n. </i>Vb represents a voltage at a node “b” in <figref idref="DRAWINGS">FIG. 5A</figref> at t=0. At t=0, the first N output line <b>170</b><i>b </i>and second S output line <b>170</b><i>d </i>have been reset to a ground potential. The voltages across the capacitances Ch<b>1</b><i>n</i>, Ch<b>2</b><i>s</i>, and Cp are 0, and no charge is accumulated by them.

0051Assume that Ct<b>1</b><i>n</i>=Ct<b>2</b><i>s</i>=Ct, and Ch<b>1</b><i>n</i>=Ch<b>2</b><i>s</i>=Ch. Letting Vd be the potential of the second S output line <b>170</b><i>d </i>at t=t<b>1</b>, equation (1) is established under the foregoing conditions according to principle of conservation of charge: <br /><i>Ct×Vb=[Ct+Ch+{Cp</i>×(<i>Ct+Ch</i>)}/{<i>Cp+Ct+Ch}]×Vd</i>  (1)<br /> Solving equation (1) for Vd yields <br /><i>Vd=Ct/[Ct+Ch+{Cp</i>×(<i>Ct+Ch</i>)}/{<i>Cp+Ct+Ch}]×Vb</i>  (2)

0052A potential Vc of the first N output line <b>170</b><i>b </i>at t=t<b>1</b> can be expressed using Vd: <br /><i>Vc=Cp</i>/(<i>Ct+Ch+Cp</i>)×<i>Vd</i>  (3)<br /> Substituting equation (2) into equation (3) yields

0053<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mtable><mtr><mtd><mrow><mi>Vc</mi><mo>=</mo><mi /><mo>⁢</mo><mrow><mrow><mi>Cp</mi><mo>/</mo><mrow><mo>(</mo><mrow><mi>Ct</mi><mo>+</mo><mi>Ch</mi><mo>+</mo><mi>Cp</mi></mrow><mo>)</mo></mrow></mrow><mo>×</mo></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mi /><mo>⁢</mo><mrow><mrow><mi>Ct</mi><mo>/</mo><mrow><mo>[</mo><mrow><mi>Ct</mi><mo>+</mo><mi>Ch</mi><mo>+</mo><mrow><mrow><mo>{</mo><mrow><mi>Cp</mi><mo>×</mo><mrow><mo>(</mo><mrow><mi>Ct</mi><mo>+</mo><mi>Ch</mi></mrow><mo>)</mo></mrow></mrow><mo>}</mo></mrow><mo>/</mo><mrow><mo>{</mo><mrow><mi>Cp</mi><mo>+</mo><mi>Ct</mi><mo>+</mo><mi>Ch</mi></mrow><mo>}</mo></mrow></mrow></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>Vb</mi></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mi /><mo>⁢</mo><mrow><mi>Cp</mi><mo>×</mo><mrow><mi>Ct</mi><mo>/</mo><mrow><mo>[</mo><mrow><mrow><mo>(</mo><mrow><mi>Ct</mi><mo>+</mo><mi>Ch</mi></mrow><mo>)</mo></mrow><mo>×</mo><mrow><mo>(</mo><mrow><mrow><mn>2</mn><mo>×</mo><mi>Cp</mi></mrow><mo>+</mo><mi>Ct</mi><mo>+</mo><mi>Ch</mi></mrow><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>×</mo><mi>Vb</mi></mrow></mrow></mtd></mtr></mtable></mtd><mtd><mrow><mo>(</mo><mn>4</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths><img file="US8309898B2_D0001.tif" /><br /> For Ct, Ch>>Cp, the following expression is approximated: <br />2×Cp+Ct+Ch≈Ct+Ch  (5)<br /> Cp is represented as a function of Ch: <br /><i>Cp=a×Ch </i>(<i><u style="single">a</u></i> is a positive decimal)  (6)<br /> Substituting equations (5) and (6) into equation (4) yields <br /><i>Vc=a×Ch×Ct</i>/(<i>Ct+Ch</i>)²<i>×Vb</i>  (7)<br /> Equation (7) reveals that a larger coefficient <u style="single">a</u> of Cp raises the voltage Vc, which is originally 0, and increases the crosstalk amount.

0054If the coupling capacitance Cp is 0, a=0 according to equation (6). No crosstalk occurs between the first N output line <b>170</b><i>b </i>and the second S output line <b>170</b><i>d </i>in the equivalent circuits of <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>.

0055This concept can also apply to calculate crosstalk between other output lines such as crosstalk from the first S output line <b>170</b><i>a </i>to the second N output line <b>170</b><i>c </i>and that from the first S output line <b>170</b><i>a </i>to the second S output line <b>170</b><i>d. </i>

0056If the crosstalk is contained equally in optical and noise signals, it can be removed by calculating the differences between optical and noise signals by the subsequent differential amplifiers <b>150</b><i>a </i>and <b>150</b><i>b. </i>In practice, however, noise arising from crosstalk cannot be removed owing differences between the coupling capacitances of output lines arising from differences between the distances between lines.

0057For example, crosstalk (Cp<b>1</b>+Cp<b>2</b>) affecting the first S output line <b>170</b><i>a </i>shown in <figref idref="DRAWINGS">FIG. 4</figref> differs from crosstalk (Cp<b>3</b>+Cp<b>4</b>) affecting the first N output line <b>170</b><i>b. </i>For this reason, a difference signal generated by the differential amplifier <b>150</b><i>a </i>still contains noise arising from crosstalk: <br /><i>N</i>1=<i>k</i>1{(<i>Cp</i>1<i>+Cp</i>2)−(<i>Cp</i>3<i>+Cp</i>4)}  (8)<br /> where k<b>1</b> is a predetermined coefficient.

0058For example, crosstalk (Cp<b>1</b>+Cp<b>3</b>) affecting the second S output line <b>170</b><i>d </i>differs from crosstalk (Cp<b>2</b>+Cp<b>4</b>) affecting the second N output line <b>170</b><i>c. </i>Thus, a difference signal generated by the differential amplifier <b>150</b><i>b </i>still contains noise arising from crosstalk: <br /><i>N</i>2<i>=k</i>2{(<i>Cp</i>1<i>+Cp</i>3)−(<i>Cp</i>2+<i>Cp</i>4)}  (9)<br /> where k2 is a predetermined coefficient.

0059Assume that a dummy pattern is formed of a substance having the same dielectric constant as a color filter so as to cover the output line group <b>160</b>. In this case, the coupling capacitances Cp<b>1</b> to Cp<b>4</b> increase at almost the same ratio in proportion to the dielectric constant. Both noise N<b>1</b> given by equation (8) and noise N<b>2</b> given by equation (9) may rise.

0060A large coupling capacitance between output lines attenuates an output level from the readout circuit to the output line. Readout of a signal from the readout circuit to the output line is determined by the following relationship between two capacitances. One capacitance is a holding capacitance Ct which is included in the readout circuit to hold optical and noise signals from a pixel. The other is a capacitance Ch including a wiring capacitance generated between the output line and mainly the ground point, and capacitances between the source and gate of a switch connected to the output line and between its source and back gate. That is, a signal is read out from the readout circuit to the output line at a gain determined by the capacitive division ratio Ct/(Ct+Ch). A coupling capacitance generated between output lines raises the capacitance Ch and thus decreases the capacitive division ratio, attenuating an output from the readout circuit. If an optical signal output S greatly attenuates, the S/N (Signal to Noise) ratio decreases, that is, the S/N (Signal to Noise) ratio becomes difficult to keep high.

0061To solve this, according to the first embodiment, no color filter exists above the output line formation region <b>401</b>, and air (or vacuum) occupies the opening <b>310</b><i>a. </i>This structure decreases the dielectric constant between output lines, compared to a conventional photoelectric conversion apparatus in which a color filter higher in dielectric constant than air exists above output lines. This means a smaller coupling capacitance between output lines than that in the conventional photoelectric conversion apparatus. The coupling capacitances Cp<b>1</b> to Cp<b>4</b> decrease at almost the same ratio in proportion to the dielectric constant. Decrease in a coupling capacitance is equivalent to decrease in a coefficient ā in equation (7), reducing the crosstalk amount. The smaller crosstalk amount between output lines allows readout from the holding capacitance to the output line with less noise. That is, both noise N<b>1</b> given by equation (8) and noise N<b>2</b> given by equation (9) decrease.

0062Equation (2) reveals that the optical signal Vb accumulated in the readout circuit <b>130</b> attenuates due to the presence of the coupling capacitance Cp when transferred to the second S output line <b>170</b><i>d. </i>When outputting a signal from the readout circuit as shown in <figref idref="DRAWINGS">FIG. 1</figref>, the coupling capacitance Cp affects the capacitive division ratio which determines a gain. More specifically, Cp is added to Ch to change the capacitive division ratio from Ct/(Ct+Ch) to Ct/(Ct+Ch+Cp). However, the first embodiment can suppress the signal attenuation on the output line by decreasing the dielectric constant on the output line and decreasing the coupling capacitance between the output lines. As a result, high S/N ratio can be maintained.

0063As described above, in the first embodiment, since no color filter is formed on output lines, this can reduce crosstalk generated upon capacitive coupling between them. Decreasing the coupling capacitance between output lines makes it possible to reduce crosstalk, decrease the signal attenuation on the output line, and maintain high S/N ratio. The embodiment is also effective for downsizing the chip because it can suppress an increase in coupling capacitance as the distance between output lines shortens.

0064The first embodiment can provide a photoelectric conversion apparatus capable of reducing crosstalk generated between output lines, obtaining a signal with good color reproduction, and reducing the chip size at high S/N ratio while making a flat upper face of a color filter layer in the photoelectric conversion region.

0065In the first embodiment, “no color filter is formed on output lines” means a state where a projected figure of the color filter does not overlap the output lines when the color filter is projected in the direction perpendicularly to a surface of the semiconductor substrate on a plane on which output lines are arranged. As shown in the sectional view of <figref idref="DRAWINGS">FIG. 4</figref>, the color filter layer <b>310</b> does not overlap the output line group <b>160</b> if the color filter layer <b>310</b> moved perpendicularly to the surface SBa of the semiconductor substrate SB on a plane on which the output line group <b>160</b> is arranged.

0066Further, “no color filter is formed on output lines” means a state in which margins <b>240</b> and <b>230</b> are set as follows in the schematic sectional view of <figref idref="DRAWINGS">FIG. 6</figref>. The margin <b>240</b> is defined between a color filter boundary X and an output line boundary Y. The margin <b>230</b> is defined between the color filter boundary X and an end Z of a semiconductor region (drain or source) <b>220</b> of the horizontal transfer switch <b>250</b>.

0067In <figref idref="DRAWINGS">FIG. 6</figref>, the margin <b>240</b> is basically designed to make a coupling capacitance generated on the boundary side (the side of the color filter boundary X) of the first S output line <b>170</b><i>a </i>equivalent to that generated between the output lines though it depends on the process conditions, chip size, layout conditions, and the like.

0068The margin <b>230</b> is designed to an interval capable of shielding incident light and scattered light <b>210</b> in order to prevent the incident light or scattered light <b>210</b> from reaching the semiconductor region <b>220</b> of a MOS transistor such as a transfer switch and changing an optical signal owing to charges generated by photoelectric conversion. For example, the margin <b>230</b> is set to about 1 μm or more, for example, about 10 μm in terms of the relationship between the film thickness from the semiconductor region <b>220</b> to the color filter and the incident angle of incident light. Note that an imaging system using the photoelectric conversion apparatus mainly determines the incident angle of incident light.

0069In <figref idref="DRAWINGS">FIG. 6</figref>, X′ and Y′ can also have the same positional relationship as that between X and Y in order to obtain the same effects as those described above.

0070Also, X′ can take the same positional relationship as that between X and Z in the semiconductor region (source or drain) of a transistor in the horizontal scanning circuit <b>140</b>.

0071The passivation layer <b>320</b> is formed on the output line group <b>160</b> in the first embodiment, but the present invention is not exclusive to this. Regardless of the presence/absence of the passivation layer, the sum of the dielectric constants of substances present on the path of a power line connecting output lines is smaller than that in a case in which a color filter is formed on output lines. This leads to a small coupling capacitance between output lines. Hence, the effects described in the embodiment can be obtained regardless of the presence/absence of the passivation layer on output lines. This also applies to the following embodiments.

0072The opening <b>310</b><i>a </i>of the color filter layer <b>310</b> may also be filled with an insulator lower in dielectric constant than each of color filters. For example, the photoelectric conversion apparatus may further include a low-dielectric-constant layer <b>340</b>, as shown in <figref idref="DRAWINGS">FIG. 7</figref>. The low-dielectric-constant layer <b>340</b> is arranged to fill the opening <b>310</b><i>a </i>of the color filter layer <b>310</b>. The low-dielectric-constant layer <b>340</b> is lower in dielectric constant than each of color filters in the color filter layer <b>310</b>. The low-dielectric-constant layer <b>340</b> is formed of, for example, a molding resin. Even this structure can reduce the coupling capacitance between output lines in comparison with a conventional photoelectric conversion apparatus having a color filter on the output line group <b>160</b>. The same effects as those of the first embodiment can be attained.

0073The effects of the first embodiment can be attained even when microlenses <b>610</b> are formed on the output line group <b>160</b>, as shown in <figref idref="DRAWINGS">FIG. 8</figref>.

0074The layout of the output lines of the output line group <b>160</b> is not limited to the order of the first S output line <b>170</b><i>a</i>, first N output line <b>170</b><i>b, </i>second N output line <b>170</b><i>c</i>, and second S output line <b>170</b><i>d </i>from the side of the readout circuit <b>130</b>. The same effects as those described above can also be obtained when the first S output line <b>170</b><i>a</i>, first N output line <b>170</b><i>b</i>, second S output line <b>170</b><i>d</i>, and second N output line <b>170</b><i>c </i>are arranged in the order named from the side of the readout circuit <b>130</b> in the output line group <b>160</b>.

0075Even three or more pairs of first and second output lines in the output line group <b>160</b> can provide the same effects as those described above.

0076The pixel array PA is not limited to the two-dimensional array of pixels, and a one-dimensional array of pixels can also obtain the same effects as those described above. When the pixel array PA is formed by one-dimensionally arraying pixels, the photoelectric conversion apparatus is a line sensor such as a photometer or auto-focus sensor, and the pixel array region IA is, for example, a region which receives light reflected by an object.

0077<figref idref="DRAWINGS">FIG. 9</figref> shows an example of an imaging system to which the photoelectric conversion apparatus of the present invention is applied.

0078As shown in <figref idref="DRAWINGS">FIG. 9</figref>, an imaging system <b>90</b> mainly includes an optical system, image sensing apparatus <b>86</b>, and signal processing unit. The optical system mainly includes a shutter <b>91</b>, lens <b>92</b>, and stop <b>93</b>. The signal processing unit mainly includes a sensed signal processing circuit <b>95</b>, A/D converter <b>96</b>, image signal processor <b>97</b>, memory <b>87</b>, external I/F <b>89</b>, timing generator <b>98</b>, overall control/arithmetic unit <b>99</b>, recording medium <b>88</b>, and recording medium control I/F <b>94</b>. The signal processing unit may not include the recording medium <b>88</b>.

0079The shutter <b>91</b> is arranged in front of the lens <b>92</b> on the optical path to control the exposure.

0080The lens <b>92</b> refracts incident light to form an object image on the pixel array (image sensing surface) of the photoelectric conversion apparatus <b>100</b> of the image sensing apparatus <b>86</b>. Alternatively, the lens <b>92</b> refracts incident light to guide the light reflected by an object to the pixel array (image sensing surface) of the photoelectric conversion apparatus <b>100</b> of the image sensing apparatus <b>86</b>.

0081The stop <b>93</b> is interposed between the lens <b>92</b> and the photoelectric conversion apparatus <b>100</b> on the optical path. The stop <b>93</b> adjusts the quantity of light guided to the photoelectric conversion apparatus <b>100</b> after passing through the lens <b>92</b>.

0082The photoelectric conversion apparatus <b>100</b> of the image sensing apparatus <b>86</b> converts an object image (or light reflected by an object) formed on the pixel array into an image signal. The image sensing apparatus <b>86</b> reads out the image signal from the photoelectric conversion apparatus <b>100</b>, and outputs it.

0083The sensed signal processing circuit <b>95</b> is connected to the image sensing apparatus <b>86</b>, and processes an image signal output from the image sensing apparatus <b>86</b>.

0084The A/D converter <b>96</b> is connected to the sensed signal processing circuit <b>95</b>. The A/D converter <b>96</b> converts a processed image signal (analog signal) output from the sensed signal processing circuit <b>95</b> into a digital signal.

0085The image signal processor <b>97</b> is connected to the A/D converter <b>96</b>. The image signal processor <b>97</b> performs various arithmetic processes such as correction for an image signal (digital signal) output from the A/D converter <b>96</b>, generating image data. The image signal processor <b>97</b> supplies the image data to the memory <b>87</b>, external I/F <b>89</b>, overall control/arithmetic unit <b>99</b>, recording medium control I/F <b>94</b>, and the like.

0086The memory <b>87</b> is connected to the image signal processor <b>97</b>, and stores image data output from the image signal processor <b>97</b>.

0087The external I/F <b>89</b> is connected to the image signal processor <b>97</b>. Image data output from the image signal processor <b>97</b> is transferred to an external device (e.g., personal computer) via the external I/F <b>89</b>.

0088The timing generator <b>98</b> is connected to the image sensing apparatus <b>86</b>, sensed signal processing circuit <b>95</b>, A/D converter <b>96</b>, and image signal processor <b>97</b>. The timing generator <b>98</b> supplies timing signals to the image sensing apparatus <b>86</b>, sensed signal processing circuit <b>95</b>, A/D converter <b>96</b>, and image signal processor <b>97</b>. The image sensing apparatus <b>86</b>, sensed signal processing circuit <b>95</b>, A/D converter <b>96</b>, and image signal processor <b>97</b> operate in synchronism with the timing signals.

0089The overall control/arithmetic unit <b>99</b> is connected to the timing generator <b>98</b>, image signal processor <b>97</b>, and recording medium control I/F <b>94</b>, and controls all of them.

0090The recording medium <b>88</b> is detachably connected to the recording medium control I/F <b>94</b>. Image data output from the image signal processor <b>97</b> is recorded on the recording medium <b>88</b> via the recording medium control I/F <b>94</b>.

0091With this arrangement, the photoelectric conversion apparatus <b>100</b> can provide a high-quality image (image data) as long as it can obtain a high-quality image signal.

0092A photoelectric conversion apparatus <b>100</b><i>i </i>according to the second embodiment of the present invention will be described with reference to <figref idref="DRAWINGS">FIG. 10</figref>. <figref idref="DRAWINGS">FIG. 10</figref> is a sectional view showing the structure of the photoelectric conversion apparatus <b>100</b><i>i </i>according to the second embodiment of the present invention. <figref idref="DRAWINGS">FIG. 10</figref> is a sectional view of a position corresponding to that in <figref idref="DRAWINGS">FIG. 4</figref> according to the first embodiment. A difference from the first embodiment will be mainly explained.

0093As shown in <figref idref="DRAWINGS">FIG. 10</figref>, the photoelectric conversion apparatus <b>100</b><i>i </i>includes an upper planarization layer <b>350</b><i>i </i>on a color filter layer <b>310</b><i>i </i>and a lower planarization layer <b>360</b><i>i </i>below it.

0094Each of color filters in the color filter layer <b>310</b><i>i </i>is formed of an acrylic resin matching the color filtering characteristic. The color filter layer <b>310</b><i>i </i>has an opening <b>310</b><i>ia </i>above an output line group <b>160</b>.

0095The upper planarization layer <b>350</b><i>i </i>is arranged to prevent steps corresponding to the upper face of the color filter layer <b>310</b><i>i </i>from appearing on the upper face of the upper planarization layer <b>350</b><i>i. </i>The upper planarization layer <b>350</b><i>i </i>can therefore assure the flatness of a face on which microlenses <b>610</b> are arranged. The upper planarization layer <b>350</b><i>i </i>is formed of, for example, an acrylic resin. The upper planarization layer <b>350</b><i>i </i>has an opening (another opening) <b>350</b><i>ia </i>aligned with the opening <b>310</b><i>ia. </i>That is, the upper planarization layer <b>350</b><i>i </i>extends to surround a plurality of output lines <b>170</b><i>a </i>to <b>170</b><i>d </i>when viewed from a direction perpendicular to a surface SBa of a semiconductor substrate SB. The upper planarization layer <b>350</b><i>i </i>has the opening <b>350</b><i>ia </i>above the output lines <b>170</b><i>a </i>to <b>170</b><i>d. </i>

0096The lower planarization layer <b>360</b><i>i </i>is arranged to prevent steps corresponding to the upper face of a passivation layer <b>320</b> from appearing on the upper face of the lower planarization layer <b>360</b><i>i. </i>Hence, the lower planarization layer <b>360</b><i>i </i>can assure the flatness of a face on which the color filter layer <b>310</b><i>i </i>is arranged. The lower planarization layer <b>360</b><i>i </i>is formed of, for example, an acrylic resin. The lower planarization layer <b>360</b><i>i </i>has an opening <b>360</b><i>ia </i>aligned with the opening <b>310</b><i>ia. </i>That is, the lower planarization layer <b>360</b><i>i </i>extends to surround the output lines <b>170</b><i>a </i>to <b>170</b><i>d </i>when viewed from a direction perpendicular to the surface SBa of the semiconductor substrate SB. The lower planarization layer <b>360</b><i>i </i>has the opening <b>360</b><i>ia </i>above the output lines <b>170</b><i>a </i>to <b>170</b><i>d. </i>

0097In this structure, not only the color filter layer <b>310</b><i>i </i>but also the lower planarization layer <b>360</b><i>i </i>and upper planarization layer <b>350</b><i>i </i>have openings above the output line group <b>160</b>. A side face <b>350</b><i>ib </i>of the opening <b>350</b><i>ia </i>of the upper planarization layer <b>350</b><i>i</i>, a side face <b>310</b><i>ib </i>of the opening <b>310</b><i>ia </i>of the color filter layer <b>310</b><i>i</i>, and a side face <b>360</b><i>ib </i>of the opening <b>360</b><i>ia </i>of the lower planarization layer <b>360</b><i>i </i>can be made continuous.

0098This structure of the photoelectric conversion apparatus <b>100</b><i>i </i>can be formed through the following steps (manufacturing method).

0099In a first step, a pixel array PA is formed in and on a semiconductor substrate SB (see <figref idref="DRAWINGS">FIG. 4</figref>) in a pixel array region IA (see <figref idref="DRAWINGS">FIG. 1</figref>). A readout circuit <b>130</b>, output unit <b>150</b>, and output line group <b>160</b> are formed above the semiconductor substrate SB in a peripheral region PR.

0100In a second step, a third resin layer is formed on a passivation layer <b>320</b> above the entire surface (pixel array region IA and peripheral region PR) of the semiconductor substrate SB. The third resin layer is a layer to be formed into the lower planarization layer <b>360</b><i>i. </i>Then, a first resin layer including a plurality of color filters is formed on the third resin layer above the entire surface (pixel array region IA and peripheral region PR) of the semiconductor substrate SB. The first resin layer is a layer to be formed into the color filter layer <b>310</b><i>i. </i>

0101In a third step, a second resin layer is formed on the first resin layer above the entire surface (pixel array region IA and peripheral region PR) of the semiconductor substrate SB. The second resin layer is a layer to be formed into the upper planarization layer <b>350</b><i>i. </i>

0102In a fourth step, the upper face of the second resin layer is planarized.

0103In a fifth step, portions of the third, first, and second resin layers that are positioned above the output line group <b>160</b> are removed. As a result, a lower planarization layer <b>360</b><i>i</i>, color filter layer <b>310</b><i>i</i>, and upper planarization layer <b>350</b><i>i </i>which extend to surround the output line group <b>160</b> are formed with openings <b>360</b><i>ia</i>, <b>310</b><i>ia</i>, and <b>350</b><i>ia </i>above the output line group <b>160</b>.

0104With these steps (manufacturing method), it is possible to ensure the flatness of the upper face of the upper planarization layer <b>350</b><i>i. </i>In addition, it is possible to obtain a continuous face including the side face <b>350</b><i>ib </i>of the opening <b>350</b><i>ia</i>, the side face <b>310</b><i>ib </i>of the opening <b>310</b><i>ia</i>, and the side face <b>360</b><i>ib </i>of the opening <b>360</b><i>ia. </i>

0105Note that, when viewed from a direction perpendicular to the surface SBa of the semiconductor substrate SB, the opening <b>350</b><i>ia </i>of the upper planarization layer <b>350</b><i>i</i>, the opening <b>310</b><i>ia </i>of the color filter layer <b>310</b><i>i</i>, and the opening <b>360</b><i>ia </i>of the lower planarization layer <b>360</b><i>i </i>can have similar shapes with their widths decreasing stepwise. The openings <b>350</b><i>ia</i>, <b>310</b><i>ia</i>, and <b>360</b><i>ia </i>are sometimes formed with such shapes owing to the difference in etching rate between the third, first, and second resins when portions of them that are positioned above the output line group <b>160</b> are etched in the fifth step.

0106No microlens is formed on the output line group <b>160</b> in <figref idref="DRAWINGS">FIG. 10</figref>, but may also be arranged on the output line group <b>160</b> as described in a modification (<figref idref="DRAWINGS">FIG. 8</figref>) to the first embodiment. Regardless of the presence/absence of the microlens on the output line group <b>160</b>, the sum of the dielectric constants of substances present on the path of a power line connecting output lines is smaller than that in a case in which a color filter is formed on the output line group <b>160</b>. Thus, the coupling capacitance between output lines decreases. The effects of the present invention can therefore be obtained regardless of the presence/absence of the microlens on the output line group <b>160</b>.

0107While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

0108This application claims the benefit of Japanese Patent Application No. 2008-179468, filed Jul. 9, 2008, which is hereby incorporated by reference herein in its entirety.