Display device, method for driving same, and electronic apparatus

CROSS REFERENCES TO RELATED APPLICATIONS

0001The present invention contains subject matter related to Japanese Patent Application JP 2007-330803 filed in the Japan Patent Office on Dec. 21, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to an active-matrix display device including light-emitting elements in its pixels, and a method for driving the same. Furthermore, the present invention relates to an electronic apparatus in which such a display device is incorporated as a display or a monitor.

00042. Description of the Related Art

0005In recent years, development of flat self-luminous display devices including organic EL (electroluminescence) devices as light-emitting elements is being actively promoted. The organic EL device is based on a phenomenon that an organic thin film emits light in response to application of an electric field thereto. The organic EL device can be driven by application voltage of 10 V or lower, and thus has low power consumption. Furthermore, because the organic EL device is a self-luminous element that emits light by itself, it does not need an illuminating unit and thus easily allows reduction in the weight and thickness of a display device. Moreover, the response speed of the organic EL device is as very high as about several microseconds, which causes no image lag in displaying of a moving image.

0006Among the flat self-luminous display devices including the organic EL devices in the pixels, particularly an active-matrix display device in which thin film transistors are integrally formed as drive elements in the respective pixels is being actively developed. Active-matrix flat self-luminous display devices are disclosed in e.g. Japanese Patent Laid-Open Nos. 2003-255856, 2003-271095, 2004-133240, 2004-029791, and 2004-093682.

SUMMARY OF THE INVENTION

0007The related-art display devices have a configuration in which a pixel array part and a drive part are integrally formed over one panel. The pixel array part at the center of the panel is formed of an aggregation of pixels arranged in a matrix. The drive part is disposed in the peripheral frame area surrounding the center pixel array part, and drives the pixel array part disposed in the center area from the periphery. The pixel array part includes row first drive lines disposed corresponding to the rows of the pixels, row second drive lines disposed corresponding to the rows of the pixels similarly, and column signal lines disposed corresponding to the columns of the pixels. In matching with this configuration, the drive part includes a horizontal drive circuit that supplies a video signal to the column signal lines, and a first vertical drive circuit and a second vertical drive circuit that cause the light-emission operation of the pixels on a row-by-row basis via the row first drive lines and the row second drive lines, respectively. Based on this configuration, the drive part allows displaying of the image dependent upon the video signal on the pixel array part.

0008The first vertical drive circuit carries out control for writing the video signal to the respective pixels on a row-by-row basis. The second vertical drive circuit carries out control of the emission-start/emission-stop operation of the pixels on a row-by-row basis. The first vertical drive circuit and the second vertical drive circuit cooperate with each other for the light-emission of the pixels on a row-by-row basis.

0009As enhancement in the definition and the density of the pixel array part in a display device is progressed, the number of rows of the pixels (the number of lines) is correspondingly increased. The vertical drive circuit is basically composed of shift registers, and sequentially transfers a start pulse input from the external to thereby output a drive signal for each stage. The stages of the shift registers each correspond to a respective one of the rows of the pixels. Increase in the number of rows of the pixels inevitably leads to increase in the number of stages of the shift registers. This causes increases in the degree of complexity and the scale of the vertical drive circuit, which is a problem that should be solved. Because the vertical drive circuit is disposed on a panel, the increase in the scale of the vertical drive circuit requires enlargement of the peripheral frame area surrounding the center pixel array part. This contradicts the trend toward smaller frame size and thus is not preferable.

0010If the number of rows of the pixels (the number of lines) is increased along with enhancement in the definition and the density of the pixel array part, the number of drive lines for driving the pixels on a row-by-row basis is also correspondingly increased. In linkage with the increase in the density of the drive lines, the size of the interconnect pattern thereof needs to be decreased and the distance between adjacent interconnect patterns also needs to be decreased. This results in a problem that short-circuit defects in the pixel array part frequently occur and therefore the yield is lowered.

0011It is desirable to provide a display device that is allowed to have a reduced scale of peripheral vertical drive circuitry and a reduced number of drive lines, and a method for driving the same. According to an embodiment of the present invention, there is provided a display device including a pixel array part configured to be formed of an aggregation of pixels arranged in a matrix and include row first drive lines disposed corresponding to rows of the pixels, row second drive lines disposed corresponding to the rows of the pixels, and column signal lines disposed corresponding to columns of the pixels. The display device further includes a drive part configured to drive the pixel array part and include a horizontal drive circuit that supplies a video signal to the column signal lines and a first vertical drive circuit and a second vertical drive circuit that cause light-emission operation of the pixels on a row-by-row basis via the row first drive lines and the row second drive lines, respectively, to thereby allow displaying of an image dependent upon a video signal on the pixel array part. The first vertical drive circuit simultaneously drives the pixels on two rows adjacent to each other. The second vertical drive circuit simultaneously drives the pixels on two rows adjacent to each other. A pair of rows of the pixels simultaneously driven by the first vertical drive circuit and a pair of rows of the pixels simultaneously driven by the second vertical drive circuit are shifted from each other by one row, for light-emission operation of the pixels on a row-by-row basis.

0012According to the embodiment of the present invention, the first vertical drive circuit simultaneously drives the pixels on two rows adjacent to each other. In other words, each stage of the shift registers included in the first vertical drive circuit corresponds to the pixels on two rows (two lines), and thus the scale of the shift registers can be halved. Similarly, the second vertical drive circuit also simultaneously drives the pixels on two rows adjacent to each other, which allows reduction in the circuit scale thereof. The pair of pixel rows simultaneously driven by the first vertical drive circuit and the pair of pixel rows simultaneously driven by the second vertical drive circuit are shifted from each other by one row (i.e. are so set as to be in a staggered relationship). This allows the light-emission operation of the pixels on a row-by-row basis. That is, it is possible to sequentially-drive the pixel rows while reducing the scale of the peripheral vertical drive circuitry. By thus simplifying the peripheral vertical drive circuitry, the frame size of the panel can be decreased and an effect of reduction in the power consumption can also be achieved.

0013By employing the operation sequence in which the pixels on two rows adjacent to each other are simultaneously driven, the drive line can be shared by the pixels on two rows adjacent to each other depending on the pixel layout. That is, the number of drive lines can be halved compared with the related arts. This allows achievement of enhancement in the definition of the pixel array part, increase in the pixel capacitance, and reduction in short-circuit defects between interconnects.

BRIEF DESCRIPTION OF THE DRAWINGS

0014<figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram showing the entire configuration of a display device according to a reference example;

0015<figref idref="DRAWINGS">FIG. 1B</figref> is a circuit diagram showing the configuration of a pixel included in the display device shown in <figref idref="DRAWINGS">FIG. 1A</figref>;

0016<figref idref="DRAWINGS">FIG. 2A</figref> is a timing chart for explaining the operation of the display device according to the reference example;

0017<figref idref="DRAWINGS">FIGS. 2B to 2I</figref> are schematic diagrams for explaining the operation of the display device according to the reference example;

0018<figref idref="DRAWINGS">FIG. 3A</figref> is a table diagram showing the operation sequence of the display device according to the reference example;

0019<figref idref="DRAWINGS">FIG. 3B</figref> is a table diagram showing the operation sequence of a display device according to an embodiment of the present invention;

0020<figref idref="DRAWINGS">FIG. 4A</figref> is a block diagram showing a display device according to a first embodiment of the present invention;

0021<figref idref="DRAWINGS">FIG. 4B</figref> is a block diagram showing a display device according to a second embodiment of the present invention;

0022<figref idref="DRAWINGS">FIGS. 5A to 5G</figref> are charts showing the operation sequence of the display device according to the reference example;

0023<figref idref="DRAWINGS">FIGS. 6A to 6C</figref> are charts showing the operation sequence of the display device according to the embodiment of the present invention;

0024<figref idref="DRAWINGS">FIGS. 6D to 6G</figref> are charts for explaining the operation of the display device according to the embodiment of the present invention;

0025<figref idref="DRAWINGS">FIG. 7A</figref> is a timing chart for explaining the operation of a display device according to a reference example;

0026<figref idref="DRAWINGS">FIG. 7B</figref> is a timing chart for explaining the operation of the display device according to the embodiment of the present invention;

0027<figref idref="DRAWINGS">FIG. 8</figref> is a sectional view showing the device structure of the display device according to the embodiment of the present invention;

0028<figref idref="DRAWINGS">FIG. 9</figref> is a plan view showing the module structure of the display device according to the embodiment of the present invention;

0029<figref idref="DRAWINGS">FIG. 10</figref> is a perspective view showing a television set including the display device according to the embodiment of the present invention;

0030<figref idref="DRAWINGS">FIG. 11</figref> is a perspective view showing a digital still camera including the display device according to the embodiment of the present invention;

0031<figref idref="DRAWINGS">FIG. 12</figref> is a perspective view showing a notebook personal computer including the display device according to the embodiment of the present invention;

0032<figref idref="DRAWINGS">FIG. 13</figref> is a schematic diagram showing a portable terminal apparatus including the display device according to the embodiment of the present invention; and

0033<figref idref="DRAWINGS">FIG. 14</figref> is a perspective view showing a video camera including the display device according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0034Embodiments of the present invention will be described in detail below with reference to the drawings. Initially, in order to clearly show the background of the present invention and facilitate understanding thereof, the general configuration of an active-matrix display device will be described below as a reference example. <figref idref="DRAWINGS">FIG. 1A</figref> is a block diagram showing the entire configuration of the display device according to the reference example. As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, this display device <b>100</b> includes a pixel array part <b>102</b> and a drive part (<b>103</b>, <b>104</b>, <b>105</b>) for driving the pixel array part <b>102</b>. The pixel array part <b>102</b> includes row scan lines WSL<b>101</b> to WSL<b>10</b><i>m</i>, column signal lines DTL<b>101</b> to DTL<b>10</b><i>n</i>, pixels (PIX) <b>101</b> disposed near the intersections of both the lines so as to be arranged in a matrix, and power feed lines DSL<b>101</b> to DSL<b>10</b><i>m </i>disposed corresponding to the respective rows of the pixels <b>101</b>. The drive part (<b>103</b>, <b>104</b>, <b>105</b>) includes a main scanner (write scanner WSCN) <b>104</b>, a power supply scanner (DSCN) <b>105</b>, and a signal selector (horizontal selector HSEL) <b>103</b>. The write scanner <b>104</b> sequentially supplies a control signal to the respective scan lines WSL<b>101</b> to WSL<b>10</b><i>m </i>to thereby line-sequentially scan the pixels <b>101</b> on a row-by-row basis. The power supply scanner <b>105</b> provides a supply voltage that is switched between a first potential and a second potential to the respective power feed lines DSL<b>101</b> to DSL<b>10</b><i>m </i>in matching with the line-sequential scanning. The signal selector <b>103</b> supplies a signal potential and a reference potential as a video signal to the column signal lines DTL<b>101</b> to DTL<b>10</b><i>n </i>in matching with the line-sequential scanning.

0035The write scanner <b>104</b> includes shift registers. The shift registers operate in response to a clock signal WSCK supplied from the external and sequentially transfer a start pulse WSST supplied from the external similarly, to thereby generate a shift pulse as the basis of the control signal. The power supply scanner <b>105</b> is also formed by using shift registers and sequentially transfers a start pulse DSST supplied from the external in response to a clock signal DSCK supplied from the external, to thereby control the switching of the potentials of the respective power feed lines DSL.

0036In the present reference example, the write scanner (WSCN) is one of the first vertical drive circuit and the second vertical drive circuit, and the power supply scanner (DSCN) is the other. Furthermore, the scan line WSL is one of the first drive line and the second drive line, and the power feed line DSL is the other. The horizontal selector (HSEL) is equivalent to the horizontal drive circuit. In this manner, the peripheral drive part of the active-matrix display device generally includes one horizontal drive circuit and at least two vertical drive circuits. The peripheral drive part including these drive circuits <b>103</b>, <b>104</b>, and <b>105</b> is disposed on the same panel as that of the center pixel array part <b>102</b>.

0037<figref idref="DRAWINGS">FIG. 1B</figref> is a circuit diagram showing the concrete configuration and the connection relationship of the pixel <b>101</b> included in the display device <b>100</b> shown in <figref idref="DRAWINGS">FIG. 1A</figref>. As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, this pixel <b>101</b> includes a light-emitting element <b>3</b>D typified by an organic EL device, a sampling transistor <b>3</b>A, a drive transistor <b>3</b>B, and a hold capacitor <b>3</b>C. The gate of the sampling transistor <b>3</b>A is connected to the corresponding scan line WSL<b>101</b>. One of the source and drain thereof is connected to the corresponding signal line DTL<b>101</b>, and the other is connected to the gate g of the drive transistor <b>3</b>B. One of the source s and drain d of the drive transistor <b>3</b>B is connected to the light-emitting element <b>3</b>D, and the other is connected to the corresponding power feed line DSL<b>101</b>. In the present reference example, the drive transistor <b>3</b>B is an N-channel transistor, and the drain d thereof is connected to the power feed line DSL<b>101</b> and the source s thereof is connected to the anode of the light-emitting element <b>3</b>D. The cathode of the light-emitting element <b>3</b>D is connected to a ground interconnect <b>3</b>H. The ground interconnect <b>3</b>H is disposed in common to all the pixels <b>101</b>. The hold capacitor <b>3</b>C is connected between the source s and the gate g of the drive transistor <b>3</b>B.

0038In this configuration, the sampling transistor <b>3</b>A is turned on in response to the control signal supplied from the scan line WSL<b>101</b>, to thereby sample the signal potential supplied from the signal line DTL<b>101</b> and hold the sampled potential in the hold capacitor <b>3</b>C. The drive transistor <b>3</b>B receives current supply from the power feed line DSL<b>101</b> at the first potential (higher potential) and applies a drive current to the light-emitting element <b>3</b>D depending on the signal potential held in the hold capacitor <b>3</b>C. The main scanner (WSCN) <b>104</b> outputs the control signal having a predetermined pulse width to the scan line WSL<b>101</b> so that the sampling transistor <b>3</b>A may be in the conductive state in the time zone during which the signal line DTL<b>101</b> is at the signal potential. Thereby, the signal potential is held in the hold capacitor <b>3</b>C, and simultaneously correction relating to the mobility μ of the drive transistor <b>3</b>B is added to the signal potential.

0039The pixel circuit <b>101</b> shown in <figref idref="DRAWINGS">FIG. 1B</figref> has a threshold voltage correction function in addition to the mobility correction function. Specifically, the power supply scanner (DSCN) <b>105</b> switches the potential of the power feed line DSL<b>101</b> from the first potential (higher potential) to the second potential (lower potential) at a first timing before the sampling of the signal potential by the sampling transistor <b>3</b>A. Furthermore, the main scanner (WSCN) <b>104</b> turns on the sampling transistor <b>3</b>A at a second timing before the sampling of the signal potential by the sampling transistor <b>3</b>A, to thereby apply the reference potential from the signal line DTL<b>101</b> to the gate g of the drive transistor <b>3</b>B and set the source of the drive transistor <b>3</b>B to the second potential. In general, the first timing is previous to the second timing. However, the second timing may be previous to the first timing depending on the case. The power supply scanner (DSCN) <b>105</b> switches the potential of the power feed line DSL<b>101</b> from the second potential to the first potential at a third timing after the second timing, to thereby hold the voltage equivalent to the threshold voltage Vth of the drive transistor <b>3</b>B in the hold capacitor <b>3</b>C. This threshold voltage correction function allows the display device <b>100</b> to cancel the influence of the threshold voltage of the drive transistor <b>3</b>B, which involves variation in the threshold voltage from pixel to pixel.

0040The pixel circuit <b>101</b> shown in <figref idref="DRAWINGS">FIG. 1B</figref> further has a bootstrap function. Specifically, at the timing when the signal potential has been held in the hold capacitor <b>3</b>C, the main scanner (WSCN) <b>104</b> turns off the sampling transistor <b>3</b>A by stopping the application of the control signal to the scan line WSL<b>101</b>, to thereby electrically isolate the gate g of the drive transistor <b>3</b>B from the signal line DTL<b>101</b>. This causes change in the gate potential (Vg) of the drive transistor <b>3</b>B to be linked to change in the source potential (Vs) of the drive transistor <b>3</b>B, and thus allows the voltage Vgs between the gate g and the source s to be kept constant.

0041<figref idref="DRAWINGS">FIG. 2A</figref> is a timing chart for explaining the operation of the pixel <b>101</b> shown in <figref idref="DRAWINGS">FIG. 1B</figref>. In this timing chart, potential changes of the scan line (WSL<b>101</b>), the power feed line (DSL<b>101</b>), and the signal line (DTL<b>101</b>) are shown along the same time axis. Furthermore, in parallel to these potential changes, changes in the gate potential (Vg) and the source potential (Vs) of the drive transistor <b>3</b>B are also shown.

0042In this timing chart, the operation period is divided into periods (B) to (I) corresponding to the transition of the operation of the pixel <b>101</b> for convenience. In the light-emission period (B), the light-emitting element <b>3</b>D is in the light-emission state. Thereafter, a new field of the line-sequential scanning starts, and the potential of the power feed line is switched to the lower potential in the first period (C) of the new field. In the next period (D), the gate potential Vg and the source potential Vs of the drive transistor are initialized. By resetting the gate potential Vg and the source potential Vs of the drive transistor <b>3</b>B in the threshold correction preparation periods (C) and (D), preparation for threshold voltage correction operation is completed. Subsequently, the threshold voltage correction operation is carried out in the threshold correction period (E), so that the voltage equivalent to the threshold voltage Vth is held between the gate g and the source s of the drive transistor <b>3</b>B. In practice, the voltage equivalent to Vth is written to the hold capacitor <b>3</b>C connected between the gate g and the source s of the drive transistor <b>3</b>B.

0043Thereafter, the operation sequence proceeds to the sampling period/mobility correction period (H) through preparation periods (F) and (G) for mobility correction. In this period, the signal potential Vin of the video signal is written to the hold capacitor <b>3</b>C in such a manner as to be added to Vth, and the voltage ΔV for the mobility correction is subtracted from the voltage held in the hold capacitor <b>3</b>C. In this sampling period/mobility correction period (H), in order that the sampling transistor <b>3</b>A may be kept at the conductive state in the time zone during which the signal line DTL<b>101</b> is at the signal potential Vin, the control signal having a pulse width shorter than this time zone is output to the scan line WSL<b>101</b>. Thereby, the signal potential Vin is held in the hold capacitor <b>3</b>C, and simultaneously the correction relating to the mobility μ of the drive transistor <b>3</b>B is added to the signal potential Vin.

0044Thereafter, the light-emission period (I) starts, so that the light-emitting element emits light with the luminance dependent upon the signal voltage Vin. In this light emission, the light-emission luminance of the light-emitting element <b>3</b>D is not affected by variations in the threshold voltage Vth and the mobility μ of the drive transistor <b>3</b>B because the signal voltage Vin has been adjusted with the voltage equivalent to the threshold voltage Vth and the voltage ΔV for the mobility correction. At the initial stage of the light-emission period (I), bootstrap operation is carried out and thereby the gate potential Vg and the source potential Vs of the drive transistor <b>3</b>B rise up in such a way that the gate-source voltage Vgs (=Vin+Vth−ΔV) of the drive transistor <b>3</b>B is kept constant.

0045With reference to <figref idref="DRAWINGS">FIGS. 2B to 2I</figref>, the operation of the pixel <b>101</b> shown in <figref idref="DRAWINGS">FIG. 1B</figref> will be described in detail below. The alphabets of the figure numbers of <figref idref="DRAWINGS">FIGS. 2B to 2I</figref> correspond to the periods (B) to (I), respectively, in the timing chart of <figref idref="DRAWINGS">FIG. 2A</figref>. To facilitate understanding, the capacitive component of the light-emitting element <b>3</b>D is represented as a capacitive element <b>3</b>I in <figref idref="DRAWINGS">FIGS. 2B to 2I</figref> for convenience of description. Referring initially to <figref idref="DRAWINGS">FIG. 2B</figref>, in the light-emission period (B), the power feed line DSL<b>101</b> is at a higher potential Vcc_H (first potential), and the drive transistor <b>3</b>B supplies a drive current Ids to the light-emitting element <b>3</b>D. As shown in <figref idref="DRAWINGS">FIG. 2B</figref>, the drive current Ids flows from the power feed line DSL<b>101</b> at the higher potential Vcc_H and passes through the light-emitting element <b>3</b>D via the drive transistor <b>3</b>B, so as to sink into the common ground interconnect <b>3</b>H.

0046At the start of the subsequent period (C), as shown in <figref idref="DRAWINGS">FIG. 2C</figref>, the potential of the power feed line DSL<b>101</b> is switched from the higher potential Vcc_H to a lower potential Vcc_L. Due to this operation, the power feed line DSL<b>101</b> is discharged to Vcc_L, and the source potential Vs of the drive transistor <b>3</b>B is shifted to a potential close to Vcc_L. If the interconnect capacitance of the power feed line DSL<b>101</b> is high, it is preferable to switch the potential of the power feed line DSL<b>101</b> from the higher potential Vcc_H to the lower potential Vcc_L at a comparatively-early timing. By ensuring the sufficiently-long period (C), the influence of the interconnect capacitance and another pixel parasitic capacitance is avoided.

0047At the start of the next period (D), as shown in <figref idref="DRAWINGS">FIG. 2D</figref>, the scan line WSL<b>101</b> is switched from the low level to the high level, and thereby the sampling transistor <b>3</b>A is turned on. At this time, the video signal line DTL<b>101</b> is at a reference potential Vo. Thus, the gate potential Vg of the drive transistor <b>3</b>B is changed to the reference potential Vo of the video signal line DTL<b>101</b> via the turned-on sampling transistor <b>3</b>A. Simultaneously, the source potential Vs of the drive transistor <b>3</b>B is immediately fixed to the lower potential Vcc_L. Through the above-described operation, the source potential Vs of the drive transistor <b>3</b>B is initialized (reset) to the potential Vcc_L sufficiently lower than the reference potential Vo of the video signal line DTL<b>101</b>. Specifically, the lower potential Vcc_L (second potential) of the power feed line DSL<b>101</b> is so set that the gate-source voltage Vgs of the drive transistor <b>3</b>B (the difference between the gate potential Vg and the source potential Vs) becomes higher than the threshold voltage Vth of the drive transistor <b>3</b>B.

0048At the start of the subsequent threshold correction period (E), as shown in <figref idref="DRAWINGS">FIG. 2E</figref>, the potential of the power feed line DSL<b>101</b> is shifted from the lower potential Vcc_L to the higher potential Vcc_H, so that the source potential Vs of the drive transistor <b>3</b>B starts to rise up. When the gate-source voltage Vgs of the drive transistor <b>3</b>B reaches the threshold voltage Vth in due course, the current is cut off. In this way, the voltage equivalent to the threshold voltage Vth of the drive transistor <b>3</b>B is written to the hold capacitor <b>3</b>C. This is the threshold voltage correction operation. In order that the current may not flow toward the light-emitting element <b>3</b>D but flow exclusively toward the hold capacitor <b>3</b>C during the threshold voltage correction operation, the potential of the common ground interconnect <b>3</b>H is so set that the light-emitting element <b>3</b>D is cut off during the threshold voltage correction operation.

0049At the start of the period (F), as shown in <figref idref="DRAWINGS">FIG. 2F</figref>, the potential of the scan line WSL<b>101</b> is shifted to the lower potential, so that the sampling transistor <b>3</b>A is set to the off-state temporarily. At this time, the gate g of the drive transistor <b>3</b>B becomes the floating state. However, because the gate-source voltage Vgs is equal to the threshold voltage Vth of the drive transistor <b>3</b>B, the drive transistor <b>3</b>B is in the cut-off state and hence the drive current Ids does not flow.

0050At the start of the subsequent period (G), as shown in <figref idref="DRAWINGS">FIG. 2G</figref>, the potential of the video signal line DTL<b>101</b> is shifted from the reference potential Vo to the sampling potential (signal potential) Vin. By this operation, preparation for the subsequent sampling operation and mobility correction operation is completed.

0051At the start of the sampling period/mobility correction period (H), as shown in <figref idref="DRAWINGS">FIG. 2H</figref>, the potential of the scan line WSL<b>101</b> is shifted to the higher potential and thereby the sampling transistor <b>3</b>A enters the on-state. Therefore, the gate potential Vg of the drive transistor <b>3</b>B becomes the signal potential Vin. In the period (H), the light-emitting element <b>3</b>D is in the cut-off state (high-impedance state), and thus the drain-source current Ids from the drive transistor <b>3</b>B flows into the capacitor <b>3</b>I of the light-emitting element, so that charging thereof is started. Therefore, the source potential Vs of the drive transistor <b>3</b>B starts to rise up, and the gate-source voltage Vgs of the drive transistor <b>3</b>B becomes Vin+Vth−ΔV in due course. In this manner, the sampling of the signal potential Vin and the adjustment with the correction amount ΔV are simultaneously carried out. The higher Vin is, the larger Ids and hence the absolute value of ΔV are. Consequently, the mobility correction dependent upon the light-emission luminance level is carried out. If Vin is constant, higher mobility μ of the drive transistor <b>3</b>B provides a larger absolute value of ΔV. In other words, higher mobility μ provides a larger negative feedback amount ΔV, and thus variation in the mobility μ from pixel to pixel can be removed.

0052Finally, at the start of the light-emission period (I), as shown in <figref idref="DRAWINGS">FIG. 2I</figref>, the potential of the scan line WSL<b>101</b> is shifted to the lower potential and thereby the sampling transistor <b>3</b>A enters the off-state. This isolates the gate g of the drive transistor <b>3</b>B from the signal line DTL<b>101</b>. Simultaneously, the drain current Ids starts to flow through the light-emitting element <b>3</b>D. This causes the anode potential of the light-emitting element <b>3</b>D to rise up by Vel depending on the drive current Ids. The rise of the anode potential of the light-emitting element <b>3</b>D is equivalent to the rise of the source potential Vs of the drive transistor <b>3</b>B. In linkage with the rise of the source potential Vs of the drive transistor <b>3</b>B, the gate potential Vg of the drive transistor <b>3</b>B also rises up based on the bootstrap operation due to the hold capacitor <b>3</b>C. The rise amount Vel of the gate potential Vg is equal to the rise amount Vel of the source potential Vs. Therefore, during the light-emission period, the gate-source voltage Vgs of the drive transistor <b>3</b>B is kept constant at Vin+Vth−ΔV.

0053<figref idref="DRAWINGS">FIG. 3A</figref> is a table diagram schematically showing the line-sequential scanning of the display device according to above-described reference example. For easy understanding, the configuration of the display device is simply shown in this diagram: the number of rows of the pixels (the number of lines) in the pixel array part is 16 in this diagram. The write scanner (WSCN) is defined as the first vertical drive circuit, and the respective output stages thereof are represented by WS(<b>1</b>) to WS(<b>16</b>). The power supply scanner (DSCN) is defined as the second vertical drive circuit, and the respective output stages thereof are represented by DS(<b>1</b>) to DS(<b>16</b>).

0054As shown in <figref idref="DRAWINGS">FIG. 3A</figref>, a pixel row of one line corresponds to one stage of each vertical drive circuit. For example, the pixel row of the first line is driven by the first output stage WS(<b>1</b>) of the first vertical drive circuit and the first output stage DS(<b>1</b>) of the second vertical drive circuit so as to carry out light-emission operation. Because the pixels on one row include pixels of RGB three primary colors, the pixels on one row are represented by the repletion of a group of R<b>1</b>, G<b>1</b>, and B<b>1</b> in the diagram. Upon the progression of the line-sequential scanning by one horizontal period (<b>1</b>H), the pixel row of the second line is driven by the second output stage WS(<b>2</b>) of the first vertical drive circuit and the second output stage DS(<b>2</b>) of the second vertical drive circuit. In this manner, the display device according to the reference example line-sequentially drives the respective lines of the pixels on a <b>1</b>H-by-<b>1</b>H basis. Therefore, the number of output stages of each vertical drive circuit is equal to the number of lines of the pixels. If the number of lines of the pixels is increased, the number of output stages of the vertical drive circuits is also increased and therefore the scale of the peripheral drive circuitry is forced to be enlarged, which is a problem that should be solved. The display device according to the reference example is based on a system in which the periods during which the respective output stages of the vertical drive circuit are in the active state are shifted from each other by every <b>1</b>H, and one output stage of the vertical drive circuit is used for driving of the pixels of only one line.

0055<figref idref="DRAWINGS">FIG. 3B</figref> is a table diagram showing the basic principle of the display device according to the embodiment of the present invention. For <figref idref="DRAWINGS">FIG. 3B</figref>, the same representation manner as that of the table diagram of <figref idref="DRAWINGS">FIG. 3A</figref> relating to the reference example is employed, for easy understanding. As is apparent from this table diagram, the pixel array part includes pixel rows of 16 lines. On the other hand, the first vertical drive circuit has eight output stages: the number of output stages is half the number of lines of the pixels. The first output stage WS(<b>1</b>) of the first vertical drive circuit simultaneously drives the pixel rows of the first line and the second line. Similarly, the second output stage WS(<b>2</b>) simultaneously drives the pixel rows of the third line and the fourth line. Similar simultaneous driving is sequentially carried out, and finally the eighth output stage WS(<b>8</b>) simultaneously drives the pixel rows of the fifteenth line and the sixteenth line.

0056The second vertical drive circuit has nine output stages DS(<b>0</b>) to DS(<b>8</b>): the number of output stages thereof is substantially half the number of lines of the pixels. Except for the first output stage DS(<b>0</b>) and the last output stage DS(<b>8</b>), each output stage simultaneously drives pixel rows of two lines. For example, the output stage DS(<b>1</b>) simultaneously drives the pixel rows of the second line and the third line. The next output stage DS(<b>2</b>) simultaneously drives the pixel rows of the fourth line and the fifth line.

0057The pair of pixel rows simultaneously driven by the first vertical drive circuit and the pair of pixel rows simultaneously driven by the second vertical drive circuit are shifted from each other by one row, so as to be in a staggered relationship. This staggered relationship allows the light-emission operation of the pixels on a row-by-row basis as with the reference example. The output of the first vertical drive circuit and the output of the second vertical drive circuit are staggered from each other, which makes it possible to use one output as outputs for two lines. For example, the pixel row of the second line is caused to carry out light-emission operation by the output stage WS(<b>1</b>) of the first vertical drive circuit and the output stage DS(<b>1</b>) of the second vertical drive circuit. The light-emission operation of the pixel row of the third line is caused by WS(<b>2</b>) and DS(<b>1</b>). The light-emission operation of the pixel row of the fourth line is caused by the combination of the output stage WS(<b>2</b>) and the output stage DS(<b>2</b>). In this manner, each line is driven by a respective one of different combinations of WS(i) and DS(j) necessarily, and therefore sequential driving on a line-by-line basis is allowed as with the reference example although the number of output stages is halved.

0058However, in practical operation sequence, the line-sequential scanning needs to be repeated twice, i.e. carried out in the former field and the latter field, for displaying an image of one frame. In the former field, the output stages of the first vertical drive circuit are sequentially driven from WS(<b>1</b>) to WS(<b>8</b>) for example. In contrast, for the second vertical drive circuit, only e.g. the odd-numbered output stages DS(<b>1</b>), DS(<b>3</b>), DS(<b>5</b>), and DS(<b>7</b>) are selectively driven. Thus, in the former field, the light-emission operation of the pixel rows of the following lines can be carried out, namely, second line, third line, sixth line, seventh line, tenth line, eleventh line, fourteenth line, and fifteenth line. In the subsequent latter field, the output stages WS(<b>1</b>) to WS(<b>8</b>) are sequentially driven as with in the former field. On the other hand, for the second vertical drive circuit, only the even-numbered output stages DS(<b>0</b>), DS(<b>2</b>), DS(<b>4</b>), DS(<b>6</b>), and DS(<b>8</b>) are driven. This allows the light-emission operation of the pixel rows of the following lines, which did not carry out the light-emission operation in the former field, namely, first line, fourth line, fifth line, eighth line, ninth line, twelfth line, thirteenth line, and sixteenth line. By the combination of the former field and the latter field, the line-sequential light-emission operation of all the lines is completed, so that an image of one frame is displayed on the pixel array part.

0059<figref idref="DRAWINGS">FIG. 4A</figref> is a block diagram schematically showing a display device according to a first embodiment of the present invention. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, this display device includes a pixel array part formed of an aggregation of pixels PIX arranged in a matrix and a drive part for driving this pixel array part. Each pixel PIX has e.g. the circuit configuration shown in <figref idref="DRAWINGS">FIG. 1B</figref>. However, the embodiment of the present invention is not limited thereto but the pixel circuit configuration can be changed according to the case.

0060The pixel array part includes row first drive lines disposed corresponding to the rows of the pixels PIX, row second drive lines disposed corresponding to the rows of the pixels PIX similarly, and column signal lines disposed corresponding to the columns of the pixels. The drive part includes a horizontal drive circuit HSEL that supplies a video signal to the column signal lines, and a first vertical drive circuit WSCN and a second vertical drive circuit DSCN that cause the light-emission operation of the pixels PIX on a row-by-row basis via the row first drive lines and the row second drive lines, respectively. Based on this configuration, the drive part allows displaying of the image dependent upon the video signal on the pixel array part.

0061As a feature of the present embodiment, the first vertical drive circuit WSCN includes output stages WS(i) whose number is half that of output stages in the reference example, and simultaneously drives the pixels PIX on two rows adjacent to each other. Similarly, the second vertical drive circuit DSCN also includes output stages DS(j) whose number is half that of output stages in the reference example, and simultaneously drives the pixels on two rows adjacent to each other. The pair of pixel rows simultaneously driven by the first vertical drive circuit WSCN and the pair of pixel rows simultaneously driven by the second vertical drive circuit DSCN are shifted from each other by one row so as to be in a staggered relationship. This allows the light-emission operation of the pixels PIX on a row-by-row basis.

0062In the concrete operation sequence, the drive part divides the pixels of one frame into those driven in the former field and those driven in the latter field, for image displaying on the pixel array part. In the former field, the first vertical drive circuit WSCN sequentially drives pairs of rows of the pixels PIX, whereas the second vertical drive circuit DSCN selectively drives every other pair of rows of the pixels PIX. This causes the light-emission operation of the pixels on one row of each of the pairs of rows of the pixels driven by the first vertical drive circuit WSCN. In the latter field, the first vertical drive circuit WSCN sequentially drives the pairs of rows of the pixels PIX again, whereas the second vertical drive circuit DSCN selectively drives the pairs of rows of the pixels that were not driven in the former field, of all the pairs of rows of the pixels PIX. This causes the light-emission operation of the pixels on the other row of each of the pairs of rows of the pixels driven by the first vertical drive circuit WSCN.

0063The pixel PIX includes the sampling transistor <b>3</b>A, the drive transistor <b>3</b>B, the hold capacitor <b>3</b>C, and the light-emitting element <b>3</b>D as shown in <figref idref="DRAWINGS">FIG. 1B</figref>. The control terminal of the sampling transistor <b>3</b>A is connected to the scan line WSL<b>101</b> as one of the first drive line and the second drive line, and the pair of current terminals thereof are connected between the signal line DTL<b>101</b> and the control terminal of the drive transistor <b>3</b>B. One of the pair of current terminals of the drive transistor <b>3</b>B is connected to the light-emitting element <b>3</b>D, and the other is connected to the power feed line DSL<b>101</b> as the other of the first drive line and the second drive line. The hold capacitor <b>3</b>C is connected between the control terminal and the current terminal of the drive transistor <b>3</b>B.

0064In the pixel PIX with this configuration, the sampling transistor <b>3</b>A is turned on in response to a drive signal supplied from the scan line WSL<b>101</b> to thereby sample a video signal from the signal line DTL<b>101</b> and write it to the hold capacitor <b>3</b>C. In addition, the drive transistor <b>3</b>B operates in response to a drive signal supplied from the power feed line DSL<b>101</b> to thereby supply the drive current dependent upon the video signal written to the hold capacitor <b>3</b>C to the light-emitting element <b>3</b>D.

0065At a timing before the writing of the video signal to the hold capacitor <b>3</b>C, the pixel PIX carries out correction operation in response to the drive signals supplied from the scan line WSL<b>101</b> and the power feed line DSL<b>101</b>, to thereby add a correction amount for cancelling variation in the threshold voltage Vth of the drive transistor <b>3</b>B to the voltage held in the hold capacitor <b>3</b>C. In addition, at the time of the writing of the video signal to the hold capacitor <b>3</b>C, the pixel PIX subtracts a correction amount for cancelling variation in the mobility μ of the drive transistor <b>3</b>B from the voltage held in the hold capacitor <b>3</b>C.

0066<figref idref="DRAWINGS">FIG. 4B</figref> is a block diagram showing a display device according to a second embodiment of the present invention. For easy understanding, the part corresponding to that in the first embodiment shown in <figref idref="DRAWINGS">FIG. 4A</figref> is given the same reference symbol. A difference from the first embodiment is that the layouts of the individual pixels PIX are mirror-inverted on adjacent rows so as to be symmetrically arranged. As shown in <figref idref="DRAWINGS">FIG. 4B</figref>, the layouts inside the pixels on rows adjacent to each other are vertically inverted from each other. This is represented by schematically inverting the reference symbols PIX in <figref idref="DRAWINGS">FIG. 4B</figref>. This configuration makes it possible that the first drive line extending from the output stage WS(i) of the first vertical drive circuit WSCN toward the pixel array part is shared by the corresponding pair of pixel rows. Thus, the number of first drive lines can be halved compared with the reference example. Similarly, the second drive line extending from the output stage DS(j) of the second vertical drive circuit DSCN toward the pixel array part is shared by the corresponding pair of pixel rows, and thus the number of second drive lines can be halved compared with the reference example. In this manner, the present embodiment allows simplification of the interconnect layout in the pixel array part, and is sufficiently compatible with enhancement in the definition and the density of the pixel array part. The simplification of the interconnect layout suppresses short-circuit defects, which can improve the yield.

0067<figref idref="DRAWINGS">FIG. 5A</figref> is a chart showing the operation sequence for one frame in the display device according to the reference example, shown in <figref idref="DRAWINGS">FIGS. 1A and 3A</figref>. As described above, the display device according to the reference example sequentially drives the pixels of 16 lines for displaying of an image of one frame. According to the shown chart, one-frame period is interposed between blanking periods BR equivalent to four horizontal periods (<b>4</b>H) and the subsequent blanking periods BR equivalent to four horizontal periods (<b>4</b>H). This one-frame period is composed of 16 horizontal periods (<b>16</b>H). In the one-frame period, video signals (DATA) <b>1</b> to <b>16</b> are written to the pixel rows of the respective lines.

0068For the first line, the pixel row of the first line is driven by the first output stage WS<b>1</b> of the first vertical drive circuit and the first output stage DS<b>1</b> of the second vertical drive circuit. Vth cancel operation (threshold voltage correction operation) is carried out by the output stage WS<b>1</b>. In the present example, the Vth cancel operation is repeated three times in a time-division manner over three horizontal periods (<b>3</b>H). The voltage Vth is not necessarily written across the hold capacitor by one time of the Vth cancel operation. In particular, if one horizontal period (<b>1</b>H) is short, it is difficult to complete the threshold voltage correction operation through only one time of the Vth cancel operation. Therefore, the Vth cancel operation is repeated three times over <b>3</b>H in the present example. In the third round of the Vth cancel operation, video signal writing operation and correction operation relating to the mobility μ are also simultaneously carried out. According to the chart, DATA<b>1</b> is written to the pixel row of the first line in the first horizontal period of the frame period. The emission-start/emission-stop of the pixel row of the first line is controlled by the output stage DS<b>1</b>. According to the shown chart, DS<b>1</b> is in the on-state and thus the corresponding pixels emit light during the period from the start of the blanking period immediately before the start of the field period to the end of the fifth horizontal period.

0069Upon the elapse of <b>1</b>H, WS<b>2</b> and DS<b>2</b> enter the active state, so that the series of operation necessary for light emission (light-emission operation) including the Vth cancel time-division operation, the signal writing operation, the mobility correction operation, and the emission-start operation of the light-emitting element is carried out for the pixel row of the second line. Upon the further progression of the phase of the operation sequence by <b>1</b>H, WS<b>3</b> and DS<b>3</b> enter the active state, so that the light-emission operation of the pixel row of the third line is carried out. The line-sequential scanning is carried out in turn in this manner. Upon the switching of the last output stages WS<b>16</b> and DS<b>16</b> to the active state, the light-emission operation of the pixel row of the sixteenth line is carried out, so that the one-frame period is completed. Thereafter, the line-sequential scanning returns to the first line and the next frame period starts.

0070<figref idref="DRAWINGS">FIG. 5B</figref> is a chart shown with focus on the operation of the first line particularly in the operation sequence for one frame, shown in <figref idref="DRAWINGS">FIG. 5A</figref>. The operation sequence of the first line, which is of interest, is surrounded by a dashed line. Upon the switching of WS<b>1</b> to the active state, the pixels of the first line carry out the Vth cancel operation three times in a time-division manner. In the horizontal period for the third round of the Vth cancel operation, the signal writing operation is also carried out together with this last Vth cancel operation. This allows the writing of the video signal DATA<b>1</b> assigned to the first line. At this time, the mobility correction for the drive transistor is also carried out simultaneously. The output of DS<b>1</b> is also switched to the active state in matching with the output of WS<b>1</b>. Due to the switching of DS<b>1</b> to the active state, the Vth cancel operation and the signal writing operation are normally carried out and the pixels enter the light-emission state. DS<b>1</b> enters the inactive state after the elapse of the predetermined light-emission period, so that the pixels stop the light emission. By thus controlling the period during which the pixels emit light by DS<b>1</b>, the luminance of the screen can be controlled. Specifically, by setting the active period of DS<b>1</b> longer, the ratio of the light-emission period to the one-frame period (duty) can be increased and thereby the screen luminance is enhanced.

0071<figref idref="DRAWINGS">FIG. 5C</figref> is a chart showing the switching of the pixels of the second line to the operating state. As shown in the diagram, WS<b>2</b> and DS<b>2</b> are in the active state.

0072<figref idref="DRAWINGS">FIG. 5D</figref> shows the operation state of the pixels of the third line. This diagram shows that the pixels of the third line carry out the series of operation due to the switching of WS<b>3</b> and DS<b>3</b> to the active state.

0073<figref idref="DRAWINGS">FIG. 5E</figref> is a chart showing the operation state of the pixel row of the third last line (i.e. the fourteenth line). As shown in the diagram, WS<b>14</b> and DS<b>14</b> enter the active state, so that the pixel row of the fourteenth line operates.

0074<figref idref="DRAWINGS">FIG. 5F</figref> shows the operation state of the pixels of the second last line. WS<b>15</b> and DS<b>15</b> enter the active state.

0075<figref idref="DRAWINGS">FIG. 5G</figref> shows the operation state of the pixels of the last line. WS<b>16</b> and DS<b>16</b> enter the active state, so that the pixels of the sixteenth line emit light. This is equivalent to the completion of the line-sequential scanning for one frame, followed by the start of the next frame.

0076<figref idref="DRAWINGS">FIG. 6A</figref> is a chart showing the operation sequence for one frame in the display device according to the embodiment of the present invention, shown in <figref idref="DRAWINGS">FIGS. 3B and 4A</figref>. For <figref idref="DRAWINGS">FIG. 6A</figref>, the same representation manner as that of the chart of <figref idref="DRAWINGS">FIG. 5A</figref> relating to the reference example is employed, for easy understanding. As shown in <figref idref="DRAWINGS">FIG. 6A</figref>, in the operation sequence according to the embodiment, a one-frame period is interposed between the previous and subsequent blanking periods, and an image of one frame is displayed in the one-frame period. The one-frame period is divided into the former field and the latter field, in each of which the sequential scanning is carried out. The combination of both the fields allows the displaying for one frame.

0077In the former field, the output stages WS<b>1</b> to WS<b>8</b> of the first vertical drive circuit sequentially enter the active state, whereas every other output stage DS<b>1</b>, DS<b>3</b>, DS<b>5</b>, and DS<b>7</b> of the second vertical drive circuit enter the active state.

0078Also in the latter field, the output stages WS<b>1</b> to WS<b>8</b> of the first vertical drive circuit sequentially enter the active state. On the other hand, for the second vertical drive circuit, the even-numbered output stages DS<b>0</b>, DS<b>2</b>, DS<b>4</b>, DS<b>6</b>, and DS<b>8</b> enter the active state differently from the former field.

0079<figref idref="DRAWINGS">FIG. 6B</figref> shows the operation state of the pixels of the second line, which is the first operation-target line. In the former field, WS<b>1</b> and DS<b>1</b> enter the active state, so that the time-division Vth cancel operation, the signal writing operation, the mobility correction operation, and the emission-start operation are carried out on the pixel row of the second line as the first operation-target line. In the latter field, WS<b>1</b> enters the active state, whereas DS<b>1</b> is kept at the inactive state. Therefore, the pixel row of the first operation-target line will not carry out the light-emission operation in the latter field. Consequently, in the operation sequence according to the embodiment, the ratio of the light-emission period to the one-frame period (duty) is at most 50%. Specifically, even when the whole of one of the former field and the latter field is used as the light-emission period, the whole of the other is the non-light-emission period, and hence the duty is at most 50%.

0080<figref idref="DRAWINGS">FIG. 6C</figref> is a chart showing the operation state of the pixels on the next row. As shown in <figref idref="DRAWINGS">FIG. 6C</figref>, upon the progression of the phase of the operation sequence by one horizontal period (<b>1</b>H) from the start of the active state of WS<b>1</b>, the output stage WS<b>2</b> enters the active state. DS<b>1</b> is kept at the active-state. Due to the switching of DS<b>1</b> and WS<b>2</b> to the active state, the series of operation of the pixels of the third line is carried out and the light-emitting elements emit light. The output of DS<b>1</b> is shared by the second line and the third line. On the other hand, the phases of the outputs of WS<b>1</b> and WS<b>2</b> are shifted from each other by <b>1</b>H. Therefore, the phase relationship between the outputs of WS<b>1</b> and DS<b>1</b> for the second line is different from that between the outputs of DS<b>1</b> and WS<b>2</b> for the third line. The phase relationship between WS<b>1</b> and DS<b>1</b> for the second line is similar to that in the reference example, and thus the time-division Vth cancel operation, the signal writing operation, and the light-emission operation can be carried out without any problem. On the other hand, for the third line, the output phase of WS<b>2</b> is backward shifted by <b>1</b>H with respect to the output phase of DS<b>1</b>. This shifted period is equivalent to the initial part of the period of the time-division Vth cancel driving, and therefore the first round of the time-division driving may not be sufficiently carried out depending on the case. To address this problem, in the embodiment of the present invention, the Vth cancel operation is repeated plural times in consideration of this phase difference. It is sufficient that the threshold voltage correction operation can be normally completed as a whole through the repetition of plural times of the operation, even if one time of the Vth cancel operation is insufficient. Therefore, no problem arises on the operation although the phase of the output stage WS of the first vertical drive circuit is shifted by <b>1</b>H from the phase of the output stage DS of the second vertical drive circuit. To put it the other way around, by employing the operation sequence that permits the phase shift of <b>1</b>H between DS and WS, the drive system according to the embodiment of the present invention can be implemented without any problem.

0081<figref idref="DRAWINGS">FIG. 6D</figref> is a chart showing the operation sequence of the pixels of the sixth line. Upon the progression of the phase by <b>1</b>H from the start of the active state of WS<b>2</b>, the output stage WS<b>3</b> enters the active state and thereafter the output stage DS<b>3</b> also enters the active state, so that the pixels of the sixth line carry out the light-emission operation.

0082<figref idref="DRAWINGS">FIG. 6E</figref> is a chart showing the operation state of the pixels of the third last operation-target line. Due to the switching of WS<b>6</b> and DS<b>6</b> to the active state in the latter field, the pixels of the twelfth line carry out the light-emission operation.

0083<figref idref="DRAWINGS">FIG. 6F</figref> is a chart showing the operation state of the pixels of the second last operation-target line. Upon the progression of the phase by <b>1</b>H from the start of the active state of WS<b>6</b>, the output stage WS<b>7</b> enters the active state, with DS<b>6</b> kept at the active state continuously. This causes the light-emission operation of the pixels of the thirteenth line.

0084<figref idref="DRAWINGS">FIG. 6G</figref> shows the state after the progression of the phase of the operation sequence by <b>1</b>H from the start of the active state of WS<b>7</b>. Due to the switching of WS<b>8</b> and DS<b>8</b> to the active state, the pixels of the sixteenth line, which is the last operation-target line, carry out the light-emission operation. This is equivalent to the completion of the one-frame period, followed by the start of the next frame period.

0085The Vth cancel operation (threshold voltage correction operation) is carried out only one time in some cases, and is repeatedly carried out in a time-division manner over plural horizontal periods in other cases. <figref idref="DRAWINGS">FIG. 7A</figref> shows the gate potential Vg and the source potential Vs of the drive transistor when the pixel configuration of the embodiment of the present invention is employed and the divided Vth cancel operation is not carried out. In <figref idref="DRAWINGS">FIG. 7A</figref>, two sets of changes in Vg and Vs are shown as the potential changes in two pixels. One set corresponds to Vg and Vs of the drive transistor driven by WS(n) and DS(n), and the other corresponds to Vg and Vs of the drive transistor driven by WS(n+1) and DS(n). According to the former set of potential changes, the initialization, the Vth cancel, and the writing (and the mobility correction) are normally carried out, and thus the desired light emission can be achieved. In contrast, according to the latter set, the potentials Vg and Vs return to those in the light-emission period of the previous field and thus the light emission occurs again instantaneously because DS is switched to Vcc_H before WS is turned on (the light emission is stopped by switching DS to Vcc_L in the circuit of <figref idref="DRAWINGS">FIG. 1B</figref>, and hence returning DS to Vcc_H again causes the restart of the light emission with the same Vgs). This is not the desired operation and therefore is not preferable.

0086<figref idref="DRAWINGS">FIG. 7B</figref> shows the gate potential Vg and the source potential Vs of the drive transistor when the pixel configuration of the embodiment of the present invention is employed and the divided Vth cancel operation is carried out. In <figref idref="DRAWINGS">FIG. 7B</figref>, two sets of changes in Vg and Vs are shown as the potential changes in two pixels, similarly to <figref idref="DRAWINGS">FIG. 7A</figref>. Differently from <figref idref="DRAWINGS">FIG. 7A</figref>, WS is turned on first and thus the initialization is normally carried out in both combinations of WS and DS, so that both the pixels can achieve the desired light emission. As is apparent from <figref idref="DRAWINGS">FIGS. 6A to 6G</figref> and <figref idref="DRAWINGS">FIG. 7B</figref>, in the case of driving based on the pixel configuration according to the embodiment of the present invention, the number of times of the divided Vth cancel operation is different by one time between the pixel lines that share an output. Therefore, it is important to sufficiently carry out the Vth cancel operation through increase in the number of times of the divided Vth cancel operation or extension of the operation period per one time of the Vth cancel operation. It is expected that a problem that the light-emission luminance differs from stage to stage occurs even when the same sampling potential is applied unless the Vth cancel operation is sufficiently carry out.

0087The display device according to the embodiment of the present invention has a thin film device structure like that shown in <figref idref="DRAWINGS">FIG. 8</figref>. <figref idref="DRAWINGS">FIG. 8</figref> shows the schematic sectional structure of a pixel formed over an insulating substrate. As shown in <figref idref="DRAWINGS">FIG. 8</figref>, the pixel includes a transistor part having plural thin film transistors (one TFT is shown in <figref idref="DRAWINGS">FIG. 8</figref>), a capacitive part such as a hold capacitor, and a light-emitting part such as an organic EL element. The transistor part and the capacitive part are formed on the substrate by a TFT process, and the light-emitting part such as an organic EL element is stacked thereon. A transparent counter substrate is attached over the light-emitting part with the intermediary of an adhesive, so that a flat panel is obtained.

0088The display device according to the embodiment of the present invention encompasses a display module having a flat module shape like that shown in <figref idref="DRAWINGS">FIG. 9</figref>. For example, this display module is obtained as follows. A pixel array part in which pixels each including an organic EL element, thin film transistors, a thin film capacitor, and so on are integrally formed into a matrix is provided on an insulating substrate. Furthermore, an adhesive is so disposed as to surround this pixel array part (pixel matrix part), and a counter substrate composed of glass or the like is bonded to the substrate. This transparent counter substrate may be provided with e.g. a color filter, protective film, and light-blocking film according to need. The display module may be provided with e.g. a flexible printed circuit (FPC) as a connector for inputting/outputting of signals and so forth to/from the pixel array part from/to the external.

0089The display device according to the above-described embodiment can be applied to a display that has a flat panel shape and is incorporated in various kinds of electronic apparatuses in any field with a function to display image or video based on a video signal input to the electronic apparatus or produced in the electronic apparatus, such as a digital camera, notebook personal computer, cellular phone, and video camera. Examples of such electronic apparatuses to which the display device is applied will be described below.

0090<figref idref="DRAWINGS">FIG. 10</figref> shows a television to which the embodiment of the present invention is applied. This television includes a video display screen <b>11</b> composed of a front panel <b>12</b>, a filter glass <b>13</b>, and so on, and is fabricated by using the display device according to the embodiment of the present invention as the video display screen <b>11</b>.

0091<figref idref="DRAWINGS">FIG. 11</figref> shows a digital camera to which the embodiment of the present invention is applied: the upper diagram is a front view and the lower diagram is a rear view. This digital camera includes an imaging lens, a light emitter <b>15</b> for flash, a display part <b>16</b>, a control switch, a menu switch, a shutter button <b>19</b>, and so on, and is fabricated by using the display device according to the embodiment of the present invention as the display part <b>16</b>.

0092<figref idref="DRAWINGS">FIG. 12</figref> shows a notebook personal computer to which the embodiment of the present invention is applied. A main body <b>20</b> thereof includes a keyboard <b>21</b> that is operated in inputting of characters and so on, and the body cover thereof includes a display part <b>22</b> for image displaying. This notebook personal computer is fabricated by using the display device according to the embodiment of the present invention as the display part <b>22</b>.

0093<figref idref="DRAWINGS">FIG. 13</figref> shows a portable terminal apparatus to which the embodiment of the present invention is applied: the left diagram shows the opened state and the right diagram shows the closed state. This portable terminal apparatus includes an upper casing <b>23</b>, a lower casing <b>24</b>, a connection (hinge) <b>25</b>, a display <b>26</b>, a sub-display <b>27</b>, a picture light <b>28</b>, a camera <b>29</b>, and so on. This portable terminal apparatus is fabricated by using the display device according to the embodiment of the present invention as the display <b>26</b> and the sub-display <b>27</b>.

0094<figref idref="DRAWINGS">FIG. 14</figref> shows a video camera to which the embodiment of the present invention is applied. This video camera includes a main body <b>30</b>, a lens <b>34</b> that is disposed on the front side of the camera and used to capture a subject image, a start/stop switch <b>35</b> for imaging operation, a monitor <b>36</b>, and so on. This video camera is fabricated by using the display device according to the embodiment of the present invention as the monitor <b>36</b>.

0095It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.