Electrostatic chucking of an insulator handle substrate

BACKGROUND

0001The present invention relates to methods of manufacturing semiconductor structures, and particularly to methods of electrostatically chucking an insulator handle substrate, and structures for effecting the same.

0002Semiconductor interposers may be employed between a semiconductor chip and packaging substrate to provide redistribution of electrical nodes on the surface of the semiconductor chip. For example, a semiconductor chip having a non-standard pitch among Controlled Collapse Chip Connection (C4) pads may be attached to a packaging substrate having a standard pitch by placing a semiconductor interposer including a first set of C4 pads having the non-standard pitch on one side and a second set of C4 pads having the standard pitch on the other side.

BRIEF SUMMARY

0003The present invention provides a method of electrostatically chucking a dielectric handle substrate in a process chamber.

0004In the present invention, a back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate sufficiently thick for mechanical handling and including a structure for a semiconductor interposer is attached to the transparent handle substrate employing an adhesive layer, which may be deactivated by ultraviolet (UV) radiation. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

0005According to an aspect of the present invention, a method of forming a semiconductor structure is provided, which comprises: forming a conductive material layer on a dielectric handle substrate; forming a bonded semiconductor structure by bonding a front surface of the dielectric handle substrate to a semiconductor interposer structure employing an adhesive layer, wherein the adhesive layer abuts the front surface of the dielectric handle substrate and a back surface of the semiconductor interposer structure; and electrostatically chucking the bonded semiconductor structure directly on an electrostatic chuck of a processing tool, wherein the dielectric handle substrate is placed in closer proximity to the electrostatic chuck than the semiconductor interposer structure.

0006According to another aspect of the present invention, a semiconductor structure is provided, which comprises: a bonded semiconductor structure including a dielectric handle substrate and a semiconductor interposer structure, wherein a front surface of the dielectric handle substrate is bonded to a back surface of a semiconductor interposer structure through an adhesive layer, wherein the semiconductor interposer structure includes metal interconnect structures electrically connected to first conductive pads located on the back surface of the semiconductor interposer structure, and wherein the adhesive layer abuts the front surface of the dielectric handle substrate and the back surface of the semiconductor interposer structure; and a conductive material layer vertically abutting a back surface of a dielectric handle substrate.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

0007<figref idref="DRAWINGS">FIG. 1</figref> is a vertical cross-sectional view of a dielectric handle substrate <b>200</b> with a conductive material layer <b>210</b> on a back surface according to a first embodiment of the present invention.

0008<figref idref="DRAWINGS">FIG. 2</figref> is a vertical cross-sectional view of a semiconductor interposer structure <b>100</b> and the dielectric handle substrate <b>200</b> with an adhesive layer <b>150</b> therebetween according to the first embodiment of the present invention.

0009<figref idref="DRAWINGS">FIG. 3A</figref> is a vertical cross-sectional view of a bonded semiconductor structure including the semiconductor interposer structure <b>100</b> and the dielectric handle substrate according to the first embodiment of the present invention.

0010<figref idref="DRAWINGS">FIG. 3B</figref> is a bottom-up view of the bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) according to the first embodiment of the present invention.

0011<figref idref="DRAWINGS">FIG. 4</figref> is a vertical cross-sectional view of the bonded semiconductor structure after grinding of the front side of the semiconductor interposer structure <b>100</b> according to the first embodiment of the present invention.

0012<figref idref="DRAWINGS">FIG. 5</figref> is a vertical cross-sectional view of the bonded semiconductor structure after deposition of at least one material layer <b>300</b> according to the first embodiment of the present invention.

0013<figref idref="DRAWINGS">FIG. 5A</figref> is a vertical cross-sectional view of the bonded semiconductor structure of <figref idref="DRAWINGS">FIG. 5</figref> as loaded onto an electrostatic chuck in a processing chamber

0014<figref idref="DRAWINGS">FIG. 6</figref> is a vertical cross-sectional view of the bonded semiconductor structure after application and patterning of a photosensitive material layer <b>307</b> according to the first embodiment of the present invention.

0015<figref idref="DRAWINGS">FIG. 7</figref> is a vertical cross-sectional view of a first composite structure after attaching a first substrate <b>400</b> to the bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>) and removal of the conductive material layer <b>210</b> according to the first embodiment of the present invention.

0016<figref idref="DRAWINGS">FIG. 8</figref> is a vertical cross-sectional view of the first composite structure after ultraviolet irradiation and detachment of the dielectric handle substrate <b>200</b> from the semiconductor interposer structure <b>100</b> according to the first embodiment of the present invention.

0017<figref idref="DRAWINGS">FIG. 9</figref> is a vertical cross-sectional view of a second composite structure after attaching a second substrate <b>600</b> to the back of the semiconductor interposer structure <b>100</b> according to the first embodiment of the present invention.

0018<figref idref="DRAWINGS">FIG. 10A</figref> is a vertical cross-sectional view of another bonded semiconductor structure in which a mesh of conductive wires <b>220</b> is patterned in a conductive material layer on the back surface of the dielectric handle substrate <b>200</b> according to a second embodiment of the present invention.

0019<figref idref="DRAWINGS">FIG. 10B</figref> is a bottom-up view of the other bonded semiconductor structure according to the second embodiment of the present invention.

0020<figref idref="DRAWINGS">FIG. 11A</figref> is a bottom-up view of another semiconductor interposer structure <b>710</b> including semiconductor dies <b>700</b> according to a third embodiment of the present invention.

0021<figref idref="DRAWINGS">FIG. 11B</figref> is a bottom-up view of another dielectric handle substrate <b>720</b> according to the third embodiment of the present invention.

0022<figref idref="DRAWINGS">FIG. 12</figref> is a vertical cross-sectional view of a dielectric handle substrate <b>700</b> having a conductive material layer <b>210</b> on a back surface according to a fourth embodiment of the present invention.

0023<figref idref="DRAWINGS">FIG. 13</figref> is a vertical cross-sectional view of a bonded semiconductor structure including a semiconductor interposer structure <b>100</b>, the dielectric handle substrate <b>700</b>, and a dielectric surface layer <b>720</b> according to the fourth embodiment of the present invention.

0024<figref idref="DRAWINGS">FIG. 14</figref> is a vertical cross-sectional view of a handle substrate <b>800</b> including an upper dielectric handle substrate <b>805</b>, an embedded conductive material layer <b>810</b>, a lower dielectric handles substrate <b>815</b> according to a fifth embodiment of the present invention.

0025<figref idref="DRAWINGS">FIG. 15</figref> is a vertical cross-sectional view of a bonded semiconductor structure including a semiconductor interposer structure <b>100</b>, the handle substrate <b>800</b>, and a dielectric surface layer <b>720</b> according to the fifth embodiment of the present invention.

0026<figref idref="DRAWINGS">FIG. 15A</figref> is a vertical cross-sectional view of the bonded semiconductor structure of <figref idref="DRAWINGS">FIG. 15</figref> as loaded onto an electrostatic chuck in a processing chamber

DETAILED DESCRIPTION

0027As stated above, the present invention relates to methods of electrostatically chucking an insulator handle substrate, and structures for effecting the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals. As used herein, when introducing elements of the present invention or the preferred embodiments thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. Throughout the drawings, the same reference numerals or letters are used to designate like or equivalent elements. Detailed descriptions of known functions and constructions unnecessarily obscuring the subject matter of the present invention have been omitted for clarity. The drawings are not necessarily drawn to scale.

0028Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a dielectric handle substrate <b>200</b> employed in embodiments of the present invention is shown. The dielectric handle substrate <b>200</b> comprises a dielectric material, i.e., an insulator material, such as quartz, borosilicate glass, amorphous silicon oxide, aluminum oxide, or other transparent dielectric materials such as transition metal oxides having a wide band gap to allow transmission of ultraviolet radiation. The dielectric handle substrate <b>200</b> may also be transparent in the visible spectrum and/or in the infrared spectrum. The thickness of the dielectric handle substrate <b>200</b> may be from about 400 μm to about 1,200 μm, although lesser and greater thicknesses are also contemplated herein.

0029According to a first embodiment of the present invention, a conductive material layer <b>210</b> is formed directly on a back surface of the dielectric handle substrate <b>200</b>. As used herein, a “back surface” refers to a surface located on the bottom side of a structure in the drawings. Likewise, a “front surface” refers to a surface located on the top side of a structure in the drawings. The conductive material layer <b>210</b> may be a contiguous blanket conductive material layer without a hole therein, and may cover the entirety of the back surface of the dielectric handle substrate <b>200</b>. The conductive material layer <b>210</b> may comprise a doped semiconductor material or a metallic material. The conductive material layer <b>210</b> has a resistivity less than 1.0×10⁻²Ω-cm, and preferably less than 1.0×10⁻⁴Ω-cm. Exemplary conductive materials that may be employed for the conductive material layer <b>210</b> include, but are not limited to, W, Ta, Ti, WN, TaN, TiN, Cu, Al, and Cu—Al alloys. The thickness of the conductive material layer <b>210</b> may be from 2 nm to 200 nm, and preferably from 50 nm to 500 nm, although lesser and greater thicknesses are also contemplated herein. The sheet resistance of the conductive material layer <b>210</b> may be from 0.1 Ω/□ to 100 Ω/□, and preferably from 1.0 Ω/□ to 30 Ω/□, although lesser and greater values for the sheet resistance are also contemplated herein.

0030Referring to <figref idref="DRAWINGS">FIG. 2</figref>, a semiconductor interposer structure <b>100</b> is provided, which comprises a first semiconductor substrate <b>10</b>, at least one dielectric material layer <b>30</b>, and metal interconnect structures embedded in the at least one dielectric material layer <b>30</b>. An array of conductive studs <b>22</b> is provided in the first semiconductor substrate <b>10</b>. The conductive studs <b>22</b> are electrically connected to the metal interconnect structures. Typically, the conductive studs <b>22</b> are resistively connected to the metal interconnect structures. The conductive studs <b>22</b> are located in a lower portion of the first semiconductor substrate <b>10</b>. The bottom surface of each conductive stud <b>22</b> may be substantially coplanar with a bottom surface of the first semiconductor layer <b>10</b>. A dielectric stud liner <b>20</b> may be provided on each conductive stud <b>22</b> so that the array of the conductive studs <b>22</b> is electrically isolated from the first semiconductor substrate.

0031The first semiconductor substrate <b>10</b> comprises a semiconductor material. The semiconductor material for the first semiconductor substrate <b>10</b> may be selected from, but is not limited to, silicon, germanium, silicon-germanium alloy, silicon carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, and other compound semiconductor materials. In some cases, the first semiconductor substrate <b>10</b> may be a single crystalline semiconductor substrate. While the present invention is described employing the first semiconductor substrate <b>10</b> comprising a semiconductor material, embodiments in which the first semiconductor substrate <b>10</b> is replaced with an insulator substrate or a substrate including conductive materials and an insulator coating on outer surfaces are explicitly contemplated herein. The thickness of the first semiconductor substrate <b>10</b> is sufficient to provide mechanical support to the semiconductor interposer structure <b>100</b>, and is typically from 400 μm to 1,200 μm, although lesser and greater thicknesses area also contemplated herein.

0032The at least one dielectric material layer <b>30</b> comprises a dielectric material that is typically employed in BEOL interconnect structures. The dielectric materials that may be used for the at least one dielectric material layer <b>30</b> include, but are not limited to, silicon nitride, a silicate glass, an organosilicate glass (OSG) material, a SiCOH-based low-k material formed by chemical vapor deposition, a spin-on glass (SOG), or a spin-on low-k dielectric material such as SiLK™, etc. The silicate glass includes an undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), etc. The dielectric material may be a low dielectric constant (low-k) material having a dielectric constant less than 3.0. The dielectric material may be non-porous or porous. The total thickness of the at least one dielectric material layer <b>30</b> may be from 1 μm to 50 μm, and typically from 2 μm to 20 μm, although lesser and greater thicknesses are also contemplated herein.

0033The metal interconnect structures may include multiple levels of metal structures. For example, the metal interconnect structures may include first-via-level metal vias <b>42</b>, first-line-level metal lines <b>44</b>, second-via-level metal vias <b>46</b>, second-line-level metal lines <b>48</b>, a third-line-level metal lines <b>50</b>, and first conductive pads <b>52</b>. The various metal structures (<b>42</b>, <b>44</b>, <b>46</b>, <b>48</b>, <b>50</b>, <b>52</b>) comprise at least one metallic material such as Cu, W, Ti, Ta, WN, TiN, TaN, and/or Al. The first-via-level metal vias <b>42</b> vertically abut the conductive studs <b>22</b> embedded in the first semiconductor substrate <b>10</b>. Dielectric isolation structures <b>24</b> may be provided on the bottom surface of the first semiconductor substrate <b>10</b> to provide electrical isolation between the first semiconductor substrate <b>10</b> and the first-via-level metal vias <b>42</b>. The first-line-level metal lines <b>44</b> vertically abut the first-via-level metal vias <b>42</b>. The second-via-level metal vias <b>46</b> vertically abut the first-line-level metal lines <b>44</b>. The second-line-level metal lines <b>48</b> vertically abut the second-via-level metal vias <b>46</b>. The third-line-level metal lines <b>50</b> vertically abut the second-line-level metal lines <b>48</b>. The first conductive pads <b>52</b> vertically abut the third-line-level metal lines <b>50</b>. The first conductive pads <b>52</b> vertically abut the third-line-level metal lines <b>50</b>. The metal interconnect structures are embedded in the at least one dielectric material layer <b>30</b>. The metal interconnect structures described herein are only for the purpose of providing an illustrative example. Any other metal interconnect structures having different numbers of metal line levels and/or metal via levels may be employed instead.

0034In one case, an adhesive layer <b>150</b> may be formed on the top surface of the dielectric handle substrate <b>200</b> on the opposite side of the conductive material layer <b>210</b>. In another case, an adhesive layer <b>150</b> maybe formed on the bottom surface of the semiconductor interposer structure, i.e., on the bottom surface of the at least one dielectric material layer <b>30</b>. The adhesive layer <b>150</b> comprises a deactivatable adhesive material which provides adhesive strength prior to deactivation but substantially loses adhesive property upon deactivation. In one case, the deactivation mechanism may be exposure to ultraviolet light, i.e., the adhesive layer <b>150</b> comprises an ultraviolet (UV) deactivatable material having reduced adhesion strength upon exposure to ultraviolet radiation. For example, the adhesive material in the adhesive layer <b>150</b> may comprise an oligomer that loses cross-linkage upon exposure to ultraviolet (UV) light. Acrylic adhesive materials, which deactivates and significantly loses adhesive property upon exposure to ultraviolet light, may be employed as an ultraviolet sensitive material in the adhesive layer <b>150</b>. Alternately, other deactivation mechanisms such as exposure to visible light or exposure to infrared radiation may be employed. The adhesive layer <b>150</b> may be formed as a single contiguous layer with, or without, holes, or it may be formed as a plurality of disjoined adhesive material portions. The thickness of the adhesive layer <b>150</b> may be from 0.5 μm to 100 μm, and typically 2 μm to 20 μm, although lesser and greater thicknesses are also contemplated herein. The semiconductor interposer structure <b>100</b> and the dielectric handle substrate <b>200</b> are brought together with the adhesive layer <b>150</b> therebetween.

0035Referring to <figref idref="DRAWINGS">FIGS. 3A and 3B</figref>, temperature and/or pressure is applied to bond the semiconductor interposer structure <b>100</b> with the dielectric handle substrate <b>200</b> through the adhesive layer <b>150</b>. <figref idref="DRAWINGS">FIG. 3A</figref> is a vertical cross-sectional view and <figref idref="DRAWINGS">FIG. 3B</figref> is a bottom-up view. A first exemplary bonded semiconductor structure including the semiconductor interposer structure <b>100</b>, the adhesive layer <b>150</b>, the dielectric handle substrate <b>200</b>, and the conductive material layer <b>210</b> is shown. The adhesive layer <b>150</b> keeps the semiconductor interposer structure <b>100</b> fixed in location relative to the dielectric handle substrate <b>200</b> so that the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) moves as a rigid body. The entirety of the back surface of the dielectric handle substrate <b>200</b> is covered by the conductive material layer, which is a blanket film of a conductive material.

0036Referring to <figref idref="DRAWINGS">FIG. 4</figref>, the front surface of the first semiconductor substrate <b>10</b> is recessed at least down to the top surfaces of the array of the conductive studs <b>22</b>. The recessing of the top surface of the first semiconductor substrate <b>10</b> may be effected, for example, by grinding, chemical etching, chemical mechanical planarization, a dry etch, or a combination thereof. The dielectric stud liner <b>20</b> and/or the conductive studs <b>22</b> may be employed as an etch stop layer. After recessing, the front surface of the first semiconductor substrate <b>10</b> is substantially coplanar with top surfaces of the conductive studs <b>22</b>. The thickness of the first semiconductor substrate <b>10</b> may be substantially the same as the height of the conductive studs <b>22</b>, and may be from about 20 μm to about 300 μm, and typically from about 50 μm to about 150 μm, although lesser and greater thicknesses are also contemplated herein.

0037Referring to <figref idref="DRAWINGS">FIG. 5</figref>, the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) is loaded into a processing chamber for deposition of at least one material layer <b>300</b>, which may be a dielectric material layer or a conductive material layer. The at least one material layer <b>200</b> may include a dielectric material layer that provides electrical isolation and/or passivation of the first semiconductor substrate <b>10</b> from other conductive structures to be subsequently formed over the first semiconductor substrate <b>10</b>. Upon deposition on the front surface of the semiconductor interposer structure <b>100</b>, the at least one material layer <b>300</b> is incorporated into the semiconductor interposer structure <b>100</b>. In case electrostatic chucking of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) is needed, the conductive material layer <b>210</b> may be employed to provide electrical contact between the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) and an electrostatic chuck <b>900</b> of the processing chamber <b>990</b> through a direct contact therebetween as illustrated in <figref idref="DRAWINGS">FIG. 5A</figref>.

0038The presence of the conductive material layer <b>210</b> enables electrostatic chucking of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) on an electrostatic chuck. If the conductive material layer <b>210</b> is absent on the back surface of the dielectric handle substrate <b>200</b>, loading a structure including the dielectric handle substrate <b>200</b> into a process chamber would induce direct contact between the dielectric handle substrate <b>200</b> and the electrostatic chuck. Since the dielectric handle substrate <b>200</b> is not conductive, electrical charges may accumulate in the semiconductor interposer structure <b>100</b> in the absence of the conductive material layer <b>210</b>, thereby causing arcing in the process chamber and inducing structural damages to the semiconductor interposer structure <b>200</b>. By providing the conductive material layer <b>210</b>, the first embodiment of the present invention prevents accumulation of electrical charges in the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>), and prevents arcing between the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) and components of the processing chamber.

0039Referring to <figref idref="DRAWINGS">FIG. 6</figref>, the at least one material layer <b>300</b> is lithographically patterned. Specifically, lithographic patterning of the at least one material layer <b>300</b> may be effected by applying a photoresist <b>307</b> to the top surface of the at least one material layer, lithographically patterning the photoresist <b>307</b>, and transferring the pattern in the photoresist <b>307</b> into the at least one material layer <b>300</b> by an etch, which may be a wet etch or a dry etch. In case a dry etch is employed, the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) may be loaded into another processing chamber and placed directly upon an electrostatic chuck. The first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) is then electrostatically chucked so that the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) remains stationary in the processing chamber. The electrostatic chucking of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) is particularly useful during the dry etch, which may be an anisotropic reactive ion etch that employs electrical bias and/or radio frequency (RF) signal within the processing chamber. The photoresist <b>307</b> may be subsequently removed.

0040The at least one material layer <b>300</b> may include at least one dielectric material layer and/or at least one conductive material layer. Each of the at least one material layer <b>300</b> may be patterned individually, or may be patterned in combination with another of the at least one material layer <b>300</b>. In one case, multiple deposition steps and multiple patterning steps may be employed to form additional metal interconnect structures (not shown). During each patterning step for any material layer of the at least one material layer <b>300</b>, the conductive material layer <b>210</b> of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) may be employed to enable electrostatic chucking of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>). At the end of the at least one patterning process, an array of conductive surfaces is exposed on the top surface of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>). The array of conductive surfaces may be an array of the top surfaces of the conductive studs <b>22</b>. Alternately, the array of conductive surfaces may be an array of conductive surfaces of the additional metal interconnect structures (not shown). The electrostatic chucking of the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) protects the semiconductor interposer structure <b>100</b> during processing steps in which a direct current (DC) voltage bias or an alternating current (AC) bias is applied between the semiconductor interposer structure <b>100</b> and any component in the processing chamber.

0041Referring to <figref idref="DRAWINGS">FIG. 7</figref>, the conductive material layer <b>210</b> is removed from the back surface of the dielectric handle substrate <b>200</b>. A wet etch or a dry etch may be employed to remove the conductive material layer <b>210</b>.

0042An array of first Controlled Collapse Chip Connection (C4) balls <b>450</b> are employed to bond the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) with a first substrate <b>400</b>. An array of first C4 pads <b>410</b> may be provided on the bottom surface of the first substrate <b>400</b>. Each first C4 ball <b>450</b> in the array of the first C4 balls <b>450</b> vertically abuts a conductive surface on the semiconductor interposer structure and a first C4 pad <b>410</b>. Each first C4 ball <b>450</b> has a diameter from 50 μm to 200 μm, and typically comprises a Sn—Ag—Cu alloy. The conductive surface may be a top surface of a conductive stud <b>22</b> or a conductive surface of one of the additional metal interconnect structures (not shown) formed in the at least one material layer <b>300</b>.

0043The first substrate <b>400</b> may be a second semiconductor substrate including a plurality of semiconductor dies (not shown). Each semiconductor die, or each “semiconductor chip,” may include a plurality of semiconductor devices. The first substrate <b>400</b> may have substantially the same area as the first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>). For example, the semiconductor interposer structure <b>100</b> and the dielectric handle substrate <b>200</b> may be wafers having a diameter of 150 mm, 200 mm, or 300 mm, and the first substrate <b>400</b> may be a semiconductor wafer having a matching diameter as the semiconductor interposer structure <b>100</b> and the dielectric handle substrate <b>200</b>. The assembly of the first substrate <b>400</b>, the first C4 pads <b>410</b>, the first C4 balls <b>450</b>, and first exemplary bonded semiconductor structure (<b>100</b>, <b>150</b>, <b>200</b>, <b>210</b>) is herein referred to as a first composite structure.

0044Referring to <figref idref="DRAWINGS">FIG. 8</figref>, the adhesive layer <b>150</b> is irradiated with a deactivating radiation through the dielectric handle substrate <b>200</b>. In case the adhesive layer <b>150</b> comprises an ultraviolet (UV) deactivatable material that has reduced adhesive strength upon exposure to ultraviolet radiation, the adhesive layer <b>150</b> is irradiated with ultraviolet radiation. In case the adhesive layer <b>150</b> comprises a optically deactivatable material that has reduced adhesive strength upon exposure to light in visible spectrum or in infrared range, the adhesive layer <b>150</b> is irradiated with light in visible spectrum or in infrared range. The dielectric handle substrate <b>200</b> and the adhesive layer <b>150</b> are detached from the semiconductor interposer structure <b>100</b>. A suitable cleaning process may be performed on the back side of the semiconductor interposer structure <b>100</b> to remove residues of the adhesive layer <b>150</b>.

0045The first composite structure comprises the semiconductor interposer structure <b>100</b>, the first C4 balls <b>450</b>, the first C4 pads <b>410</b>, and the first substrate <b>400</b>. The first composite structure may then be diced along dicing channels (not shown) located between the semiconductor dies in the first substrate <b>400</b>.

0046Referring to <figref idref="DRAWINGS">FIG. 9</figref>, a second substrate <b>600</b> is attached to the back surface of the semiconductor interposer structure <b>100</b>. The second substrate <b>600</b> may be a packaging substrate having second C4 pads <b>610</b>. Second C4 balls <b>650</b> may be employed to bond the second substrate to the semiconductor interposer structure <b>100</b>. Each second C4 ball <b>650</b> in the array of the second C4 balls <b>650</b> vertically abuts a first conductive pad <b>52</b> and a second C4 pad <b>610</b>. Each second C4 ball <b>650</b> has a diameter from 50 μm to 200 μm, and typically comprises a Sn—Ag—Cu alloy.

0047Referring to <figref idref="DRAWINGS">FIGS. 10A and 10B</figref>, a second exemplary bonded semiconductor structure is shown. <figref idref="DRAWINGS">FIG. 10A</figref> is a vertical cross-sectional view and <figref idref="DRAWINGS">FIG. 10B</figref> is a bottom-up view. The second exemplary bonded semiconductor structure may be formed by patterning a mesh of conductive wires <b>220</b> in the conductive material layer <b>210</b>. Formation of the mesh of conductive wires <b>220</b> may be effected by flipping the structure in <figref idref="DRAWINGS">FIG. 1</figref> upside down and applying a photoresist (not shown) directly on the conductive material layer <b>210</b>. The photoresist is patterned in the form of a mesh, and the pattern in the photoresist is subsequently transferred into the conductive material layer <b>210</b> by an etch so that the mesh of conductive wires <b>220</b> is formed directly on a surface of the dielectric handle substrate <b>200</b>. The photoresist is employed as an etch mask during the etching process. An isotropic etch or an anisotropic etch may be employed for the etching process.

0048An adhesive layer <b>150</b> is applied to the surface of the dielectric handle substrate <b>200</b> located on an opposite side of the mesh of conductive wires <b>220</b>. The dielectric handle substrate <b>200</b> is attached to a semiconductor interposer structure <b>100</b> in the same manner as in the first embodiment. During subsequent processing steps in which electrical bias is applied between the semiconductor interposer structure <b>100</b> and any component in a processing chamber, the mesh of conductive wires <b>220</b> may be employed to electrostatically chuck the second exemplary bonded semiconductor structure in the same manner as the electrostatic chucking of the first exemplary bonded semiconductor structure of the first embodiment.

0049Unlike the first embodiment, removal of the mesh of the conductive wires <b>220</b> is optional because the adhesive layer <b>150</b> may be irradiated without removing the mesh of the conductive wires <b>220</b>. In other words, the processing step of removal of the conductive material layer <b>210</b> may be omitted in the second embodiment. The mesh of the conductive wires <b>220</b> is removed at the same time as the removal of the dielectric handle substrate <b>200</b>.

0050Referring to <figref idref="DRAWINGS">FIGS. 11A and 11B</figref>, exemplary structures according to a third embodiment of the present invention are shown. <figref idref="DRAWINGS">FIG. 11A</figref> is a bottom-up view of a semiconductor interposer structure <b>710</b> including semiconductor dies <b>700</b>, and <figref idref="DRAWINGS">FIG. 11B</figref> is a bottom-up view of a dielectric handle substrate <b>720</b>. The semiconductor interposer structure <b>710</b> includes semiconductor dies <b>700</b>, each of which have an identical pattern to accommodate a semiconductor chip (not shown) in a first substrate <b>400</b> (See <figref idref="DRAWINGS">FIG. 7</figref>). Preferably, the semiconductor interposer structure <b>710</b> and the dielectric handle substrate <b>720</b> have the same diameter, e.g., 150 mm, 200 mm, or 300 mm. A mesh of conductive wires <b>230</b> is formed on the back surface of the dielectric handle substrate <b>720</b>. The semiconductor interposer structure <b>710</b> includes an array of semiconductor dies <b>700</b> and dicing channels between the semiconductor dies <b>700</b>. The dicing channels surround each of the semiconductor dies. Typically, the area of the dicing channels and the area of the semiconductor dies <b>700</b> complimentarily constitute the entirety of the patterned area in the semiconductor interposer structure <b>710</b>. Typically, the semiconductor dies <b>700</b> are located in a rectangular array, and the dicing channels laterally abut and laterally surround each semiconductor die <b>700</b>.

0051The area of for the mesh of the conductive wires <b>230</b> is selected so that the mesh of the conductive wires <b>230</b> underlies dicing channels between the semiconductor dies <b>700</b> in the semiconductor interposer structure <b>710</b> after bonding. Holes in the mesh of conductive wires <b>230</b> underlie a semiconductor die area in the semiconductor interposer structure <b>710</b>. The mesh of conductive wires <b>230</b> on the dielectric handle substrate <b>720</b> may be formed in the same manner as in the second embodiment with the proviso that the area of the mesh of conductive wires <b>230</b> is selected to underlie the dicing channels in the semiconductor interposer structure <b>100</b>.

0052An adhesive layer (not shown) may be applied to the front surface of the dielectric handle substrate <b>720</b> or the back surface of the semiconductor interposer structure <b>710</b>. The front surface of the dielectric handle substrate <b>720</b> and the back surface of the semiconductor interposer structure <b>710</b> are brought together with the adhesive layer therebetween as in the first embodiment. A third exemplary bonded semiconductor structure (not shown) having a similar vertical cross-sectional view as the second exemplary bonded semiconductor structure of <figref idref="DRAWINGS">FIGS. 10A and 10B</figref> is formed. The difference between the third exemplary bonded semiconductor structure and the second exemplary bonded semiconductor structure is that the the mesh of the conductive wires <b>230</b> underlies dicing channels between the semiconductor dies <b>700</b> in the semiconductor interposer structure <b>710</b>. The holes in the mesh of the conductive wires <b>230</b> underlie a semiconductor die area, i.e., the area of a semiconductor die <b>700</b>, in the semiconductor interposer structure <b>710</b>.

0053The adhesive layer of the third embodiment may, or may not, comprise a deactivatable material. In other words, the adhesive layer of the third embodiment may comprise an ultraviolet deactivatable material, a visible-spectrum-deactivatable material, an infrared-deactivatable material, or an optically stable material that does not change adhesive strength upon exposure to radiation of ultraviolet light, visible light, and infrared radiation. The same processing steps may be employed for the rest of the processing sequence as in the second embodiment.

0054The entirety of the mesh of the conductive wires <b>230</b> may be removed during dicing of a stack of a semiconductor interposer structure and a dielectric handle substrate. Within each diced structure of a semiconductor interposer die and a dielectric handle die, no portion of the mesh of the conductive wires <b>230</b> is present. Thus, no other processing step is necessary for removal of the mesh of the conductive wires <b>230</b>. Further, the semiconductor interposer die and the dielectric handle die within each diced structure separate naturally since no adhesive material is present between the semiconductor interposer die and the dielectric handle die. Thus, no processing step for deactivation of the material of the adhesive layer is needed. Moreover, any adhesive material, deactivatable or non-deactivatable, may be employed for the adhesive layer of the third embodiment of the present invention.

0055In addition to electrostatic chucking employing direct contact between an electrostatic chuck and a conductive material layer described above, the present invention further provides electrostatic chucking employing a capacitive coupling between an electrostatic chuck and a conductive material layer embedded in a substrate. In this case, electrostatic chucking is performed using either monopolar (single voltage polarity) or bipolar (positive and negative voltage polarity) electrostatic chucks. The charge on an electrostatic chuck is capacitively coupled to a dielectric substrate being chucked. Electrical charges of the opposite polarity are induced within a conductive material layer embedded or contacting the dielectric substrate even if the conductive material layer does not directly contact the electrostatic chuck. The charge build up on the chucked substrate can occur in the conductive material layer, which may be located on the surface of the dielectric substrate or embedded inside the insulating substrate.

0056Referring to <figref idref="DRAWINGS">FIG. 12</figref>, a dielectric handle substrate <b>700</b> is provided according to a fourth embodiment of the present invention. The dielectric handle substrate <b>700</b> may comprise any dielectric material that may be employed for the dielectric handled substrate <b>200</b> of the first embodiment of the present invention as described above. A conductive material layer <b>210</b> is formed by depositing a conductive material on the bottom surface of the dielectric handle substrate <b>700</b>. The conductive material layer <b>210</b> may have the same composition and thickness as in the first embodiment.

0057Referring to <figref idref="DRAWINGS">FIG. 13</figref>, the dielectric handle substrate <b>700</b> is bonded to a semiconductor interposer structure <b>100</b> employing an adhesive layer <b>150</b> in the same manner as in the first embodiment. A dielectric surface layer <b>720</b> comprising a dielectric material is deposited on the bottom surface of the conductive material layer <b>210</b>. The dielectric surface layer <b>720</b> comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a dielectric metal oxide, photosensitive polyimide, a polymer, or a combination thereof. The thickness of the dielectric surface layer <b>720</b> may be from 50 nm to 50 microns, although lesser and greater thicknesses are also contemplated herein.

0058Processing steps corresponding to <figref idref="DRAWINGS">FIGS. 3A</figref>, <b>3</b>B, and <b>4</b>-<b>9</b> in the first embodiment may be performed on the fourth exemplary semiconductor structure. Particularly, the fourth exemplary semiconductor structure may be electrostatically chucked in a process chamber including an electrostatic chuck. As described above, induced charges are formed in the conductive material layer <b>210</b> in response to electrical charges that accumulate within the electrostatic chuck. Electrical charges on the electrostatic chuck induce electrical charges of the opposite polarity in the conductive material layer <b>210</b> located on the bottom surface of the dielectric handle substrate <b>700</b>. Thus, the assembly of the semiconductor interposer structure <b>100</b>, the adhesive layer <b>150</b>, the dielectric handle substrate <b>700</b>, the conductive material layer <b>210</b>, and the dielectric surface layer <b>720</b> is electrostatically chucked to the electrostatic chuck in the processing chamber. The electrical coupling between the electrical charges in the electrostatic chuck and the electrical charges in the conductive material layer <b>210</b> is a capacitive coupling through the dielectric surface layer <b>720</b>.

0059Referring to <figref idref="DRAWINGS">FIG. 14</figref>, a handle substrate <b>800</b> including an upper dielectric handle substrate <b>805</b>, an embedded conductive material layer <b>210</b>, a lower dielectric handles substrate <b>815</b> is provided according to a fifth embodiment of the present invention. Each of the upper dielectric handle substrate <b>805</b> and the lower dielectric handle substrate <b>815</b> includes a dielectric material, which may be any of the dielectric material that may be employed for the dielectric handle substrate <b>200</b> of the first embodiment of the present invention.

0060The handle substrate <b>800</b> includes an embedded conductive material layer <b>810</b>, which comprises a conductive material such as doped semiconductor or a metallic material. The embedded conductive material layer <b>810</b> is formed between the upper dielectric handle substrate <b>805</b> and the lower dielectric handles substrate <b>815</b>. For example, the embedded conductive material layer <b>810</b> may be formed on one of the upper dielectric handle substrate <b>805</b> and the lower dielectric handles substrate <b>815</b>. The other of the upper dielectric handle substrate <b>805</b> and the lower dielectric handles substrate <b>815</b> may then be bonded to a surface of the embedded conductive material layer <b>810</b> to form the handle substrate <b>810</b>. The embedded conductive material layer <b>810</b> may include the same material as the conductive material layer <b>210</b> of the first embodiment. The thickness of the embedded conductive material layer <b>810</b> may be from 10 nm to 50 microns, although lesser and greater thicknesses are also contemplated herein.

0061Referring to <figref idref="DRAWINGS">FIG. 13</figref>, the dielectric handle substrate <b>800</b> is bonded to a semiconductor interposer structure <b>100</b> employing an adhesive layer <b>150</b> in the same manner as in the first embodiment. In one case, a dielectric surface layer <b>720</b> comprising a dielectric material is deposited on the bottom surface of the handle substrate <b>800</b>. The dielectric surface layer <b>720</b> comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a dielectric metal oxide, photosensitive polyimide, a polymer, or a combination thereof. The thickness of the dielectric surface layer <b>720</b> may be from 50 nm to 50 microns, although lesser and greater thicknesses are also contemplated herein. The dielectric surface layer <b>720</b> is optional. Formation of a dielectric surface layer <b>720</b> may be omitted in some other cases.

0062Processing steps corresponding to <figref idref="DRAWINGS">FIGS. 3A</figref>, <b>3</b>B, and <b>4</b>-<b>9</b> in the first embodiment may be performed on the fifth exemplary semiconductor structure. Particularly, the fifth exemplary semiconductor structure may be electrostatically chucked in a process chamber including an electrostatic chuck. As described above, induced charges are formed in the embedded conductive material layer <b>810</b> in response to electrical charges that accumulate within the electrostatic chuck. Electrical charges on the electrostatic chuck induce electrical charges of the opposite polarity in the embedded conductive material layer <b>810</b> within the handle substrate <b>800</b>. Thus, the assembly of the semiconductor interposer structure <b>100</b>, the adhesive layer <b>150</b>, the upper dielectric handle substrate <b>805</b>, the embedded conductive material layer <b>810</b>, the lower dielectric handle substrate <b>815</b>, and the optional dielectric surface layer <b>720</b> is electrostatically chucked to the electrostatic chuck <b>900</b> in the processing chamber <b>990</b> as illustrated in <figref idref="DRAWINGS">FIG. 15A</figref>. The electrical coupling between the electrical charges in the electrostatic chuck and the electrical charges in the embedded conductive material layer <b>810</b> is a capacitive coupling through the lower dielectric handle substrate <b>815</b> and the optional dielectric surface layer <b>720</b>.

0063While the invention has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the invention is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the invention and the following claims.