Method for growing semiconductor layer, method for producing semiconductor light-emitting element, semiconductor light-emitting element, and electronic device

CROSS REFERENCES TO RELATED APPLICATIONS

0001The present invention contains subject matter related to Japanese Patent Application JP 2007-133340 filed in the Japan Patent Office on May 18, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a method for growing semiconductor layers, a method for producing a semiconductor light-emitting element, a semiconductor light-emitting element, and an electronic device. More particularly, the present invention relates to a III-V nitride compound semiconductor light-emitting diode and a variety of apparatus and equipment provided with the light-emitting diode.

00042. Description of the Related Art

0005The existing method for producing a light-emitting diode based on a GaN semiconductor is mostly by growing an n-type layer, an active layer, and a GaN semiconductor layer including a layer on the (0001) plane (or C-plane) of a sapphire substrate by the MOCVD process (Metal Organic Chemical Vapor Deposition), with orientation in the C axis.

0006Unfortunately, when grown on the (0001) plane (or C-plane) of a sapphire substrate, the pseudomorphic quantum well layer of InGaN oriented in the C axis suffers the disadvantage that a large piezoelectric field occurs in the direction perpendicular to the well plane (or the C axis direction), thereby spatially separating electrons and holes from each other and reducing the probability of electron-hole recombination (which is known as the quantum confined Stark effect). The result is a decrease in internal quantum efficiency in a light-emitting diode based on InGaN/GaN, which in turn leads to a decrease in external quantum efficiency. This is one cause to impede improvement in the light-emitting output.

0007One way to suppress the quantum confined Stark effect in the active layer is to grow a GaN semiconductor layer with the (11-20) plane (or A-plane) on a sapphire substrate with the (1-102) plane (or R-plane). Unfortunately, the GaN semiconductor layer with the (11-20) plane has many threading dislocations which deteriorate its crystal quality.

0008There has been proposed in Japanese Patent Laid-Open No. Hei 11-112029 (hereinafter referred to as Patent Document 1) a method for suppressing the quantum confined Stark effect in a semiconductor light-emitting element which is produced by growing a plurality of GaN semiconductor layers including a pseudomorphic quantum well layer. According to the proposed method, the pseudomorphic quantum well layer is grown in a plane direction differing from that in which the piezoelectric field is maximum. In the case where the GaN semiconductor layer has the wurtzite crystal structure, such a plane direction is oblique more than 1° (say, 40°, 90°, or 140°) from the [0001] direction. A semiconductor light-emitting element produced by the foregoing method is shown in <figref idref="DRAWINGS">FIG. 39</figref>. It includes a substrate <b>101</b> of SiC or GaN, a buffer layer (not shown) of AlN, a contact layer <b>102</b> of n-type GaN, a cladding layer <b>103</b> of n-type AlGaN, a multiple quantum well layer <b>104</b> of GaInN/GaN or GaInN/GaInN, a cladding layer <b>105</b> of p-type AlGaN, and a contact layer <b>106</b> of p-type GaN, which are sequentially grown one over the other. The contact layer <b>102</b> and the cladding layer <b>103</b> are grown in the {0001} plane direction. The multiple quantum well layer <b>104</b> is grown on the {2-1-14} plane or {01-12} plane which has been formed by selective growing or selecting etching on the cladding layer <b>103</b>. The <b>104</b><i>a </i>and <b>104</b><i>b </i>planes on which the multiple quantum well layer <b>104</b> is grown coincide with the {2-1-14} plane or {01-12} plane. The cladding layer <b>105</b> and the contact layer <b>106</b> change in crystal structure as they grow, with their plane direction switched from that of the multiple quantum well layer <b>104</b> to the {0001} plane direction. Incidentally, the reference numerals <b>107</b> and <b>108</b> denote a p-side electrode and an n-side electrode, respectively.

0009The existing semiconductor light-emitting element as shown in <figref idref="DRAWINGS">FIG. 39</figref> permits the multiple quantum well layer <b>104</b> as an active layer to decrease in piezoelectric field; however, it suffers the disadvantage that it is not typically easy in practice to grow under good control the multiple quantum well layer <b>104</b> with the oblique facet of the {2-1-14} plane or {01-12} plane. Therefore, it presents difficulties in its efficient production.

0010The present invention was completed to address the foregoing problems. Thus it is an aim of the present invention to provide a method for growing semiconductor layers on a substrate such that the plane direction or the growing plane facet can be selected as desired, or the semiconductor layers can be made to decrease in piezoelectric field and to improve in crystal quality according to need.

0011It is another aim of the present invention to provide an easy-to-produce semiconductor light-emitting element and a method for producing the same. This aim is achieved by employing the above-mentioned method for growing semiconductor layers at the time of growing the semiconductor layers to form the light-emitting element structure. The resulting semiconductor light-emitting element is identified by good crystal quality of semiconductor layers and reduced quantum confined Stark effect in active layers.

0012It is further another aim of the present invention to provide a high-performance electronic device equipped with outstanding semiconductor light-emitting elements as mentioned above.

SUMMARY OF THE INVENTION

0013The first mode of the present invention is directed to a method for growing a semiconductor layer which includes growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.

0014The method according to the first mode of the present invention is carried out typically in such a way that the semiconductor layer grows with the facets of the (11-20) plane, the (0001) plane, and the (11-22) plane facing outward, or with the facets of the (1-100) plane, the (0001) plane, and the (10-13) plane facing outward.

0015The semiconductor is formed from a semiconductor layer of hexagonal crystal structure, typically one which has the wurtzite crystal structure. Examples of the semiconductor having the wurtzite crystal structure include III-V nitride compound semiconductors, oxide semiconductors, and α-ZnS (not restrictive).

0016The III-V nitride compound semiconductors is represented commonly by Al_xB_yGa_1-x-y-zIn_zAs_uN_1-u-vP_v(where 0≦x≦1, 0≦y≦1, 0≦z≦1, 0≦u≦1, 0≦v≦1, 0≦x+y+z&lt;1, and 0≦u+v&lt;1).

0017It is represented more specifically by Al_xB_yGa_1-x-y-zIn_zN (where 0≦x≦1, 0≦y≦1, 0≦z≦1, and 0≦x+y+z&lt;1).

0018It is represented typically by Al_xGa_1-x-zIn_zN (where 0≦x≦1, and 0≦z≦1).

0019Its typical examples include GaN, InN, AlN, AlGaN, InGaN, and AlGaInN. The III-V nitride compound semiconductor (e.g., GaN) has its dislocations bent when it is doped with B or Cr. Therefore, it may be BGaN, GaN:B (B-doped GaN), or GaN:Cr (Cr-doped GaN).

0020Preferred example of the III-V nitride compound semiconductor include GaN, In_xGa_1-xN (0&lt;x&lt;0.5), Al_xGa_1-xN (0&lt;x&lt;0.5), and Al_xIn_yGa_1-x-yN (0&lt;x&lt;0.5, 0&lt;y&lt;0.2).

0021The so-called low-temperature buffer layer to be grown first on the substrate is usually a GaN buffer layer, AlN buffer layer, or AlGaN buffer layer, with or without Cr doping. It also includes a CrN buffer layer.

0022Examples of the oxide semiconductor include titanium (IV) oxide (TiO₂), vanadium (V) oxide (V₂O₅), chromium (III) oxide (Cr₂O₃), manganese (II) oxide (MnO), iron (III) oxide (Fe₂O₃), tricobalt (II) tetraoxide (Co₃O₄), nickel (II) oxide (NiO), copper (I) oxide (Cu₂O), zinc (II) oxide (ZnO), tin (IV) oxide (SnO₂), gallium (III) oxide (Ga₂O₃), indium (III) oxide (In₂O₃), bismuth (III) oxide (Bi₂O₃), strontium (II) oxide (SrO), strontium titanate (SrTiO₃), barium titanate (BaTiO₃), and yttrium oxide (Y₂O₃). An additional example is oxychalcogenide LnCuOOCh (Ln=La, Ce, Nd, Pr; Ch=S, Se, Te), such as CuAlO and SrCu₂O₂. They are not restrictive.

0023The semiconductor layer may be grown by any epitaxial method, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy, halide vapor phase epitaxy growth (HVPE), and molecular beam epitaxy (MBE). Adequate one of them is selected according to need.

0024Examples of the substrate of hexagonal crystal structure include sapphire, SiC (including 6H and 4H), α-ZnS, and ZnO. Substrates of III-V nitride compound semiconductor (such as GaN, AlGaInN, AlN, and GaInN) may also be used. An alternative substrate may be a substance of hexagonal crystal structure which has been grown on a substrate differing from the substance of hexagonal crystal structure.

0025The substrate may be one whose one principal plane is the (1-100) plane or one which has at least one hollow part (groove) (typically a plurality of hollow parts (grooves)) on the principal plane such that one side of the hollow part is the (1-100) plane.

0026The substrate whose one principal plane is the (1-100) plane should preferably have more than one raised part which is formed thereon from a material different from or identical with the substrate. In this case, the semiconductor layer begins to grow from the bottom of the hollow part between the raised parts. Typically, the raised parts and the hollow parts are formed periodically and alternately on the substrate. The intervals of the raised parts and hollow parts are 3 to 5 μm (not restrictive). The raised parts and hollow parts should be formed such that the ratio of their bases is 0.5 to 3 (not restrictive). The height of the raised part from the substrate should be greater than 0.3 μm, preferably greater than 1 μm (not restrictive). The raised part should have a side oblique to the principal plane of the substrate (for example, a side which is in contact with one principal plane of the substrate). The angle (θ) between the side and the principal plane of the substrate should be 120°&lt;θ&lt;150°, preferably 140°, from the standpoint of efficient light emission (not restrictive). The raised part may have any cross section, such as triangle, square, pentagon, hexagon, circle, and ellipse, and it may also have a flat or curved side. Of these cross sections, a triangle (with or without its apex truncated or rounded) is desirable. The hollow part may also have any cross section, such as triangle, square, pentagon, hexagon, circle, and ellipse. Of these cross sections, an inverted trapezoid is desirable from the standpoint of efficient light emission. The inverted trapezoid ss that of accurate shape as well as approximate shape (the same shall apply hereinafter). The height of the raised part (or the depth of the hollow part), which is denoted by d, should be 0.5 μm&lt;d&lt;5 μm, typically 1.0±0.2 μm (not restrictive). The raised parts with an excessively large value of d prevent sufficient supply of raw material gas to the hollow parts, thereby hampering the growth of the semiconductor layer from the bottom of the hollow part. Conversely, the raised parts with an excessively small value of d cause the semiconductor layer to grow not only from the bottom of the hollow part but also from the side of the raised part. The width (W_g) of the hollow part is 0.5 to 5 μm, typically 2±0.5 μm (not restrictive). The width (W_t) of the raised part with a trapezoidal cross section is 1 to 1000 μm, typically 4±2 μm (not restrictive).

0027The raised parts and the hollow parts may extend straight in one direction in parallel to each other on the substrate. Alternatively, they may extend straight in different directions on the substrate so that they form two-dimensional patterns, such as polygons (triangle, square, pentagon, hexagon, etc., with or without their apexes truncated), circle, ellipse, and dot. A preferred example is a honeycomb pattern composed of hexagons, each side being the raised part surrounded by the hollow part. This structure permits the active layer to emanate light in all directions (360°). Another preferred example is a honeycomb pattern composed of hexagons, each side being the hollow part surrounded by the raised part. In this case, the raised part may be a triangular pyramid, square pyramid, pentagonal pyramid, hexagonal pyramid, cone, elliptic cone, etc. (with or without their apexes truncated or rounded).

0028The raised part may be formed any material, conductive or non-conductive, such as dielectric material of oxide, nitride, and carbide, and conductive material (including transparent one) of metal and alloy. The oxides include silicon oxide (SiO_x), titanium oxide (TiO_x), and tantalum oxide (TaO_x). They may be used in combination with one another in the form of laminate film. The nitrides include silicon nitride (SiN_x, including Si₃N₄), SiON, CrN, and CrNO. They may be used in combination with one another in the form of laminate film. The carbides include SiC, HfC, ZrC, WC, TiC, and CrC. They may be used in combination with one another in the form of laminate film. The metals and alloys include B, Al, Ga, In, W, Ni, Co, Pd, Pt, Ag, AgNi, AgPd, AuNi, and AuPd. They may be used in combination with one another in the form of laminate film. The transparent conducting materials include ITO (indium-tin compound oxide), IZO (indium-zinc compound oxide), ZO (zinc oxide), FTO (fluorine-doped tin oxide) and tin oxide. They may be used in combination with one another in the form of laminate film. Moreover, the foregoing materials may be used in combination with one another in the form of laminate film. Alternatively, the nitride, oxide, or carbide may be formed by forming the raised part from metal and then nitriding, oxidizing, or carbonizing at least the surface thereof.

0029The second mode of the present invention is directed to a method for growing a semiconductor layer which includes growing on the (1-102) plane of a substrate of hexagonal crystal structure a semiconductor layer of hexagonal crystal structure having the (11-20) plane direction such that at least one facet faces outward which is selected from those of the (11-22) plane, (0001) plane, (000-1) plane, (33-62) plane, and (1-100) plane.

0030According to the second mode of the present invention, a semiconductor layer is grown while forming the (11-22) plane facet, (0001) plane facet, and (000-1) plane facet, or while forming the (11-22) plane facet, (1-100) plane facet, and (33-62) plane facet, or while forming the (1-100) plane facet, or while forming the (1-100) plane facet and (11-20) plane facet.

0031What is mentioned above about the first mode of the present invention is applicable to the second mode of the present invention except for restrictions mentioned above.

0032The third mode of the present invention is directed to a method for producing a semiconductor light-emitting element which includes growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure.

0033The semiconductor light-emitting element is constructed of semiconductor layers including an n-type layer, an active layer, and a p-type layer. Typically, all the semiconductor layers, including the active layer, are those of hexagonal crystal structure. The semiconductor light-emitting element is a light-emitting diode or a semiconductor laser.

0034The substrate may be left attached to or removed from the eventually formed semiconductor light-emitting element.

0035What is mentioned above about the first mode of the present invention is applicable to the third mode of the present invention except for restrictions mentioned above.

0036The fourth mode of the present invention is directed to a method for producing a semiconductor light-emitting element which includes growing on the (1-102) plane of a substrate of hexagonal crystal structure a semiconductor layer of hexagonal crystal structure having the (11-20) plane direction such that at least one facet faces outward which is selected from those of the (11-22) plane, (0001) plane, (000-1) plane, (33-62) plane, and (1-100) plane.

0037What is mentioned above about the first mode of the present invention is applicable to the fourth mode of the present invention except for restrictions mentioned above.

0038The fifth mode of the present invention is directed to a semiconductor light-emitting element which includes a substrate of hexagonal crystal structure and a semiconductor layer grown on the (1-100) plane thereof which has the (11-22) or (10-13) plane direction.

0039The sixth mode of the present invention is directed to a semiconductor light-emitting element which includes a semiconductor layer which is formed from a semiconductor of hexagonal crystal structure and has the (11-22) or (10-13) plane direction.

0040The seventh mode of the present invention is directed to an electronic device having one or more semiconductor light-emitting elements wherein at least one of the semiconductor light-emitting elements is composed of a substrate of hexagonal crystal structure and a semiconductor layer of hexagonal crystal structure grown on the (1-100) plane thereof which has the (11-22) or (10-13) plane direction.

0041The eighth mode of the present invention is directed to an electronic device having one or more semiconductor light-emitting elements wherein at least one of the semiconductor light-emitting elements is a semiconductor layer of hexagonal crystal structure which has the (11-22) or (10-13) plane direction.

0042What is mentioned above about the first and third modes of the present invention is applicable to the fifth to eighth modes of the present invention except for restrictions mentioned above.

0043The electronic device is exemplified by LED backlight (for liquid crystal display), LED illuminator, LED display, LED projector, LED rear projection TV, and grating light valve (GLV). It broadly includes those (either portable and stationary) which have at least one semiconductor light-emitting element for display, illumination, optical communications, and light transmission. Typical examples are portable telephones, mobile machines, robots, personal computers, on-vehicle equipment, home electric appliances, LED optical communications equipment, LED light transmission equipment, and portable security equipment (such as electronic key).

0044The electronic device also includes those which are composed of semiconductor light-emitting elements capable of emitting more than one kind of light differing in waveband, such as far infrared, infrared, red, yellow, green, blue, violet, and ultraviolet. LED illuminators with more than one kind of LED capable of emitting visible light differing in waveband, such as red, yellow, green, blue, and violet, produce natural light or white light composed of such visible lights.

0045The semiconductor light-emitting element that emits at least one waveband of blue, violet, and ultraviolet can be used as a light source to excite a phosphor which produces natural light or white light.

0046The LEDs capable of emitting visible light of different wavebands may be combined into a unit and a plurality of such units may be arranged (two-dimensionally for an array or linearly for one or more lines) on a substrate or frame. The unit may be referred to as cell unit, quartet unit, or cluster unit (which contains an undefined number of LEDs but consists of a plurality of LEDs emitting identical or different wavebands). To be specific, the unit consists of three LEDs (one each for red, green, and blue), four LEDs (one for red, two for green, and one for blue), or five or more LEDs.

0047The semiconductor light-emitting element according to the fifth or sixth mode of the present invention may be used as at least one of the semiconductor light-emitting elements for red, green, and blue light for the backlight, illuminator, display, or light-source cell unit to be arranged on a substrate. The semiconductor of AlGaInP may be used as the light-emitting element for red light.

0048The semiconductor light-emitting element and the method for production thereof according to the third to sixth modes of the present invention may be applicable to semiconductor elements in general, such as ordinary LED, inter-subband transition light emitting type (quantum cascade type) LED, ordinary semiconductor laser, and inter-subband transition light emitting type (quantum cascade type) semiconductor laser. Additional examples other than light-emitting elements are electron transit elements, such as photodiode (photodetector and sensor), solar cell, and transistors including high electron mobility transistor typified by field effect transistor (FET) and bipolar transistor typified by heterojunction bipolar transistor (HBT).

0049The present invention mentioned above offers the following advantages. If the substrate has the (1-100) plane, the semiconductor layer can be grown in the (11-12) or (10-13) plane direction. If the substrate has the (1-102) plane, the semiconductor layer can be grown in the (11-20) plane direction, with at least one facet facing outward which is selected from those of the (11-22) plane, (0001) plane, (000-1) plane, (33-62) plane, and (1-100) plane. The semiconductor layer with the adequately selected plane direction and growth plane facet has a suppressed piezoelectric field and an improved crystal quality. In addition, the semiconductor layer can be grown easily under adequately established conditions.

EFFECT OF THE INVENTION

0050According to the present embodiment, the semiconductor layer can be grown on a substrate in a desired plane direction with a desired growth plane facet, and the resulting semiconductor layer has a suppressed piezoelectric field and an improved crystal quality. The method for growing the semiconductor layer can be applied to the growth of the semiconductor layers as the constituents of the light-emitting element, and the resulting semiconductor layer has an improved crystal quality and a suppressed quantum confined Stark effect in the active layer. The semiconductor light-emitting element can be produced more easily than that disclosed in Patent Document 1. The high-performance semiconductor element can be used to realize a variety of electronic equipment such as high-performance backlight, illuminator, and display.

BRIEF DESCRIPTION OF THE DRAWINGS

0051<figref idref="DRAWINGS">FIG. 1</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0052<figref idref="DRAWINGS">FIG. 2</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0053<figref idref="DRAWINGS">FIG. 3</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0054<figref idref="DRAWINGS">FIGS. 4A to 4B</figref> are schematic diagrams showing the result of X-ray diffractometry performed on a GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0055<figref idref="DRAWINGS">FIG. 5</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the second embodiment of the present invention;

0056<figref idref="DRAWINGS">FIG. 6</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the second embodiment of the present invention;

0057<figref idref="DRAWINGS">FIG. 7</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0058<figref idref="DRAWINGS">FIGS. 8A to 8C</figref> are schematic diagrams showing the result of X-ray diffractometry performed on a GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the first embodiment of the present invention;

0059<figref idref="DRAWINGS">FIG. 9</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0060<figref idref="DRAWINGS">FIG. 10</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0061<figref idref="DRAWINGS">FIG. 11</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0062<figref idref="DRAWINGS">FIG. 12</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0063<figref idref="DRAWINGS">FIG. 13</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0064<figref idref="DRAWINGS">FIG. 14</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0065<figref idref="DRAWINGS">FIG. 15</figref> is an electron micrograph showing a sample of GaN layer which has been grown by the method for growing the III-V nitride compound semiconductor layer according to the third embodiment of the present invention;

0066<figref idref="DRAWINGS">FIG. 16</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the fourth embodiment of the present invention;

0067<figref idref="DRAWINGS">FIG. 17</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the fifth embodiment of the present invention;

0068<figref idref="DRAWINGS">FIG. 18</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the sixth embodiment of the present invention;

0069<figref idref="DRAWINGS">FIG. 19</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the seventh embodiment of the present invention;

0070<figref idref="DRAWINGS">FIG. 20</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the eighth embodiment of the present invention;

0071<figref idref="DRAWINGS">FIG. 21</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the ninth embodiment of the present invention;

0072<figref idref="DRAWINGS">FIG. 22</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the tenth embodiment of the present invention;

0073<figref idref="DRAWINGS">FIG. 23</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the eleventh embodiment of the present invention;

0074<figref idref="DRAWINGS">FIG. 24</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the twelfth embodiment of the present invention;

0075<figref idref="DRAWINGS">FIG. 25</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the thirteenth embodiment of the present invention;

0076<figref idref="DRAWINGS">FIG. 26</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the fourteenth embodiment of the present invention;

0077<figref idref="DRAWINGS">FIG. 27</figref> is a schematic diagram illustrating the method for growing the III-V nitride compound semiconductor layer according to the fifteenth embodiment of the present invention;

0078<figref idref="DRAWINGS">FIGS. 28A to 28C</figref> are schematic diagrams illustrating the method for producing a light-emitting diode according to the sixteenth embodiment of the present invention;

0079<figref idref="DRAWINGS">FIG. 29</figref> is a schematic diagram illustrating the method for producing a light-emitting diode according to the sixteenth embodiment of the present invention;

0080<figref idref="DRAWINGS">FIGS. 30A to 30C</figref> are schematic diagrams illustrating the method for producing a light-emitting diode according to the seventeenth embodiment of the present invention;

0081<figref idref="DRAWINGS">FIGS. 31A to 31C</figref> are schematic diagrams illustrating the method for producing a light-emitting diode backlight according to the eighteenth embodiment of the present invention;

0082<figref idref="DRAWINGS">FIG. 32</figref> is a schematic diagram illustrating the method for producing a light-emitting diode backlight according to the eighteenth embodiment of the present invention;

0083<figref idref="DRAWINGS">FIG. 33</figref> is a schematic diagram illustrating the method for producing a light-emitting diode backlight according to the eighteenth embodiment of the present invention;

0084<figref idref="DRAWINGS">FIG. 34</figref> is a schematic diagram illustrating the method for producing a light-emitting diode backlight according to the nineteenth embodiment of the present invention;

0085<figref idref="DRAWINGS">FIGS. 35A to 35B</figref> are plan views showing the light source cell unit according to the twentieth embodiment of the present invention and an enlarged view of the light source cell unit;

0086<figref idref="DRAWINGS">FIG. 36</figref> is a plan view showing a typical example of the light source cell unit according to the twentieth embodiment of the present invention;

0087<figref idref="DRAWINGS">FIG. 37</figref> is a plan view showing another typical example of the light source cell unit according to the twentieth embodiment of the present invention;

0088<figref idref="DRAWINGS">FIG. 38</figref> is a plan view showing another example of the structure of the light source unit cell according to the twentieth embodiment of the present invention; and

0089<figref idref="DRAWINGS">FIG. 39</figref> is a sectional view showing the semiconductor light-emitting element proposed in Patent Document 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

0090In what follows, the embodiments of the present invention are described in more detail with reference to the accompanying drawings, in which identical or corresponding parts are designated by the same symbols.

0091The first embodiment of the present invention, which is illustrated in <figref idref="DRAWINGS">FIG. 1</figref>, is concerned with a basic method for growing a III-V nitride compound semiconductor layer.

0092According to the first embodiment, the sapphire substrate <b>11</b>, whose principal plane is the (1-100) plane (or M-plane), permits the growth thereon of the III-V nitride compound semiconductor layer <b>12</b> having the (11-22) plane direction. The sapphire substrate <b>11</b> has the raised parts <b>13</b> extending straight in one direction, which have been previously formed thereon from SiO₂or SiN. The sapphire substrate <b>11</b> and the III-V nitride compound semiconductor layer <b>12</b> have the crystal orientation indicated in <figref idref="DRAWINGS">FIG. 1</figref>. The III-V nitride compound semiconductor layer <b>12</b> may be grown by the MOCVD process, for example.

0093The III-V nitride compound semiconductor layer <b>12</b> in its initial stage of growth is shown in <figref idref="DRAWINGS">FIG. 2</figref>. It grows with its facets orienting in the (11-20) plane (or A-plane), the (0001) plane (or C-plane), and the (11-22) plane. In this case, its growth in the direction of C axis is limited.

0094The III-V nitride compound semiconductor layer <b>12</b> is grown under the following conditions. <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0095">Growth rate: 0.5 to 8 μm/h</li><li id="ul0001-0002" num="0096">Flow rate of trimethylgallium (CH₃)₃Ga, TMG, or trimethylindium (CH₃)₃In, TMI, as the source of III group element:</li><li id="ul0001-0003" num="0097">10 to 90 sccm</li><li id="ul0001-0004" num="0098">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0001-0005" num="0099">Growth temperature: 950 to 1250° C.</li><li id="ul0001-0006" num="0100">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0001-0007" num="0101">Growth pressure: 0.01 to 1 atm.</li></ul>

0102<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process, the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>. The GaN layer is a continuous film which has resulted from growth via the stage shown in <figref idref="DRAWINGS">FIG. 2</figref>. The sample with the GaN layer grown to the stage shown in <figref idref="DRAWINGS">FIG. 3</figref> was examined by X-ray diffractometry. The GaN layer gave diffraction peaks due to the (11-20) plane (or A-plane) and the (11-22) plane as shown in <figref idref="DRAWINGS">FIGS. 4A and 4B</figref>, respectively.

0103The second embodiment of the present invention, which is illustrated in <figref idref="DRAWINGS">FIG. 5</figref>, is concerned with a basic method for growing a III-V nitride compound semiconductor layer.

0104According to the second embodiment, the sapphire substrate <b>11</b>, whose principal plane is the (1-100) plane (or M-plane), permits the growth thereon of the III-V nitride compound semiconductor layer <b>12</b> having the (10-13) plane direction. The sapphire substrate <b>11</b> has the raised parts <b>13</b> in the same way as in the first embodiment. The sapphire substrate <b>11</b> and the III-V nitride compound semiconductor layer <b>12</b> have the crystal orientation indicated in <figref idref="DRAWINGS">FIG. 5</figref>. The III-V nitride compound semiconductor layer <b>12</b> may be grown by the MOCVD process, for example.

0105The III-V nitride compound semiconductor layer <b>12</b> in its initial stage of growth is shown in <figref idref="DRAWINGS">FIG. 6</figref>. It grows with its facets facing outward from the (1-100) plane (or M-plane), the (0001) plane (or C-plane), and the (10-13) plane. In this case, its growth in the direction of A axis is limited.

0106The III-V nitride compound semiconductor layer <b>12</b> is grown under the following conditions. <ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0107">Growth rate: 0.5 to 8 μm/h</li><li id="ul0002-0002" num="0108">Flow rate of TMG or TMI as the source of III group element: 10 to 90 sccm</li><li id="ul0002-0003" num="0109">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0002-0004" num="0110">Growth temperature: 950 to 1250° C.</li><li id="ul0002-0005" num="0111">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0002-0006" num="0112">Growth pressure: 0.01 to 1 atm.</li></ul>

0113<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process, the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>. The sample with the GaN layer grown to the stage shown in <figref idref="DRAWINGS">FIG. 6</figref> was examined by X-ray diffractometry. The GaN layer gave diffraction peaks due to the (1-100) plane, the (10-13) plane, and the (0001) plane (or C-plane) as shown in <figref idref="DRAWINGS">FIGS. 8A</figref>, <b>8</b>B, and <b>8</b>C, respectively.

0114The third embodiment of the present invention, which is illustrated in <figref idref="DRAWINGS">FIG. 9</figref>, is concerned with a basic method for growing a III-V nitride compound semiconductor layer.

0115According to the third embodiment, the sapphire substrate <b>11</b>, whose principal plane is the (1-102) plane (or R-plane), permits the growth thereon of the III-V nitride compound semiconductor layer <b>12</b> having the (11-20) plane direction. The sapphire substrate <b>11</b> has the raised parts <b>13</b> in the same way as in the first embodiment. The sapphire substrate <b>11</b> and the III-V nitride compound semiconductor layer <b>12</b> have the crystal orientation indicated in <figref idref="DRAWINGS">FIG. 9</figref>. The III-V nitride compound semiconductor layer <b>12</b> may be grown by the MOCVD process, for example.

0116The III-V nitride compound semiconductor layer <b>12</b> in its initial stage of growth is shown in <figref idref="DRAWINGS">FIG. 10</figref>. In the first example, it grows with its facets facing outward from the (0001) plane (or C-plane) and the (000-1) plane. In the second example, it grows with its facets facing outward from the (11-20) plane, the (33-62) plane, and the (000-1) plane. In the latter case, its growth in the direction of C axis is limited.

0117The III-V nitride compound semiconductor layer <b>12</b> is grown under the following conditions.

0000In the first example:

0000<ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0118">Growth rate: 0.5 to 8 μm/h</li><li id="ul0003-0002" num="0119">Flow rate of TMG or TMI as the source of III group element:</li><li id="ul0003-0003" num="0120">10 to 90 sccm</li><li id="ul0003-0004" num="0121">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0003-0005" num="0122">Growth temperature: 800 to 950° C.</li><li id="ul0003-0006" num="0123">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0003-0007" num="0124">Growth pressure: 0.01 to 1 atm. <br /> In the second example: </li><li id="ul0003-0008" num="0125">Growth rate: 0.5 to 8 μm/h</li><li id="ul0003-0009" num="0126">Flow rate of TMG or TMI as the source of III group element: 10 to 90 sccm</li><li id="ul0003-0010" num="0127">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0003-0011" num="0128">Growth temperature: 950 to 1250° C.</li><li id="ul0003-0012" num="0129">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0003-0013" num="0130">Growth pressure: 0.01 to 1 atm.</li></ul>

0131<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process (with its facet according to the first example), the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>. <figref idref="DRAWINGS">FIG. 12</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process (with its facet according to the second example), the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>.

0132The III-V nitride compound semiconductor layer <b>12</b> in its initial stage of growth according to the third and fourth embodiments is shown in <figref idref="DRAWINGS">FIG. 13</figref>. In the third embodiment, it grows with its facets facing outward from the (1-100) plane. In the fourth embodiment, it grows with its facets facing outward from the (11-20) plane at the top plane and the (1-100) plane at other planes. In the latter case, its growth in the direction of A axis is limited.

0133The III-V nitride compound semiconductor layer <b>12</b> is grown under the following conditions.

0000In the third example:

0000<ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0134">Growth rate: 0.5 to 8 μm/h</li><li id="ul0004-0002" num="0135">Flow rate of TMG or TMI as the source of III group element: 10 to 90 sccm</li><li id="ul0004-0003" num="0136">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0004-0004" num="0137">Growth temperature: 800 to 950° C.</li><li id="ul0004-0005" num="0138">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0004-0006" num="0139">Growth pressure: 0.01 to 1 atm. <br /> In the fourth example: </li><li id="ul0004-0007" num="0140">Growth rate: 0.5 to 8 μm/h</li><li id="ul0004-0008" num="0141">Flow rate of TMG or TMI as the source of III group element:</li><li id="ul0004-0009" num="0142">10 to 90 sccm</li><li id="ul0004-0010" num="0143">Flow rate of NH₃as the source of nitrogen: 5 to 30 slm</li><li id="ul0004-0011" num="0144">Growth temperature: 950 to 1250° C.</li><li id="ul0004-0012" num="0145">Ratio of V/III in source for growth: 1000 to 15000</li><li id="ul0004-0013" num="0146">Growth pressure: 0.01 to 1 atm.</li></ul>

0147<figref idref="DRAWINGS">FIG. 14</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process (with its facet according to the third example), the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>. <figref idref="DRAWINGS">FIG. 15</figref> is a cross-sectional transmission electron micrograph showing a sample composed of a sapphire substrate <b>11</b> and a GaN layer grown thereon by the MOCVD process (with its facet according to the fourth example), the GaN layer functioning as the III-V nitride compound semiconductor layer <b>12</b>.

0148The fourth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0149The growing method according to the fourth embodiment shown in <figref idref="DRAWINGS">FIG. 16</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is +60° off toward the C-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the first embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 16</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (11-20) plane (or A-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0150The fifth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0151The growing method according to the fifth embodiment shown in <figref idref="DRAWINGS">FIG. 17</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −60° off toward the C-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the first embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 17</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (0001) plane (or C-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth but it is oblique to the top of the III-V nitride compound semiconductor layer <b>12</b> and hence there are less dislocations that reach the surface of the III-V nitride compound semiconductor layer <b>12</b> than in the case where the III-V nitride compound semiconductor layer <b>12</b> grows on the C-plane of the sapphire substrate.

0152The sixth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0153The growing method according to the sixth embodiment shown in <figref idref="DRAWINGS">FIG. 18</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −120° off toward the C-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the first embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 18</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (11-20) plane (or A-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0154The seventh embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0155The growing method according to the seventh embodiment shown in <figref idref="DRAWINGS">FIG. 19</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is +60° off toward the A-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the second embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 19</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (1-100) plane (or M-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0156The eighth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0157The growing method according to the eighth embodiment shown in <figref idref="DRAWINGS">FIG. 20</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −60° off toward the C-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the second embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 20</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (0001) plane (or C-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth but only those dislocations that occur from the side <b>14</b><i>a </i>of the hollow part <b>14</b> reach the surface of the III-V nitride compound semiconductor layer <b>12</b> and hence there are less dislocations that reach the surface of the III-V nitride compound semiconductor layer <b>12</b> than in the case where the III-V nitride compound semiconductor layer <b>12</b> grows on the C-plane of the sapphire substrate.

0158The ninth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0159The growing method according to the ninth embodiment shown in <figref idref="DRAWINGS">FIG. 21</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −120° off toward the C-axis from the M-plane. This etching forms a hollow part <b>14</b>, with a cross section of trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the M-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the second embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 21</figref> takes place from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (1-100) plane (or M-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the M-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0160The tenth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0161The growing method according to the tenth embodiment shown in <figref idref="DRAWINGS">FIG. 22</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is +90° off toward the C-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of rectangle, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment. Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 22</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (000-1) plane. In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0162The eleventh embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0163The growing method according to the eleventh embodiment shown in <figref idref="DRAWINGS">FIG. 23</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −90° off toward the C-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of rectangle, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment (the first example). Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 23</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (0001) plane (or the C-plane). In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0164The twelfth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0165The growing method according to the twelfth embodiment shown in <figref idref="DRAWINGS">FIG. 24</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −80° off toward the C-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment (the second example). Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 24</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (33-62) plane. In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth and hence there are very few dislocations that reach the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0166The thirteenth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0167The growing method according to the thirteenth embodiment shown in <figref idref="DRAWINGS">FIG. 25</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is −30° off toward the C-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment (the first example). Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 25</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (11-22) plane. In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth but this direction is oblique to the top of the III-V nitride compound semiconductor layer <b>12</b> and hence there are very few dislocations that reach the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0168The fourteenth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0169The growing method according to the fourteenth embodiment shown in <figref idref="DRAWINGS">FIG. 26</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is ±30° off toward the A-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment (the third example). Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 26</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (1-100) plane. In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth but this direction is oblique to the top of the III-V nitride compound semiconductor layer <b>12</b> and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0170The fifteenth embodiment of the present invention mentioned below is concerned with a method for growing a III-V nitride compound semiconductor layer.

0171The growing method according to the fifteenth embodiment shown in <figref idref="DRAWINGS">FIG. 27</figref> starts with etching the principal plane of the sapphire substrate <b>11</b> which is ±90° off toward the A-axis from the R-plane. This etching forms a hollow part <b>14</b>, with a cross section of inverted trapezoid, extending straight in one direction. One side <b>14</b><i>a </i>of the hollow part <b>14</b> is the R-plane. The thus prepared sapphire substrate <b>11</b> permits the III-V nitride compound semiconductor layer <b>12</b> to be grown thereon in the same way as in the third embodiment (the third example). Growth in the direction indicated by the arrow in <figref idref="DRAWINGS">FIG. 26</figref> takes place from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b>. The top of the III-V nitride compound semiconductor layer <b>12</b> is the facet of the (33-62) plane. In this case, the dislocation <b>15</b> that occurs from the side <b>14</b><i>a </i>of the R-plane of the hollow part <b>14</b> extends in the direction of growth and hence there is no dislocation that reaches the surface of the III-V nitride compound semiconductor layer <b>12</b>.

0172The sixteenth embodiment of the present invention mentioned below is concerned with a method for producing a light-emitting diode.

0173The production method according to the sixteenth embodiment starts with growing a III-V nitride compound semiconductor layer <b>12</b> with the (11-22) plane direction on the sapphire substrate <b>11</b> having the M-plane as the principal plane, in the same way as in the first embodiment.

0174To be specific, as shown in <figref idref="DRAWINGS">FIG. 28A</figref>, on the sapphire substrate <b>11</b> having the M-plane as the principal plane are formed the raised parts <b>13</b> (each having a trapezoidal cross section) at regular intervals. Between the raised parts <b>13</b>, the hollow part <b>14</b> having a cross section of inverted trapezoid is formed. The raised parts <b>13</b> and the hollow parts <b>14</b> in their plan view extend straight in one direction for example. The raised parts <b>13</b> are formed from SiN (such as Si₃N₄) or SiO₂by any known method as follows. First, the sapphire substrate <b>11</b> is entirely coated with a film of the material for the raised parts <b>13</b> by CVD process, vacuum vapor deposition, or sputtering. Then, the film is coated with a resist of prescribed pattern by photolithography. Finally, the film undergoes taper etching by reactive ion etching (RIE) or the like through the resist pattern as a mask. Thus there are obtained the raised parts <b>13</b> each having a trapezoidal cross section.

0175After thermal cleaning is performed on the sapphire substrate <b>11</b> and the raised parts <b>13</b> to clean their surface, the sapphire substrate <b>11</b> is coated with a buffer layer of GaN, AlN, CrN, Cr-doped GaN, or Cr-doped AlN (not shown) by any know process at a growth temperature of about 550° C. On the bottom of the hollow part <b>14</b> is grown the III-V nitride compound semiconductor layer <b>12</b> by the MOCVD process in the same way as in the first embodiment, as shown in <figref idref="DRAWINGS">FIG. 28B</figref>. It may be a GaN layer which is doped with a p-type or n-type impurity or not doped.

0176The growing step is continued under the condition that the facet of the (11-22) plane preferentially appears, so that the III-V nitride compound semiconductor layer <b>12</b> grows into a thick continuous film, as shown in <figref idref="DRAWINGS">FIG. 28C</figref>.

0177On the III-V nitride compound semiconductor layer <b>12</b> are sequentially grown the n-type III-V nitride compound semiconductor layer <b>16</b>, the active layer <b>17</b> of III-V nitride compound semiconductor, and the p-type III-V nitride compound semiconductor layer <b>18</b> by e.g. the MOCVD process as shown in <figref idref="DRAWINGS">FIG. 29</figref>. These three layers <b>16</b>, <b>17</b>, and <b>18</b> have the (11-22) plane direction. In this case, the III-V nitride compound semiconductor layer <b>15</b> is of n-type.

0178The sapphire substrate <b>11</b> on which the III-V nitride compound semiconductor layers have been grown are removed from the MOCVD apparatus.

0179On the p-type III-V nitride compound semiconductor layer <b>18</b> the p-side electrode <b>19</b> from an ohmic metal having a high reflectance for the light of emitted wavelength is formed.

0180Heat treatment is performed to activate the p-type impurity in the p-type III-V nitride compound semiconductor layer <b>18</b>. The atmosphere for heat treatment is a mixture gas composed of N₂(99%) and O₂(1%). The temperature of heat treatment is 550 to 750° C. (e.g., 650° C.) or 580 to 620° C. (e.g., 600° C.). Addition of O₂to N₂enhances activation. The atmospheric gas, which is N₂or a mixture of N₂and O₂, may be mixed with a nitrogen halide (such as NF₃and NCl₃) as a source of F or Cl, which has high electronegativity like O and N. Duration of heat treatment is 5 minutes to 2 hours, or 40 minutes to 2 hours, usually 10 to 60 minutes. The temperature of heat treatment is kept low to protect the active layer <b>16</b> from deterioration. Incidentally, this heat treatment may be carried out after the p-type III-V nitride compound semiconductor layer <b>18</b> has been epitaxially grown and before the p-side electrode <b>19</b> is formed.

0181The layers <b>16</b>, <b>17</b>, and <b>18</b> undergo patterning into a prescribed shape by RIE method, powder blasting, or sand blasting, so as to form the desired mesa part.

0182On the III-V nitride compound semiconductor layer <b>12</b> is formed the n-side electrode <b>21</b>, which is adjacent to the mesa part.

0183The substrate <b>11</b>, which has the light-emitting structure formed thereon, undergoes grinding or lapping on its back side, so as to reduce its thickness. It is divided into bars by scribing and each bar is divided into chips by scribing. In this way there are obtained light-emitting diodes as desired.

0184The light-emitting diode mentioned above has the typical structure as follows.

0185The III-V nitride compound semiconductor layer <b>12</b> is an n-type GaN layer. The n-type III-V nitride compound semiconductor layer <b>16</b> is composed of an n-type GaN layer and an n-type GaInN layer (upward). The p-type III-V nitride compound semiconductor layer <b>18</b> is composed of a p-type AlInN layer, a p-type GaN layer, and a p-type GaInN layer (upward). The active layer <b>17</b> has e.g. the multiple quantum well (MQW) structure consisting of e.g. GaInN quantum well layers and GaN barrier layers which are placed one over the other. The In content in the active layer <b>17</b> varies depending on the desired wavelength of the light-emitting diode. It is about 11% for 405 nm, about 18% for 450 nm, and about 24% for 520 nm for example. The p-side electrode <b>19</b> is formed from Ag or Pd/Ag. It may have an optional barrier metal such as Ti, W, Cr, WN, and CrN. The n-side electrode <b>21</b> has the Ti/Pt/Au structure.

0186According to the sixteenth embodiment, the active layer <b>14</b> has the (11-22) plane direction and controls the piezoelectric field. Consequently, it suppresses the quantum confined Stark effect therein. This greatly contributes to the luminous efficiency of the light-emitting diode based on a III-V nitride compound semiconductor. In addition, the layers <b>16</b>, <b>17</b>, and <b>18</b> can be grown easily, which leads to the easy production of the semiconductor light-emitting element.

0187The seventeenth embodiment of the present invention mentioned below is concerned with a method for producing a light-emitting diode.

0188The production method according to the seventeenth embodiment starts with etching the sapphire substrate <b>11</b>, whose principal plane is +60° off toward the C-axis from the M-plane, in the same way as in the fourth embodiment, as shown in <figref idref="DRAWINGS">FIG. 30A</figref>. This etching gives rise to the hollow parts <b>14</b> whose one side <b>14</b><i>a </i>is the M-plane. The III-V nitride compound semiconductor layer <b>12</b> having the (11-22) plane direction is grown on the sapphire substrate <b>11</b>, until the hollow parts <b>14</b> are completely filled, as shown in <figref idref="DRAWINGS">FIG. 30B</figref>, in the same way as in the fourth embodiment.

0189Growing is continued such that the (11-20) plane facet preferentially appears and the III-V nitride compound semiconductor layer <b>12</b> becomes thick to form a continuous film as shown in <figref idref="DRAWINGS">FIG. 30C</figref>.

0190Subsequently, the same steps as in the sixteenth embodiment are carried out to complete the production of the light-emitting diode as desired. Incidentally, the n-type III-V nitride compound semiconductor layer <b>16</b>, the active layer <b>17</b>, and the p-type III-V nitride compound semiconductor layer <b>18</b> have the (11-20) plane (or A-plane) direction.

0191According to the seventeenth embodiment, the active layer <b>14</b> has the (11-20) plane (or A-plane) direction and controls the piezoelectric field. Consequently, it suppresses the quantum confined Stark effect therein. It also eliminates threading dislocations in the III-V nitride compound semiconductor layer <b>12</b>. This in turn eliminates threading dislocations in the layers <b>16</b>, <b>17</b>, and <b>18</b> formed on the layer <b>12</b>. Hence the layers <b>16</b>, <b>17</b>, and <b>18</b> have a good crystal quality, which leads to the high luminous efficiency of the light-emitting diode based on a III-V nitride compound semiconductor. In addition, the layers <b>16</b>, <b>17</b>, and <b>18</b> can be grown easily, which leads to the easy production of the semiconductor light-emitting element.

0192The following is a description of the eighteenth embodiment of the present invention.

0193The eighteenth embodiment is concerned with a backlight of light-emitting diode consisting of a blue light-emitting diode and a green light-emitting diode (both produced by the method of the sixteenth or seventeenth embodiment) in combination with a red light-emitting diode (such as AlGaInP light-emitting diode) which is prepared separately.

0194The backlight is produced as follows. A blue light-emitting diode is formed on the sapphire substrate <b>11</b> by the method according to the sixteenth or seventeenth embodiment. The p-side electrode <b>19</b> and the n-side electrode <b>21</b> each are provided with bumps (not shown). After division into chips, each chip is made into a blue light-emitting diode by flip chip bonding. In the same way as above, a green light-emitting diode is formed by flip chip bonding. On the other hand, a red light-emitting diode is formed by coating an n-type GaAs substrate with an AlGaInP semiconductor layer and then forming thereon a p-side electrode. This diode is also used in the form of chip.

0195These red, green, and blue light-emitting diode chips are mounted on a sub-mount of AlN. The resulting assemblies are arranged regularly on a substrate of Al, with the sub-mount downward, as shown in <figref idref="DRAWINGS">FIG. 31A</figref>. Numerals <b>61</b>, <b>62</b>, <b>63</b>, <b>64</b>, and <b>65</b> in <figref idref="DRAWINGS">FIG. 31A</figref> refer respectively to the substrate, the sub-mount, the red light-emitting diode chip, the green light-emitting diode chip, and the blue light-emitting diode chip. These light-emitting diode chips measure 350 μm square. The red light-emitting diode chip <b>63</b> is mounted such that its n-side electrode comes into contact with the sub-mount <b>62</b>. The green light-emitting diode chip <b>64</b> and the blue light-emitting chip <b>65</b> are mounted such that their p-side electrode and n-side electrode come into contact with the sub-mount <b>62</b> through bumps. The sub-mount <b>62</b>, on which the red light-emitting diode chips <b>63</b> are mounted, has lead electrodes (not shown) regularly formed thereon for the n-side electrodes. On the lead electrode is mounted that part of the red light-emitting diode chip <b>63</b> which is adjacent to the n-side electrode. The p-side electrode of the red light-emitting diode chip <b>63</b> and the pad electrode <b>66</b> on the substrate <b>61</b> are connected together through the bonded wire <b>67</b>. And, one end of the lead electrode and another pad electrode on the substrate <b>61</b> are connected together through the bonded wire (not shown). The sub-mount <b>62</b>, on which the green light-emitting diode chips <b>64</b> are mounted, has lead electrodes (not shown) regularly formed thereon for the p-side electrode and the n-side electrodes. On the lead electrode is mounted through bumps thereon that part of the green light-emitting diode chip <b>64</b> which is adjacent to the p-side electrode and the n-side electrode. One end of the lead electrode for the p-side electrode of the green light-emitting diode chip <b>64</b> is connected to the pad electrode on the substrate <b>61</b> through the bonded wire (not shown), and one end of the lead electrode for the n-side electrode of the green light-emitting diode chip <b>64</b> is connected to the pad electrode on the substrate <b>61</b> through the bonded wire (not shown). The blue light-emitting diode chip <b>65</b> also has the same structure as mentioned above.

0196The sub-mount <b>62</b> may be omitted. In this case, the red, green, and blue light-emitting diode chips <b>63</b>, <b>64</b>, and <b>65</b> may be directly mounted on a printed circuit board or chassis inside wall capable of heat dissipation. Such direct mounting reduces the production cost of backlight or panel.

0197The red, green, and blue light-emitting diode chips <b>63</b>, <b>64</b>, and <b>65</b> mentioned above are combined into a unit cell, and as many unit cells as necessary for a prescribed pattern are arranged on the substrate <b>61</b>, as shown in <figref idref="DRAWINGS">FIG. 32</figref>. Each unit cell is covered with a transparent resin <b>68</b> by potting as shown in <figref idref="DRAWINGS">FIG. 31B</figref>. This step is followed by curing to solidify the transparent resin <b>68</b>. Curing results in slight shrinkage, as shown in <figref idref="DRAWINGS">FIG. 31C</figref>. In this way there is obtained the light-emitting diode backlight shown in <figref idref="DRAWINGS">FIG. 33</figref>, which is an array of the unit cells, each consisting of the red, green, and blue light-emitting diode chips <b>63</b>, <b>64</b>, and <b>65</b>, arranged on the substrate <b>61</b>. In this case, the transparent resin <b>68</b> is in contact with the reverse side of the sapphire substrate <b>11</b> for the green and blue light-emitting diode chips <b>64</b> and <b>65</b>. Contact with the transparent resin <b>68</b> leads to a lower refractive index than contact with air. This reduces the amount of light reflected by the reverse side of the sapphire substrate <b>11</b> and increases the light emission efficiency.

0198The light-emitting diode backlight mentioned above will find use as the backlight of liquid crystal panel.

0199The following is a description of the nineteenth embodiment of the present invention.

0200The nineteenth embodiment is concerned with a backlight which is produced as follows in the same way as in the eighteenth embodiment. The red, green, and blue light-emitting diodes chips <b>63</b>, <b>64</b>, and <b>65</b> are regularly arranged on the substrate <b>61</b>, and then they are covered by potting individually and respectively with transparent resins <b>69</b>, <b>70</b>, and <b>71</b> suitable for them. This step is followed by curing to solidify the transparent resins <b>69</b>, <b>70</b>, and <b>71</b>. Curing results in slight shrinkage. In this way there is obtained the light-emitting diode backlight, which is an array of the unit cells, each consisting of the red, green, and blue light-emitting diode chips <b>63</b>, <b>64</b>, and <b>65</b>, arranged on the substrate <b>61</b>. In this case, the transparent resins <b>70</b> and <b>71</b> are in contact with the reverse side of the sapphire substrate <b>11</b> for the green and blue light-emitting diode chips <b>64</b> and <b>65</b>. This leads to a lower refractive index than contact with air. This reduces the amount of light reflected by the reverse side of the sapphire substrate <b>11</b> and increases the light emission efficiency.

0201The light-emitting diode backlight mentioned above will find use as the backlight of liquid crystal panel.

0202The following is a description of the twentieth embodiment of the present invention.

0203The twentieth embodiment is concerned with a light source cell unit consisting of a blue light-emitting diode and a green light-emitting diode (both produced by the method of the sixteenth or seventeenth embodiment) in combination with a red light-emitting diode which is prepared separately.

0204The light source cell unit <b>75</b> (shown in <figref idref="DRAWINGS">FIG. 35A</figref>) according to the twentieth embodiment consists of at least one each of the red light-emitting diode chip <b>63</b>, the green light-emitting diode chip <b>64</b>, and the blue light-emitting diode chip <b>65</b>, which are regularly arranged in the same way as in the eighteenth or nineteenth embodiment. As many light source cell units <b>75</b> as necessary are regularly arranged on the printed circuit board <b>76</b>. In the illustrated case, each light source cell unit <b>75</b> consists of one each of the red, green, and blue light-emitting diode chips <b>63</b>, <b>64</b>, and <b>65</b>, which are arranged at the apexes of a triangle. <figref idref="DRAWINGS">FIG. 35B</figref> is an enlarged view of the cell unit <b>75</b>. In each cell unit <b>75</b>, the red, green, and blue light-emitting diodes chips <b>63</b>, <b>64</b>, and <b>65</b> are a certain distance (a) apart from one another, which is 4 mm, for example, although not restrictive. Adjacent cell units are also a certain distance (b) apart from one another, which is 30 mm, for example, although not restrictive. The printed circuit board <b>76</b> includes, for example, FR4 (Flame Retardant Type 4) board, metal core board, and flexible board. Any ones capable of heat dissipation can be used. Each unit cell <b>76</b> is covered with the transparent resin <b>68</b> by potting in the same way as the eighth embodiment. Alternatively, the red, green, and blue light-emitting diodes chips <b>63</b>, <b>64</b>, and <b>65</b> are covered by potting respectively with the transparent resins <b>69</b>, <b>70</b>, and <b>71</b>, in the same way as the ninth embodiment. Thus there is obtained the light source cell unit consisting of the red, green, and blue light-emitting diodes chips <b>63</b>, <b>64</b>, and <b>65</b> which are arranged on the printed circuit board <b>76</b>.

0205<figref idref="DRAWINGS">FIGS. 36 and 37</figref> show the typical examples of the arrangement of the cell units <b>75</b> on the printed circuit board <b>76</b>. The examples are not restrictive. In <figref idref="DRAWINGS">FIGS. 36 and 37</figref>, the unit cells <b>75</b> constitute a 4×3 two-dimensional array and a 6×2 two-dimensional array, respectively.

0206<figref idref="DRAWINGS">FIG. 38</figref> shows another example of the cell unit <b>75</b>, which consists of one red light-emitting diode chip <b>63</b>, two green light-emitting diode chips <b>64</b>, and one blue light-emitting diode chip <b>65</b>, which are placed at the apexes of a square. The two green light-emitting diode chips <b>64</b> are placed at the ends of one diagonal line, and the red and blue light-emitting diode chips <b>63</b> and <b>65</b> are placed at the ends of the other diagonal line.

0207One or more light source cell units (which are adequately arranged) constitute a backlight consisting of light-emitting diodes, which will find use as the backlight of liquid crystal panel.

0208While the invention has been described above in its preferred embodiments, it is to be understood that the embodiments are not intended to restrict the scope of the invention and various changes can be made on the basis of the technical idea of the invention. If necessary, modifications may be made on the values, materials, structure, construction, shape, substrate, raw materials, and process used in the first to twentieth embodiments mentioned above.

0209It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.