Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode

TECHNICAL FIELD OF THE PRESENT DISCLOSURE

The present disclosure relates generally to information handling devices and systems. More particularly, the present disclosure describes an apparatus, method, and system useful for enhancement of locked loop operations including clock and voltage scaling on an interface, such as an interface that uses a double data rate or a multiple data rate, for example a chip-to-chip interface that allows connecting the interconnects of two different systems on chips, and/or for providing a digital phase lock loop high speed bypass mode.

BACKGROUND OF THE PRESENT DISCLOSURE

In order to reduce dynamic and static power consumption on leaky processes, devices implement dynamic voltage and frequency scaling to adapt energy to the required performance. Voltage and frequency changes impact system behavior and should be properly managed. For example, voltage and frequency changes impact delay-locked loops (DLLs) used in interfaces such as memory controllers by causing loss of lock of the delay-locked loops (DLLs) so that on-going accesses to devices such as memory may be corrupted. For conventional devices to continue to process properly during frequency transitions requires heavy and undesirable software management, for example. Performing dynamical voltage and frequency scaling (DVFS) conventionally on an interface such as a memory controller causes the delay-locked loop (DLL) or any equivalent delay control cell, used, for example, to manage an external double data rate (DDR) memory, to lose its lock and, therefore, corrupt memory accesses. Conventionally, dynamic voltage and frequency scaling (DVFS) is only applied on processors.

In order to optimize multi-processor devices and uni-processor, multi-core processor devices, a multiple asynchronous clock domain architecture is implemented. Each of the multiple asynchronous clock domains may potentially be supplied by a dedicated digital phase-locked loop (DPLL) to match the various frequency requirements. However, each of the digital phase-locked loops (DPLLs) in each of the asynchronous clock domains generates a high speed synthesized clock and has a significant dynamic power consumption. Furthermore, when a new synthesized frequency value is programmed on a given digital phase-locked loop (DPLL), for example, in a dynamic voltage and frequency scaling (DVFS) context, processing performance is negatively impacted during the digital phase-locked loop (DPLL) re-lock operation.

SUMMARY OF THE PRESENT DISCLOSURE

According to various illustrative embodiments, an apparatus, method, and system for enhancement of locked loop operations including clock and voltage scaling on an interface and/or for providing a digital phase lock loop high speed bypass mode are described. In one aspect, the apparatus comprises a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface. The apparatus also comprises a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature. The apparatus also comprises a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency.

In another aspect, a method for a digital phase lock loop high speed bypass mode comprises providing a first digital phase lock loop in a first clock domain having a high speed clock. The method also comprises providing at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input. The method also comprises controlling the first output of the first glitchless multiplexer according to preselected settings using a device power manager synchronized locally to ensure proper switching. The method also comprises controlling a second output of the second glitchless multiplexer using a control logic element of the at least one second digital phase lock loop, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

In yet another aspect, a system for clock and voltage scaling on an interface and for providing a digital phase lock loop high speed bypass mode is provided, the system comprising a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface. The system also comprises a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature. The system also comprises a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency. The system also comprises a first digital phase lock loop in a first clock domain having a high speed clock. The system also comprises at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input, wherein the device power manager is arranged to control the first output of the first glitchless multiplexer according to preselected settings and synchronized locally to ensure proper switching. The system also comprises a control logic element of the at least one second digital phase lock loop arranged to control a second output of the second glitchless multiplexer, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The following figures form part of the present specification and are included to further demonstrate certain aspects of the present claimed subject matter, and should not be used to limit or define the present claimed subject matter. The present claimed subject matter may be better understood by reference to one or more of these drawings in combination with the description of embodiments presented herein. Consequently, a more complete understanding of the present embodiments and further features and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which the leftmost significant digit(s) in the reference numerals denote(s) the first figure in which the respective reference numerals appear, wherein:

<figref idrefs="DRAWINGS">FIG. 1</figref> schematically illustrates a particular example of various illustrative embodiments of an apparatus in accord with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 2</figref> schematically illustrates another particular example of various illustrative embodiments of an apparatus in accord with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 3</figref> schematically illustrates yet another particular example of various illustrative embodiments of an apparatus in accord with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 4</figref> schematically illustrates a particular example of various illustrative embodiments of a method in accord with the present disclosure;

<figref idrefs="DRAWINGS">FIG. 5</figref> schematically illustrates a particular example of various illustrative embodiments of a system in accord with the present disclosure.

It is to be noted, however, that the appended drawings illustrate only typical embodiments of the present claimed subject matter and are, therefore, not to be considered limiting of the scope of the present claimed subject matter, as the present claimed subject matter may admit to other equally effective embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components and configurations. As one skilled in the art having the benefit of the present disclosure will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and, thus, should be interpreted to mean “including, but not limited to . . . ,” and so forth. Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection or though an indirect electrical connection via other devices and/or connections. Furthermore, the term “information” is intended to refer to any data, instructions, or control sequences that may be communicated between components of a device. For example, if information is sent between two components, data, instructions, control sequences, or any combination thereof may be sent between the two components.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Illustrative embodiments of the present claimed subject matter are described in detail below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort would be a routine undertaking for those of ordinary skill in the art having the benefit of the present disclosure.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 1</figref> and <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, an apparatus <b>100</b> for clock and voltage scaling on an interface <b>110</b> may comprise a device power manager <b>120</b> coupled to the interface <b>110</b> and arranged to supply a scalable frequency clock <b>115</b> to the interface <b>110</b>. The apparatus <b>100</b> may also comprise a delay-locked loop <b>130</b> supplied by a substantially constant fixed frequency clock <b>125</b> from the device manager <b>120</b> and a substantially constant voltage <b>135</b> from an embedded low dropout regulator <b>140</b>, the delay-locked loop <b>130</b> arranged to generate a unique code <b>145</b> depending on at least one of process, voltage, and temperature. The apparatus <b>100</b> may also comprise a plurality of controlled delay line elements <b>150</b> coupled to the delay-locked loop <b>130</b> and arranged to use the unique code <b>145</b> to build a delay and generate an appropriate delayed data strobe <b>155</b> from an input data strobe <b>105</b>, the delay being adjusted by having up to N controlled delay line elements <b>150</b> chained together, N being a ratio between the substantially constant fixed frequency <b>125</b> and the scalable frequency <b>115</b>. <figref idrefs="DRAWINGS">FIG. 1</figref> and <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, show the case where up to 4 controlled delay line elements <b>150</b> may be chained together. Those of ordinary skill in the art having the benefit of the present disclosure would recognize that the ratio N between the substantially constant fixed frequency <b>125</b> and the scalable frequency <b>115</b> may be any appropriate or suitable non-zero integer value.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, the apparatus <b>100</b> may further comprise a plurality <b>200</b> of the plurality of controlled delay line elements <b>150</b>, <b>250</b> each coupled to the delay-locked loop <b>130</b> and each arranged to use the unique code <b>145</b> to build the delay and generate appropriate respective delayed data strobes <b>155</b>, <b>255</b> from respective input data strobes <b>105</b>, <b>205</b>. <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, shows the case where the plurality <b>200</b> of the plurality of controlled delay line elements <b>150</b>, <b>250</b> may comprise two sets of the controlled delay line elements <b>150</b>, <b>250</b> each coupled to the delay-locked loop <b>130</b> and each arranged to use the unique code <b>145</b> to build the delay and generate two appropriate respective delayed data strobes <b>155</b>, <b>255</b>. Those of ordinary skill in the art having the benefit of the present disclosure would recognize that the number of the sets of the controlled delay line elements <b>150</b>, <b>250</b> comprising the plurality of controlled delay line elements <b>150</b>, <b>250</b> may be any appropriate or suitable non-zero integer value.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 1</figref> and <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, the interface <b>110</b> may be arranged to switch <b>160</b> between one of the controlled delay line elements <b>150</b> and a chain of more than one of the controlled delay line elements <b>150</b>, <b>250</b> based on a handshake protocol <b>170</b> with the device power manager <b>120</b> when there is no on-going access on an interface <b>185</b>. In various illustrative embodiments, the substantially constant fixed frequency clock <b>125</b> and the scalable frequency clock <b>115</b> may be derived from the same clock source. In various illustrative embodiments, the substantially constant fixed frequency clock <b>125</b> and the scalable frequency clock <b>115</b> may not be balanced. In various illustrative embodiments, at least one multiplexer <b>180</b>, <b>280</b> may allow selection among the control delay line elements <b>150</b>, <b>250</b>, respectively.

In various illustrative embodiments, a substantially constant fixed frequency clock <b>125</b> and a substantially constant voltage <b>135</b> may be provided to the delay-locked loop (DLL) <b>130</b> while a scalable frequency clock <b>115</b> provided to the interface <b>110</b> may be changed. The clock delay, phase, and jitter may be managed so that any module in a device that comprises the apparatus <b>100</b> may access properly a device such as an external memory during a dynamic voltage and frequency scaling (DVFS) transition. In various illustrative embodiments, the apparatus <b>100</b> may manage delay elements <b>130</b>, <b>150</b>, <b>250</b> properly during frequency and voltage scaling.

In various illustrative embodiments, the apparatus <b>100</b> may implement the delay-locked loop (DLL) <b>130</b> and the controlled delay line elements (CDLs) <b>150</b>, <b>250</b> for use with a double data rate (DDR) interface <b>110</b>. The delay-locked loop (DLL) <b>130</b> may be fed by a substantially constant fixed frequency clock <b>125</b> and may generate the unique code <b>145</b> that may be used by several of the controlled delay line element (CDL) components <b>150</b>, <b>250</b> that provide the respective appropriately delayed data strobe lines (DQS) <b>155</b>, <b>255</b> so that the interface <b>110</b> may sample input read data properly. Similarly, the respective appropriately delayed data strobe lines (DQS) <b>155</b>, <b>255</b> may be output and may be delayed so that a double data rate (DDR) device such as a DDR memory may sample write data properly.

In various illustrative embodiments, the unique code <b>145</b> may vary depending on process and/or voltage and/or temperature (PVT) variations that also impact the controlled delay line element (CDL) components <b>150</b>, <b>250</b> consistently. In various illustrative embodiments, in order to avoid re-locking the delay-locked loop (DLL) <b>130</b>, the delay-locked loop (DLL) <b>130</b> may be supplied with a substantially constant fixed frequency clock <b>125</b> that is separated from the scalable frequency clock <b>115</b> that may be used for the dynamic voltage and frequency scaling (DVFS) of the interface <b>110</b>. The substantially constant fixed frequency clock <b>125</b> and the scalable frequency clock <b>115</b> may be derived from the same clock source, but the substantially constant fixed frequency clock <b>125</b> and the scalable frequency clock <b>115</b> do not need to be balanced. Also, substantially constant voltage for the delay-locked loop (DLL) <b>130</b> may be ensured by using the embedded low dropout regulator (LDO) <b>140</b>.

In various illustrative embodiments, since the unique code <b>145</b> from the delay-locked loop (DLL) <b>130</b> may remain substantially stable for a given process and/or voltage and/or temperature (PVT) when the scalable clock <b>115</b> for the interface <b>110</b> scales, between 1 and N controlled delay line elements (CDLs) <b>150</b>, <b>250</b> may be chained together in order to adapt data strobe line (DQS) delays according to the new interface <b>110</b> frequency. N corresponds to the ratio between the initial and final frequencies of the interface <b>110</b>. In various illustrative embodiments, N may be a ratio between the substantially constant fixed frequency of the substantially constant fixed frequency clock <b>125</b> and the scaled frequency of the scalable frequency clock <b>115</b>. The switch <b>160</b> between 1 and a chain of several controlled delay line elements (CDLs) <b>150</b>, <b>250</b> may be handled by the interface <b>110</b> based on a handshake protocol <b>170</b> with the device power manager <b>120</b> so that the switch <b>160</b> may be performed when there is no on-going access on the interface <b>185</b>.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 1</figref> and <figref idrefs="DRAWINGS">FIG. 2</figref>, for example, the delay-locked loop (DLL) <b>130</b> may be supplied by a substantially constant fixed frequency clock <b>125</b> from the device manager <b>120</b> and a substantially constant voltage <b>135</b> from the embedded low dropout regulator <b>140</b>. For a given process, voltage, and/or temperature, the delay-locked loop <b>130</b> may generate a unique code (DCB) <b>145</b>. This unique code (DCB) <b>145</b> may be used by the controlled delay line elements (CDLs) <b>150</b>, <b>250</b> to build the delays and generate appropriate delayed data strobes (DSOx) <b>155</b>, <b>255</b> where DSOx is generated by CDLx for any suitable non-zero integer x, each (DSOx) <b>155</b>, <b>255</b> corresponding to a respective input data strobe DSIx <b>105</b>, <b>205</b>. Depending on the ratio N between the substantially constant fixed frequency <b>125</b> and the scalable frequency <b>115</b> of the interface <b>110</b>, from 1 to N controlled delay line elements (CDLs) <b>150</b>, <b>250</b> may be chained so that the delay may be properly adjusted to the new scaled scalable frequency <b>115</b> of the interface <b>110</b>, where N is equal to 4 in <figref idrefs="DRAWINGS">FIG. 1</figref> and <figref idrefs="DRAWINGS">FIG. 2</figref>, for example. Due to the handshake <b>170</b> with the device power manager <b>120</b> that initiates the frequency change, the interface <b>110</b>, logic ensures that switches <b>160</b> between delay chains are properly handled when there are no on-going operations such as memory accesses. The use of delay switches <b>160</b> avoids re-locking the delay-locked loop (DLL) <b>130</b> to generate a code for the new frequency of the interface <b>110</b>.

In various illustrative embodiments, the apparatus <b>100</b> may substantially ease power management software implementation by making the dynamic voltage and frequency scaling (DVFS) transition transparent. In various illustrative embodiments, the apparatus <b>100</b> may substantially optimize dynamic voltage and frequency scaling (DVFS) efficiency by removing the delay-locked loop (DLL) <b>130</b> re-lock time upon frequency scaling of the interface <b>110</b>. In various illustrative embodiments, the apparatus <b>100</b> may remove substantially any architecture constraint on modules that need to access a device such as an external memory, such as first in first out (FIFO) size, and the like. In various illustrative embodiments, the apparatus <b>100</b> may substantially prevent any system access to a device such as an external memory during the frequency change. In various illustrative embodiments, the apparatus <b>100</b> may support dynamic voltage and frequency scaling (DVFS) on interconnects and other interfaces <b>110</b>, whereas, conventionally, dynamic voltage and frequency scaling (DVFS) is only applied on processors.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 3</figref> and <figref idrefs="DRAWINGS">FIG. 4</figref>, for example, a method <b>400</b> for a digital phase lock loop high speed bypass mode may comprise providing a first digital phase lock loop <b>310</b> of an apparatus <b>300</b> in a first clock domain <b>320</b> having a high speed clock <b>325</b>, as indicated at <b>410</b>. The method <b>400</b> may also comprise providing at least one second digital phase lock loop <b>330</b> in a second clock domain <b>340</b>, the at least one second digital phase lock loop <b>330</b> having a first glitchless multiplexer <b>350</b> having the high speed clock <b>325</b> as one input and a low speed system reference clock <b>335</b> as another input and a second glitchless multiplexer <b>360</b> having a first output <b>345</b> of the first glitchless multiplexer <b>350</b> as a first input <b>345</b> and a synthesized clock <b>355</b> from a core <b>370</b> of the at least one second digital phase lock loop <b>330</b> as a second input <b>355</b>, as indicated at <b>420</b>. The method <b>400</b> may also comprise controlling the first output <b>345</b> of the first glitchless multiplexer <b>350</b> according to preselected settings using a device power manager <b>380</b> synchronized locally to ensure proper switching, as indicated at <b>430</b>. The method <b>400</b> may also comprise controlling a second output <b>375</b> of the second glitchless multiplexer <b>360</b> using a control logic element <b>390</b> of the at least one second digital phase lock loop <b>330</b>, the second output <b>375</b> of the second glitchless multiplexer <b>360</b> comprising the synthesized clock <b>355</b> when the at least one second digital phase lock loop <b>330</b> is in a lock mode and comprising the first output <b>345</b> of the first glitchless multiplexer <b>350</b> when the at least one second digital phase lock loop <b>330</b> is in the digital phase lock loop high speed bypass mode, as indicated at <b>440</b>.

In various illustrative embodiments, the first digital phase lock loop <b>310</b> supplies the high speed clock <b>325</b> to the at least one second digital phase lock loop <b>330</b>. In various illustrative embodiments, controlling the first output <b>345</b> of the first glitchless multiplexer <b>350</b> according to preselected settings using the device power manager <b>380</b> synchronized locally further comprises using a synchronization element <b>395</b> disposed in the at least one second digital phase lock loop <b>330</b>.

In various illustrative embodiments, the first output <b>345</b> of the first glitchless multiplexer <b>350</b> when the at least one second digital phase lock loop <b>330</b> is in the digital phase lock loop high speed bypass mode comprises the high speed clock <b>325</b>. In various illustrative embodiments, the first output <b>345</b> of the first glitchless multiplexer <b>350</b> when the at least one second digital phase lock loop <b>330</b> is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock <b>335</b>. In various illustrative embodiments, the low speed system reference clock <b>335</b> is input to the core <b>370</b> of the at least one second digital phase lock loop <b>330</b>. In various illustrative embodiments, the control logic element <b>390</b> of the at least one second digital phase lock loop <b>330</b> is coupled to the core <b>370</b> of the at least one second digital phase lock loop <b>330</b>.

In various illustrative embodiments, the method <b>400</b> may provide a savings in the power consumption of the digital phase lock loops (DPLLs) <b>310</b>, <b>330</b>. For a given clock domain, such as the second clock domain <b>340</b>, when the required frequency does not exceed a frequency used by another clock domain, such as the first clock domain <b>320</b>, the at least one second digital phase lock loop (DPLL) <b>330</b> may be set in bypass mode and use the high speed clock output <b>325</b> of the first digital phase lock loop (DPLL) <b>310</b> in the first clock domain <b>320</b> as an alternative high speed clock source, saving overall power consumption.

In various illustrative embodiments, the method <b>400</b> may maintain higher processing performance during the time required for a digital phase lock loop (DPLL) re-lock operation. For a given clock domain, such as the second clock domain <b>340</b>, when a re-lock is programmed on the at least one second digital phase lock loop (DPLL) <b>330</b> of the second clock domain <b>340</b>, or when the at least one second digital phase lock loop (DPLL) <b>330</b> loses its lock under hardware conditions, the at least one second digital phase lock loop (DPLL) <b>330</b> automatically switches to the bypass mode. In the bypass mode, the output of the at least one second digital phase lock loop (DPLL) <b>330</b> switches from the high speed synthesized clock <b>355</b> to either the low speed system reference clock <b>335</b> or the high speed clock <b>325</b> of the first digital phase lock loop (DPLL) <b>310</b> in the first clock domain <b>320</b>. By using an additional high speed bypass clock input, generated from another clock domain, such as the high speed clock <b>325</b> of the first digital phase lock loop (DPLL) <b>310</b> in the first clock domain <b>320</b>, the at least one second digital phase lock loop (DPLL) <b>330</b> may output a high speed clock even during re-lock and allows processing maintaining higher performance during the re-lock operation.

In various illustrative embodiments, the method <b>400</b> may involve an implementation with an additional high speed clock input, such as the high speed clock <b>325</b>, and specific bypass multiplexers (muxes) with appropriate controls, such as the first glitchless multiplexer <b>350</b> and the second glitchless multiplexer <b>360</b>. A user may define whether the at least one second digital phase lock loop (DPLL) <b>330</b> outputs the low speed (low frequency) system reference clock <b>335</b> or the high speed (high frequency) clock <b>325</b> when the at least one second digital phase lock loop (DPLL) <b>330</b> switches to the bypass mode, in the at least one second digital phase lock loop (DPLL) <b>330</b> low power mode or during re-lock.

In various illustrative embodiments, a digital phase lock loop (DPLL), such as the at least one second digital phase lock loop (DPLL) <b>330</b>, may implement a scheme, such as method <b>400</b>, where any clock domain, such as the second clock domain <b>340</b>, may use a clock issued from another clock domain, such as the high speed clock <b>325</b> issued from the first clock domain <b>320</b>, as a domain clock source when the digital phase lock loop (DPLL), such as the at least one second digital phase lock loop (DPLL) <b>330</b>, enters in a bypass mode. The scheme, such as method <b>400</b>, may comprise adding an additional high speed clock input, such as the high speed clock <b>325</b>, and a glitchless multiplexer (mux), such as the first glitchless multiplexer <b>350</b>.

This glitchless multiplexer (mux), such as the first glitchless multiplexer <b>350</b>, may be controlled by a device power manager (DPM), such as the device power manager <b>380</b>, according to the user settings. This glitchless multiplexer (mux), such as the first glitchless multiplexer <b>350</b>, may allow selecting the bypass clock source to be either the digital phase lock loop (DPLL) reference clock input, such as the low speed (low frequency) system reference clock <b>335</b>, or the high speed clock input, such as the high speed (high frequency) clock <b>325</b>. Control of this glitchless multiplexer (mux), such as the first glitchless multiplexer <b>350</b>, may be synchronized locally to ensure proper switching.

In a lock mode, the digital phase lock loop (DPLL), such as the at least one second digital phase lock loop (DPLL) <b>330</b>, may output a synthesized clock, such as the synthesized clock <b>355</b>. A bypass clock source may be automatically output from the digital phase lock loop (DPLL), such as the at least one second digital phase lock loop (DPLL) <b>330</b>, when the digital phase lock loop (DPLL), such as the at least one second digital phase lock loop (DPLL) <b>330</b>, enters into the bypass mode, during re-lock or upon user request, for example, due to another glitchless multiplexer (mux), such as the second glitchless multiplexer <b>360</b>, as described above.

In various illustrative embodiments, the method <b>400</b> may save overall power consumption and/or may substantially optimize dynamic voltage and frequency scaling (DVFS) performance. In various illustrative embodiments, the method <b>400</b> may be substantially generic for substantially any multiple clock domain platform. In various illustrative embodiments, the method <b>400</b> may be simple to implement. In various illustrative embodiments, the method <b>400</b> may be easy to validate. In various illustrative embodiments, the method <b>400</b> may be low cost.

In various illustrative embodiments, as shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, <figref idrefs="DRAWINGS">FIG. 3</figref>, and <figref idrefs="DRAWINGS">FIG. 5</figref>, for example, a system <b>500</b> for clock and voltage scaling on a interface <b>110</b> and for providing a digital phase lock loop high speed bypass mode may comprise a device power manager <b>120</b>, <b>380</b> coupled to the interface <b>110</b> and arranged to supply a scalable frequency clock <b>115</b> to the interface <b>110</b>. The system <b>500</b> may also comprise a delay-locked loop <b>130</b> supplied by a substantially constant fixed frequency clock <b>125</b> from the device manager <b>120</b>, <b>380</b> and a substantially constant voltage <b>135</b> from an embedded low dropout regulator <b>140</b>, the delay-locked loop <b>130</b> arranged to generate a unique code <b>145</b> depending on at least one of process, voltage, and temperature. The system <b>500</b> may also comprise a plurality of controlled delay line elements <b>150</b> coupled to the delay-locked loop <b>130</b> and arranged to use the unique code <b>145</b> to build a delay and generate an appropriate delayed data strobe <b>155</b> from an input data strobe <b>105</b>, the delay being adjusted by having up to N controlled delay line elements <b>150</b> chained together, N being a ratio between the substantially constant fixed frequency <b>125</b> and the scalable frequency <b>115</b>.

The system <b>500</b> may also comprise a first digital phase lock loop <b>310</b> in a first clock domain <b>320</b> having a high speed clock <b>325</b>. The system <b>500</b> may also comprise at least one second digital phase lock loop <b>330</b> in a second clock domain <b>340</b>, the at least one second digital phase lock loop <b>330</b> having a first glitchless multiplexer <b>350</b> having the high speed clock <b>325</b> as one input and a low speed system reference clock <b>335</b> as another input and a second glitchless multiplexer <b>360</b> having a first output <b>345</b> of the first glitchless multiplexer <b>350</b> as a first input <b>345</b> and a synthesized clock <b>355</b> from a core <b>370</b> of the at least one second digital phase lock loop <b>330</b> as a second input <b>355</b>, wherein the device power manager <b>120</b>, <b>380</b> is arranged to control the first output <b>345</b> of the first glitchless multiplexer <b>350</b> according to preselected settings and is synchronized locally to ensure proper switching. The system <b>500</b> may also comprise a control logic element <b>390</b> of the at least one second digital phase lock loop <b>330</b> arranged to control a second output <b>375</b> of the second glitchless multiplexer <b>360</b>, the second output <b>375</b> of the second glitchless multiplexer <b>360</b> comprising the synthesized clock <b>355</b> when the at least one second digital phase lock loop <b>330</b> is in a lock mode and comprising the first output <b>345</b> of the first glitchless multiplexer <b>350</b> when the at least one second digital phase lock loop <b>330</b> is in the digital phase lock loop high speed bypass mode.

According to various illustrative embodiments, an apparatus, method, and system for enhancement of locked loop operations including clock and voltage scaling on an interface and/or for providing a digital phase lock loop high speed bypass mode are described. In one aspect, the apparatus comprises a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface. The apparatus also comprises a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature. The apparatus also comprises a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency.

In various aspects, the apparatus further comprises a plurality of the plurality of controlled delay line elements each coupled to the delay-locked loop and each arranged to use the unique code to build the delay and generate an appropriate respective delayed data strobe. In various aspects, the apparatus further comprises the interface being arranged to switch between one of the controlled delay line elements and a chain of more than one of the controlled delay line elements based on a handshake protocol with the device power manager when there is no on-going access on a second interface.

In various aspects, the apparatus further comprises the substantially constant fixed frequency clock and the scalable frequency clock being derived from the same clock source. In various aspects, the apparatus further comprises the substantially constant fixed frequency clock and the scalable frequency clock being not balanced. In various aspects, the apparatus further comprises the up to N controlled delay line elements being chained together by at least one multiplexer.

In another aspect, a method for a digital phase lock loop high speed bypass mode comprises providing a first digital phase lock loop in a first clock domain having a high speed clock. The method also comprises providing at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input. The method also comprises controlling the first output of the first glitchless multiplexer according to preselected settings using a device power manager synchronized locally to ensure proper switching. The method also comprises controlling a second output of the second glitchless multiplexer using a control logic element of the at least one second digital phase lock loop, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

In various aspects, the method further comprises the first digital phase lock loop supplying the high speed clock to the at least one second digital phase lock loop. In various aspects, the method further comprises controlling the first output of the first glitchless multiplexer according to preselected settings using the device power manager synchronized locally further comprising using a synchronization element disposed in the at least one second digital phase lock loop.

In various aspects, the method further comprises the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprising the high speed clock. In various aspects, the method further comprises the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprising the low speed system reference clock. In various aspects, the method further comprises the low speed system reference clock being input to the core of the at least one second digital phase lock loop. In various aspects, the method further comprises the control logic element of the at least one second digital phase lock loop being coupled to the core of the at least one second digital phase lock loop.

In yet another aspect, a system for clock and voltage scaling on an interface and for providing a digital phase lock loop high speed bypass mode is provided, the system comprising comprises a device power manager coupled to the interface and arranged to supply a scalable frequency clock to the interface. The system also comprises a delay-locked loop supplied by a substantially constant fixed frequency clock from the device manager and a substantially constant voltage from an embedded low dropout regulator, the delay-locked loop arranged to generate a unique code depending on at least one of process, voltage, and temperature. The system also comprises a plurality of controlled delay line elements coupled to the delay-locked loop and arranged to use the unique code to build a delay and generate an appropriate delayed data strobe, the delay being adjusted by having up to N controlled delay line elements chained together, N being a ratio between the substantially constant fixed frequency and the scalable frequency. The system also comprises a first digital phase lock loop in a first clock domain having a high speed clock. The system also comprises at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input, wherein the device power manager is arranged to control the first output of the first glitchless multiplexer according to preselected settings and synchronized locally to ensure proper switching. The system also comprises a control logic element of the at least one second digital phase lock loop arranged to control a second output of the second glitchless multiplexer, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

In accordance with the present disclosure, an apparatus, system, and method useful for clock and voltage scaling on an interface are disclosed. In various aspects, an apparatus in accordance with the present disclosure may comprise means for clock and voltage scaling on an interface and means for enabling the means for clock and voltage scaling on the interface, both the means for clock and voltage scaling on the interface and the means for enabling the means for clock and voltage scaling on the interface covering corresponding structures and/or materials described herein and equivalents thereof.

In various other aspects, a system in accordance with the present disclosure may comprise means for clock and voltage scaling on an interface, means for enabling the means for clock and voltage scaling on the interface, and means for using the means for clock and voltage scaling on the interface, all of the means for clock and voltage scaling on the interface, the means for enabling the means for clock and voltage scaling on the interface, and the means for using the means for clock and voltage scaling on the interface covering corresponding structures and/or materials described herein and equivalents thereof. In yet various other aspects, a method in accordance with the present disclosure may comprise steps for clock and voltage scaling on an interface and steps for enabling the steps for clock and voltage scaling on the interface, both the steps for clock and voltage scaling on the interface and the steps for enabling the steps for clock and voltage scaling on the interface covering corresponding acts described herein and equivalents thereof.

In accordance with the present disclosure, an apparatus, system, and method useful for providing a digital phase lock loop high speed bypass mode are disclosed. In various aspects, an apparatus in accordance with the present disclosure may comprise means for providing a digital phase lock loop high speed bypass mode and means for enabling the means for providing the digital phase lock loop high speed bypass mode, both the means for providing the digital phase lock loop high speed bypass mode and the means for enabling the means for providing the digital phase lock loop high speed bypass mode covering corresponding structures and/or materials described herein and equivalents thereof.

In various other aspects, a system in accordance with the present disclosure may comprise means for providing a digital phase lock loop high speed bypass mode, means for enabling the means for providing the digital phase lock loop high speed bypass mode, and means for using the means for providing the digital phase lock loop high speed bypass mode, all of the means for providing the digital phase lock loop high speed bypass mode, the means for enabling the means for providing the digital phase lock loop high speed bypass mode, and the means for using the means for providing the digital phase lock loop high speed bypass mode covering corresponding structures and/or materials described herein and equivalents thereof. In yet various other aspects, a method in accordance with the present disclosure may comprise steps for providing a digital phase lock loop high speed bypass mode and steps for enabling the steps for providing the digital phase lock loop high speed bypass mode, both the steps for providing the digital phase lock loop high speed bypass mode and the steps for enabling the steps for providing the digital phase lock loop high speed bypass mode covering corresponding acts described herein and equivalents thereof.

The particular embodiments disclosed above are illustrative only, as the present claimed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular illustrative embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the present claimed subject matter. In particular, every range of values (of the form, “from about a to about b,” or, equivalently, “from approximately a to b,” or, equivalently, “from approximately a-b”) disclosed herein is to be understood as referring to the power set (the set of all subsets) of the respective range of values, in the sense of Georg Cantor. Accordingly, the protection sought herein is as set forth in the claims below.