Instruction encoding for system register bit set and clear

CROSS REFERENCE TO RELATED APPLICATION(S)

0001This application is a continuation of U.S. patent application Ser. No. 10/279,210, which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

0002This invention relates in general to the field of computer architecture, and more specifically to a method and apparatus for instruction encoding to allow atomic updating of specified bit fields within privileged architecture registers in a microprocessor.

BACKGROUND OF THE INVENTION

0003A microprocessor is a digital device that is utilized to execute instructions defined within a computer program. Such instructions include adding two data values together, comparing data values, moving data from one location to another, etc. In addition, a microprocessor is designed to communicate with other devices, such as network controllers, disk drives, keyboards, displays, etc., that are external to it. Typically, such external devices request the attention of the microprocessor by signaling one of several interrupt lines on the microprocessor. When this occurs, the microprocessor halts program execution, runs a special program called an “exception handler” to determine which device requested the interrupt, and what the nature of the interrupt is. Once the microprocessor has determined the nature of the interrupt, it executes an interrupt routine that is specific to the nature of the interrupt. Upon completion, the microprocessor typically returns to the program it was executing before the interrupt occurred.

0004One skilled in the art will appreciate that the above description of interrupt handling is very simplistic. That is, it has not considered the difference between hardware interrupts, software interrupts, internal exceptions, etc., nor has it considered what occurs when multiple interrupts occur simultaneously, or when a second interrupt occurs during processing of a first interrupt. However, the way a microprocessor handles an interrupt is, in many ways, dependent on the specific architecture of the microprocessor. For purposes of illustrating the present invention, an interrupt problem will be described with particular reference to the architecture of MIPS32™ and MIPS64™ microprocessors (hereinafter MIPS® microprocessors) designed by MIPS Technologies, Inc. of Mountain View, Calif.

0005More specifically, like many modern microprocessors, MIPS microprocessors contain privileged architecture registers that are updated during events such as interrupts and exceptions. These registers are not directly accessible by user programs that execute on the microprocessors. Rather, when an interrupt or exception occurs, program execution is halted, and a special program, called an exception handler, is run which accesses the privileged architecture registers, both to determine the nature of the interrupt, and to set or clear bits within one or more of the registers, which control how the interrupt will be handled. (Note: The exception handler typically resides within an area of memory that can only be accessed by the microprocessor if it is in “kernel” mode. That is, to prevent user programs from accessing or changing the contents of the privileged architecture registers, a task switch must first occur which authorizes the execution of the exception handler, and thus access to the registers.) Once the exception handler has read the appropriate privileged registers, and established how the interrupt will be handled, an interrupt service routine is used to service the interrupt. Upon completion of servicing the interrupt, the exception handler returns execution to the user program.

0006A particular privileged architecture register within a MIPS microprocessor is called the status register (SR). The SR contains a number of bit fields that may be examined, and set or cleared, during handling of an interrupt. Like most privileged architecture registers, the SR register cannot be modified directly. Rather, the process for examining and modifying the contents of the SR register involves the steps of: 1) Reading the contents of the SR register into one of the general purpose registers within the microprocessor; 2) Modifying, or setting/clearing particular bits within the general purpose register that contains the contents of the SR register; and 3) Writing the modified contents of the general purpose register back into the SR register. This three-step process is referred to as a R-M-W sequence, and is often required during interrupt processing.

0007Sample program code that performs this R-M-W sequence is shown below:

0008<tables id="TABLE-US-00001" num="00001"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="offset" colwidth="21pt" align="left" /><colspec colname="1" colwidth="42pt" align="left" /><colspec colname="2" colwidth="56pt" align="left" /><colspec colname="3" colwidth="98pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row><row><entry /><entry>Label</entry><entry>Instruction</entry><entry>Operands</entry></row><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>1:</entry><entry>mfc0</entry><entry>t0, SR</entry></row><row><entry /><entry /><entry>or</entry><entry>t0, things_to_set</entry></row><row><entry /><entry /><entry>and</entry><entry>t0, things_to_preserve</entry></row><row><entry /><entry>2:</entry><entry>mtc0</entry><entry>t0, SR</entry></row><row><entry /><entry namest="offset" nameend="3" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0009The first instruction “mfc<b>0</b>” causes the microprocessor to move the contents of the SR register into a general purpose register designated t<b>0</b>. This is the read cycle. The next two instructions “or” and “and” set or preserve particular bits within the t<b>0</b> register, corresponding to the “things_to_set” mask, or the “things_to_preserve” mask. This is the modify cycle. The fourth instruction “mtc<b>0</b>” causes the microprocessor to move the contents of the t<b>0</b> register back into the SR register. This is the write cycle. Specifics relating to which of the SR bits are modified during an interrupt, how the above instructions operate and other information related to the MIPS32 and MIPS64 architectures can be found in the following references, each of which is available from MIPS Technologies, Inc. and incorporated herein by reference in its entirety for all purposes: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0010">1. MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32 Architecture, MIPS Technologies, Inc. (2002);</li><li id="ul0002-0002" num="0011">2. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, MIPS Technologies, Inc. (2002);</li><li id="ul0002-0003" num="0012">3. MIPS32 Architecture For Programmers Volume III: The MIPS32 Privileged Resource Architecture, MIPS Technologies, Inc. (2002);</li><li id="ul0002-0004" num="0013">4. MIPS64 Architecture For Programmers Volume I: Introduction to the MIPS64 Architecture, MIPS Technologies, Inc. (2002);</li><li id="ul0002-0005" num="0014">5. MIPS64 Architecture For Programmers Volume II: The MIPS64 Instruction Set, MIPS Technologies, Inc. (2002);</li><li id="ul0002-0006" num="0015">6. MIPS64 Architecture For Programmers Volume III: The MIPS64 Privileged Resource Architecture, MIPS Technologies, Inc. (2002);</li></ul></li></ul>

0016During execution of an interrupt service routine, it may be desirable to perform the above described R-M-W sequence. One problem that exists is that the R-M-W sequence may itself be interrupted. For example, suppose that the R-M-W sequence described above is executing in response to a first interrupt. Further, suppose a second interrupt occurs between label <b>1</b> and label <b>2</b> above. The processor might halt execution of this R-M-W sequence and begin servicing the second interrupt. Now, suppose that while servicing the second interrupt, the contents of the SR register are changed. Upon return from servicing the second interrupt, the code at label <b>2</b> will write its altered value into SR, but will lose any changes made to the SR register by the second interrupt routine. Such a situation is unacceptable since changes to the SR register cannot be ignored.

0017In response to the above problem, several solutions have been developed to prevent changes in the SR register from being lost or ignored. A first solution is to simply disable all interrupts prior to performing the R-M-W sequence above. However, this situation is a catch-22, because in order to disable interrupts, interrupt mask bits in the SR register must be cleared, the clearing of which requires the same R-M-W sequence! What happens if an interrupt occurs while executing the R-M-W sequence that disables interrupts? One method of solving this problem is to insist that no interrupt change the value of SR during execution of any interrupt code. That is, by requiring that all interrupt code begin by saving off the value of SR, and end by restoring the saved value of SR back into SR, it can be assured that the SR value doesn't change. In many environments, however, this is considered too restrictive, as well as too time consuming. Moreover, in operating environments where interrupt routines are not strictly nested, you can never be sure you return to the spot where the proper SR value can be restored.

0018A second solution is to use a system call to disable interrupts. A system call works by causing an exception that disables interrupts in a single cycle. Then, the R-M-W sequence can proceed without risk of interruption. Many programmers consider use of a system call, to simply overcome the inherent problems of updating the SR register, overly dramatic, and again, too time consuming.

0019Therefore, what is needed is a mechanism that allows a programmer to set or clear bits within a privileged architecture register of a processor, while guaranteeing that the modification process is not interrupted.

0020Furthermore, what is needed is a method and apparatus that sets or clears selected portions of a privileged architecture register atomically (i.e., within a single non-interruptible instruction). By modifying privileged bits atomically, the above presented problems associated with the R-M-W sequence are solved without imposing any additional processing delays, and without insisting that interrupt routines be strictly nested.

0021Furthermore, what is needed is a method and apparatus for encoding within an instruction, what privileged architecture register is to be affected by the instruction, what bits are to be set or cleared within the control register, and where the previous contents of the control register are to be saved (if requested).

SUMMARY

0022The present invention provides a method and apparatus for encoding an instruction to atomically set or clear specified bits within a privileged architecture register when a microprocessor is in a privileged state.

0023In one aspect, the present invention provides a microprocessor having a privileged architecture register that is modifiable by instructions, the privileged architecture register having bit fields. The microprocessor includes an execution core that receives the instructions and modifies the privileged architecture register upon execution of the instructions. The instructions include a first operand which specifies the privileged architecture register as a register to be modified. The instructions further include a second operand which specifies a bit field within the privileged architecture register to be modified. The instructions further include a third operand which specifies whether the bit field is to be set or cleared. The bit field in the privileged architecture register is modified atomically when the instructions execute.

0024In another aspect, the present invention provides a method for atomically setting or clearing a bit field within a privileged architecture register of a microprocessor. The method includes: providing a privileged instruction which instructs the microprocessor to set or clear the bit field within the privileged architecture register. The privileged instruction includes: a first operand for specifying which one of a plurality of privileged architecture registers contains the bit field to be set or cleared, and a designator for specifying whether the bit field is to be set or cleared. The method further includes decoding the privileged instruction by examining the first operand to determine which one of the plurality of privileged architecture registers contains the bit field, and by examining the designator to determine whether the bit field is to be set or cleared; and executing the privileged instruction thereby causing the bit field to be atomically set or cleared according to the designator.

0025In a further aspect, the present invention provides a disable interrupt instruction for execution on a microprocessor, the microprocessor having a privileged architecture register. The disable interrupt instruction atomically executes on the microprocessor when the microprocessor is in a privileged state. The disable interrupt instruction includes an opcode an operand and a designator. The opcode specifies that a bit field within the privileged architecture register is to be modified. The operand specifies which one of a plurality of bit fields within the privileged architecture register is the bit field to be modified. The designator specifies that the modification to be performed on the specified bit field is to clear the bit field. When the disable interrupt instruction executes on the microprocessor, the specified bit field is cleared, atomically.

0026In a further aspect, the present invention provides a computer program product for use with a computing device. The computer program product includes: a computer usable medium, having computer readable program code embodied in said medium, for causing a microprocessor having a privileged architecture register that is modifiable by a plurality of instructions, the privileged architecture register having bit fields, to be described. The computer readable program code includes first program code for providing an execution core, for receiving the plurality of instructions and for modifying the privileged architecture register upon execution of one of the plurality of instructions; and second program code for providing the plurality of instructions. Each of the plurality of instructions includes: a first field, for specifying the privileged architecture register as a register to be modified; a second field, for specifying a bit within the privileged architecture register to be modified; and a third field, for specifying whether the bit is to be set or cleared. The bit in the privileged architecture register is modified atomically by the plurality of instructions.

0027In yet another aspect, the present invention provides a computer data signal embodied in a transmission medium comprising. The computer-readable program code provides a disable interrupt instruction for execution on a microprocessor, the microprocessor having a privileged architecture register, the disable interrupt instruction executing on the microprocessor when the microprocessor is in a privileged state. The program code includes first program code for providing an opcode for specifying that a bit field within the privileged architecture register is to be modified; second program code for providing an operand for specifying which one of a plurality of bit fields within the privileged architecture register is the bit field to be modified; and third program code for providing a designator, for specifying that the modification to be performed on the specified bit field is to clear the bit field. When the disable interrupt instruction executes on the microprocessor, the specified bit field is cleared, atomically.

0028Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

0029<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of a microprocessor coupled to Coprocessors according to the present invention.

0030<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram illustrating the bits of a Coprocessor <b>0</b> status register (SR).

0031<figref idref="DRAWINGS">FIG. 3</figref> is a flow chart illustrating a read-modify-write (R-M-W) sequence required for updating the status register in Coprocessor <b>0</b>.

0032<figref idref="DRAWINGS">FIG. 4</figref> is a flow chart illustrating one methodology for dealing with an interrupt during the SR update process provided in <figref idref="DRAWINGS">FIG. 3</figref>.

0033<figref idref="DRAWINGS">FIG. 5</figref> is a flow chart illustrating a second methodology for dealing with an interrupt during the SR update process provided in <figref idref="DRAWINGS">FIG. 3</figref>.

0034<figref idref="DRAWINGS">FIG. 6</figref> is a table illustrating two instructions for atomically updating a privileged architecture register within a microprocessor.

0035<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram illustrating the bit architecture for a DI instruction according to the present invention.

0036<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram illustrating the bit architecture for an EI instruction according to the present invention.

0037<figref idref="DRAWINGS">FIG. 9</figref> is a flow chart illustrating the impact of an interrupt receiving during an atomic update of a privileged architecture register using the atomic update instructions illustrated in <figref idref="DRAWINGS">FIGS. 6-8</figref>.

DETAILED DESCRIPTION

0038Referring to <figref idref="DRAWINGS">FIG. 1</figref>, a block diagram <b>100</b> is shown illustrating a microprocessor (or CPU) <b>102</b> coupled to a floating point Coprocessor <b>112</b> and a second Coprocessor <b>114</b> via an interface bus <b>116</b>. In one embodiment, the second Coprocessor <b>114</b> may be a graphics Coprocessor, an audio Coprocessor, or any other Coprocessor capable of executing instructions not designed specifically for the CPU <b>102</b>. The CPU <b>102</b> includes an execution core <b>104</b>, having decode logic <b>105</b>, coupled to a general purpose register file (GPR) <b>106</b> for receiving instructions from memory (or a cache) and for execution of CPU <b>102</b> instructions. One skilled in the art will appreciate that the execution core <b>104</b> includes one or more pipelines for executing instructions, including all states necessary to decode, execute and write back results. The GPR <b>106</b> has a number of architecturally visible registers, including a register rt <b>107</b>. The decode logic <b>105</b> receives an instruction, and decodes bit fields in the instruction to allow the execution core <b>104</b> to execute the instruction. In one embodiment, the processor <b>102</b> is a RISC microprocessor, although one skilled in the art should appreciate that the present invention could also be implemented within a CISC processor, where the decode logic <b>105</b> acts as a translator between macro instructions and micro instructions.

0039When floating point instructions are presented to the core <b>104</b>, it provides those instructions to the floating point Coprocessor <b>112</b> for execution. When instructions are presented to the core <b>104</b> that are designed for the second Coprocessor <b>114</b>, the CPU <b>102</b> provides those instructions to the second Coprocessor <b>114</b>. While the present invention is not restricted to any specific CPU, for purposes of discussion, the invention will be described with reference to the MIPS 32 and 64 bit processor architectures, available from MIPS Technologies, Inc. of Mountain View, Calif.

0040In addition to its normal computational functions, the CPU <b>102</b> includes a control unit to handle interrupts <b>120</b>, configuration options e.g., such as the endianness of data, and observing or controlling on-chip functions like caches and timers. The control unit within the CPU <b>102</b> for performing such tasks is called Coprocessor <b>0</b><b>108</b>, or CP<b>0</b>. CP<b>0</b><b>108</b> is coupled to control registers <b>110</b> which contain values that set how the CPU <b>102</b> is to operate. A portion of the control registers are shown expanded out in block <b>111</b>. Blocks <b>110</b> and <b>111</b> are equivalent, but block <b>111</b> particularly illustrates a portion of the control registers within the block <b>110</b>, including: PRId, SR, Cause, EPC, BadVaddr, MMU, Count, and etc. . . Etc. indicates that other control registers are within the block <b>110</b>, but are not shown. For a complete listing of the control registers <b>110</b> within the MIPS 32/64 bit architecture, reference is made to Table 1 below. A complete description of each of these registers may be found in the MIPS32 and MIPS64 architecture Specifications, which are available from MIPS Technologies, Inc., and which are incorporated herein by reference for all purposes.

0041CP<b>0</b> provides an abstraction of the functions necessary to support an operating system: exception handling, memory management, scheduling, and control of critical resources. The interface to CP<b>0</b> is through various instructions encoded with a COP<b>0</b> opcode, including the ability to move data to and from the control registers <b>110</b>. The control registers <b>110</b> and the interaction with them make up what is called the Privileged Resource Architecture.

0042<tables id="TABLE-US-00002" num="00002"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="35pt" align="center" /><colspec colname="2" colwidth="14pt" align="center" /><colspec colname="3" colwidth="49pt" align="left" /><colspec colname="4" colwidth="119pt" align="left" /><thead><row><entry namest="1" nameend="4" rowsep="1">TABLE 1</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry>Register</entry><entry /><entry /><entry /></row><row><entry>Number</entry><entry>Sel</entry><entry>Register Name</entry><entry>Function</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="35pt" align="char" char="." /><colspec colname="2" colwidth="14pt" align="center" /><colspec colname="3" colwidth="49pt" align="left" /><colspec colname="4" colwidth="119pt" align="left" /><tbody valign="top"><row><entry>0</entry><entry>0</entry><entry>Index</entry><entry>Index into the TLB array</entry></row><row><entry>1</entry><entry>0</entry><entry>Random</entry><entry>Randomly generated index into the</entry></row><row><entry /><entry /><entry /><entry>TLB array</entry></row><row><entry>2</entry><entry>0</entry><entry>EntryLo0</entry><entry>Low-order portion of the TLB entry for</entry></row><row><entry /><entry /><entry /><entry>even-numbered virtual pages</entry></row><row><entry>3</entry><entry>0</entry><entry>EntryLo1</entry><entry>Low-order portion of the TLB entry for</entry></row><row><entry /><entry /><entry /><entry>odd-numbered virtual pages</entry></row><row><entry>4</entry><entry>0</entry><entry>Context</entry><entry>Pointer to page table entry in memory</entry></row><row><entry>5</entry><entry>0</entry><entry>PageMask</entry><entry>Control for variable page size in TLB</entry></row><row><entry /><entry /><entry /><entry>entries</entry></row><row><entry>6</entry><entry>0</entry><entry>Wired</entry><entry>Controls the number of fixed (“wired”)</entry></row><row><entry /><entry /><entry /><entry>TLB entries</entry></row><row><entry>7</entry><entry>All</entry><entry /><entry>Reserved for future extensions</entry></row><row><entry>8</entry><entry>0</entry><entry>BadVAddr</entry><entry>Reports the address for the most</entry></row><row><entry /><entry /><entry /><entry>recent address-related exception</entry></row><row><entry>9</entry><entry>0</entry><entry>Count</entry><entry>Processor cycle count</entry></row><row><entry>10</entry><entry>0</entry><entry>EntryHi</entry><entry>High-order portion of the TLB entry</entry></row><row><entry>11</entry><entry>0</entry><entry>Compare</entry><entry>Timer interrupt control</entry></row><row><entry>12</entry><entry>0</entry><entry>Status</entry><entry>Processor status and control</entry></row><row><entry>13</entry><entry>0</entry><entry>Cause</entry><entry>Cause of last general exception</entry></row><row><entry>14</entry><entry>0</entry><entry>EPC</entry><entry>Program counter at last exception</entry></row><row><entry>15</entry><entry>0</entry><entry>PRId</entry><entry>Processor identification and revision</entry></row><row><entry>16</entry><entry>0</entry><entry>Config</entry><entry>Configuration register</entry></row><row><entry>16</entry><entry>1</entry><entry>Config1</entry><entry>Configuration register 1</entry></row><row><entry>17</entry><entry>0</entry><entry>LLAddr</entry><entry>Load linked address</entry></row><row><entry>18</entry><entry>0-n</entry><entry>WatchLo</entry><entry>Watchpoint address</entry></row><row><entry>19</entry><entry>0-n</entry><entry>WatchHi</entry><entry>Watchpoint control</entry></row><row><entry>20</entry><entry>0</entry><entry>XContext</entry><entry>XContext in 64-bit implementations</entry></row><row><entry>21</entry><entry>All</entry><entry /><entry>Reserved for future extensions</entry></row><row><entry>22</entry><entry>All</entry><entry /><entry>Available for implementation</entry></row><row><entry /><entry /><entry /><entry>dependent use</entry></row><row><entry>23</entry><entry>0</entry><entry>Debug</entry><entry>EJTAG Debug register</entry></row><row><entry>24</entry><entry>0</entry><entry>DEPC</entry><entry>Program counter at last EJTAG</entry></row><row><entry /><entry /><entry /><entry>debug exception</entry></row><row><entry>25</entry><entry>0-n</entry><entry>PerfCnt</entry><entry>Performance counter interface</entry></row><row><entry>26</entry><entry>0</entry><entry>ErrCtl</entry><entry>Parity/ECC error control and status</entry></row><row><entry>27</entry><entry>0-3</entry><entry>CacheErr</entry><entry>Cache parity error control and status</entry></row><row><entry>28</entry><entry>0</entry><entry>TagLo</entry><entry>Low-order portion of cache tag</entry></row><row><entry /><entry /><entry /><entry>interface</entry></row><row><entry>28</entry><entry>1</entry><entry>DataLo</entry><entry>Low-order portion of cache data</entry></row><row><entry /><entry /><entry /><entry>interface</entry></row><row><entry>29</entry><entry>0</entry><entry>TagHi</entry><entry>High-order portion of cache tag</entry></row><row><entry /><entry /><entry /><entry>interface</entry></row><row><entry>29</entry><entry>1</entry><entry>DataHi</entry><entry>High-order portion of cache data</entry></row><row><entry /><entry /><entry /><entry>interface</entry></row><row><entry>30</entry><entry>0</entry><entry>ErrorEPC</entry><entry>Program counter at last error</entry></row><row><entry>31</entry><entry>0</entry><entry>DESAVE</entry><entry>EJTAG debug exception save register</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0043Referring to <figref idref="DRAWINGS">FIG. 2</figref> a block diagram <b>200</b> is shown illustrating the bit fields within a status register (SR) that is located within the control registers <b>110</b> of CPO <b>108</b>. For a description of each of the bit fields within the SR, reference is made to Table 2 below.

0044<tables id="TABLE-US-00003" num="00003"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="3"><colspec colname="1" colwidth="56pt" align="center" /><colspec colname="2" colwidth="133pt" align="left" /><colspec colname="3" colwidth="28pt" align="left" /><thead><row><entry namest="1" nameend="3" rowsep="1">TABLE 2</entry></row></thead><tbody valign="top"><row><entry namest="1" nameend="3" align="center" rowsep="1" /></row><row><entry>Fields</entry><entry /><entry>Read/</entry></row></tbody></tgroup><tgroup align="left" colsep="0" rowsep="0" cols="4"><colspec colname="1" colwidth="28pt" align="left" /><colspec colname="2" colwidth="28pt" align="center" /><colspec colname="3" colwidth="133pt" align="left" /><colspec colname="4" colwidth="28pt" align="left" /><tbody valign="top"><row><entry>Name</entry><entry>Bits</entry><entry>Description</entry><entry>Write</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry>CU</entry><entry>31:28</entry><entry>Controls access to Coprocessors 3, 2,</entry><entry>R/W</entry></row><row><entry /><entry /><entry>1, and 0, respectively:</entry></row><row><entry /><entry /><entry>0: access not allowed</entry></row><row><entry /><entry /><entry>1: access allowed</entry></row><row><entry /><entry /><entry>Coprocessor 0 is always usable when</entry></row><row><entry /><entry /><entry>the processor is running in Kernel Mode</entry></row><row><entry /><entry /><entry>or Debug Mode, independent of the</entry></row><row><entry /><entry /><entry>state of the CU₀bit.</entry></row><row><entry /><entry /><entry>If there is no provision for connecting a</entry></row><row><entry /><entry /><entry>Coprocessor, the corresponding CU bit</entry></row><row><entry /><entry /><entry>must be ignored on write and read as</entry></row><row><entry /><entry /><entry>zero.</entry></row><row><entry>RP</entry><entry>27</entry><entry>Enables reduced power mode on some</entry><entry>R/W</entry></row><row><entry /><entry /><entry>implementations. The specific</entry></row><row><entry /><entry /><entry>operation of this bit is implementation</entry></row><row><entry /><entry /><entry>dependent.</entry></row><row><entry /><entry /><entry>If this bit is not implemented, it must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero. If</entry></row><row><entry /><entry /><entry>this bit is implemented, the reset state</entry></row><row><entry /><entry /><entry>must be zero so that the processor</entry></row><row><entry /><entry /><entry>starts at full performance.</entry></row><row><entry>FR</entry><entry>26</entry><entry>Controls the floating point register mode</entry><entry>R</entry></row><row><entry /><entry /><entry>on 64-bit MIPS processors. Not used</entry></row><row><entry /><entry /><entry>by MIPS32 processors. This bit must</entry></row><row><entry /><entry /><entry>be ignored on write and read as zero.</entry></row><row><entry>RE</entry><entry>25</entry><entry>Used to enable reverse-endian memory</entry><entry>R/W</entry></row><row><entry /><entry /><entry>references while the processor is</entry></row><row><entry /><entry /><entry>running in user mode:</entry></row><row><entry /><entry /><entry>0: User mode uses configured</entry></row><row><entry /><entry /><entry>endianness</entry></row><row><entry /><entry /><entry>1: User mode uses reversed</entry></row><row><entry /><entry /><entry>endianness</entry></row><row><entry /><entry /><entry>Neither Kernel Mode nor Supervisor</entry></row><row><entry /><entry /><entry>Mode references are affected by the</entry></row><row><entry /><entry /><entry>state of this bit.</entry></row><row><entry /><entry /><entry>If this bit is not implemented, it must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry>MX</entry><entry>24</entry><entry>Enables access to MDMX* resources</entry><entry>R</entry></row><row><entry /><entry /><entry>on MIPS64* processors. Not used by</entry></row><row><entry /><entry /><entry>MIPS32* processors. This bit must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry>PX</entry><entry>23</entry><entry>Enables access to 64-bit operations on</entry><entry>R</entry></row><row><entry /><entry /><entry>MIPS64 processors. Not used by</entry></row><row><entry /><entry /><entry>MIPS32 processors. This bit must</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry>BEV</entry><entry>22</entry><entry>Controls the location of exception</entry><entry>R/W</entry></row><row><entry /><entry /><entry>vectors:</entry></row><row><entry /><entry /><entry>0: Normal</entry></row><row><entry /><entry /><entry>1: Bootstrap</entry></row><row><entry>TS</entry><entry>21</entry><entry>Indicates that the TLB has detected a</entry><entry>R/W</entry></row><row><entry /><entry /><entry>match on multiple entries. It is</entry></row><row><entry /><entry /><entry>implementation dependent whether this</entry></row><row><entry /><entry /><entry>detection occurs at all, on a write to the</entry></row><row><entry /><entry /><entry>TLB, or an access to the TLB. When</entry></row><row><entry /><entry /><entry>such a detection occurs, the processor</entry></row><row><entry /><entry /><entry>initiates a machine check exception and</entry></row><row><entry /><entry /><entry>sets this bit. It is implementation</entry></row><row><entry /><entry /><entry>dependent whether this condition can</entry></row><row><entry /><entry /><entry>be corrected by software. If the</entry></row><row><entry /><entry /><entry>condition can be corrected, this bit</entry></row><row><entry /><entry /><entry>should be cleared before resuming</entry></row><row><entry /><entry /><entry>normal operation.</entry></row><row><entry /><entry /><entry>If this bit is not implemented, it must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry /><entry /><entry>Software writes to this bit may not</entry></row><row><entry /><entry /><entry>cause a 0-1 transition. Hardware may</entry></row><row><entry /><entry /><entry>ignore software attempts to cause such</entry></row><row><entry /><entry /><entry>a transition.</entry></row><row><entry>SR</entry><entry>20</entry><entry>Indicates that the entry through the</entry><entry>R/W</entry></row><row><entry /><entry /><entry>reset exception vector was due to a</entry></row><row><entry /><entry /><entry>Soft Reset:</entry></row><row><entry /><entry /><entry>0: Not Soft Reset (NMI or Reset)</entry></row><row><entry /><entry /><entry>1: Soft Reset</entry></row><row><entry /><entry /><entry>If this bit is not implemented, it must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry /><entry /><entry>Software may only write a zero to this</entry></row><row><entry /><entry /><entry>bit to clear the SR condition. Hardware</entry></row><row><entry /><entry /><entry>may ignore software attempts to write a</entry></row><row><entry /><entry /><entry>one to this bit.</entry></row><row><entry>NMI</entry><entry>19</entry><entry>Indicates that the entry through the</entry><entry>R/W</entry></row><row><entry /><entry /><entry>reset exception vector was due to an</entry></row><row><entry /><entry /><entry>NMI</entry></row><row><entry /><entry /><entry>0: Not NMI (Soft Reset or Reset)</entry></row><row><entry /><entry /><entry>1: NMI</entry></row><row><entry /><entry /><entry>If this bit is not implemented, it must be</entry></row><row><entry /><entry /><entry>ignored on write and read as zero.</entry></row><row><entry /><entry /><entry>Software may only write a zero to this</entry></row><row><entry /><entry /><entry>bit to clear the NMI condition.</entry></row><row><entry /><entry /><entry>Hardware may ignore software attempts</entry></row><row><entry /><entry /><entry>to write a one to this bit.</entry></row><row><entry>0</entry><entry>18</entry><entry>Must be written as zero; returns zero on</entry><entry>0</entry></row><row><entry /><entry /><entry>read</entry></row><row><entry>Impl</entry><entry>17:16</entry><entry>These bits are implementation</entry></row><row><entry /><entry /><entry>dependent and not defined by the</entry></row><row><entry /><entry /><entry>architecture. If they are not</entry></row><row><entry /><entry /><entry>implemented, they must be ignored on</entry></row><row><entry /><entry /><entry>write and read as zero.</entry></row><row><entry>IM7-</entry><entry>15:8 </entry><entry>Interrupt Mask: Controls the enabling of</entry><entry>R/W</entry></row><row><entry>IM0</entry><entry /><entry>each of the external, internal and</entry></row><row><entry /><entry /><entry>software interrupts.</entry></row><row><entry /><entry /><entry>0: interrupt request disabled</entry></row><row><entry /><entry /><entry>1: interrupt request enabled</entry></row><row><entry>KX</entry><entry> 7</entry><entry>Enables access to 64-bit kernel address</entry><entry>R</entry></row><row><entry /><entry /><entry>space on 64-bit MIPS processors. Not</entry></row><row><entry /><entry /><entry>used by MIPS32* processors. This bit</entry></row><row><entry /><entry /><entry>must be ignored on write and read as</entry></row><row><entry /><entry /><entry>zero</entry></row><row><entry>SX</entry><entry> 6</entry><entry>Enables access to 64-bit supervisor</entry><entry>R</entry></row><row><entry /><entry /><entry>address space on 64-bit MIPS</entry></row><row><entry /><entry /><entry>processors. Not used by MIPS32*</entry></row><row><entry /><entry /><entry>processors. This bit must be ignored on</entry></row><row><entry /><entry /><entry>write and read as zero.</entry></row><row><entry>UX</entry><entry> 5</entry><entry>Enables access to 64-bit user address</entry><entry>R</entry></row><row><entry /><entry /><entry>space on 64-bit MIPS processors. Not</entry></row><row><entry /><entry /><entry>used by MIPS32* processors. This bit</entry></row><row><entry /><entry /><entry>must be ignored on write and read as</entry></row><row><entry /><entry /><entry>zero.</entry></row><row><entry>KSU</entry><entry>4:3</entry><entry>If Supervisor Mode is implemented, the</entry><entry>R/W</entry></row><row><entry /><entry /><entry>encoding of this field denotes the base</entry></row><row><entry /><entry /><entry>operating mode of the processor. The</entry></row><row><entry /><entry /><entry>encoding of this field is:</entry></row><row><entry /><entry /><entry>00: Base mode is Kernel Mode</entry></row><row><entry /><entry /><entry>01: Base mode is Supervisor Mode</entry></row><row><entry /><entry /><entry>10: Base mode is User Mode</entry></row><row><entry /><entry /><entry>11: Reserved. The operation of the</entry></row><row><entry /><entry /><entry>processor is UNDEFINED if this value is</entry></row><row><entry /><entry /><entry>written to the KSU field</entry></row><row><entry /><entry /><entry>Note: This field overlaps the UM and</entry></row><row><entry /><entry /><entry>R0 fields, described below.</entry></row><row><entry>ERL</entry><entry> 2</entry><entry>Error Level; Set by the processor when</entry><entry>R/W</entry></row><row><entry /><entry /><entry>a Reset, Soft Reset, NMI or Cache</entry></row><row><entry /><entry /><entry>Error exception is taken.</entry></row><row><entry /><entry /><entry>0: normal level</entry></row><row><entry /><entry /><entry>1: error level</entry></row><row><entry /><entry /><entry>When ERL is set:</entry></row><row><entry /><entry /><entry>The processor is running in Kernel</entry></row><row><entry /><entry /><entry>Mode</entry></row><row><entry /><entry /><entry>Interrupts are disabled</entry></row><row><entry /><entry /><entry>The ERET instruction will use the</entry></row><row><entry /><entry /><entry>return address held in ErrorEPC instead</entry></row><row><entry /><entry /><entry>of EPC</entry></row><row><entry /><entry /><entry>The lower 2²⁹bytes of kuseg are</entry></row><row><entry /><entry /><entry>tread as an unmapped and uncached</entry></row><row><entry /><entry /><entry>region. This allows main memory to be</entry></row><row><entry /><entry /><entry>accessed in the presence of cache</entry></row><row><entry /><entry /><entry>errors. The operation of the processor</entry></row><row><entry /><entry /><entry>is UNDEFINED if the ERL bit is set</entry></row><row><entry /><entry /><entry>while the processor is executing</entry></row><row><entry /><entry /><entry>instructions from kuseg.</entry></row><row><entry>EXL</entry><entry> 1</entry><entry>Exception Level; Set by the processor</entry><entry>R/W</entry></row><row><entry /><entry /><entry>when any exception other than Reset,</entry></row><row><entry /><entry /><entry>Soft Reset, NMI or cache Error</entry></row><row><entry /><entry /><entry>exception is taken.</entry></row><row><entry /><entry /><entry>0: normal level</entry></row><row><entry /><entry /><entry>1: exception level</entry></row><row><entry /><entry /><entry>When EXL is set:</entry></row><row><entry /><entry /><entry>The processor is running in Kernel</entry></row><row><entry /><entry /><entry>Mode</entry></row><row><entry /><entry /><entry>Interrupts are disabled</entry></row><row><entry /><entry /><entry>TLB refill exceptions will use the</entry></row><row><entry /><entry /><entry>general exception vector instead of the</entry></row><row><entry /><entry /><entry>TLB refill vector.</entry></row><row><entry /><entry /><entry>EPC and Cause_BDwill not be updated</entry></row><row><entry /><entry /><entry>if another exception is taken</entry></row><row><entry>IE</entry><entry> 0</entry><entry>Interrupt Enable: Acts as the master</entry><entry>R/W</entry></row><row><entry /><entry /><entry>enable for software and hardware</entry></row><row><entry /><entry /><entry>interrupts:</entry></row><row><entry /><entry /><entry>0: disable interrupts</entry></row><row><entry /><entry /><entry>1: enables interrupts</entry></row><row><entry namest="1" nameend="4" align="center" rowsep="1" /></row><row><entry namest="1" nameend="4" align="left" id="FOO-00001">*Information about MIPS32, MIPS64, MDMX architecture specifications are available from MIPS Technologies, Inc of Mountain View, California.</entry></row></tbody></tgroup></table></tables>

0045While the invention, as it will be described below, may be implemented to modify the contents of any of these registers, as well as registers within the floating point Coprocessor <b>112</b>, or the other Coprocessor <b>114</b>, it will be particularly described with reference to register number <b>12</b>, called the status register (SR). That is, the present invention can be used to atomically modify bits within a variety of registers, for a variety of different purposes. Atomically implies that modification of the bits is performed without interruption by either the processor or devices outside the processor. Alternatively, atomically implies that the bits are modified by a single instruction being executed by the microprocessor. However, to provide a context for appreciating the novel aspects of the present invention, the discussion below will focus on updating bit <b>0</b> of the SR register—the bit associated with enabling and disabling of interrupts for the processor <b>102</b>. One skilled in the art will readily appreciate how the present invention can alternatively specify other bits within the SR register, or within other registers, to be modified.

0046With the above understanding of the control registers <b>110</b> within the control unit <b>108</b> of processor <b>102</b>, an overview will first be provided of interrupt handling within the processor <b>102</b>, with reference to <figref idref="DRAWINGS">FIGS. 3-5</figref>. An embodiment of the present invention will then be described with reference to <figref idref="DRAWINGS">FIGS. 6-9</figref>.

0047When an interrupt occurs during execution of either a user program, or in the middle of servicing another interrupt, the CPU <b>102</b> may be required to modify bits within the SR register <b>200</b>. The logical flow of such modification is shown below with reference to <figref idref="DRAWINGS">FIG. 3</figref>.

0048In <figref idref="DRAWINGS">FIG. 3</figref>, a flow chart <b>300</b> is provided that particularly illustrates program flow within the CPU <b>102</b> upon occurrence of an interrupt. A user mode program <b>301</b> is shown executing, until an interrupt <b>303</b> occurs. One skilled in the art will appreciate that the interrupt may occur from any of a number of sources external to the CPU <b>102</b>, or from the CPU <b>102</b> itself. At this point, all instructions that have successfully completed execution within the CPU <b>102</b> continue to pass thru remaining pipeline stages (not shown) within the CPU <b>102</b>. However, instructions that have not yet completed execution are halted, and will be restarted upon return from the interrupt.

0049Within the MIPS architecture, when an interrupt occurs, the interrupt will be serviced by the CPU <b>102</b> if: 1) interrupts are enabled (the IE bit within the SR register is set); 2) the mask bit (IMO-<b>7</b>) for the particular interrupt is set; and 3) the EXL bit is clear. Otherwise, the CPU <b>102</b> will ignore interrupts. More specifically, if the CPU <b>102</b> is in user mode, the EXL bit is clear. When an interrupt occurs, the interrupt will cause the EXL bit to be set, thereby disabling all further interrupts until the EXL bit is cleared. So, if the CPU <b>102</b> is in user mode when interrupt <b>303</b> occurs, the EXL bit is set by the interrupt, and instruction flow proceeds to decision block <b>302</b>. The EXL bit is described above in Table 2.

0050At decision block <b>302</b> a determination is made as to whether the interrupt will require very little processing, or significant processing (as determined from the type of interrupt). If the interrupt serviced by the routine can be completed in just a few instructions, the programmer may allow the EXL bit to remain set, thereby disabling further interrupts while servicing the interrupt. If the programmer determines that the interrupt will require very little processing, and that there is no need to re-enable other interrupts, flow proceeds to block <b>304</b>. Otherwise, flow proceeds to block <b>306</b>.

0051At block <b>304</b>, the interrupt is serviced. Upon completion of servicing the interrupt, the CPU <b>102</b> executes a return from exception instruction to cause the processor to jump back to user mode where it left off. In addition, the return from exception instruction clears the EXL bit to allow interrupts.

0052Back at decision block <b>302</b>, if the interrupt requires more significant time to process, the programmer may wish to re-enable other interrupts before proceeding with the processing. Flow therefore proceeds to block <b>306</b>.

0053At block <b>306</b>, the state of the CPU <b>102</b> is stored to memory. One skilled in the art will appreciate that the state of the processor includes the contents of the EPC register (i.e., the register holding the contents of the program counter prior to jumping to the exception handler), the SR, and possibly other state information. The state of the processor is stored prior to enabling interrupts so that if the exception routine is interrupted, and the contents of SR and/or EPC get overwritten, they may later be restored. Flow then proceeds to block <b>308</b>.

0054At block <b>308</b> interrupts are re-enabled. To accomplish this, the programmer clears the EXL bit, and modifies the contents of the interrupt mask bits (IMO-<b>7</b>) to disable the interrupt bit pertaining to the present interrupt, while enabling other interrupts. Clearing and modification of bits in the SR register have not, prior to the present invention, been modified directly. Rather, bits in status registers, such as SR, are first moved into the GPR <b>106</b>, then modified, and then moved back to the SR. So, at block <b>308</b> the contents of the SR register are moved to a register within the GPR <b>106</b>. Then, according to the exception handler program, particular bits within the SR are set or cleared in the copy of SR that was moved to GPR <b>106</b>. Such bits include the interrupt mask bits IMO-<b>7</b>, the EXL bit, and possibly the interrupt enable bit (IE). After modification, the contents of the register in GPR <b>106</b> that contains the modified fields within the SR are moved back into the SR register. At this point, updating of the SR register is complete, and interrupts are re-enabled. One skilled in the art will appreciate at this point that the R-M-W sequence has not been interrupted because during the modification, the EXL bit is still set. Flow then proceeds to block <b>310</b>.

0055At block <b>310</b>, the service routine for the particular interrupt executes. Upon completion of servicing the interrupt, it is necessary to restore the state of the CPU <b>102</b> to the state it was in before the interrupt occurred. However, since restoring the state of the processor requires a R-M-W sequence that may itself be interrupted, interrupts are first disabled. This is shown at block <b>312</b>.

0056At block <b>312</b>, the contents of the SR register are moved to a register in the GPR <b>106</b>, the interrupt enable (IE) bit is cleared thereby disabling interrupts, and the contents of the register in the GPR <b>106</b> are moved back to the SR. Once the IE bit in the SR has been cleared, the state of the CPU <b>102</b> may be restored without fear of being interrupted. Flow then proceeds to block <b>314</b>.

0057At block <b>314</b>, the state of the CPU <b>102</b> is restored. EPC is restored from memory, SR is restored from memory, and any other state information that was stored in block <b>306</b> is restored. A return from the exception places the contents of EPC into the program counter of the CPU <b>102</b> to cause instruction flow to begin again at the point of interruption.

0058The flow chart of <figref idref="DRAWINGS">FIG. 3</figref> is provided to particularly illustrate several aspects of interrupt handling. The first is that when an interrupt occurs, a context switch is made to kernel mode within the CPU <b>102</b>, unless of course the CPU <b>102</b> is already executing in kernel mode (in which case a switch is made to Kernel mode with the EXL bit being set). That is, interrupt service routines, exception handlers, etc., that require access to the control registers <b>110</b> within the CPU <b>102</b>, operate in a different, i.e., higher privilege level than user programs (since user programs do not have access to the control registers <b>110</b>).

0059In addition, when an interrupt occurs, if the service routine requires more than a few instructions to execute, the state of the processor must first be stored into memory, and interrupts re-enabled. Upon completion of servicing the interrupt, the state of the processor must be restored. However, since interrupts may still occur, interrupts must first be disabled prior to restoring the state of the processor. But, to disable interrupts, a R-M-W sequence must occur between the SR and the GPR <b>106</b>, a sequence which itself might be interrupted.

0060<figref idref="DRAWINGS">FIG. 4</figref> provides a flow chart <b>400</b> illustrating the effect of multiple interrupts while handling the first interrupt described above in <figref idref="DRAWINGS">FIG. 3</figref>. Suppose an interrupt <b>402</b> occurs prior to deciding whether the first interrupt is going to be time consuming, or while handling a short interrupt. At this point, interrupt <b>402</b> will be ignored because the EXL bit remains set, thereby disabling all interrupts. Therefore, no problem occurs with respect to the state of the CPU <b>102</b>, or the SR register.

0061Suppose an interrupt <b>404</b> occurs while the state of the CPU <b>102</b> is being saved, or while other interrupts are being enabled at block <b>306</b>. At this point, the EXL bit is still set thereby disabling interrupt <b>404</b>. The state of the CPU <b>102</b> is preserved, and the instruction flow that modifies the SR is preserved. Still there is no problem.

0062Suppose however that an interrupt <b>406</b> occurs after interrupts have been re-enabled. Recall that to insure that the CPU <b>102</b> returns to the state that it was in prior to handling the first interrupt, its state at the time of the first interrupt must be restored. The restoration of the state of the SR however is a R-M-W sequence that itself may be interrupted. That is why block <b>312</b> disables interrupts prior to restoring the state of the CPU <b>102</b>. But, block <b>312</b> may itself be interrupted. If this occurs, it is possible that the state of the CPU <b>102</b> might not be restored to the condition it was in before the interrupt. Such an instance can be disastrous.

0063Referring now to <figref idref="DRAWINGS">FIG. 5</figref>, a flow chart <b>500</b> is shown that illustrates a methodology for insuring that the R-M-W sequence of block <b>312</b> is not prevented from accomplishing its purpose completing and proceeding to block <b>314</b>. More specifically, <figref idref="DRAWINGS">FIG. 5</figref> illustrates a requirement that all interrupt service routines be strictly nested. That is, that all interrupts store the state of CP<b>0</b> prior to proceeding, restore it upon completion, and always return to the location they interrupted.

0064Flow starts at block <b>502</b> where update of the SR begins (such as the disabling of interrupts by clearing the IE bit, as shown in block <b>312</b>). Flow then proceeds to block <b>504</b>.

0065At block <b>504</b>, the contents of the SR register are moved to the GPR <b>106</b>. At this point, an interrupt <b>530</b> occurs. Since the interrupt <b>530</b> has not been disabled, program flow jumps to an exception handler that begins an interrupt service routine, at block <b>512</b>. Flow then proceeds to block <b>514</b>.

0066At block <b>514</b>, to insure that the contents of the SR are not lost, at least at the point of the interrupt, the state of the CPO <b>108</b>, including the SR register, is saved. Flow then proceeds to block <b>516</b>.

0067At block <b>516</b>, the interrupt <b>530</b> is serviced by an appropriate interrupt service routine. One skilled in the art will appreciate that the interrupt service routine may change the state of the SR register. Flow then proceeds to block <b>518</b>.

0068At block <b>518</b>, the state of CPO, including the SR register is restored to the condition it was in before servicing interrupt <b>530</b>. Flow then proceeds to block <b>520</b>.

0069At block <b>520</b>, a return from interrupt is executed that places program execution back in the R-M-W sequence, at block <b>506</b>. Instruction flow then proceeds thru blocks <b>506</b>, <b>508</b>, and <b>510</b> to complete the update of the SR.

0070At least two aspects of the solution presented in <figref idref="DRAWINGS">FIG. 5</figref> should be clear to one skilled in the art. First, the instruction flow of <figref idref="DRAWINGS">FIG. 5</figref> insists that no interrupt service routine be allowed to change the contents of SR. That is, whatever else happens during servicing of an interrupt, at the end of the interrupt, the service routine must restore the contents of the SR that existed when the service routine began. As mentioned above, this imposition is unacceptable in many environments. Second, the instruction flow presented in <figref idref="DRAWINGS">FIG. 5</figref> insists that all interrupt service routines be strictly nested. That is, whenever a departure in normal program flow occurs, as a result of an interrupt, the interrupt service routine is required, upon completion, to return to the point of departure. This requirement is common in some programming environments, but in many real-time environments, such as network routing, strict nesting of interrupt service routines is not desired. Moreover, in some environments, substantial program code has already been developed that does not enforce strict nesting of interrupts, and rewriting of the code to overcome the R-M-W problems described above would be too time consuming, as well as too costly.

0071The problem described above with reference to <figref idref="DRAWINGS">FIGS. 3-5</figref> is just one of many problems that occur within the processing environment <b>100</b> when the contents of control registers cannot be modified atomically. For these reasons, the instruction encoding methodology of the present invention is desired, and will now be described with reference to <figref idref="DRAWINGS">FIGS. 6-9</figref>.

0072Referring first to <figref idref="DRAWINGS">FIG. 6</figref>, a table <b>600</b> is provided that illustrates two new instructions that are being added to the MIPS32 and MIPS64 architecture. The instructions include: DI, and EI. The DI instruction disables interrupts by atomically clearing an IE bit within the SR register of the Coprocessor <b>0</b>. The EI instruction enables interrupts by atomically setting the IE bit within the SR register of the Coprocessor <b>0</b>.

0073<figref idref="DRAWINGS">FIG. 7</figref> provides a block diagram <b>700</b> of the 32-bit COP<b>0</b> opcode for the instruction DI (Disable Interrupt). The purpose of the DI instruction is to atomically clear the IE bit within the status register of Coprocessor <b>0</b>, and if requested, to move the current value of the status register into the general purpose register rt. The format of the instruction is: <br />DI<br />DI rt<br /> and is described as follows: <br />rt←Status; Status_IE←0

0074When the DI instruction is executed, the current value of the status register is sign extended and loaded into general purpose register rt. Also, the Interrupt Enable (IE) bit in the status register is cleared. If access to the Coprocessor <b>0</b> is not enabled at the time DI begins execution, a Coprocessor Unusable Exception is signaled.

0075The effect of executing the DI instruction is similar to that accomplished by a sequence of reading the status register into a GPR (using MFC<b>0</b>—an instruction within the MIPS architecture), clearing the IE bit, and writing the result back to the status register (using MTC<b>0</b>—another instruction within the MIPS architecture). However, unlike the multiple instruction sequence, the DI instruction is atomic, and thus cannot be aborted in the middle by an interrupt or exception.

0076One skilled in the art should appreciate that the DI instruction is merely one implementation of any number of instructions that could be used to atomically set or clear specified bits within specified privileged architecture registers. For such other instructions, the sc field in bit position <b>5</b> is a variable, capable of containing a value of “0” to indicate that a bit field is to be cleared (as in the case of the DI instruction), or a value of “1” to indicate that a bit field is to be set (as in the case of the EI instruction shown below). The COP<b>0</b> opcode indicates that the instruction is designated for Coprocessor <b>0</b>. If a bit is to be set or cleared within an alternate Coprocessor, a different opcode would be used. The UCO function indicates that the Coprocessor is to atomically set or clear a value in any bit position (as specified by the pos field—bit positions <b>6</b>-<b>10</b>) within a 32-bit Coprocessor <b>0</b> register specified by the rd and sel fields. For purposes of this discussion, the terms fields and operands are used interchangeably to refer to areas within an instruction that specifies locations to be modified. For the DI instruction, a pos value of 000 00 indicates bit position <b>0</b>, of the SR register which is designated as rd=0110 0, and sel=000. Thus, when the decode logic <b>105</b> receives the DI instruction, it must decode the rd, pos and sel fields to determine which field, within which register, within the Coprocessor <b>0</b> is to be set or cleared, as designated by the sc field. If it is desired to set or clear other bits within the same or other privileged architecture registers, an instruction according to the present invention would be encoded with rd and sel bits to specify the register of interest, and the pos field would be encoded to specify the particular bit of interest. Of course, the sc field would be encoded with either a “0” or a “1” to clear or set the specified bit, respectively.

0077The below operation specification is for the DI instruction:

0078<tables id="TABLE-US-00004" num="00004"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="42pt" align="left" /><colspec colname="1" colwidth="175pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>if IsCoprocessorEnabled(0) then</entry></row><row><entry /><entry> data←Status</entry></row><row><entry /><entry> GPR[rt]←sign_extend(data)</entry></row><row><entry /><entry> Status_IE←0</entry></row><row><entry /><entry>else</entry></row><row><entry /><entry> SignalException(CoprocessorUnusable, 0)</entry></row><row><entry /><entry>endif</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0079Referring now to <figref idref="DRAWINGS">FIG. 8</figref>, a block diagram <b>800</b> is shown specifying the 32-bit COP<b>0</b> opcode for the instruction EI (Enable Interrupt). The purpose of the EI instruction is to atomically set the IE bit within the status register of Coprocessor <b>0</b>, and if requested, to move the value of the status register into the general purpose register rt. The format of the instruction is: <br />EI<br />EI rt<br /> and is described as follows: <br />rt←Status; Status_IE←1

0080When the EI instruction is executed, the current value of the status register is sign extended and loaded into general register rt. Also, the Interrupt Enable (IE) bit in the status register is set. If access to the Coprocessor <b>0</b> is not enabled at the time EI begins execution, a Coprocessor Unusable Exception is signaled.

0081The effect of executing the EI instruction is similar to that accomplished by the sequence of reading the status register into a GPR (using MFC<b>0</b>), setting the IE bit, and writing the result back to Status (using MTC<b>0</b>). However, unlike the multiple instruction sequence, the EI instruction is atomic, and thus cannot be aborted in the middle by an interrupt or exception.

0082The below operation specification is for the EI instruction:

0083<tables id="TABLE-US-00005" num="00005"><table frame="none" colsep="0" rowsep="0"><tgroup align="left" colsep="0" rowsep="0" cols="2"><colspec colname="offset" colwidth="42pt" align="left" /><colspec colname="1" colwidth="175pt" align="left" /><thead><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></thead><tbody valign="top"><row><entry /><entry>if IsCoprocessorEnabled(0) then</entry></row><row><entry /><entry> data←Status</entry></row><row><entry /><entry> GPR[rt]←sign_extend(data)</entry></row><row><entry /><entry> Status_IE←1</entry></row><row><entry /><entry>else</entry></row><row><entry /><entry> SignalException(CoprocessorUnusable, 0)</entry></row><row><entry /><entry>endif</entry></row><row><entry /><entry namest="offset" nameend="1" align="center" rowsep="1" /></row></tbody></tgroup></table></tables>

0084The above discussion of <figref idref="DRAWINGS">FIGS. 7-8</figref>, describes the operation of each of two special instances of instruction encoding to effect atomic update of privileged architecture registers according to the present invention. That is, the two instructions described are used to atomically clear and set the IE bit within the status register. However, one skilled in the art should appreciate that these two instructions are merely a subset of possible instructions that can be encoded to atomically set or clear any number of bits within any number of architecturally privileged registers.

0085To better comprehend the application of these instructions, within the context of an interrupt, reference is now directed to <figref idref="DRAWINGS">FIG. 9</figref>. <figref idref="DRAWINGS">FIG. 9</figref> provides a flow chart <b>900</b> that illustrates the benefit of the atomic update instructions to modify the state of the SR register, particularly when disabling interrupts by clearing the IE bit. During execution of a user program <b>901</b>, an interrupt <b>903</b> occurs. Instruction flow jumps to an exception handler responsible for handling the interrupt <b>903</b>. Instruction flow proceeds similarly to that described above with reference to <figref idref="DRAWINGS">FIG. 3</figref>. However, at block <b>912</b>, the DI atomic update instruction as described above with reference to <figref idref="DRAWINGS">FIGS. 6-8</figref> is used to update the contents of SR, without requiring the R-M-W sequence described above, thereby atomically disabling interrupts. Thus, when the interrupt <b>911</b> occurs during execution of block <b>912</b>, it is not serviced because interrupts will have already been disabled by the atomic instruction. Moreover, if requested, the previous contents of the SR register will have been transferred into the rt register of the GPR. This allows the previous value of the SR register to be examined by the exception handler, or the previous value of the SR register to later be restored, if necessary.

0086More generally, depending on whether an exception handler wishes to set or clear bits in the SR, the exception handler utilizes one of the instructions shown in <figref idref="DRAWINGS">FIG. 6</figref>. If the programmer of the exception handler wishes to enable interrupts, s/he will use the EI instruction. If the programmer wishes to disable interrupts, s/he will use the DI instruction. As mentioned above, the IE bit within the SR will be set or cleared based on the encoding of the sc field within the instruction.

0087One skilled in the art will appreciate that since selected bit fields in the SR register, or any other of the control registers <b>110</b>, are set atomically (i.e., within a single cycle), there is no requirement that interrupt service routines be strictly nested. Nor is there any requirement that interrupts be disabled during modification of any of the control registers, such as when restoring the state of the CPU <b>102</b>. Thus, utilization of the present invention, to encode particular instructions for setting and clearing the IE bit within the SR register imposes none of the previous limitations relating to interrupt handling (e.g., disabling of interrupts, strict nesting of interrupt service routines, etc.), while enhancing a kernel programs ability to modify selected control registers <b>110</b> without a R-M-W sequence. Furthermore, when modification of a control register <b>110</b> is desired, it may be accomplished more efficiently since such modification requires only a single processing cycle.

0088Although the present invention and its objects, features and advantages have been described in detail, other embodiments are encompassed by the invention. In addition to implementations of the invention using hardware, the invention can be implemented in computer readable code (e.g., computer readable program code, data, etc.) embodied in a computer usable (e.g., readable) medium. The computer code causes the enablement of the functions or fabrication or both of the invention disclosed herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++, JAVA, and the like); GDSII databases; hardware description languages (HDL) including Verilog HDL, VHDL, Altera HDL (AHDL), and so on; or other programming and/or circuit (i.e., schematic) capture tools available in the art. The computer code can be disposed in any known computer usable (e.g., readable) medium including semiconductor memory, magnetic disk, optical disk (e.g., CD-ROM, DVD-ROM, and the like), and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical or analog-based medium). As such, the computer code can be transmitted over communication networks, including Internets and intranets. It is understood that the invention can be embodied in computer code (e.g., as part of an IP (intellectual property) core, such as a microprocessor core, or as a system-level design, such as a System on Chip (SOC)) and transformed to hardware as part of the production of integrated circuits. Also, the invention may be embodied as a combination of hardware and computer code.

0089Also, although the Coprocessor interface has been described with particular reference to the MIPS32 and MIPS64 Instruction Set Architecture, one skilled in the art will appreciate that the applicability of the atomic update of privileged resources is not limited to such architecture. The embodiment described above, with respect to the DI and EI instructions are merely illustrative of the novel idea of encoding within an instruction, which privileged architecture registers are to be affected, and which bit or bits within a privileged architecture register is to be set or cleared. Another instruction, or pair of instructions, might be encoded to set or clear one or more of the interrupt mask bits IMO-<b>7</b> in bit positions <b>8</b>-<b>15</b> within the SR register. Such instructions would be encoded by specifying either an alternate bit location (within the pos field), or possibly multiple alternate bit locations (within one or more pos fields). The particular fields described with reference to <figref idref="DRAWINGS">FIGS. 7-8</figref>, that designate which privileged architecture register is to be affected, and which bit within the designated register is to be affected, should not be restrictive. That is, larger or smaller fields may be used within a particular instruction architecture to designate more or less privileged architecture registers, or more or less bits within a designated register, without departing from the scope of the present invention. In addition, multiple fields might be used to specify more than one bit to be atomically set or cleared within a designated privileged architecture register.

0090Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.