Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer

0001This application is a divisional of application Ser. No. 11/409,356, filed on Apr. 20, 2006, now abandoned, the entire disclosure of which is hereby incorporated by reference.

FIELD OF THE INVENTION

0002This invention relates to semiconductor fabrication processing and, more particularly, to fabrication methods for forming dual depth trench isolation in semiconductor devices, such as semiconductor flash memory devices.

BACKGROUND OF THE INVENTION

0003Semiconductor devices, such as memory devices, use field effect transistors (FETs) to create the integrated circuits required during the fabrication of complimentary metal oxide semiconductor (CMOS) devices on a semiconductor wafer or other substrate. The fabrication of CMOS devices require advanced isolation techniques to create isolation between neighboring FETs.

0004One conventional isolation technique known as shallow trench isolation (STI) is used where a trench is etched into a silicon substrate and the trench is filled with an oxide insulator material and planarized. The STI then functions as isolation between subsequently formed FETs and provides many desirable circuit device properties.

0005However, the current STI techniques also possess some disadvantages. For example, <figref idref="DRAWINGS">FIG. 1</figref> depicts a current STI dry etch process used to fabricate a flash device. <figref idref="DRAWINGS">FIG. 1</figref> shows array section <b>10</b> and periphery section <b>11</b> on substrate <b>12</b>. In array section <b>10</b>, trenches <b>13</b> have been etched into substrate <b>12</b> and in periphery section <b>11</b>, trenches <b>14</b> have been etched into substrate <b>12</b>. At this point, the current technique is to form a mask over array section <b>10</b> and a subsequent etch step is performed on periphery section <b>11</b> to increase the depth of trenches <b>14</b>. In this example, the resulting depth Δ between the depth of array trenches <b>12</b> and periphery trenches <b>14</b> is only approximately 380 Å and as indicated, to create the depth Δ between trenches <b>12</b> and <b>14</b> an additional mask step and etch step are required that increase production cost of the device and possibly limit the electrical properties of the device.

0006Accordingly, STI formation techniques are needed that will improve the electrical property of CMOS devices and also reduce production costs.

BRIEF DESCRIPTION OF THE DRAWINGS

0007<figref idref="DRAWINGS">FIG. 1</figref> is a cross-sectional view depicting a semiconductor substrate with trenches formed therein using a convention STI formation technique.

0008<figref idref="DRAWINGS">FIG. 2</figref> depicts a first exemplary implementation of the present invention showing a cross-sectional view of a semiconductor substrate having an array section and a periphery section with trenches formed therein where the side wall slope of the array trench is set such that a desired trench depth in the array section and a desired trench depth the periphery section are obtained.

0009<figref idref="DRAWINGS">FIG. 3</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 2</figref> depicting the resulting trenches after a dry etch step of the present invention is performed to create the desired trench depths in the array section and the periphery section.

0010<figref idref="DRAWINGS">FIG. 4</figref> depicts a second exemplary implementation of the present invention showing a cross-sectional view of a semiconductor substrate having an array section and a periphery section with trenches formed therein after a first dry etch step is performed that stops at a polysilicon layer in the array section, but stops at a layer used as an etch stop layer in the periphery section.

0011<figref idref="DRAWINGS">FIG. 5</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 4</figref> taken after a second dry etch is performed to selectively etch oxide in the periphery section and, in turn, deposit a polymer on the silicon surfaces of the trenches in both the array and periphery sections.

0012<figref idref="DRAWINGS">FIG. 6</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 5</figref> taken after a conventional trench dry etch is performed to remove polymer and achieve a desired trench depth in the array section and a desired trench depth the periphery section.

0013<figref idref="DRAWINGS">FIG. 7</figref> is a cross-sectional view of <figref idref="DRAWINGS">FIG. 6</figref> depicting the resulting trenches after a conventional trench dry etch step is performed to create the desired trench depths in the array section and the periphery section.

0014<figref idref="DRAWINGS">FIG. 8</figref> depicts a third exemplary implementation of the present invention showing a cross-sectional view of a semiconductor substrate having an array section and a periphery section with trenches formed therein at desired depths by a first dry etch step.

0015<figref idref="DRAWINGS">FIG. 9</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 8</figref> taken after a second dry etch is performed to increase the trench depth in both the array section and in the periphery section and, in turn, deposit a polymer on the silicon surfaces of the trenches in both the array and periphery sections.

0016<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 9</figref> showing a kink induced by the second dry etch step of <figref idref="DRAWINGS">FIG. 9</figref>.

0017<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view of <figref idref="DRAWINGS">FIG. 10</figref> depicting the resulting trenches after a specific break-through etch step is performed to remove any polymer deposited in the bottom of the trenches and to remove an induced kink shown in <figref idref="DRAWINGS">FIG. 10</figref>.

0018<figref idref="DRAWINGS">FIG. 12</figref> is a simplified block diagram of a semiconductor system comprising a processor and a memory device to which the present invention may be applied.

DETAILED DESCRIPTION OF THE INVENTION

0019In the following description, the terms “wafer” and “substrate” are to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but may be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others.

0020Exemplary implementations of the present invention directed to processes for forming trench isolation between active devices in a semiconductor assembly, such as a flash memory device, are depicted in <figref idref="DRAWINGS">FIG. 2-11</figref> and a general application of each exemplary implementation as depicted in <figref idref="DRAWINGS">FIG. 12</figref>.

0021A first exemplary implementation of the present invention is depicted in <figref idref="DRAWINGS">FIGS. 2 and 3</figref>. Referring now to the cross-sectional view of <figref idref="DRAWINGS">FIG. 2</figref>, a semiconductor substrate <b>20</b>, such as a silicon substrate, is prepared for semiconductor device fabrication. Semiconductor substrate <b>20</b> is divided into an array section <b>21</b> and a periphery section <b>22</b>. Array trenches <b>23</b> and periphery trenches <b>24</b> are etched into semiconductor substrate <b>20</b> by performing a dry etch process designed such that the side wall slope <b>25</b> at the base of the array trenches <b>23</b> is set such that a desired trench depth in the array section <b>21</b> and a desired trench depth in the periphery section <b>22</b> are obtained. The dry etch process is set so that the array trenches <b>23</b> will close the trench and thus form a desired trench depth in both the array section <b>21</b> and the periphery section <b>22</b> while maintaining the desired critical dimension (CD) of a given fabrication process.

0022<figref idref="DRAWINGS">FIG. 3</figref> depicts the resulting trenches after an initial dry etch, known to one skilled in the art, is used to form the upper portion of the trenches having substantially vertical sidewalls by performing the initial dry etch dry etch process operated at 5-60 mTorr, 200-1000 W top RF power plasma etcher (to create plasma), 100-600 W bottom RF power (to create a bias voltage to direct ions to the substrate), using an etch chemistry of HBr/Cl₂/CH₂F₂, having a flow ratio of approximately 20:2:(0-2), applied in an RF plasma etcher, such as a Transformer Coupled Plasma (TCP) etcher chamber.

0023Next, a dry etch step of the present invention is performed to create the desired trench depth in array section <b>21</b> and periphery section <b>22</b> which also results in a desirable trench Δ depth <b>30</b> (the difference between depths of array trenches <b>23</b> and periphery trenches <b>24</b>). As an example, in the first exemplary implementation of the present invention, the designed dry etch process was operated at 5-90 mTorr, 300-900 W top RF power plasma etcher (to create plasma), 100-500 W bottom RF power (to create a bias voltage to direct ions to the substrate), using an etch chemistry of HBr/Cl₂/CH₂F₂, having a flow ratio of approximately 12:2:(3-5), applied in an RF plasma etcher, such as a Transformer Coupled Plasma (TCP) etcher chamber.

0024In a preferred exemplary implementation of forming the v-shaped trench, the etch process comprises utilizing an RF plasma etcher operated at 30 mTorr +/−10 mTorr, 800 W+/−200 W top RF power, 300 W+/−100 W bottom RF power, using an etch chemistry of HBr/Cl₂/CH₂F₂having a flow of HBr: 120 sccm +/−20 sccm, Cl₂: 25 sccm +/−10 sccm, CH₂F₂: 30 sccm +/−10 sccm. The preferred etch to form the v-shaped trench allows for various combinations of the etching parameters to achieve the desired result of a v-shaped trench, that becomes self-limiting as the base of the trench basically causes this etch to stop at the tip of the v-shaped trench (defined as the vortex of the v-shaped trench).

0025In the above example, a trench Δ depth <b>30</b> of approximately 2120 Å is obtained with an etching time of approximately 35-52 seconds. A main advantage provided by the designed etch is the fact that the trench Δ depth between the periphery and the array is controllable.

0026A major significance of obtaining a substantial trench Δ depth (2120 Å in this example, but again the Δ depth is controllable) will improve the electrical property in a neighboring periphery and array active device, as in the periphery the active device, having a thicker gate oxide (approximately 350 Å, compared to approximately 75 Å gate oxide thickness for the array active device), is activated by a high voltage of approximately 20V and thus requires better isolation, which is provided by the trench depth in the periphery as developed by the present invention.

0027Finally, as further depicted in <figref idref="DRAWINGS">FIG. 3</figref>, array trenches <b>23</b> and periphery trenches <b>24</b> are filled with an isolation material, such as an oxide that is planarized using techniques know to one skilled in the art, to form dual trench isolation comprising array trench isolation <b>31</b> and periphery trench isolation <b>32</b>.

0028<figref idref="DRAWINGS">FIGS. 4-7</figref> depict a second exemplary implementation of the present invention. Referring now to the cross-sectional view of <figref idref="DRAWINGS">FIG. 4</figref>, a semiconductor substrate <b>40</b>, such as a silicon substrate, having an array section <b>41</b> and a periphery section <b>42</b> is depicted. A pad oxide <b>43</b> is formed on each substrate <b>40</b> in array section <b>41</b> and periphery section <b>42</b>. The thickness of pad oxide <b>43</b> differs in the array section and the periphery section, which is a common occurrence resulting from conventional fabrication processes.

0029This exemplary implementation of the present invention takes advantage of the pad oxide thickness difference by first using a dry etch step to form array trenches <b>45</b> and periphery trenches <b>46</b> into polysilicon material <b>44</b>. The etch stops in the array section before clearing the polysilicon material at the bottom of the array trenches <b>45</b>, but clears the polysilicon material at the bottom of the periphery trench <b>46</b> and stops on pad oxide layer <b>43</b> in the periphery section. This etch is a conventional dry etch known to one skilled in the art, such as a general dry etch process operated at 5-50 mTorr, 300-900 W top RF power, 50-500 W bottom RF power, using an etch chemistry of CF₄/He/CH₂F₂with a flow ratio of 2:4:(0-1) that is applied in an RF plasma etcher.

0030Referring now to <figref idref="DRAWINGS">FIG. 5</figref>, a second dry etch is performed to selectively etch oxide <b>43</b> at the bottom of periphery trench <b>46</b> while depositing a polymer <b>50</b> on the bottom polysilicon of array trench <b>45</b>. Due to the generally anisotropic ion bombardment, polymer <b>50</b> is also deposited on the side walls of polysilicon surfaces <b>44</b> and along the side walls of oxide layer <b>43</b> of the trenches in periphery <b>42</b> section. A polymer <b>50</b> is also deposited on the sidewalls and on the bottom of array trenches <b>45</b> (regardless of whether the side walls are polysilicon or some other material) due to the anisotropic nature of the dry etch providing less ion bombardment along the side walls.

0031As an example, in the second exemplary implementation of the present invention the dry etch process was operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of O₂/He/CH₂F₂having a flow ratio of approximately 3:7:60, applied in an RF plasma etcher.

0032A following etch step in the second exemplary implementation could involve a plasma chemistry of high selectivity between silicon to oxide, which would stop on oxide layer <b>43</b> or etch very slowly through the oxide layer <b>43</b> in the array section <b>41</b> while etching into the silicon substrate much faster in trench <b>46</b> in the periphery section <b>42</b>. This selective etch step would clear polymer <b>50</b> deposited earlier at the bottoms of both the array and periphery trenches. For example, in the array section, at array trench <b>45</b>, the etch would clear polymer <b>50</b> from the bottom and then etch into polysilicon, but would stop or etch through the oxide layer <b>43</b> much slower then it etches the silicon substrate in the periphery section at periphery trench <b>46</b> (due to the chemistry etching silicon at a much higher rate than oxide). The side wall polymer <b>50</b> at both array and periphery would be consumed slowly since the dry etch process has a relatively lower etch rate in the lateral direction than in the vertical direction.

0033Referring now to <figref idref="DRAWINGS">FIG. 6</figref>, an effective dry etch process was operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/O₂/He having a flow rate of approximately 20:(0-3):5, applied in an RF plasma etcher. In this example, additional trench Δ depth <b>51</b> between periphery trench <b>46</b> and array trench <b>45</b> is obtained by two ways: the additional thickness of the thicker oxide layer <b>43</b> at periphery section <b>42</b> by selectively clearing the oxide before the etch continues into silicon substrate <b>40</b> at both array section <b>41</b> and periphery section <b>42</b>; and/or by manipulating the selectivity of the dry etch chemistries of subsequent dry etch steps that would allow etching into silicon substrate <b>40</b> in periphery section <b>42</b> but would stop etching at oxide layer <b>43</b> in array section <b>41</b>. Both methods would give controllable depth Δ between periphery trench <b>46</b> and array trench <b>45</b>. In the later scenario, another two steps might be necessary to break through the oxide layer <b>43</b> at array section <b>41</b> and thus etch into the silicon substrate <b>40</b> to a desired depth for array trench <b>45</b> at array section <b>41</b>.

0034<figref idref="DRAWINGS">FIG. 7</figref> depicts the resulting trenches after the three step dry etch process of the second exemplary implementation of present invention is performed to create the desired trench depth in array section <b>41</b> and periphery section <b>42</b> which also results in a desirable trench Δ depth <b>51</b> (again, the difference between depth of array trenches <b>41</b> and periphery trenches <b>42</b>). Finally, as further depicted in <figref idref="DRAWINGS">FIG. 7</figref>, array trenches <b>45</b> and periphery trenches <b>46</b> are filled with an isolation material, such as an oxide that is planarized using techniques know to one skilled in the art, to form dual trench isolation comprising array trench isolation <b>71</b> and periphery trench isolation <b>72</b>.

0035<figref idref="DRAWINGS">FIGS. 8-11</figref> depict a third exemplary implementation of the present invention. Referring now to the cross-sectional view of <figref idref="DRAWINGS">FIG. 8</figref>, a semiconductor substrate <b>80</b>, such as a silicon substrate, having an array section <b>81</b> and a periphery section <b>82</b> is depicted. Array trenches <b>83</b> and periphery trench <b>84</b> are etched into silicon substrate <b>80</b> to a desired depth by a conventional dry etch step know to one skilled in the art.

0036Referring now to <figref idref="DRAWINGS">FIG. 9</figref>, a second dry etch is performed to increase the trench depth in both array section <b>81</b> and in periphery section <b>82</b>, and in turn deposit a polymer <b>90</b> on the silicon surfaces of the trenches in both the array <b>81</b> and periphery <b>82</b> sections. Polymer <b>90</b> coats the sidewalls of array trenches <b>83</b> and the sidewalls of periphery trench <b>83</b>. Polymer <b>90</b> also covers the bottom of array trenches <b>83</b>, but does not coat the bottom of periphery trench <b>84</b>, due to the respective narrow versus wide trench widths of the two sections. The polymer eventually closes off (blocks) the narrower array trenches while the etch continues to increase the depth of the wider periphery trenches.

0037As an example, in the third exemplary implementation of the present invention the designed dry etch process was operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of HBr/Cl₂/CH₂F₂, having a flow ratio of approximately 12:2:(3-5), applied in an RF plasma etcher. In this example, trench Δ depth bias between the array and the periphery becomes controllable without the need of another mask step as the array trenches <b>83</b> will become pinched off with polymer <b>90</b> while the periphery trench <b>84</b> will continue to be etched deeper into silicon substrate <b>80</b>.

0038<figref idref="DRAWINGS">FIG. 10</figref> is a cross-sectional view following <figref idref="DRAWINGS">FIG. 9</figref> showing a kink <b>100</b> that may be induced by the second dry etch step of <figref idref="DRAWINGS">FIG. 9</figref>. Kink <b>100</b> may appear in both the array section <b>81</b> and the periphery section <b>82</b> of <figref idref="DRAWINGS">FIG. 9</figref>. In order to address kink <b>100</b>, a specific break-through etch step is performed to remove any remaining polymer <b>90</b> deposited in the bottom of the trenches and to remove the induced kink <b>100</b>. As an example, the specific break-through etch step was operated at 5-90 mTorr, 300-900 W top RF power, 100-500 W bottom RF power, using an etch chemistry of CF₄/He/NF₃, having a flow ratio of approximately 10:12:(1-2), applied in an RF plasma etcher.

0039<figref idref="DRAWINGS">FIG. 11</figref> is a cross-sectional view depicting the resulting array trenches <b>83</b> and periphery trench <b>84</b> after a specific break-through etch step was performed to remove any polymer remaining in the bottom of the trenches and to remove the induced kink <b>100</b> shown in <figref idref="DRAWINGS">FIG. 10</figref>. After the three step dry etch process of the third exemplary implementation of the present invention is performed to create the desired trench depth in array section <b>81</b> and periphery section <b>82</b>, the process also results in a desirable trench Δ depth <b>110</b> (the difference between depth of array trenches <b>83</b> and periphery trenches <b>84</b>). Finally, as further depicted in <figref idref="DRAWINGS">FIG. 11</figref>, array trenches <b>83</b> and periphery trenches <b>84</b> are filled with an isolation material, such as an oxide that is planarized using techniques know to one skilled in the art, to form dual trench isolation comprising array trench isolation <b>111</b> and periphery trench isolation <b>112</b>.

0040In each exemplary implementation of the present invention, the approximation of the flow ratio of each etching chemistry may vary by 20 to 50%. Finally, in each exemplary implementation of the present invention, the semiconductor device is completed using conventional fabrication processes know to one skilled in the art.

0041<figref idref="DRAWINGS">FIG. 12</figref> is a block diagram of a semiconductor flash memory device <b>122</b>, representing a flash memory device comprising portions fabricated by the exemplary implementations of the present invention, which is coupled to a processor <b>121</b>. The flash memory device <b>122</b> and the processor <b>121</b> may form part of an electronic system <b>120</b>. The flash memory device <b>122</b> includes memory array <b>123</b> of non-volatile floating-gate memory cells arranged in banks of rows and columns. An address buffer circuit <b>124</b> is provided to latch address signals provided on address input connections A₀-A_X<b>125</b>. Address signals are received and decoded by row decoder <b>126</b> and column decoder <b>127</b> to access the memory array <b>123</b>.

0042The flash memory device <b>122</b> reads data in the memory array <b>123</b> by sensing voltage or current changes in the memory array columns using sense/latch circuitry <b>128</b>. Data input and output buffer circuitry <b>129</b> is included for bi-directional data communication over a plurality of data connections <b>130</b> with processor <b>121</b>. Write circuitry <b>131</b> is provided to write data to memory array <b>123</b>. Command control circuitry <b>132</b> decodes signals provided on control connections <b>133</b> from processor <b>121</b>. These signals are used to control the operations of the flash memory device <b>122</b>, including data read, data write and erase operations. The flash memory device illustrated has been simplified to facilitate a basis understanding thereof. A more detailed understanding of the internal circuitry and functions of flash memory devices are known to those skilled in the art.

0043It is to be understood that although the present invention has been described with reference to several preferred embodiments, various modifications, known to those skilled in the art, may be made to the process steps presented herein without departing from the invention as recited in the several claims appended hereto.