Semiconductor device with local interconnects

BACKGROUND OF THE INVENTION

00011. Field of the Invention

0002The invention relates to semiconductor technology and in particular to a semiconductor device with local interconnects having low contact resistance.

00032. Description of the Related Art

0004For the fabrication of semiconductor integrated circuits, the size of semiconductor devices in the integrated circuits, such as transistors, resistors, capacitors or other semiconductor elements well known in the art, has been continuously reduced in order to increase device density. Accordingly, a multi-layered interconnect structure is typically required for electrical connection of the individual semiconductor devices. Along with reduction in the size and dimension of semiconductor devices, more components are being placed on an integrated circuit or die, which increases design complexity of the multi-layered interconnect structure.

0005Typically, the multi-layered interconnect structure comprises plugs and metal layers, which are provided by a conventional dual damascene process. In the dual damascene process, via openings are first anisotropically etched through an inter-metal dielectric (IMD)/interlayer dielectric (ILD) layer by a conventional photolithography and etching process. A second anisotropically etched opening referred to as a trench opening is then formed overlying one or more of the via openings by a second photolithography and etching process. The via openings and the trench opening together makeup the dual damascene structure which is subsequently filled with metal to form plugs and metal layers. As the size and dimension of semiconductor devices are reduced, the size of plugs is also reduced, thus increasing the aspect ratio of the via openings, which decreases fabrication yields. Aspect ratio is defined herein as the height/width ratio of the via opening. As the aspect ratio increases, the contact resistance of the plugs increases. Accordingly, as device density increases, it becomes more difficult to maintain or increase the electrical properties and the reliability of the devices.

0006Therefore, there exists a need for an improved interconnect structure, which is capable of reducing contact resistance as the size of a device is reduced to increase device density.

BRIEF SUMMARY OF INVENTION

0007A detailed description is given in the following embodiments with reference to the accompanying drawings. A semiconductor device with local interconnects is provided. An embodiment of a semiconductor device with local interconnects comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions.

BRIEF DESCRIPTION OF DRAWINGS

0008The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

0009<figref idref="DRAWINGS">FIG. 1</figref> is a plan view of an embodiment of a semiconductor device with local interconnects according to the invention;

0010<figref idref="DRAWINGS">FIG. 2</figref> is a cross section along line <b>2</b>-<b>2</b>′ shown in <figref idref="DRAWINGS">FIG. 1</figref>; and

0011<figref idref="DRAWINGS">FIG. 3</figref> is a plan view of another embodiment of a semiconductor device with local interconnects according to the invention.

DETAILED DESCRIPTION OF INVENTION

0012The following description is of the best-contemplated mode of carrying out the invention. This description is provided for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Embodiments of a semiconductor device with local interconnects is described with reference to the accompanying drawings.

0013<figref idref="DRAWINGS">FIGS. 1 and 2</figref> illustrate an embodiment of a semiconductor device with local interconnects, in which <figref idref="DRAWINGS">FIG. 1</figref> is a plan view and <figref idref="DRAWINGS">FIG. 2</figref> is a cross section along line <b>2</b>-<b>2</b>′ shown in <figref idref="DRAWINGS">FIG. 1</figref>. Referring to <figref idref="DRAWINGS">FIGS. 1 and 2</figref>, the semiconductor device <b>200</b> comprises a substrate <b>100</b>, such as a silicon substrate or other semiconductor substrates. The substrate <b>100</b> may contain a variety of elements (not shown), including transistors, resistors, and other semiconductor elements which are well known in the art. In the embodiment, the substrate has at least two active areas <b>100</b><i>a </i>and <b>100</b><i>b </i>separated from each other and surrounded by an isolation structure <b>110</b>, for example, a shallow trench isolation (STI) structure.

0014A dielectric layer <b>120</b> is formed overlying the substrate <b>100</b>, used as an ILD layer. The dielectric layer <b>120</b> may be silicon dioxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or low dielectric constant (k) material, such as fluorosilicate glass (FSG) or organosilicate glass (OSG). A first gate line structure <b>116</b> is disposed in the dielectric layer <b>120</b> and on the substrate <b>100</b> of the active area <b>100</b><i>a</i>. A second gate line structure <b>118</b> is disposed in the dielectric layer <b>120</b> and on the substrate <b>100</b> of the active area <b>100</b><i>b</i>. In the embodiment, the first gate line structure <b>116</b> and the second gate line structure <b>118</b> are separated from each other and substantially arranged collinear. Each of the first gate line structure <b>116</b> and the second gate line structure <b>118</b> may comprise a gate dielectric layer <b>111</b> on the substrate <b>100</b> of corresponding active areas. A gate electrode <b>113</b>, such as a polysilicon, is disposed on the gate dielectric layer <b>111</b> and may be covered by a cap layer (not shown), such as a silicon nitride layer. Gate spacers <b>115</b> are disposed on sidewalls of the gate electrode <b>113</b>.

0015A first pair of source/drain regions <b>101</b> is formed in the substrate <b>100</b> of the first active area <b>100</b><i>a </i>and located on both sides of the first gate line structure <b>116</b>. A second pair of source/drain regions <b>103</b> is formed in the substrate <b>100</b> of the second active area <b>100</b><i>b </i>and located on both sides of the second gate line structure <b>118</b>. As a result, two transistors are formed on the first and second active areas <b>100</b><i>a </i>and <b>100</b><i>b</i>, respectively. In the embodiment, the first pair of source/drain regions <b>101</b> and the second pair of source/drain regions <b>103</b> may have the same conductivity type, such as N-type or P-type, or have different conductivity types. For example, if the first pair of source/drain regions <b>101</b> and the second pair of source/drain regions <b>103</b> have the same conductivity type, the gate electrodes <b>113</b> of the first gate line structure <b>116</b> and the second gate line structure <b>118</b> would merge with each other to form a common gate line structure, as shown in <figref idref="DRAWINGS">FIG. 3</figref>.

0016A pair of conductive lines <b>112</b> is disposed in the dielectric layer <b>120</b> and on the substrate <b>100</b> on both sides of the first gate line structure <b>116</b> and the second gate line structure <b>118</b>, such that the pair of conductive lines <b>112</b> is at the same level as the gate electrodes <b>113</b> and each conductive line <b>112</b> serves as a local interconnect to electrically connect one of the first pair of source/drain regions <b>101</b> and one of the second pair of source/drain regions <b>103</b> on the same side of the first gate line structure <b>116</b> and the second gate line structure <b>118</b>. In the embodiment, the pair of conductive lines <b>112</b> may comprise tungsten, copper, or aluminum. Moreover, each conductive line <b>112</b> is substantially parallel to the first gate line structure <b>116</b> and the second gate line structure <b>118</b>. That is, the conductive line <b>112</b> and the first gate line structure <b>116</b> and the second gate line structure <b>118</b> are extended along the same direction.

0017A dielectric layer <b>130</b> is formed overlying the dielectric layer <b>120</b> and the pair of conductive lines <b>112</b>, used as an IMD layer. The dielectric layer <b>130</b> may be a single layer or a multi-layered structure. Moreover, the dielectric layer <b>130</b> may comprise the same or similar material as the dielectric layer <b>120</b>. At least one conductive plug <b>132</b>, such as a tungsten or copper plug, is disposed in the dielectric layer <b>130</b> and above one of the pair of conductive lines <b>112</b>, to be connected thereto. A metal layer <b>136</b>, such as a copper layer, is disposed in the dielectric layer <b>130</b> and above the conductive plug <b>132</b>, to be electrically connected to the two transistors via the conductive plug <b>132</b> and the conductive line <b>112</b> thereunder.

0018According to the invention, since the two transistors formed on the first and second active areas <b>100</b><i>a </i>and <b>100</b><i>b </i>are electrically connected to each other by the conductive line <b>112</b>, which provides a larger contact area than that of conventional conductive plugs, the contact resistance of the conductive line <b>112</b> is lower than that of conventional conductive plugs. That is, device density for semiconductor devices can further be reduced due to the lower contact resistance of the conductive line <b>112</b> serving as a local interconnect, when compared to using conventional conductive plugs. Moreover, since the gate electrode lines <b>113</b> for the two transistors are collinear (i.e., the gate electrodes <b>113</b> extend along a single straight line), the process for formation of the source/drain regions <b>101</b> and <b>103</b> is relatively simple. Furthermore, since the collinear gate electrodes <b>113</b> can be formed by patterning a single conductive layer along only one dimension, good critical dimension (CD) control during the lithography process can be obtained. Additionally, since the gate electrodes <b>113</b> and the conductive lines <b>112</b> are parallel, the layout is also relatively simple. Moreover, layouts in accordance with the invention can result in a relatively high density transistor layout.

0019While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.