A/D conversion circuit, electronic apparatus, and A/D conversion method

BACKGROUND

1. Technical Field

The present invention relates to an A/D conversion circuit, an electronic apparatus, and an A/D conversion method.

2. Related Art

From the past, as an A/D conversion circuit for converting analog signals into digital data, there has been known a successive-approximation type A/D conversion circuit. The successive-approximation type A/D conversion circuit is provided with a comparison circuit, a successive-approximation register, and a D/A conversion circuit, and performs A/D conversion on the signal, which is obtained by sampling (performing a sample and hold operation on) an input signal, by the successive approximation action, thereby outputting the digital data. As a related art technology of such a successive approximation type A/D conversion circuit, there is known a technology disclosed in JP-A-8-321779.

In such an A/D conversion circuit, the most part of the conversion accuracy depends on the accuracy of the D/A conversion circuit. Further, when attempting to improve the accuracy of the D/A conversion circuit, the size of the circuit is enlarged due to the area of capacitors (in the case of a charge redistribution type) or the area of resistors (in the case of a ladder resistor type). On the other hand, if devices are added to the D/A conversion circuit in order for preventing the increase in the circuit size, then, there arises the problem that so-called missing code is caused due to an error of differential non-linearity or integral non-linearity.

SUMMARY

According to some aspects of the invention, there can be provided an A/D conversion circuit, an electronic apparatus, and an A/D conversion method capable of improving the A/D conversion characteristic.

An aspect of the invention relates to an A/D conversion circuit including a comparison circuit, a control circuit having a successive approximation register to which register values are set in accordance with a comparison result signal from the comparison circuit, and adapted to output successive approximation data, a first D/A conversion circuit adapted to perform D/A conversion on the successive approximation data from the control circuit to output D/A output signal corresponding to the successive approximation data, and a second D/A conversion circuit adapted to perform D/A conversion on time-varying code data to output a code signal corresponding to the code data, wherein the comparison circuit performs one of a process of comparing an addition signal of a sampled signal of an input signal and the code signal with the D/A output signal, and a process of comparing the sampled signal with an addition signal of the D/A output signal and the code signal, and the control circuit outputs output data obtained based on successive approximation result data of the successive approximation register and the code data as A/D conversion data of the input signal.

According to the aspect of the invention, the successive approximation data from the control circuit having the successive approximation register is input to the first D/A conversion circuit, and the D/A output signal corresponding to the successive approximation data is output. Further, the time-varying code data is input to the second D/A conversion circuit, and the code signal corresponding to the code data is output. Then, a process of comparing an addition signal of a sampled signal of an input signal and the code signal with the D/A output signal, or a process of comparing the sampled signal with an addition signal of the D/A output signal and the code signal is performed. Then, the output data obtained based on the successive approximation result data and the code data is output as the A/D conversion data of the input signal. Further, in a certain aspect of the invention, there are provided a sample-and-hold circuit adapted to sample and hold an input signal to output a sampled signal, a control circuit adapted to output successive approximation data, a first D/A conversion circuit adapted to perform D/A conversion on the successive approximation data to output a first D/A output signal, a second D/A conversion circuit adapted to perform D/A conversion on time-varying code data to output a second D/A output signal, and a comparison circuit adapted to perform a process of comparing the first D/A output signal, and an addition signal of the sampled signal and the second D/A output signal, and to output a comparison result signal, and the control circuit has a successive approximation register to which register values are set in accordance with the comparison result signal, outputs successive approximation result data after all of the register values of the successive approximation register have been determined, and subtracts the code data from the successive approximation result data to output the result as A/D conversion data of the input signal. Further, in a certain aspect of the invention, there are provided a sample-and-hold circuit adapted to sample and hold an input signal to output a sampled signal, a control circuit adapted to output successive approximation data, a first D/A conversion circuit adapted to perform D/A conversion on the successive approximation data to output a first D/A output signal, a second D/A conversion circuit adapted to perform D/A conversion on time-varying code data to output a second D/A output signal, and a comparison circuit adapted to perform a process of comparing the sampled signal, and an addition signal of the first D/A output signal and the second D/A output signal, and to output a comparison result signal, and the control circuit has a successive approximation register to which register values are set in accordance with the comparison result signal, outputs successive approximation result data after all of the register values of the successive approximation register have been determined, and adds the code data to the successive approximation result data to output the result as A/D conversion data of the input signal. According to the configurations described above, the code shift becomes to be performed in accordance with the time-varying code data, thus the characteristic of the A/D conversion can be improved.

Further, according to another aspect of the invention, it is also possible that denoting a minimum resolution of the first D/A conversion circuit as RS<b>1</b>, and a minimum resolution of the second D/A conversion circuit as RS<b>2</b>, RS<b>2</b>≧RS<b>1</b> is satisfied.

According to the configuration described above, it becomes possible to perform the addition process of the code signal with an amplitude being equal to or larger than the minimum resolution RS<b>1</b> of the first D/A conversion circuit to realize the code shift.

Further, according to the aspect of the invention, it is also possible that a code data generation section adapted to generate the code data and then output the code data to the second D/A conversion circuit is provided, and the code data generation section outputs the data taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a predetermined data range as the code data.

According to the configuration described above, the addition process of the code signal corresponding to the code data taking the value varying every A/D conversion timing or every plurality of A/D conversion timings is performed, and thus the code shift is realized. Thus, it becomes possible to temporally diffuse, for example, deterioration of the DNL characteristic to the codes around to thereby improve the characteristic of the A/D conversion.

Further, according to the aspect of the invention, it is also possible that the first D/A conversion circuit and the second D/A conversion circuit are each a charge redistribution D/A conversion circuit.

It should be noted that it is also possible to realize a part or the whole of the first and second D/A conversion circuits with a ladder circuit.

Further, according to the aspect of the invention, it is also possible that the first D/A conversion circuit includes a first capacitor array section having a plurality of capacitors having one ends connected to a comparison node of the comparison circuit, a first switch array section having a plurality of switch elements, which is connected to the other ends of the respective capacitors of the first capacitor array section, and on which switching control is performed based on higher-bit data of the successive approximation data, a first series capacitor disposed between the comparison node and a first node, a second capacitor array section having a plurality of capacitors having one ends connected to the first node, and a second switch array section having a plurality of switch elements, which is connected to the other ends of the respective capacitors of the second capacitor array section, and on which switching control is performed based on lower-bit data of the successive approximation data, and the second D/A conversion circuit includes a second series capacitor disposed between the comparison node and a second node, a third capacitor array section having a plurality of capacitors having one ends connected to the second node, and a third switch array section having a plurality of switch elements, which is connected to the other ends of the respective capacitors of the third capacitor array section, and on which switching control is performed based on the code data.

By using the first D/A conversion circuit having the configuration described above, it becomes possible to achieve higher bit A/D conversion while suppressing increase in the circuit area to the minimum. Further, by using the second D/A conversion circuit having the configuration described above, it becomes possible to realize the process of comparing the sampled signal with the addition signal of the D/A output signal and the code signal.

Further, according to the aspect of the invention, it is also possible that a code data generation section adapted to generate the code data and then output the code data to the second D/A conversion circuit is provided, and the code data generation section outputs the data taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a data range of the lower-bit data of the successive approximation data as the code data.

According to the configuration described above, the code shift can be realized by varying the code signal within the range being equal to or larger than the voltage corresponding to 1 LSB of the successive approximation data.

Further, according to the aspect of the invention, it is also possible that the control circuit performs the process of subtracting the code data from the successive approximation result data of the successive approximation register in the case in which the comparison process between the addition signal of the sampled signal and the code signal, and the D/A output signal is performed.

According to this configuration, by performing the subtraction process of the code data in the case in which the comparison process between the addition signal of the sampled signal and the code signal, and the D/A output signal, it become possible to output appropriate A/D conversion data.

Further, according to the aspect of the invention, it is also possible that the control circuit performs the process of adding the code data to the successive approximation result data of the successive approximation register in the case in which the comparison process between the sampled signal, and the addition signal of the D/A output signal and the code signal is performed.

According to this configuration, by performing the adding process of the code data in the case in which the comparison process between the sampled signal, and the addition signal of the D/A output signal and the code signal, it becomes possible to output the appropriate A/D conversion data.

Further, another aspect of the invention relates to an electronic apparatus including any one of the A/D conversion circuits described above.

Further, still another aspect of the invention relates to an A/D conversion method in a successive approximation A/D conversion circuit having a comparison circuit, a successive approximation register, and a D/A conversion circuit, the method including the steps of generating a code signal corresponding to time-varying code data, performing one of a process of comparing an addition signal of a sampled signal of an input signal and the code signal with a D/A output signal from the D/A conversion circuit, and a process of comparing the sampled signal with an addition signal of the D/A output signal and the code signal, and outputting output data obtained based on successive approximation result data from the successive approximation register and the code data as A/D conversion data of the input signal.

According to this aspect of the invention, the code signal corresponding to the code data is generated, and the process of comparing the addition signal of the sampled signal of the input signal and the code signal with the D/A output signal, or the process of comparing the sampled signal with the addition signal of the D/A output signal and the code signal is performed. Then, the output data obtained based on the successive approximation result data and the code data is output as the A/D conversion data of the input signal. According to the configurations described above, the code shift becomes to be performed in accordance with the time-varying code data, thus the characteristic of the A/D conversion can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.

<figref idrefs="DRAWINGS">FIG. 1</figref> is a diagram showing a configuration example of an A/D conversion circuit according to an embodiment of the invention.

<figref idrefs="DRAWINGS">FIG. 2</figref> is a diagram showing a first comparative example of the A/D conversion circuit.

<figref idrefs="DRAWINGS">FIGS. 3A through 3C</figref> are diagrams for explaining a code shift method in the present embodiment.

<figref idrefs="DRAWINGS">FIG. 4</figref> is a diagram showing a detailed configuration example of the A/D conversion circuit according to the present embodiment.

<figref idrefs="DRAWINGS">FIG. 5</figref> is a diagram for explaining an operation of the A/D conversion circuit.

<figref idrefs="DRAWINGS">FIG. 6</figref> is a diagram showing a second comparative example of the A/D conversion circuit.

<figref idrefs="DRAWINGS">FIG. 7</figref> is a diagram showing a third comparative example of the A/D conversion circuit.

<figref idrefs="DRAWINGS">FIG. 8</figref> is an explanatory diagram regarding a negative influence exerted by a parasitic capacitance.

<figref idrefs="DRAWINGS">FIGS. 9A and 9B</figref> are explanatory diagrams of DNL and INL, respectively.

<figref idrefs="DRAWINGS">FIGS. 10A and 10B</figref> are diagrams showing a simulation result of DNL.

<figref idrefs="DRAWINGS">FIG. 11</figref> is a diagram showing a configuration example of a full-differential A/D conversion circuit according to the present embodiment.

<figref idrefs="DRAWINGS">FIG. 12</figref> is a configuration example of an electronic apparatus of the present embodiment.

DESCRIPTION OF AN EXEMPLARY EMBODIMENT

Hereinafter, a preferred embodiment of the invention will be described in detail. It should be noted that the present embodiment explained below does not unreasonably limit the content of the invention as set forth in the appended claims, and all of the constituents set forth in the present embodiments are not necessarily essential as means for solving the problems of the invention.

1. Configuration

<figref idrefs="DRAWINGS">FIG. 1</figref> shows a configuration example of an A/D conversion circuit according to the present embodiment. The A/D conversion circuit includes a comparison circuit <b>10</b>, a control circuit <b>20</b>, a first D/A conversion circuit DAC<b>1</b>, and a second D/A conversion circuit DAC<b>2</b>. Further, the A/D conversion circuit can include a sample-and-hold (S/H) circuit <b>30</b> and a code data generation section <b>90</b>.

It should be noted that the configuration of the A/D conversion circuit according to the present embodiment is not limited to the configuration shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, but various practical modifications such as elimination of some of the constituents or addition of other constituents are possible. For example, it is also possible to eliminate the constituent corresponding to the S/H circuit <b>30</b>, and to provide the D/A conversion circuit with a sample and hold function for the input signal VIN. Further, it is also possible to eliminate the constituent corresponding to the code data generation section <b>90</b>, and to input the code data CDA directly from the outside.

The comparison circuit <b>10</b> is realized with a comparator (e.g., a comparator with a hysteresis function), and performs a comparing process between a signal SADD and a signal DQ.

The control circuit <b>20</b> has a successive approximation register (SAR) and outputs successive approximation data RDA (D/A input data). The successive approximation register SAR is a register having a register value set in accordance with a comparison result signal CPQ from the comparison circuit <b>10</b>. For example, when the comparison circuit <b>10</b> performs a successive approximation process from the MSB to the LSB, the result (“1” or “0”) of the process at each bit is stored as the register value of the successive approximation register SAR.

It should be noted that the control circuit <b>20</b> can also perform control process of each circuit block of the A/D conversion circuit. For example, the control circuit <b>20</b> performs on/off control of the switch elements (a switch array) included in the D/A conversion circuits DAC<b>1</b>, DAC<b>2</b>.

The D/A conversion circuit DAC<b>1</b> performs the D/A conversion of the successive approximation data RDA from the control circuit <b>20</b>. Then, the D/A conversion circuit DAC<b>1</b> outputs the D/A output signal DQ (an analog signal obtained by performing the D/A conversion on the RDA, and also referred to as a first D/A output signal) corresponding to the successive approximation data RDA. The D/A conversion circuit DAC<b>1</b> can be of a charge redistribution type using a capacitor array, or partially or wholly of a ladder resistor type.

The D/A conversion circuit DAC<b>2</b> performs D/A conversion on the code data CDA. Then, the D/A conversion circuit DAC<b>2</b> outputs a code signal SCD (a signal obtained by performing D/A conversion on the code data CDA, also referred to as a second D/A output signal) corresponding to the code data CDA. Here, the code data CDA is time-varying data (digital data varying every predetermined timing). Specifically, the code data CDA is data taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a predetermined data range.

It should be noted that the data range in this case is a range having first digital data as the upper limit value and second digital data as the lower limit value. The A/D conversion timing is, for example, a timing corresponding to each of A/D conversion periods for converting an analog signal into digital data.

The S/H (sample and hold) circuit <b>30</b> is a circuit for sampling and holding the input signal VIN to be an object of the A/D conversion. It should be noted that in the case of the charge redistribution type, the function of the S/H circuit <b>30</b> can be realized by the D/A conversion circuit.

The code data generation section <b>90</b> generates the code data CDA, and then outputs the code data CDA to the D/A conversion circuit DAC<b>2</b>. For example, the code data generation section <b>90</b> outputs the code data CDA taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a predetermined data range. Specifically, the code data generation section <b>90</b> outputs the code data CDA taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a data range of lower bit data of the successive approximation data.

Then, in the present embodiment, the comparison circuit <b>10</b> performs a process of comparing an addition signal SADD, which is obtained by adding a sampled signal SIN (a signal obtained by sampling and holding the input signal VIN) of the input signal VIN and the code signal SCD to each other, and the D/A output signal DQ with each other. Specifically, the comparison circuit <b>10</b> compares the addition signal SADD (an addition voltage) input to a first input terminal and the D/A output signal DQ (a D/A conversion voltage) input to a second input terminal with each other. It should be noted that in, for example, the case of the charge redistribution type, the comparison circuit <b>10</b> performs a process of comparing the sampled signal SIN and an addition signal obtained by adding the D/A output signal DQ and the code signal SCD with each other. For example, the comparison circuit <b>10</b> compares the sampled voltage of the sampled signal SIN and the addition voltage, which is obtained by adding the signals DQ and SCD, with each other.

Then, the control circuit <b>20</b> outputs output data DOUT obtained based on successive approximation result data QDA (the determinate data) from the successive approximation register SAR and the code data CDA, as A/D conversion data of the input signal VIN. For example, in the case in which the comparison process between the addition signal SADD of the sampled signal SIN and the code signal SCD, and the D/A output signal DQ is performed, the control circuit <b>20</b> performs a process of subtracting the code data CDA from the successive approximation result data QDA of the successive approximation register SAR. On the other hand, in the case in which a comparison process between the sampled signal SIN and the addition signal obtained by adding the D/A output signal DQ and the code signal SCD is performed as in the case of the charge redistribution type described later, the control circuit <b>20</b> performs a process of adding the code data CDA to the successive approximation result data QDA.

Then, the operation of the present embodiment will be explained taking the case in which the number of bits of the A/D conversion is eight as an example.

Firstly, the S/H circuit <b>30</b> performs the sample and hold operation on the input signal VIN to output the sampled signal SIN. Further, the code data generation section <b>90</b> outputs the code data CDA with an arbitrary value within a predetermined data range (e.g., 0000 through 1111), and the D/A conversion circuit DAC<b>2</b> outputs the code signal SCD corresponding to the code data CDA.

The control circuit <b>20</b> outputs the successive approximation data RDA of, for example, 10000000 with the MSB thereof set to be “1,” and the D/A conversion circuit DAC<b>1</b> outputs the D/A output signal DQ corresponding to the successive approximation data RDA.

Then, the comparison circuit <b>10</b> compares the voltage of the signal SADD obtained by adding the code signal SCD to the sampled signal SIN and the voltage of the D/A output signal DQ with each other, and then outputs the comparison result signal CPQ taking a value of “1” or “0.” For example, the comparison circuit <b>10</b> outputs “1” if the voltage of the signal DQ is higher than the voltage of the signal SADD, or “0” if it is lower. Thus, “1” or “0” is set to the MSB of the register value of the successive approximation register SAR.

Subsequently, the control circuit <b>20</b> outputs the successive approximation data RDA of 11000000 or 01000000 with the second MSB set to be “1.” For example, the control circuit <b>20</b> outputs the successive approximation data RDA of 11000000 if the comparison result regarding the MSB is “1,” or 01000000 if it is “0.” Then, the D/A conversion circuit DAC<b>1</b> outputs the D/A output signal DQ corresponding to the successive approximation data RDA.

Then, the comparison circuit <b>10</b> compares the voltage of the signal SADD obtained by adding the code signal SCD to the sampled signal SIN and the voltage of the D/A output signal DQ with each other, and then outputs the comparison result signal CPQ taking a value of “1” or “0.” Thus, “1” or “0” is set to the second MSB of the register value of the successive approximation register SAR.

By executing the successive approximation operation described above on the bits from the MSB to the LSB, the determinate successive approximation result data QDA is obtained. In other words, by performing the successive approximation operation so that the voltage of the input signal VIN and the voltage of the D/A output signal DQ become equal to each other, the determinate successive approximation result data QDA is obtained. Then, the data obtained by subtracting the code data CDA from the successive approximation result data QDA thus obtained is output as the data DOUT obtained by performing the A/D conversion on the input signal VIN.

<figref idrefs="DRAWINGS">FIG. 2</figref> shows an A/D conversion circuit of a first comparative example of the present embodiment. In the first comparative example, the code data generation section <b>90</b> and the second D/A conversion circuit DAC<b>2</b> are not provided. Further, in the first comparative example, as shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>, a missing code occurs in a specific code due to, for example, an error of DNL. For example, if the DNL exceeds 1 LSB, there is caused the phenomenon of the missing code in which a code with no output code is generated.

In contrast, according to the present embodiment, even if such a missing code occurs, by adding the signal SCD of the time-varying code data CDA to the sampled signal SIN, code shift shown in <figref idrefs="DRAWINGS">FIG. 3B</figref> is performed. It should be noted that the solid line shown in <figref idrefs="DRAWINGS">FIG. 3B</figref> represents the characteristic thereof after the code shift, and the broken line represents the characteristic thereof before the code shift.

In other words, in the present embodiment, by setting the value of the code data CDA so as to vary every A/D conversion timing or every plurality of A/D conversion timings, the position of the code at which the missing code occurs varies every A/D conversion timing or every plurality of A/D conversion timings as shown in <figref idrefs="DRAWINGS">FIG. 3B</figref>. For example, even if the missing code occurs in the code of 00010000, the position thereof is shifted to the positions of 00010001, 00010010, or 00001111. As a result, from a viewpoint of a long period of time, the DNL and the INL are improved as shown in <figref idrefs="DRAWINGS">FIG. 3C</figref>, and thus there can be obtained a preferable characteristic preventing the phenomenon of the missing code from occurring. In other words, deterioration (the missing code) in the DNL characteristic having occurred in a specific code is diffused to the codes around by the time-varying code data CDA, thereby achieving the improvement of the characteristic.

As described above, according to the present embodiment, by the simple process of generating and then adding the code data CDA, it is achieved to prevent the missing code from occurring, and to improve the characteristics in the DNL and the INL of the A/D conversion circuit.

2. Detailed Configuration Example

<figref idrefs="DRAWINGS">FIG. 4</figref> shows a detailed configuration example of the A/D conversion circuit according to the present embodiment. <figref idrefs="DRAWINGS">FIG. 4</figref> shows a detailed configuration example of the D/A conversion circuits DAC<b>1</b>, DAC<b>2</b>, and the comparison circuit <b>10</b> shown in <figref idrefs="DRAWINGS">FIG. 1</figref>, the D/A conversion circuits DAC<b>1</b>, DAC<b>2</b> are each formed of a charge redistribution D/A conversion circuit.

Specifically, the first D/A conversion circuit DAC<b>1</b> includes a first capacitor array section <b>41</b> and a first switch array section <b>51</b>. Further, the first D/A conversion circuit DAC<b>1</b> includes a first series capacitor CS<b>1</b> disposed between a comparison node NC and a first node N<b>1</b>. Further, the first D/A conversion circuit DAC<b>1</b> includes a second capacitor array section <b>42</b> and a second switch array section <b>52</b>. Further, the first D/A conversion circuit DAC<b>1</b> includes switch elements SS<b>1</b>, SS<b>2</b> for setting the nodes NC, N<b>1</b> to be GND (AGND) in the sampling period.

It should be noted that it is also possible to connect one end of a third series capacitor to the node N<b>1</b>, and to provide the other end of the third series capacitor with a capacitor array section and a switch array section having the configurations substantially the same as those of the capacitor array section <b>42</b> and the switch array section <b>52</b>, respectively.

The first capacitor array section <b>41</b> of the first D/A conversion circuit DAC<b>1</b> includes a plurality of capacitors CA<b>1</b> through CA<b>4</b>. These capacitors CA<b>1</b> through CA<b>4</b> have one ends connected to the comparison node NC of the comparison circuit <b>10</b>. Here, the comparison node NC (a sampling node) is a node to be connected to a first input terminal (an inverting input terminal) of the comparison circuit <b>10</b>, and a second input terminal (a non-inverting input terminal) of the comparison circuit <b>10</b> is set to be the GND. Further, the capacitors CA<b>1</b> through CA<b>4</b> are binary weighted, and the capacitance values of the capacitors CA<b>1</b>, CA<b>2</b>, CA<b>3</b>, and CA<b>4</b> are set to be C, 2C, 4C, and 8C, respectively, in the case of, for example, 4 bits. Further, the first capacitor array section <b>41</b> also includes a dummy capacitor CDM.

The first switch array section <b>51</b> of the first D/A conversion circuit DAC<b>1</b> includes a plurality of switch elements SA<b>1</b> through SA<b>4</b>. These switch elements SA<b>1</b> through SA<b>4</b> are connected respectively to the other ends of the capacitors CA<b>1</b> through CA<b>4</b> of the first capacitor array section <b>41</b>. Further, the switch elements SA<b>1</b> through SA<b>4</b> are switch-controlled based on the higher bit data (e.g., the higher 4 bit data in the case in which the successive approximation data RDA is 8-bit data) the successive approximation data RDA.

The second capacitor array section <b>42</b> of the first D/A conversion circuit DAC<b>1</b> includes a plurality of capacitors CB<b>1</b> through CB<b>4</b>. These capacitors CB<b>1</b> through CB<b>4</b> have one ends connected to the first node N<b>1</b>. Here, the first node N<b>1</b> is a node on the other end side of the series capacitor CS<b>1</b> whose one end is connected to the comparison node NC. Further, the capacitors CB<b>1</b> through CB<b>4</b> are binary weighted, and the capacitance values of the capacitors CB<b>1</b>, CB<b>2</b>, CB<b>3</b>, and CB<b>4</b> are set to be C, 2C, 4C, and 8C, respectively, in the case of, for example, 4 bits.

The second switch array section <b>52</b> of the first D/A conversion circuit DAC<b>1</b> includes a plurality of switch elements SB<b>1</b> through SB<b>4</b>. These switch elements SB<b>1</b> through SB<b>4</b> are connected respectively to the other ends of the capacitors CB<b>1</b> through CB<b>4</b> of the second capacitor array section <b>42</b>. Further, the switch elements SB<b>1</b> through SB<b>4</b> are switch-controlled based on the lower bit data (e.g., the lower 4 bit data in the case in which the successive approximation data RDA is 8-bit data) of the successive approximation data RDA.

The second D/A conversion circuit DAC<b>2</b> includes a second series capacitor CS<b>2</b> disposed between the comparison node NC and a second node N<b>2</b>. Further, the second D/A conversion circuit DAC<b>2</b> includes a third capacitor array section <b>43</b> and a third switch array section <b>53</b>. Further, the second D/A conversion circuit DAC<b>2</b> includes a switch element SS<b>3</b> for setting the second node N<b>2</b> to be the GND in the sampling period.

The third capacitor array section <b>43</b> of the second D/A conversion circuit DAC<b>2</b> includes a plurality of capacitors CC<b>1</b> through CC<b>4</b>. These capacitors CC<b>1</b> through CC<b>4</b> have one ends connected to the second node N<b>2</b>. Here, the second node N<b>2</b> is a node on the other end side of the series capacitor CS<b>2</b> whose one end is connected to the comparison node N<b>2</b>. Further, the capacitors CC<b>1</b> through CC<b>4</b> are binary weighted, and the capacitance values of the capacitors CC<b>1</b>, CC<b>2</b>, CC<b>3</b>, and CC<b>4</b> are set to be C, 2C, 4C, and 8C, respectively, in the case of, for example, 4 bits.

The third switch array section <b>53</b> of the second D/A conversion circuit DAC<b>2</b> includes a plurality of switch elements SC<b>1</b> through SC<b>4</b>. These switch elements SC<b>1</b> through SC<b>4</b> are connected respectively to the other ends of the capacitors CC<b>1</b> through CC<b>4</b> of the third capacitor array section <b>43</b>. Further, the switch elements SC<b>1</b> through SC<b>4</b> are switch-controlled based on the code data CDA.

In other words, the code data generation section <b>90</b> outputs the code data CDA to the D/A conversion circuit DAC<b>2</b>, and switching control of the switch elements SC<b>1</b> through SC<b>4</b> is performed based on the code data CDA. For example, the code data generation section <b>90</b> outputs the data taking a value varying every A/D conversion timing or every plurality of A/D conversion timings within a data range of lower bit data of the successive approximation data RDA as the code data CDA.

Specifically, in the case of the 8-bit A/D conversion shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, the code data generation section <b>90</b> varies the code data CDA within a data range of lower 4 bits of the successive approximation data RDA. For example, the code data generation section <b>90</b> varies the code data CDA in a random manner within the data range (or within a data range narrower than the data range of 0000 through 1111) of 0000 through 1111 to perform switching control of the switch elements SC<b>1</b> through SC<b>4</b> of the switch array section <b>53</b> of the D/A conversion circuit DAC<b>2</b>. In this case, the switching control of the switch elements SB<b>1</b> through SB<b>4</b> of the switch array section <b>52</b> of the D/A conversion circuit DAC<b>1</b> is also performed in accordance with the lower 4-bit data of the successive approximation data RDA. As described above, by setting the range in which the code data CDA is varied within the data range of the successive approximation data RDA for performing the switching control of the switch elements of the first D/A conversion circuit DAC<b>1</b>, the missing code can effectively be prevented from occurring.

It should be noted that the minimum resolution (a voltage corresponding to the LSB, or a quantized voltage) of the first D/A conversion circuit DAC<b>1</b> is denoted as RS<b>1</b>, and the minimum resolution of the second D/A conversion circuit DAC<b>2</b> is denoted as RS<b>2</b>. In this case, RS<b>2</b>=RS<b>1</b> is satisfied in <figref idrefs="DRAWINGS">FIG. 4</figref>. Specifically, the capacitance values of the series capacitors CS<b>1</b>, CS<b>2</b> are arranged to be the same (substantially the same), and the capacitance value of the capacitor CB<b>1</b> corresponding to the LSB of the first D/A conversion circuit DAC<b>1</b> and the capacitance value of the capacitor CC<b>1</b> corresponding to the LSB of the second D/A conversion circuit DAC<b>2</b> are also arranged to be the same (substantially the same). In other words, the second D/A conversion circuit DAC<b>2</b> outputs a code voltage higher than a noise voltage instead of the noise voltage lower than the minimum resolution RS<b>1</b> (the LSB) of the first D/A conversion circuit DAC<b>1</b>. According to such a configuration, the code shift shown in <figref idrefs="DRAWINGS">FIG. 3B</figref> can be realized. It should be noted that RS<b>2</b>=RS<b>1</b> is not a limitation, but RS<b>2</b>≧RS<b>1</b> can be adopted.

Then, the operation of the present embodiment will be explained in detail with reference to <figref idrefs="DRAWINGS">FIG. 5</figref>. As shown in <figref idrefs="DRAWINGS">FIG. 5</figref>, in the sampling period of the input signal VIN, the switch elements SS<b>1</b>, SS<b>2</b> of the primary D/A conversion circuit DAC<b>1</b> are switched on to thereby set the nodes NC, N<b>1</b> to be the GND. Further, the other ends of the capacitors CA<b>1</b> through CA<b>4</b>, and CB<b>1</b> through CB<b>4</b> are set to be the voltage level of the input signal VIN via the respective switch elements SA<b>1</b> through SA<b>4</b>, and SB<b>1</b> through SB<b>4</b> of the first D/A conversion circuit DAC<b>1</b>.

Thus, sampling of the input signal VIN is achieved. Then, when the switch elements SA<b>1</b> through SA<b>4</b>, and SB<b>1</b> through SB<b>4</b> are switched off, the voltage of the input signal VIN is held at that timing. It should be noted that in the sampling period, the other end of the dummy capacitor CDM is set to be the voltage level of the input signal VIN via the switch element SDM for the dummy capacitor CDM.

Further, in the sampling period, the switch element SS<b>3</b> of the second D/A conversion circuit DAC<b>2</b> for the code shift is switched on to thereby set the node N<b>2</b> to be the GND. Further, the other ends of the capacitors CC<b>1</b> through CC<b>4</b> are set to be the GND via the switch elements SC<b>1</b> through SC<b>4</b>. Thus, the both ends of the capacitors CC<b>1</b> through CC<b>4</b> are set to be the GND to thereby be set to the state in which no charge is stored.

Subsequently, when the successive approximation period for the A/D conversion takes place, the switch elements SS<b>1</b>, SS<b>2</b> of the primary D/A conversion circuit DAC<b>1</b> are switched off. Further, the other end of the switch element SDM for the dummy capacitor CDM is set to be the GND.

Then, the switching control of the switch elements SA<b>1</b> through SA<b>4</b>, and SB<b>1</b> through SB<b>4</b> of the first D/A conversion circuit DAC<b>1</b> is performed based on the respective bits of the successive approximation data RDA, and the other ends of the capacitors CA<b>1</b> through CA<b>4</b>, and CB<b>1</b> through CB<b>4</b> are set to be the VREF or the GND.

For example, if the successive approximation data RDA is equal to 10000000, the other end of the capacitor CA<b>4</b> corresponding to the MSB of the successive approximation data RDA is set to be the reference voltage VREF. Further, the other ends of the other capacitors CA<b>3</b> through CA<b>1</b>, and CB<b>4</b> through CB<b>1</b> are set to be the GND.

Further, if the successive approximation data RDA is equal to 10001000, the other ends of the capacitors CA<b>4</b> and CB<b>4</b> are set to be the reference voltage VREF. Further, the other ends of the other capacitors CA<b>3</b> through CA<b>1</b>, and CB<b>3</b> through CB<b>1</b> are set to be the GND.

Subsequently, when the successive approximation period for the A/D conversion takes place, the switch element SS<b>3</b> of the second D/A conversion circuit DAC<b>2</b> for the code shift is switched off. Then, the switching control of the switch elements SC<b>1</b> through SC<b>4</b> of the second D/A conversion circuit DAC<b>2</b> is performed based on the respective bits of the code data CDA, and the other ends of the capacitors CC<b>1</b> through CC<b>4</b> are set to be the reference voltage VREF or the GND.

In the case in which the code data CDA is equal to, for example, 1000, the other end of the capacitor CC<b>4</b> is set to be the reference voltage VREF, and the other ends of the other capacitors CC<b>3</b> through CC<b>1</b> are set to be the GND. Further, in the case in which the code data CDA is equal to, for example, 1100, the other ends of the capacitors CC<b>4</b> and CC<b>3</b> are set to be the reference voltage VREF, and the other ends of the other capacitors CC<b>2</b> and CC<b>1</b> are set to be the GND.

In this case, the code data CDA varies every A/D conversion timing shown in <figref idrefs="DRAWINGS">FIG. 5</figref>. Specifically, the code data varies every A/D conversion period composed of the sampling period and the successive approximation period. It should be noted that it is also possible to vary the code data CDA every plurality of A/D conversion timings.

In the charge redistribution A/D conversion circuit shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, there is performed a comparison process between the sampled signal (the sampled voltage) of the input signal VIN, and the addition signal (an addition voltage) of the D/A output signal and the code signal (a code voltage). In this case, the control circuit <b>20</b> performs a process of adding the code data CDA to the successive approximation result data QDA of the successive approximation register SAR.

Specifically, in the sampling period, the charge corresponding to the input signal VIN is stored in the capacitors CA<b>1</b> through CA<b>4</b>, and CB<b>1</b> through CB<b>4</b>. Further, the charge stored in accordance with the input signal VIN and the charge stored in the capacitors CA<b>1</b> through CA<b>4</b>, CB<b>1</b> through CB<b>4</b>, and CC<b>1</b> through CC<b>4</b> in accordance with the successive approximation data RDA and the code data CDA in the successive approximation period are compared to each other. Then, the successive approximation data RDA with which both of the charges are the same is output from the successive approximation register SAR as the successive approximation result data QDA. Then, the data obtained by adding the code data CDA to the successive approximation result data QDA is output as the data DOUT obtained by performing the A/D conversion on the input signal VIN. According to the process described above, it becomes possible to output appropriate A/D conversion data while realizing the code shift with the code data CDA shown in <figref idrefs="DRAWINGS">FIG. 3B</figref>.

<figref idrefs="DRAWINGS">FIG. 6</figref> shows an A/D conversion circuit of a second comparative example of the present embodiment. This second comparative example is an example of realizing the first comparative example shown in <figref idrefs="DRAWINGS">FIG. 2</figref> using the charge redistribution circuit, and the D/A conversion circuit DAC (and the S/H circuit <b>330</b>) is realized by a capacitor array section <b>321</b>, a switch array section <b>331</b>, and a switch element SS.

A significant factor for determining the conversion accuracy of the A/D conversion circuit is the conversion accuracy of the D/A conversion circuit DAC. In the second comparative example shown in <figref idrefs="DRAWINGS">FIG. 6</figref>, assuming that the resolution of the DAC is n bits, the capacitor array section <b>321</b> is composed of n capacitors CA<b>1</b> through CAn binary weighted and one dummy capacitor CDM. Further, in the sampling period, the other ends of the capacitors CA<b>1</b> through CAn are connected to the input signal VIN, and the comparison node NC is set to be the GND.

Then, in the successive approximation period, the successive approximation process is performed sequentially from the MSB, the most significant bit. Specifically, connection destinations of the other ends of the capacitors CA<b>1</b> through CAn are switched between the reference voltage VREF and the GND in accordance with the input value of the D/A conversion circuit using the switch elements SA<b>1</b> through SAn of the switch array section <b>331</b>. Thus, the voltage of the comparison node NC of the inverting input terminal of the comparison circuit <b>310</b> becomes the voltage obtained by subtracting the sampled voltage of the input signal VIN from the output value of the D/A conversion circuit DAC.

However, in the second comparative example shown in <figref idrefs="DRAWINGS">FIG. 6</figref>, if the resolution of the D/A conversion circuit DAC is set to be 12 bits in order for setting the resolution of the A/D conversion circuit to be, for example, 12 bits, the total capacitance value of 2¹²×C is required. Therefore, the size of the circuit is enlarged, and at the same time, a large current is required for charging the capacitors. Since the higher the resolution of the A/D conversion circuit is set, the stronger the tendency becomes, the second comparative example shown in <figref idrefs="DRAWINGS">FIG. 6</figref> has a problem that there is a limitation of increasing the number of bits.

<figref idrefs="DRAWINGS">FIG. 7</figref> shows a third comparative example of the A/D conversion circuit. In order for solving the problem of the second comparative example described above, the third comparative example has a configuration of providing the series capacitor CS to thereby provide multiple stages of binary weighted capacitors. Specifically, there is provided a series capacitor CS having one end connected to the comparison node NC and the other end connected to the node N<b>1</b>. Further, there are provided a capacitor array section <b>341</b> connected to the comparison node NC, a switch array section <b>351</b> for performing the switching control of the capacitor array section <b>341</b>, a capacitor array section <b>342</b> connected to the node N<b>1</b>, and a switch array section <b>352</b> for performing the switching control of the capacitor array section <b>342</b>.

According to the configuration of the third comparative example shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, it is possible to make, for example, the capacitance value of the capacitor CA<b>1</b> of the capacitor array section <b>341</b> and the capacitance value of the capacitor CB<b>1</b> of the capacitor array section <b>342</b> equal to each other. Therefore, taking the 8-bit case as an example, the capacitance value of 2⁵×C is enough for the third comparative example shown in <figref idrefs="DRAWINGS">FIG. 7</figref> while the capacitance value of 2⁸×C is required for the second comparative example shown in <figref idrefs="DRAWINGS">FIG. 6</figref>. Therefore, reduction in the area of the circuit can be achieved, and at the same time, the charge current of the capacitors can also be reduced.

However, in the third comparative example shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, there arises a problem that the capacitance parasitic on the node N<b>1</b> deteriorates the differential non-linearity (DNL) or the integral non-linearity (INL) of the D/A conversion circuit DAC. This is caused by the fact that the ratio between the binary weighted capacitances is deviated by the parasitic capacitance. This negative influence remarkably arises in the vicinity of the code with the fifth LSB changed when taking the 8-bit case shown in <figref idrefs="DRAWINGS">FIG. 7</figref> as an example. Specifically, it arises at the transition between 00001111 and 00010000 (the MSB is at the forefront), and causes the problem of the missing code as shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>.

As a method of solving such a problem, it is possible to adopt a method of trimming the capacitance value of the series capacitor CS to fine-tune the characteristic. However, if the trimming is used alone, there exist limitations in the unit and the range of the capacitance which can be trimmed. Further, the trimming process is required in the manufacturing process, which incurs increase in cost. Further, although it is also possible to perform a digital compensation process for correcting the A/D-converted data in a digital manner to thereby achieve higher accuracy, there arises a problem that the process becomes complicated, and at the same time, an extra process is required.

Then, a logical expression of the SAR type A/D conversion circuit in the case in which the parasitic capacitances CP<b>1</b>, CP<b>2</b> are added to the nodes NC, N<b>1</b> will be explained with reference to <figref idrefs="DRAWINGS">FIG. 8</figref>. The logical expression not including the parasitic capacitances CP<b>1</b>, CP<b>2</b> can be derived by setting the parasitic capacitances CP<b>1</b>, CP<b>2</b> to be zero. It should be noted that the capacitance values of the capacitors CA<b>1</b>, CB<b>1</b> are assumed to be C, the capacitance values of the capacitors CA<b>2</b>, CB<b>2</b> are assumed to be 2C, the capacitance values of the capacitors CA<b>3</b>, CB<b>3</b> are assumed to be 4C, and the capacitance values of the capacitors CA<b>4</b>, CB<b>4</b> are assumed to be 8C. Further, the capacitance value of the series capacitor CS is assumed to be C. Further, the dummy capacitor CDM is used for the purpose (full-scale adjustment) of adjusting the amount of charge charged when sampling, and the capacitance value of the dummy capacitor CDM is ignored for the sake of simplification of explanation.

<figref idrefs="DRAWINGS">FIG. 8</figref> shows a state of the switch element in the sampling period. The charge amount Q<b>1</b> charged in the node NC in the sampling period is expressed by the following formula (1).

<maths id="MATH-US-00001" num="00001"><math overflow="scroll"><mtable><mtr><mtd><mtable><mtr><mtd><mrow><mrow><mi>Q</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>1</mn></mrow><mo>=</mo><mrow><mrow><mo>(</mo><mrow><mi>C</mi><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mn>4</mn><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mn>8</mn><mo>⁢</mo><mi>C</mi></mrow></mrow><mo>)</mo></mrow><mo>⁢</mo><mrow><mo>(</mo><mrow><mn>0</mn><mo>-</mo><mi>VIN</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mrow><mrow><mo>-</mo><mn>15</mn></mrow><mo>⁢</mo><mrow><mi>C</mi><mo>·</mo><mi>VIN</mi></mrow></mrow></mrow></mtd></mtr></mtable></mtd><mtd><mrow><mo>(</mo><mn>1</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths>

Further, the charge amount Q<b>2</b> charged in the node N<b>1</b> in the sampling period is expressed by the following formula (2).

<maths id="MATH-US-00002" num="00002"><math overflow="scroll"><mtable><mtr><mtd><mtable><mtr><mtd><mrow><mrow><mi>Q</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow><mo>=</mo><mrow><mrow><mo>(</mo><mrow><mi>C</mi><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mn>4</mn><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mn>8</mn><mo>⁢</mo><mi>C</mi></mrow></mrow><mo>)</mo></mrow><mo>⁢</mo><mrow><mo>(</mo><mrow><mn>0</mn><mo>-</mo><mi>VIN</mi></mrow><mo>)</mo></mrow></mrow></mrow></mtd></mtr><mtr><mtd><mrow><mo>=</mo><mrow><mrow><mo>-</mo><mn>15</mn></mrow><mo>⁢</mo><mrow><mi>C</mi><mo>·</mo><mi>VIN</mi></mrow></mrow></mrow></mtd></mtr></mtable></mtd><mtd><mrow><mo>(</mo><mn>2</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths>

It should be noted that since the both ends of the series capacitor CS and the parasitic capacitances CP<b>1</b>, CP<b>2</b> are provided with GND (the ground potential), no charge is charged thereto.

Subsequently, the voltage V<b>1</b> of the node NC and the voltage V<b>2</b> of the node N<b>1</b> in the successive approximation period are obtained. For example, in <figref idrefs="DRAWINGS">FIG. 8</figref>, the switching control of the switch elements SB<b>1</b> through SB<b>4</b> is performed in accordance with the lower 4 bits D<b>0</b> through D<b>3</b> of the successive approximation data RDA, and the switching control of the switch elements SA<b>1</b> through SA<b>4</b> is performed in accordance with the higher 4 bits D<b>4</b> through D<b>7</b> of the successive approximation data RDA. Specifically, if the bit Di is equal to 1 (0≦i≦7), the corresponding switch element is connected to the input signal VIN, and if the bit Di is equal to 0, the corresponding switch element is connected to the GND. In this case, the charge amounts Q<b>1</b>, Q<b>2</b> to be accumulated in the nodes NC, N<b>1</b> during the successive approximation period are expressed respectively as the following formulas (3), (4). <br /><i>Q</i>1<i>=CP</i>1(<i>V</i>1−0)+<i>CS</i>(<i>V</i>1<i>−V</i>2) +<i>C</i>(<i>V</i>1<i>−V</i>REF·<i>D</i>0)+2<i>C</i>(<i>V</i>1<i>−V</i>REF·<i>D</i>1)+4<i>C</i>(<i>V</i>1<i>−V</i>REF·<i>D</i>2)+8<i>C</i>(<i>V</i>1<i>−V</i>REF·<i>D</i>3)  (3)<br /><i>Q</i>2<i>=CP</i>2(<i>V</i>2−0)+<i>CS</i>(<i>V</i>2<i>−V</i>1) +<i>C</i>(<i>V</i>2<i>−V</i>REF·<i>D</i>4)+2<i>C</i>(<i>V</i>2<i>−V</i>REF·<i>D</i>5)+4<i>C</i>(<i>V</i>2<i>−V</i>REF·<i>D</i>6)+8<i>C</i>(<i>V</i>2<i>−V</i>REF·<i>D</i>7)   (4)

Further, according to the law of conservation of charge, the charge amount Q<b>1</b> in the formulas (1) and (3) is the same, and the charge amount Q<b>2</b> in the formulas (2) and (4) is the same. Further, since the voltage of the node NC of the inverting input terminal of the comparison circuit <b>310</b> becomes equal to the GND of the non-inverting input terminal after the comparison operation with respect to all of the bits D<b>0</b> through D<b>7</b> of the successive approximation data RDA has been completed, the following formula (5) becomes true. <br />V1=0  (5)

Therefore, by solving the simultaneous formulas (1) through (5) with respect to the input signal VIN, the following formula (6) is derived.

<maths id="MATH-US-00003" num="00003"><math overflow="scroll"><mtable><mtr><mtd><mrow><mrow><mi>VIN</mi><mo>=</mo><mrow><mrow><mrow><mfrac><mi>VREF</mi><mrow><mrow><mn>255</mn><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mn>15</mn><mo>⁢</mo><mi>CP</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow></mrow></mfrac><mo>[</mo><mrow><mrow><mrow><mo>(</mo><mrow><mrow><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>0</mn></mrow><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>1</mn></mrow><mo>+</mo></mrow><mo> </mo></mrow><mo>⁢</mo><mn>4</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow><mo>+</mo><mrow><mrow><mo> </mo><mo> </mo></mrow><mo>⁢</mo><mn>8</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>3</mn></mrow><mo>+</mo><mrow><mn>16</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>4</mn></mrow><mo>+</mo><mrow><mn>32</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>5</mn></mrow><mo>+</mo><mrow><mn>64</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>6</mn></mrow><mo>+</mo><mrow><mn>128</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>7</mn></mrow></mrow><mo>)</mo></mrow><mo>⁢</mo><mi>C</mi></mrow><mo>+</mo><mrow><mrow><mo>(</mo><mrow><mrow><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>4</mn></mrow><mo>+</mo><mrow><mn>2</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>5</mn></mrow><mo>+</mo><mrow><mn>4</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>6</mn></mrow><mo>+</mo><mrow><mn>8</mn><mo>⁢</mo><mi>D</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>7</mn></mrow></mrow><mo>)</mo></mrow><mo>⁢</mo><mi>CP</mi><mo>⁢</mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo>⁢</mo><mn>2</mn></mrow></mrow></mrow><mo>]</mo></mrow></mtd><mtd><mrow><mo>(</mo><mn>6</mn><mo>)</mo></mrow></mtd></mtr></mtable></math></maths>

As is obvious from the formula (6), no influence of the parasitic capacitance CP<b>1</b> of the node NC is exerted on the A/D conversion result of the input signal VIN, and only the parasitic capacitance CP<b>2</b> of the node N<b>2</b> exerts a negative influence on the characteristic. Therefore, in order for reducing the negative influence of the parasitic capacitance CP<b>2</b>, the series capacitor CS needs to be trimmed. Further, according to the formula (6), it is understood that the negative influence of the parasitic capacitance CP<b>2</b> appears when the connection of the switch element corresponding to any one of the bits D<b>4</b> or higher is changed, and thus the missing code shown in <figref idrefs="DRAWINGS">FIG. 3A</figref> occurs.

It should be noted that <figref idrefs="DRAWINGS">FIGS. 9A and 9B</figref> are explanatory diagrams of DNL and INL, respectively. The DNL shown in <figref idrefs="DRAWINGS">FIG. 9A</figref> corresponds to a difference between the ideal code width and the measured code width. For example, in <figref idrefs="DRAWINGS">FIG. 9A</figref>, due to the deterioration of the characteristic of the DNL, the width of the code <b>010</b> is narrowed, while the width of the code <b>011</b> is widened. Further, if the width of the code <b>010</b> is further narrowed to disappear, the code <b>010</b> turns to the missing code shown in <figref idrefs="DRAWINGS">FIG. 3A</figref>.

Further, the INL shown in <figref idrefs="DRAWINGS">FIG. 9B</figref> corresponds to the maximum difference between the actual code transition point (the broken line) and the ideal transition point (the solid line) corresponding thereto after the gain error and the offset error have been removed. The INL taking a positive value shows that the transition is delayed from the ideal point while the INL taking a negative value shows that the transition is earlier than the ideal point.

<figref idrefs="DRAWINGS">FIGS. 10A and 10B</figref> show examples of a simulation result of the DNL. Here, the explanation will be presented taking the case as an example, in which the full-differential A/D conversion circuit described later is used, a 14-bit D/A conversion circuit is used as the primary D/A conversion circuit DAC<b>1</b>, and a 4-bit D/A conversion circuit is used as the D/A conversion circuit DAC<b>2</b> for the code shift. Although in <figref idrefs="DRAWINGS">FIG. 4</figref> the primary D/A conversion circuit DAC<b>1</b> has a two-stage serial configuration of 4-bit D/A conversion circuits, the 14-bit primary D/A conversion circuit DAC<b>1</b> has a three-stage configuration of a 6-bit D/A conversion circuit and two 4-bit D/A conversion circuits.

<figref idrefs="DRAWINGS">FIG. 10A</figref> shows an example of the simulation result of the DNL in the case in which the code shift method of the present embodiment is not adopted. In <figref idrefs="DRAWINGS">FIG. 10A</figref>, the missing code in which the DNL becomes 1 LSB or more occurs.

<figref idrefs="DRAWINGS">FIG. 10B</figref> shows an example of the simulation result of the DNL in the case in which the code shift method of the present embodiment is adopted. In <figref idrefs="DRAWINGS">FIG. 10B</figref>, the DNL is kept lower than 1 LSB, thus the missing code is prevented from occurring.

As described above, according to the present embodiment, as shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, the D/A conversion circuit DAC<b>2</b> for the code shift is added to the third comparative example shown in <figref idrefs="DRAWINGS">FIG. 7</figref> to add the signal of the code data by the D/A conversion circuit DAC<b>2</b>, thereby realizing the code shift.

Specifically, in the third comparative example shown in <figref idrefs="DRAWINGS">FIG. 7</figref>, due to the parasitic capacitance CP<b>2</b> of the node N<b>1</b>, the missing code shown in <figref idrefs="DRAWINGS">FIG. 3A</figref> and <figref idrefs="DRAWINGS">FIG. 10A</figref> is caused. In contrast thereto, according to the present embodiment, the signal of the time-varying code data is added by the D/A conversion circuit DAC<b>2</b>, thereby deterioration (the missing code) of the DNL having occurred in the specific code is temporally diffused to the codes around. For example, in the case in which the missing code occurs at the fourth MSB, namely 00010000, the signal of the random code data varying within the data range of 0000 through 1111 is added. According to the process described above, the DNL can be kept lower than 1 LSB as shown in <figref idrefs="DRAWINGS">FIG. 3B</figref> and <figref idrefs="DRAWINGS">FIG. 10B</figref>, thereby preventing the missing code from occurring. Therefore, also in the case in which the series capacitor CS<b>1</b> is provided for reducing the circuit size, the missing code caused by the parasitic capacitance of the node N<b>1</b> can be prevented from occurring. As a result, it becomes possible to achieve both of reduction in the circuit size and prevention of deterioration of the characteristic of the A/D conversion.

3. Full-Differential A/D Conversion Circuit

<figref idrefs="DRAWINGS">FIG. 11</figref> shows a configuration example of the full-differential A/D conversion circuit to which the code shift method according to the present embodiment is applied. The A/D conversion circuit shown in <figref idrefs="DRAWINGS">FIG. 11</figref> includes the comparison circuit <b>10</b>, a primary D/A conversion circuit DAC<b>1</b>P connected to a non-inverting input terminal of the comparison circuit <b>10</b>, and a primary D/A conversion circuit DAC<b>1</b>N connected to an inverting input terminal thereof. Further, the A/D conversion circuit includes a D/A conversion circuit DAC<b>2</b>P for the code shift connected to the non-inverting input terminal of the comparison circuit <b>10</b> and a D/A conversion circuit DAC<b>2</b>N for the code shift connected to the inverting input terminal thereof.

The configuration of each of the primary D/A conversion circuit DAC<b>1</b>P on the non-inverting side (the positive side) and the primary D/A conversion circuit DAC<b>1</b>N on the inverting side (the negative side) includes the capacitor array section and the switch array section similarly to the primary D/A conversion circuit DAC<b>1</b> shown in <figref idrefs="DRAWINGS">FIG. 4</figref>. Further, the D/A conversion circuit DAC<b>1</b>P is provided with an input signal PIN on the non-inverting side (the positive side) constituting a differential signal input thereto, and the D/A conversion circuit DAC<b>1</b>N is provided with an input signal NIN on the inverting side (the negative side) constituting the differential signal input thereto.

Further, in the sampling period nodes NCP, N<b>1</b>P of the D/A conversion circuit DAC<b>1</b>P are set to be a common voltage (an intermediate voltage) VCM by respective switch elements SS<b>1</b>P, SS<b>2</b>P. Further, nodes NCN, N<b>1</b>N of the D/A conversion circuit DAC<b>1</b>N are set to be the common voltage VCM by respective switch elements SS<b>1</b>N, SS<b>2</b>N.

Further, in the sampling period one ends of switch elements SA<b>1</b>P through SA<b>4</b>P and SB<b>1</b>P through SB<b>4</b>P of the D/A conversion circuit DAC<b>1</b>P are connected to the signal PIN on the non-inverting side of the differential signal, and one ends of switch elements SA<b>1</b>N through SA<b>4</b>N and SB<b>1</b>N through SB<b>4</b>N of the D/A conversion circuit DAC<b>1</b>N are connected to the signal NIN on the inverting side of the differential signal.

On the other hand, in the successive approximation period the one ends of the switch elements SA<b>1</b>P through SA<b>4</b>P and SB<b>1</b>P through SB<b>4</b>P of the D/A conversion circuit DAC<b>1</b>P are connected to the VREF if the corresponding bit of the successive approximation data is set to be “1,” or connected to the GND if it is set to be “0.”

In contrast thereto, the one ends of the switch elements SA<b>1</b>N through SA<b>4</b>N and SB<b>1</b>N through SB<b>4</b>N of the D/A conversion circuit DAC<b>1</b>N are connected to the GND if the corresponding bit of the successive approximation data is set to be “1,” or connected to the VREF if it is set to be “0.”

The D/A conversion circuit DAC<b>2</b>P for the code shift on the non-inverting side and the D/A conversion circuit DAC<b>2</b>N for the code shift on the inverting side each include the capacitor array section and the switch array section similarly to the D/A conversion circuit DAC<b>2</b> for the code shift shown in <figref idrefs="DRAWINGS">FIG. 4</figref>.

Further, in the sampling period a node N<b>2</b>P of the D/A conversion circuit DAC<b>2</b>P is set to be the VCM by a switch element SS<b>3</b>P. Further, a node N<b>2</b>N of the D/A conversion circuit DAC<b>2</b>N is set to be the VCM by a switch element SS<b>3</b>N. Further, one ends of switch elements SC<b>1</b>P through SC<b>4</b>P of the D/A conversion circuit DAC<b>2</b>P and switch elements SC<b>1</b>N through SC<b>4</b>N of the D/A conversion circuit DAC<b>2</b>N are connected to the VCM.

On the other hand, in the successive approximation period the one ends of the switch elements SC<b>1</b>P through SC<b>4</b>P of the D/A conversion circuit DAC<b>2</b>P are connected to the VREF if the corresponding bit of the code data is set to be “1,” or connected to the GND if it is set to be “0.” In contrast thereto, the one ends of the switch elements SC<b>1</b>N through SC<b>4</b>N of the D/A conversion circuit DAC<b>2</b>N are connected to the GND if the corresponding bit of the code data is set to be “1,” or connected to the VREF if it is set to be “0.”

According also to the configuration shown in <figref idrefs="DRAWINGS">FIG. 11</figref>, it is also possible to improve the DNL and the INL of the A/D conversion circuit using the code shift method, thereby preventing the missing code and so on from occurring. Further, by configuring the A/D conversion circuit as the full-differential A/D conversion circuit, the amplitude can be increased, the S/N ratio can be improved, and at the same time, an influence of the common mode noise can be reduced.

4. Electronic Apparatus

<figref idrefs="DRAWINGS">FIG. 12</figref> shows a configuration example of an electronic apparatus including the A/D conversion circuit according to the present embodiment. The electronic apparatus includes a sensor <b>510</b>, a detection circuit <b>520</b>, an A/D conversion circuit <b>530</b>, and a processing section <b>540</b>. It should be noted that various modified implementations such as elimination of some constituents or addition of other constituents are also possible. For example, the detection circuit <b>520</b>, the A/D conversion circuit <b>530</b>, and the processing section <b>540</b> can be realized by an integrated circuit device.

As the electronic apparatus shown in <figref idrefs="DRAWINGS">FIG. 12</figref>, various apparatuses such as a bioinstrumentation apparatus (e.g., a pulse meter and a pedometer), a personal digital assistance, a video apparatus (a digital camera, a video camera), or a timepiece can be assumed.

The sensor <b>510</b> corresponds to a gyro sensor, an acceleration sensor, a photo sensor, or a pressure sensor, and various sensors corresponding to the purpose of the electronic apparatus can be used. The detection circuit <b>520</b> amplifies the sensor signal output from the sensor <b>510</b> to extract a desired signal. Further, the A/D conversion circuit <b>530</b> converts the detection signal (the desired signal) from the detection circuit <b>520</b> into digital data, and outputs it to the processing section <b>540</b>.

The processing section <b>540</b> executes a necessary digital signal processing on the digital data from the A/D conversion circuit <b>530</b>. Further, the processing section <b>540</b> can also perform gain control of the detection circuit <b>520</b>. Here, as the digital signal processing performed by the processing section <b>540</b>, various kinds of processing such as a fast Fourier transformation for extracting appropriate desired signal from the sensor signal can be assumed.

It should be noted that although the present embodiment is hereinabove explained in detail, it should easily be understood by those skilled in the art that various modifications not substantially departing from the novel matters and the effects of the invention are possible. Therefore, such modified examples should be included in the scope of the invention. For example, a term described at least once with a different term with a broader sense or the same meaning in the specification or the accompanying drawings can be replaced with the different term in any part of the specification or the accompanying drawings. Further, all of the combinations of the present embodiment and the modified examples can also be included in the scope of the invention. Further, the configurations and the operations, the A/D conversion method, the code generation method, and the code shift method of the A/D conversion circuit and the electronic apparatus are not limited to those explained in the present embodiment, and various modified implementations thereof are also possible. For example, although an example of the case of the primary D/A conversion circuit DAC<b>1</b> having the two-stage configuration is shown in <figref idrefs="DRAWINGS">FIG. 4</figref>, a configuration of three or more stages can also be adopted.

The entire disclosure of Japanese Patent Application No. 2009-112511, filed May 7, 2009 is expressly incorporated by reference herein.