Multileveled printed circuit board unit including substrate interposed between stacked bumps

CROSS REFERENCE TO RELATED APPLICATIONS

0001The present invention is a divisional of U.S. patent application Ser. No. 10/747,080, filed Dec. 30, 2003; which is a divisional of U.S. patent application Ser. No. 09/749,505, filed Dec. 28, 2000, now U.S. Pat. No. 6,697,261, issued Feb. 24, 2004; which is a continuation of PCT/JP99/01263, filed on Mar. 16, 1999.

BACKGROUND OF THE INVENTION

00021. Field of the Invention

0003The present invention relates to a printed circuit board unit including stacked solder or conductive bumps between a printed wiring substrate and a mounted component, and particularly, to an interposer or relay substrate interposed between the stacked conductive bumps.

00042. Description of the Prior Art

0005A printed circuit board unit is well known to include a mounted component such as a ball grid array (BGA) device, for example. When the electric circuit generates heat in the printed circuit board unit, a heat or thermal stress is in general induced in the printed wiring substrate, made of a glass epoxy or polyimide resin, and the ceramic substrate of the BGA device. Since the printed wiring substrate made of resin and the ceramic substrate have different thermal expansion coefficients, the substrates usually suffer from a relative movement or shift along the surface of the printed wiring substrate due to the thermal expansion.

0006Such a relative movement between the printed wiring substrate made of resin and the ceramic substrate induces a shearing stress in solder bumps disposed between the printed wiring substrate and the ceramic substrate. The shearing stress may repeatedly be generated in the solder bumps in response to switching between on and off statuses of the electric circuit in the printed circuit board unit. The solder bumps may sometimes suffer from cracks when the shearing strain finally overcomes the strength of the solder bumps. The thus repeated and intermittent generation of the shearing stress is supposed to deteriorate the durability of the solder bumps.

0007It is conventionally known that a higher or taller solder bump leads to reduction in the shearing stress induced in the solder bump. A higher solder bump contributes to a broader distribution of the shearing stress, so that a smaller shearing stress can be defined within a horizontal cross-section of the solder bump. However, an increase in the height of a spherical solder bump or solder ball inevitably induces an increase in the width of the solder ball. A higher or taller solder ball in this manner is supposed to suffer from a smaller distribution density of the solder balls.

0008In view of the above-described disadvantage, it is proposed that solder bumps are vertically stacked on the printed wiring substrate below the mounted component. The stacked solder bumps are supposed to realize an increase in the height without increasing the width. In this proposal, the solder bumps and relay substrates are alternately stacked on one another on the printed wiring substrate. The relay substrate serves to connect the adjacent stacked solder bumps.

0009As disclosed in Japanese Patent Application Laid-open No. 09-214088, for example, it is proposed that the thermal expansion coefficient of the relay substrate is set at an intermediate level between the thermal expansion coefficients of the printed wiring substrate and the mounted component. In this case, a shearing stress is equally distributed over the stacked solder bumps. Japanese Patent Application Laid-open No. 62-18049 still proposes to interpose a relay substrate in the form of a film having a smaller Young's modulus between the stacked solder bumps. The relay substrate is supposed to absorb a larger shearing stress.

SUMMARY OF THE INVENTION

0010It is accordingly an object of the present invention to provide an interposer or a relay substrate for a multileveled printed circuit board unit capable of more efficiently absorbing a repetitive shearing stress induced in conductive bumps stacked between a printed wiring substrate and a mounted component, and a printed circuit board unit employing the same interposer.

0011It is another object of the present invention to provide an interposer or relay substrate capable of introducing additional functions in a multileveled printed circuit board unit.

0012According to a first aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising an interposer substrate made of a porous material interposed between stacked conductive bumps.

0013In the multileveled printed circuit board unit employing the interposer, when any difference in the expansion is caused between the printed wiring substrate and the mounted component, one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force. A shearing stress is induced in the interposer substrate. Deformation of the porous material serves to absorb the shearing stress in the interposer substrate. The conductive bumps bonded on one side of the interposer substrate as well as the conductive bumps bonded on the other side of the interposer substrate may be relieved from a shearing stress. Accordingly, the durability of the conductive bumps can be improved. The conductive bumps are allowed to keep a stronger bonding in a longer duration.

0014The porous material is preferably designed to define pores penetrating through the interposer substrate. The pore may be utilized to provide a via establishing an electric connection between the conductive bumps on the opposite sides. It is not necessary to bore the interposer substrate solely for the via. Production process of the interposer substrate can be facilitated.

0015The pore is designed as a slit located between adjacent ones of the conductive bumps arranged on an identical level. Even when one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force in the aforementioned manner, a shearing stress can be absorbed by deformation of the slit. In this case, the size of the slit at a central area of the interposer substrate is preferably set smaller than that of the slit located at a area remoter from the central area, since the planar displacement or shift gets larger at a location remoter from the center of the interposer substrate upon a thermal expansion of the printed wiring substrate and the mounted component.

0016According to a second aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising multilayered films made of different materials interposed between stacked conductive bumps.

0017It is possible to provide different characteristics at the opposite sides of the interposer substrate, respectively. For example, when the film contacting the mounted component may be made of a material having a thermal expansion coefficient identical to that of the mounted component, no shearing stress is induced in the conductive bumps between the mounted component and the film. On the other hand, when the film contacting the printed wiring substrate may be made of a material having a thermal expansion coefficient identical that of the printed wiring substrate, no shearing stress is likewise induced in the conductive bumps between the film and the printed wiring substrate. The material of the film contacting the mounted component may be selected from inorganic materials forming the substrate of the mounted component. The material of the film contacting the printed wiring substrate is selected from organic materials forming the printed wiring substrate. A relative sliding movement between the films may be accomplished by an adhesive layer interposed between the films. The adhesive layer may be made of an adhesive for coupling the films with each other.

0018According to a third aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit, comprising: a first conductive bump on a first level; and a second conductive bump on a second level stacked on the first conductive bump between a printed wiring substrate and a mounted component, said second conductive bump having a size different from that of the first conductive bump.

0019In general, the larger the size or diameter of a conductive bump gets, the larger the strength of the conductive bump can be obtained. The first and second conductive bumps are allowed to provide different strengths optimally required in the separate levels of the stacked conductive bumps, so that it is possible to minimize the size or diameter of the first and second conductive bumps. The overall height of the stacked solder bumps can thus be reduced, keeping a required strength. Alternatively, the first and second conductive bumps may be made of different materials, so that diffusion bonding of various strengths can be obtained between the conductive bumps and the interposer substrates as well as the other substrates, respectively.

0020According to a fourth aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a conductive wiring pattern formed on the interposer substrate so as to electrically connect at least the conductive bumps arranged on an identical level.

0021In the multileveled printed circuit board unit employing the interposer, the conductive wiring pattern on the interposer substrate serves to establish an alternative electric path for a disconnected wiring pattern on the printed wiring substrate and/or the mounted component. Also, the conductive wiring pattern may establish a modified electric path in place of a wiring pattern initially formed on the printed wiring substrate and/or the mounted component. In this case, two or more components may be mounted on the interposer substrate. In such a printed circuit board unit, the conductive wiring pattern on the interposer substrate may serve to establish an alternative electric path for a disconnected wiring pattern on the printed wiring substrate so as to electrically connect the mounted components to each other. Otherwise, the conductive wiring pattern may establish a modified electric path for a wiring pattern initially formed on the printed wiring substrate so as to connect the mounted components to each other.

0022According to a fifth aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a conductive pad disposed at a periphery of an area receiving the conductive bumps on the interposer substrate so as to receive a connecting wire.

0023In the multileveled printed circuit board unit employing the interposer, the connecting wire can simply be employed to establish an electric connection between the mounted components. In addition, since the conductive pads are allowed to receive the connecting wire at the periphery of the area receiving the conductive bumps on the interposer substrate, it is possible to easily fix the connecting wire to the target conductive pad without disassembling the multileveled printed circuit board unit.

0024According to a sixth aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a conductive pad disposed at a periphery of an area receiving the conductive bumps on the interposer substrate so as to receive a probe.

0025In the multileveled printed circuit board unit employing the interposer, it is possible to easily conduct an inspection for electric connection between the mounted component and the printed wiring substrate by simply contacting the tip ends of inspection probes with the target conductive pads. The inspection may serve to reveal a disconnection of the wiring pattern formed on the printed wiring substrate, a disconnection of the wiring pattern within the mounted component, and a disconnection at the respective conductive bumps. Moreover, since the conductive pads are allowed to receive the inspection probe at the periphery of the area receiving the conductive bumps on the interposer substrate, it is possible to easily contact the inspection probe with the target conductive pad without disassembling the multileveled printed circuit board unit.

0026According to a seventh aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a heat radiator attached to the interposer substrate.

0027In the multileveled printed circuit board unit employing the interposer, when the electric circuit operates to generate heat in the interposer substrate, heat radiation from the interposer substrate can be promoted through the heat radiator. The heat radiator may take the form of a fin, a thermal conductive pattern formed on the surface of the interposer substrate, and the like.

0028According to an eighth aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a standoff member standing on the interposer substrate so as to receive at least one of the printed wiring substrate and the mounted component at its tip end.

0029Employment of the interposer enables a method of mounting a component on a printed wiring substrate, comprising: preparing an interposer including a standoff member standing on an interposer substrate; preparing conductive bumps stacked between the printed wiring substrate and the component while allowing the interposer interposed between stacked conductive bumps; and reflowing the conductive bumps while the interposer and the component are urged against the printed wiring substrate. In this method, a pressure during a reflowing process enables leveling the height of the resulting conducive bumps, regulated by the height of the standoff member, on the identical level even if an irregularity can be found in the height of the conductive bumps on the identical level before reflowing. The respective conductive bumps reliably achieve a bonding between the mounted component and interposer substrate as well as between the interposer substrate and the printed wiring substrate.

0030According to a ninth aspect of the present invention, there is provided an interposer for a multileveled printed circuit board unit in which conductive bumps are stacked between a printed wiring substrate and a mounted component, comprising: an interposer substrate interposed between stacked conductive bumps; and a guide member located on the interposer substrate at a predetermined location for adjustment of a relative position between the printed wiring substrate and the mounted component.

0031The guide member serves to prevent a displacement or slippage of the mounted component relative to the printed wiring substrate even when the conductive bumps are caused to melt during a ref lowing process. The conductive bumps can reliably be bonded to the corresponding electrode pads on the mounted component, the interposer substrate and the printed wiring substrate, respectively.

0032The aforementioned interposers can be applied to a multileveled printed circuit board unit comprising: a printed wiring substrate; a component to be mounted on the printed wiring substrate; and conductive bumps stacked between the printed wiring substrate and the mounted component. It should be noted that the mounted component may include a ball grid array (BGA) device, a pin grid array (PGA) device, a flip chip, a chip for a multichip module (MCM), and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

0033The above and other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments in conjunction with the accompanying drawings, wherein:

0034<figref idref="DRAWINGS">FIGS. 1A to 1D</figref> are side views schematically illustrating the structure of a multileveled printed circuit board unit comprising solder bumps stacked one another between a printed wiring substrate and a mounted component, and a method of producing the same;

0035<figref idref="DRAWINGS">FIGS. 2A and 2B</figref> are side views illustrating the structure of an assembly comprising a mounted component and an interposer substrate;

0036<figref idref="DRAWINGS">FIG. 3</figref> is a side view illustrating a joined structure of interposer substrates;

0037<figref idref="DRAWINGS">FIGS. 4A and 4B</figref> are side view illustrating the structure of a multileveled printed circuit board unit filled with a potting material;

0038<figref idref="DRAWINGS">FIGS. 5A and 5B</figref> are side views illustrating the structure of an assembly comprising a mounted component and an interposer substrate filled with a potting material;

0039<figref idref="DRAWINGS">FIG. 6</figref> is a side view illustrating a joined structure of interposer substrates filled with a potting material;

0040<figref idref="DRAWINGS">FIG. 7</figref> is a plan view illustrating an interposer substrate according to a first embodiment of the present invention;

0041<figref idref="DRAWINGS">FIG. 8</figref> is an enlarged partial sectional view taken along the line <b>8</b>-<b>8</b> in <figref idref="DRAWINGS">FIG. 7</figref>;

0042<figref idref="DRAWINGS">FIG. 9</figref> is a plan view illustrating an interposer substrate according to a second embodiment of the present invention;

0043<figref idref="DRAWINGS">FIG. 10</figref> is an enlarged partial sectional view taken along the line <b>10</b>-<b>10</b> in <figref idref="DRAWINGS">FIG. 9</figref>;

0044<figref idref="DRAWINGS">FIG. 11</figref> is a plan view illustrating a modification of the interposer substrate according to the second embodiment of the present invention;

0045<figref idref="DRAWINGS">FIG. 12</figref> is a side view illustrating an interposer substrate according to a third embodiment of the present invention;

0046<figref idref="DRAWINGS">FIG. 13</figref> is an enlarged partial sectional view illustrating the structure of an interposer substrate according to a fourth embodiment of the present invention;

0047<figref idref="DRAWINGS">FIG. 14</figref> is a sectional view illustrating the behavior of the interposer substrate;

0048<figref idref="DRAWINGS">FIG. 15</figref> is a side view schematically illustrating the structure of a multileveled printed circuit board unit comprising an interposer substrate according to a fifth embodiment of the present invention, and a method of producing the same;

0049<figref idref="DRAWINGS">FIG. 16</figref> is a side view schematically illustrating the structure of a multileveled printed circuit board unit comprising an interposer substrate according to a sixth embodiment of the present invention, and a method of producing the same;

0050<figref idref="DRAWINGS">FIGS. 17A and 17B</figref> is plan and side views illustrating the structure of a multileveled printed circuit board unit comprising an interposer substrate according to a seventh embodiment of the present invention;

0051<figref idref="DRAWINGS">FIGS. 18A and 18B</figref> are plan and side views illustrating a modified example of a multileveled printed circuit board unit employing the interposer substrate according to the seventh embodiment;

0052<figref idref="DRAWINGS">FIG. 19</figref> is a plan view illustrating an interposer substrate according to an eighth embodiment of the present invention;

0053<figref idref="DRAWINGS">FIGS. 20A and 20B</figref> are plan and side views of the multileveled printed circuit board unit for illustrating the function of the interposer substrate according to the eighth embodiment;

0054<figref idref="DRAWINGS">FIG. 21</figref> is a plan view illustrating an interposer substrate according to a ninth embodiment of the present invention;

0055<figref idref="DRAWINGS">FIGS. 22A and 22B</figref> are plan and side views of the multileveled printed circuit board unit for illustrating the function of the interposer substrate according to the ninth embodiment;

0056<figref idref="DRAWINGS">FIGS. 23A and 23B</figref> are plan and side views of the multileveled printed circuit board unit for illustrating the function of the interposer substrate according to the ninth embodiment;

0057<figref idref="DRAWINGS">FIG. 24</figref> is a side view illustrating an interposer substrate according to tenth embodiment of the present invention;

0058<figref idref="DRAWINGS">FIG. 25</figref> is a plan view illustrating a modified example of the interposer substrate according to the tenth embodiment;

0059<figref idref="DRAWINGS">FIG. 26</figref> is a side view schematically illustrating the structure of a multileveled printed circuit board unit comprising an interposer substrate according to an eleventh embodiment of the present invention, and a method of producing the same;

0060<figref idref="DRAWINGS">FIG. 27</figref> is a side view illustrating an example of an interposer substrate according to the eleventh embodiment;

0061<figref idref="DRAWINGS">FIG. 28</figref> is a side view illustrating another example of an interposer substrate according to the eleventh embodiment;

0062<figref idref="DRAWINGS">FIG. 29</figref> is a side view illustrating further example of an interposer substrate according to the eleventh embodiment;

0063<figref idref="DRAWINGS">FIG. 30</figref> is a side view illustrating still further example of an interposer substrate according to the eleventh embodiment;

0064<figref idref="DRAWINGS">FIG. 31</figref> is a side view illustrating still further example of an interposer substrate according to the eleventh embodiment;

0065<figref idref="DRAWINGS">FIG. 32</figref> is a side view schematically illustrating the structure of a multileveled printed circuit board unit comprising an interposer substrate according to a twelfth embodiment of the present invention, and a method of producing the same;

0066<figref idref="DRAWINGS">FIG. 33</figref> is a side view illustrating another example of an interposer substrate according to the twelfth embodiment;

0067<figref idref="DRAWINGS">FIG. 34</figref> is a side view illustrating further example of an interposer substrate according to the twelfth embodiment;

0068<figref idref="DRAWINGS">FIG. 35</figref> is a plan view illustrating still further example of an interposer substrate according to the twelfth embodiment; and

0069<figref idref="DRAWINGS">FIG. 36</figref> is a plan view illustrating still further example of an interposer substrate according to the twelfth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

0070<figref idref="DRAWINGS">FIG. 1D</figref> illustrates a multileveled printed circuit board unit. The printed circuit board unit <b>10</b> includes a printed wiring substrate <b>11</b> on which conductive or electrode pads and a conductive or wiring pattern for electrically connecting the electrode pads are printed. The printed wiring substrate <b>11</b> may be made of a resin material such as a glass epoxy resin, a polyimide resin, or the like.

0071A component <b>12</b> is mounted on the printed wiring substrate <b>11</b>. The component <b>12</b> is fixed on the printed wiring substrate <b>11</b> with multileveled or stacked solder bumps <b>13</b> disposed between the printed wiring substrate <b>11</b> and the component <b>12</b>. The component <b>12</b> can be represented by a ball grid array (BGA) device, a flip chip, and the like. The component <b>12</b> may include a ceramic substrate <b>14</b>, for example.

0072An interposer or relay substrate <b>15</b> is interposed between the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>of the stacked solder bumps <b>13</b>. A via, not shown, may be formed in the interposer substrate <b>15</b> so as to electrically connect the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>. When the solder bumps <b>13</b> are stacked over three or more levels one another, the interposer substrate <b>15</b> can be interposed between the respective pairs of upper and lower solder bumps <b>13</b>.

0073As shown in <figref idref="DRAWINGS">FIG. 1A</figref>, when the component <b>12</b> is mounted on the printed wiring substrate <b>11</b>, the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>may be formed on the component <b>12</b> and the printed wiring substrate <b>11</b>, respectively. After the interposer substrate <b>15</b> is interposed between the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>, a reflowing process of the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>is conducted. As shown in <figref idref="DRAWINGS">FIG. 1B</figref>, the upper and lower bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>may be attached to the component <b>12</b> and the interposer substrate <b>15</b>, respectively, when the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>are stacked between the component <b>12</b> and the printed wiring substrate <b>11</b>. Furthermore, as shown in <figref idref="DRAWINGS">FIG. 1C</figref>, the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>may be formed on opposite surfaces of the interposer substrate <b>15</b> when the stacked solder bumps <b>13</b> are disposed between the component <b>12</b> and the printed wiring substrate <b>11</b>. When a reflowing process is conducted, an assembly of the component <b>16</b> and the interposer substrate <b>15</b> may previously be prepared, as shown in <figref idref="DRAWINGS">FIGS. 2A and 2B</figref>. Alternatively, a joined structure <b>17</b> of the interposer substrates <b>15</b> may be employed, as shown in <figref idref="DRAWINGS">FIG. 3</figref>.

0074A potting material <b>18</b> may be supplied to enclose the upper and/or lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>. As shown in <figref idref="DRAWINGS">FIG. 4A</figref>, the potting material <b>18</b> may simply be introduced into a space between the printed wiring substrate <b>11</b> and the lowest interposer substrate <b>15</b>. Alternatively, the potting material <b>18</b> may fill up an overall space between the printed wiring substrate <b>11</b> and the component <b>12</b> for completely enclosing the interposer substrate <b>15</b> as shown in <figref idref="DRAWINGS">FIG. 4B</figref>. An assembly of the component <b>19</b> and the interposer substrate <b>15</b>, filled with the potting material <b>18</b>, may previously be prepared, as shown in <figref idref="DRAWINGS">FIGS. 5A and 5B</figref>. Otherwise, a joined structure <b>20</b> of the interposer substrates <b>15</b>, filled with the potting material <b>18</b>, may be employed, as shown in <figref idref="DRAWINGS">FIG. 6</figref>.

0075<figref idref="DRAWINGS">FIG. 7</figref> illustrates an interposer or relay substrate <b>22</b> according to a first embodiment of the present invention. A plurality of conductive electrode pads <b>23</b> are arranged on the upper surface of the interposer substrate <b>22</b> in a grid array so as to correspond to respective conductive electrode pads on the component <b>12</b> to be mounted. As shown in <figref idref="DRAWINGS">FIG. 8</figref>, a plurality of conductive electrode pads <b>24</b> are also arranged on the lower surface of the interposer substrate <b>22</b> so as to correspond to the respective electrode pads <b>23</b> on the upper surface. The electrode pads <b>24</b> on the lower surface also correspond to respective conductive electrode pads on the printed wiring substrate <b>11</b>. Vias <b>25</b> serve to establish electric connections between the electrode pads <b>23</b> on the upper surface and the corresponding electrode pads <b>24</b> on the lower surface.

0076The interposer substrate <b>22</b> is made of a porous material sheet or film defining tiny pores <b>26</b>. The respective pores <b>26</b> are designed to penetrate through the interposer substrate <b>22</b> in the direction of its thickness. The electrode pads <b>23</b> on the upper surface suffer from a relatively smaller displacement or shift P<b>1</b> along the upper surface of the interposer substrate <b>22</b> when an expansion is induced in the component <b>12</b>. On the other hand, the electrode pads <b>24</b> on the lower surface suffer from a relatively larger displacement or shift P<b>2</b> along the lower surface of the interposer substrate <b>22</b> when an expansion is induced in the printed wiring substrate <b>11</b>. A shearing stress is thus induced between the electrode pads <b>23</b>, <b>24</b> in the interposer substrate <b>22</b>. The pores <b>26</b> are allowed to deform absorbing the shearing stress in the porous material sheet. Accordingly, less shearing stress is induced in the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>bonded on the respective electrode pads <b>23</b>, <b>24</b>. Moreover, since the tiny pores <b>26</b> can selectively be employed to establish the vias <b>25</b>, it is not necessary to bore the interposer substrate <b>22</b> solely for the vias <b>25</b>. Production process of the interposer substrate <b>22</b> can be facilitated. Here, the porous material sheet is preferably made of a high elastic material. The porous material sheet can be formed by utilizing a foamed agent introduced in a resin material in molding.

0077<figref idref="DRAWINGS">FIGS. 9 and 10</figref> illustrate an interposer or relay substrate <b>28</b> according to a second embodiment of the present invention. A plurality of conductive electrode pads <b>29</b>, <b>30</b> are likewise arranged on the upper and lower surfaces of the interposer substrate <b>28</b>, respectively, in the same manner as the aforementioned first embodiment. Vias <b>31</b> serve to establish electric connections between the electrode pads <b>29</b> on the upper surface and the corresponding electrode pads <b>30</b> on the lower surface.

0078The interposer substrate <b>28</b> is designed to define slits <b>32</b> penetrating through the interposer substrate <b>28</b> in the direction of its thickness. The respective slits <b>32</b> are located between the adjacent ones of the electrode pads <b>29</b>, <b>30</b> arranged on the identical level. When the electrode pads <b>29</b> suffer from a relatively smaller displacement or shift P<b>1</b> while the electrode pads <b>30</b> suffer from a relatively larger displacement or shift P<b>2</b> in the aforementioned manner, the respective slits <b>32</b> are allowed to deform so as to absorb a shearing stress induced between the electrode pads <b>29</b>, <b>30</b> in the interposer substrate <b>28</b>. Accordingly, less shearing stress is induced in the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>bonded on the respective electrode pads <b>29</b>, <b>30</b>. In particular, the size of the slits <b>32</b> at the central area of the interposer substrate <b>28</b> is preferably set smaller than that of the slits <b>32</b> located at the area remoter from the central area, as shown in <figref idref="DRAWINGS">FIG. 11</figref>, since the planar displacement or shift P<b>1</b>, P<b>2</b> gets larger at a location remoter from the center of the interposer substrate <b>28</b> upon a thermal expansion of the printed wiring substrate <b>11</b> and the component <b>12</b>.

0079<figref idref="DRAWINGS">FIG. 12</figref> illustrates an interposer or relay substrate <b>34</b> according to a third embodiment of the present invention. In this embodiment, the interposer substrate <b>34</b> is shaped to have undulation in the cross-section. The interposer substrate <b>34</b> is allowed to absorb a shearing stress caused by the planar displacement or shift P<b>1</b>, P<b>2</b> without utilizing the aforementioned pores <b>26</b> and the slits <b>32</b>. Accordingly, less shearing stress is induced in the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>bonded on the upper and lower surfaces of the interposer substrate <b>34</b>.

0080<figref idref="DRAWINGS">FIG. 13</figref> illustrates an interposer or relay substrate <b>36</b> according to a fourth embodiment of the present invention. In this embodiment, the interposer substrate <b>36</b> includes a multilayered films comprising a first film <b>37</b> and a second film <b>38</b> superposed on the first film <b>37</b>. The first film <b>37</b> is made of an inorganic material such as a ceramic material in the same manner as the ceramic substrate <b>14</b> of the component <b>12</b>. The second film <b>38</b> is made of an organic material such as a glass epoxy or polyimide resin in the same manner as the printed wiring substrate <b>11</b>. An adhesive layer <b>39</b> made of an adhesive, for example, is interposed between the first and second films <b>37</b>, <b>38</b> so as to adhere the first and second films <b>37</b>, <b>38</b> to each other.

0081Assume that the ceramic substrate <b>14</b> and the printed wiring substrate <b>11</b> suffer from a thermal expansion, respectively. As shown in <figref idref="DRAWINGS">FIG. 14</figref>, the first film <b>37</b> is supposed to expand in unison with the expansion of the ceramic substrate <b>14</b> of the component <b>12</b> while the second film <b>38</b> is supposed to expand in unison with the expansion of the printed wiring substrate <b>11</b> in this case. The adhesive layer <b>39</b> serves to allow a sliding movement between the first and second films <b>37</b>, <b>38</b>. A natural thermal expansion can be accepted in the first and second films <b>37</b>, <b>38</b>, respectively, irrespective of the difference in the thermal expansion coefficients. No shearing stress is induced in the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>. The stacked solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>with the interposer substrate <b>36</b> interposed therebetween can absorb a remarkable shearing stress The levels of the stacked solder bumps <b>13</b> can accordingly be reduced. In this embodiment, vias <b>40</b> are preferably made of an elastic and electrically conductive material, since the aforementioned sliding movement cannot be achieved between the first and second films <b>37</b>, <b>38</b> without deformation of the vias <b>40</b>.

0082<figref idref="DRAWINGS">FIG. 15</figref> illustrates a multileveled printed circuit board unit <b>42</b> employing an interposer or relay substrate according to a fifth embodiment of the present invention. The printed circuit board unit <b>42</b> includes solder bumps <b>43</b><i>a</i>, <b>43</b><i>b</i>, <b>43</b><i>c </i>of different sizes or diameters stacked one another between the component <b>12</b> and the printed wiring substrate <b>11</b>. The interposer substrate <b>15</b> is interposed between the respective pairs of upper and lower solder bumps <b>43</b><i>a</i>, <b>43</b><i>b</i>, <b>43</b><i>c</i>. The solder bumps <b>43</b><i>a</i>, <b>43</b><i>b</i>, <b>43</b><i>c </i>on the identical level may have the same diameter, respectively. In general, the larger the size or diameter of gets, the larger the strength of the solder bump can be obtained. Even when different strengths are required in the separate levels of the stacked solder bumps <b>43</b>, it is possible to minimize the size or diameter of the solder bumps <b>43</b><i>a</i>, <b>43</b><i>b</i>, <b>43</b><i>c</i>. The overall height of the stacked solder bumps <b>43</b> can thus be reduced, keeping a required strength. Like reference numerals are attached to the structures accomplishing the function and effect identical to that of the structure included in the aforementioned embodiments. Detailed descriptions have been omitted.

0083<figref idref="DRAWINGS">FIG. 16</figref> illustrates a multileveled printed circuit board unit <b>45</b> employing an interposer or relay substrate according to a sixth embodiment of the present invention. In this embodiment, solder bumps <b>46</b><i>a</i>, <b>46</b><i>b</i>, <b>46</b><i>c </i>are made of different materials, so that diffusion bonding of various strengths can be obtained between the solder bumps <b>46</b><i>a</i>, <b>46</b><i>b</i>, <b>46</b><i>c </i>and the interposer substrates <b>15</b> as well as the other substrates, respectively. Even when the solder bumps <b>46</b><i>a</i>, <b>46</b><i>b</i>, <b>46</b><i>c </i>are designed to have the same size or diameter, it is possible to separately set the strength of the solder bumps <b>46</b><i>a</i>, <b>46</b><i>b</i>, <b>46</b><i>c </i>of the respective levels. In general, a material of the solder bump is selected from Pb—Sn materials in a mounted component such as a BGA device. On the other hand, a leadless cream solder is often printed on a printed wiring substrate. If such a BGA device is directly mounted on the printed wiring substrate, the Pb—Sn solder may be mixed with the leadless solder. Such mixture of the Pb—Sn material and the leadless solder sometimes serves to reduce a bonding strength. If the interposer substrate <b>15</b> is interposed between the component <b>12</b> and the printed wiring substrate <b>11</b>, it is possible to prevent the Pb—Sn solder bumps <b>46</b><i>a </i>on the component <b>12</b> from being mixed with the leadless solder bumps <b>46</b><i>b</i>, <b>46</b><i>c </i>on the interposer substrate <b>15</b> and the printed wiring substrate <b>11</b>. Moreover, employment of the interposer substrate <b>15</b> allows the treatment of the cream solder having a relatively lower melting point to be conducted separately from the treatment of the solder bumps <b>46</b><i>a </i>having a relatively higher melting point. Specifically, after the component <b>12</b> has been mounted on the interposer substrate <b>15</b> in the atmosphere of a higher temperature, a reflowing process can be effected to mount the interposer substrate <b>15</b> on the printed wiring board <b>11</b> at a lower temperature.

0084<figref idref="DRAWINGS">FIGS. 17A and 17B</figref> illustrate a multileveled printed circuit board unit <b>48</b> employing an interposer or relay substrate <b>50</b> according to a seventh embodiment of the present invention. A conductive wiring pattern is formed on the interposer substrate <b>50</b> so as to establish an electric connection at least between conductive or solder bumps <b>49</b><i>a</i>, <b>49</b><i>b </i>on the identical level in the printed circuit board unit <b>48</b>. As is apparent from <figref idref="DRAWINGS">FIG. 17A</figref>, a plurality of conductive electrode pads <b>51</b> are arranged on the upper surface of the interposer substrate <b>50</b> in a grid array. The conductive wiring pattern <b>52</b> is formed on the upper surface of the interposer substrate <b>50</b> so as to connect the electrode pad <b>51</b><i>a </i>corresponding to the solder bump <b>49</b><i>a </i>and the electrode pad <b>51</b><i>b </i>corresponding to the solder bump <b>49</b><i>b</i>. In this printed circuit board unit <b>48</b>, the conductive wiring pattern <b>52</b> on the interposer substrate <b>50</b> may serve to establish an alternative electric path for a disconnected wiring pattern on the printed wiring substrate <b>11</b> and/or the component <b>12</b>. Also, the conductive wiring pattern <b>52</b> may establish a modified electric path in place of a wiring pattern initially formed on the printed wiring substrate <b>11</b> and/or the component <b>12</b>. Like reference numerals are attached to the structures accomplishing the function and effect identical to that of the structure included in the aforementioned embodiments. Detailed descriptions have been omitted.

0085As shown in <figref idref="DRAWINGS">FIGS. 18A and 18B</figref>, two or more components <b>12</b> may be mounted on the interposer substrate <b>50</b>. In such a printed circuit board unit <b>48</b>, the conductive wiring pattern <b>52</b> on the interposer substrate <b>50</b> may serve to establish an alternative electric path for a disconnected wiring pattern on the printed wiring substrate <b>11</b> so as to electrically connect the components <b>12</b> to each other. Otherwise, the conductive wiring pattern <b>52</b> may establish a modified electric path for a wiring pattern initially formed on the printed wiring substrate <b>11</b> so as to connect the components <b>12</b> to each other.

0086<figref idref="DRAWINGS">FIG. 19</figref> illustrates an interposer or relay substrate <b>54</b> according to an eighth embodiment of the present invention. A plurality of conductive electrode pads <b>55</b> are arranged on the upper surface of the interposer substrate <b>54</b> in a grid array in correspondence with electrode pads on the component <b>12</b>. Likewise, conductive pads <b>56</b> are arranged on the upper surface of the interposer substrate <b>54</b> at a periphery of an area receiving the conductive electrode pads <b>55</b> so as to receive a connecting wire. A conductive wiring pattern <b>57</b> is designed to establish an electric connection between the specific electrode pads <b>55</b> and the conductive pads <b>56</b> in a one-to-one correspondence.

0087As shown in <figref idref="DRAWINGS">FIGS. 20A and 20B</figref>, the connecting wire <b>58</b> can be employed to establish an electric connection between the components <b>12</b> mounted on the printed wiring substrate <b>11</b>. For example, the interposer substrate <b>48</b> shown in <figref idref="DRAWINGS">FIGS. 18A and 18B</figref> may be employed to likewise connect the components <b>12</b> to each other on the printed wiring substrate <b>11</b>. However, if the components <b>12</b> are spaced apart from each other on the printed wiring substrate <b>11</b>, the interposer substrate <b>48</b> should be made larger enough. On the other hand, the connecting wire <b>58</b> alone is simply utilized to connect the components <b>12</b> to each other without unnecessarily enlarging the size of the interposer substrate <b>48</b> in this embodiment. Moreover, since the conductive pads <b>56</b> are allowed to receive the connecting wire <b>58</b> at the periphery of the area receiving the solder bumps <b>13</b><i>a </i>on the interposer substrate <b>54</b>, it is possible to easily fix the connecting wire <b>58</b> to the target conductive pad <b>56</b> without disassembling the multileveled printed circuit board unit.

0088<figref idref="DRAWINGS">FIG. 21</figref> illustrates an interposer or relay substrate <b>60</b> according to a ninth embodiment of the present invention. A plurality of conductive electrode pads <b>61</b> are arranged on the upper surface of the interposer substrate <b>60</b> in a grid array in correspondence with respective electrode pads on the component <b>12</b>. Likewise, conductive pads <b>62</b> are arranged on the upper surface of the interposer substrate <b>60</b> at a periphery of an area receiving the conductive electrode pads <b>61</b> so as to receive a probe. A conductive wiring pattern <b>63</b> is designed to establish an electric connection between the specific electrode pads <b>61</b> and the conductive pads <b>62</b> in a one-to-one correspondence.

0089As shown in <figref idref="DRAWINGS">FIGS. 22A and 22B</figref>, it is possible to easily conduct an inspection for electric connection between the component <b>12</b> and the printed wiring substrate <b>11</b> by simply contacting the tip ends of inspection probes <b>65</b> with the target conductive pads <b>62</b>. The inspection may serve to reveal a disconnection of the wiring pattern formed on the printed wiring substrate <b>11</b>, a disconnection of the wiring pattern within the component <b>12</b>, and a disconnection at the respective solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>. Moreover, since the conductive pads <b>62</b> are allowed to receive the inspection probe <b>65</b> at the periphery of the area receiving the solder bumps <b>13</b><i>a </i>on the interposer substrate <b>60</b>, it is possible to easily contact the inspection probe <b>65</b> with the target conductive pad <b>62</b> without disassembling the multileveled printed circuit board unit.

0090In addition, the conductive pads <b>62</b> may be located on the interposer substrates <b>60</b><i>a</i>, <b>60</b><i>b </i>of various levels, as shown in <figref idref="DRAWINGS">FIGS. 23A and 23B</figref>. In this case, an upper interposer substrate <b>60</b><i>a </i>is preferably made smaller than a lower interposer substrate <b>60</b><i>b</i>. With this arrangement, the inspection probes <b>65</b>, <b>66</b> are always allowed to approach the conductive pads <b>62</b> in a vertical direction.

0091<figref idref="DRAWINGS">FIG. 24</figref> illustrates an interposer or relay substrate <b>67</b> according to a tenth embodiment of the present invention. A heat radiator <b>68</b> is attached to the interposer substrate <b>67</b>. The heat radiator <b>68</b> comprises cooling fins <b>69</b> located at the periphery of the area receiving the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>. When the electric circuit operates to generate heat in the interposer substrate <b>67</b>, heat radiation from the interposer substrate <b>67</b> can be promoted through the cooling fins <b>69</b>. The cooling fins <b>69</b> are preferably made of a high thermal conductivity material such as a metal.

0092As shown in <figref idref="DRAWINGS">FIG. 25</figref>, the heat radiator <b>68</b> may comprise a thermal conductive pattern <b>70</b> formed on the surface of the interposer substrate <b>67</b>. The thermal conductive pattern <b>70</b> may be shaped in a grid so as to be located off the conductive electrode pads <b>71</b>. The thermal conductive pattern <b>70</b> is preferably made of a high thermal conductivity material such as a metal. Additionally, the heat radiator <b>68</b> may comprise not only the thermal conductive pattern <b>70</b> but also the aforementioned cooling fins <b>69</b>. In this case, the cooling fins <b>69</b> are preferably connected to the thermal conductive pattern <b>70</b>.

0093<figref idref="DRAWINGS">FIG. 26</figref> illustrates a multileveled printed circuit board unit <b>73</b> employing an interposer or relay substrate according to an eleventh embodiment of the present invention. When the printed circuit board unit <b>73</b> is to be fabricated, the stacked solder bumps <b>13</b> are first prepared. The stacked solder bumps <b>13</b> are interposed between the printed wiring substrate <b>11</b> and the component <b>12</b>. In this case, the upper solder bumps <b>13</b><i>a </i>among the stacked solder bumps <b>13</b> may be formed on the component <b>12</b>, while the lower solder bumps <b>13</b><i>b </i>may be formed on the interposer substrate <b>74</b>. The interposer substrate <b>74</b> is also previously prepared. Standoff members <b>75</b> have been fixed on the interposer substrate <b>74</b>. The standoff members <b>75</b> are designed to stand on the upper and lower surfaces of the interposer substrate <b>74</b>. The thus prepared interposer substrate <b>74</b> and the component <b>12</b> are sequentially placed on the printed wiring substrate <b>11</b>. During a ref lowing process, the component <b>12</b> and the interposer substrate <b>74</b> are urged against the printed wiring substrate <b>11</b> by their own weight and an additional urging force <b>77</b>. The solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>are allowed to melt under a pressurized condition. The printed wiring substrate <b>11</b> is thereafter cooled down. The standoff members <b>75</b> serve to keep a predetermined space between the printed wiring substrate <b>11</b> and the component <b>12</b>, so that the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>can be prevented from excessively squashing in a pressurized condition. A pressure during a ref lowing process enables leveling the height of the final solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>, regulated by the height of the standoff members <b>75</b>, on the identical level even if an irregularity can be found in the height of the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>on the identical level before reflowing. The respective solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>reliably achieve a bonding between the component <b>12</b> and interposer substrate <b>74</b> as well as between the interposer substrate <b>74</b> and the printed wiring substrate <b>11</b>.

0094As shown in <figref idref="DRAWINGS">FIG. 27</figref>, the standoff member <b>75</b> may be a solder bump of a higher melting point located at corners of the area receiving the solder bumps <b>13</b><i>b</i>. The solder bump of a higher melting point is refrained from melting during the reflowing process of the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b</i>, so that the standoff members <b>75</b> is allowed to keep its shape and height during the reflowing. In place of the solder bump, the standoff member <b>75</b> may be a pin, as shown in <figref idref="DRAWINGS">FIG. 28</figref>. In addition, the standoff members <b>75</b> are not necessarily located outside the area receiving the solder bumps <b>13</b><i>b</i>. As shown in <figref idref="DRAWINGS">FIG. 29</figref>, the standoff member <b>75</b> can be embedded in a via connecting the upper and lower solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>to each other. Furthermore, the standoff member <b>75</b> may be formed as a protrusion integral to the conductive electrode pads, as shown in <figref idref="DRAWINGS">FIGS. 30 and 31</figref>.

0095<figref idref="DRAWINGS">FIG. 32</figref> illustrates a multileveled printed circuit board unit <b>80</b> employing an interposer or relay substrate according to a twelfth embodiment of the present invention. The printed circuit board unit <b>80</b> includes guide members <b>81</b> located on the interposer substrate <b>82</b> at a predetermined position for adjustment of a relative position between the printed wiring substrate <b>11</b> and the component <b>12</b>. The guide member <b>81</b> is received in a guide bore <b>83</b> defined in the component <b>12</b> and a guide bore <b>84</b> defined in the printed wiring substrate <b>11</b>. The guide members <b>81</b> serve to prevent a displacement or slippage of the component <b>12</b> relative to the printed wiring substrate <b>11</b> even when the solder bumps <b>13</b><i>a</i>, <b>13</b><i>b </i>are caused to melt during a reflowing process. The solder bumps <b>13</b><i>a </i>can reliably be bonded to the corresponding electrode pads on the interposer substrate <b>82</b>, respectively, while the solder bumps <b>13</b><i>b </i>can reliably be bonded to the corresponding electrode pads on the printed wiring substrate <b>11</b>.

0096As shown in <figref idref="DRAWINGS">FIG. 33</figref>, the guide member <b>81</b> may be allowed to protrude from one of the upper and lower surfaces of the interposer substrate <b>82</b>. Alternatively, the guide member <b>81</b> may protrude from both the upper and lower surfaces of the interposer substrate <b>82</b>, as shown in <figref idref="DRAWINGS">FIG. 34</figref>. When a plurality of interposer substrates <b>82</b> are interposed between the printed wiring substrate <b>11</b> and the component <b>12</b>, the interposer substrate <b>82</b> solely defining the guide bores <b>85</b> can be employed, as shown in <figref idref="DRAWINGS">FIG. 35</figref>. Otherwise, the guide members <b>81</b> and the guide bores <b>85</b> may be disposed in every interposer substrate <b>82</b>, as shown in <figref idref="DRAWINGS">FIG. 36</figref>.