Distributed block coding (DBC)

CLAIM OF PRIORITY

0001This application is a divisional of application Ser. No. 11/510,171, filed Aug. 25, 2006, now U.S. Pat. No. 7,958,426, which application is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

0002The present invention generally relates to coding digital data and to communication systems for digital data transmission and reception or for digital data storage and retrieval. Although not limited to this application, the present invention is useful in connection with forward error correction (FEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors.

BACKGROUND OF THE INVENTION

0003Error correcting codes are widely used in communications systems. A good reference book for coding in connection with communications systems is R. D. Gitlin, J. F. Hayes and S. B. Weinstein, “<i>Data Communication Principles”, </i>1992 Plenum Press, New York, ISBN 0-306-43777-5 which is incorporated herein by reference. Chapter 3 gives a good description of error correcting and detecting codes and provides references to many other good sources of information in the field. In the field of communications, source information is transmitted or stored into an imperfect medium. A receiver recovers the source information which may be corrupted by errors due to the imperfect medium. Error correcting codes have been developed that add redundancy to transmitted information, enabling correction of errors in the remote receiver.

0004Block codes are error correcting codes that operate on a fixed size block of digital information. Examples of block codes are Hamming codes and Bose-Chaudhuri-Hocquenghem (BCH) codes. Digital information is transmitted or stored in units or symbols which may contain single digital data bits of information or multiple digital data bits of information. Block codes combine a fixed number of source data symbols and a fixed number of redundant symbols into a coded block containing a fixed number of coded symbols. The coded block of coded symbols is referred to as a “codeword” and the redundant symbols are referred to as “parity symbols”. A block encoder is a device that accepts a fixed number of source data symbols, computes redundant parity symbols relating to the source data symbols and outputs a coded block, or codeword, containing the source data symbols and redundant parity symbols.

0005Various coding algorithms are available or may be developed for computing the redundant parity symbols. Coding algorithms can be differentiated by the ratio of redundant symbols to source symbols, complexity of encoding, complexity of decoding, number of errors that can be corrected, type of errors that can be corrected, etc. A block decoder is a device that receives the coded block, or codeword, corrects errors in the source symbols, and outputs the corrected source symbols, while discarding the redundant parity symbols.

0006There is another type of error correcting code known as a “convolutional” error correcting code. The convolutional code operates on a sequence of source symbols to generate an output sequence with additional redundant information. A convolutional encoder is a sequential circuit with memory of previous symbols. Each output symbol is related to all previous symbols, unlike the block encoder, which generates coded blocks, or codewords, that are completely independent of previous blocks or codewords.

0007Forward error correction (FEC) systems are used in many data communication and storage systems today. These systems “forward” redundant information to the remote receiver to facilitate “error correction.” Systematic codes typically transmit unmodified user source data directly in a block with appended redundant parity information at the end of the block. The encoded block of source data and parity information is commonly known as a “codeword.” A decoder in the remote receiver utilizes the redundant information to correct errors that may have occurred during transmission.

0008FEC codes are selected for properties that benefit specific applications. Hamming codes and Bose-Chaudhuri-Hocquenghem (BCH) codes are two of many examples. The popular Reed-Solomon (RS) codes are a subclass of BCH codes. Many FEC systems implement concatenated codes, such as a RS block code concatenated with a convolutional trellis code. Block codes, such as the Hamming, BCH, and RS codes, can correct multiple errors that may occur in a block of data. Most codes are designed to correct random errors, although some codes are designed to correct burst errors that occur on sequential symbols. Burst error events may cause a large number of errors in a single block. In burst error environments, the FEC system may include an interleaved block code concatenated with a distributed trellis encoder. The FEC block codes encode k source data symbols into a fixed block or codeword of n symbols containing p redundant parity check symbols where p=n−k. RS codes can correct up to p/2 random symbol errors in a block of n symbols. A burst of errors in excess of the error correcting capacity of the code (p/2) will cause the FEC decoder to fail, resulting in errors in the decoded block. Interleaving methods are used to interleave the blocks dispersing the symbols of each encoded block over a large number of blocks. The interleaved blocks are transmitted into or stored in a communication medium susceptible to burst error events. A deinterleaver in the receiver reassembles the encoded blocks, while beneficially dispersing the burst errors among many blocks. Each block then has fewer errors that can be reliably corrected by the code.

0009Interleavers, such as a convolutional interleaver, are used in the art to disperse burst errors. A convolutional interleaver may pass coded symbols through B sections or branches of increasing delay. Each section has delay increasing in steps of M symbols. The first section has a delay of zero and the last section has a delay of M*(B−1) symbols. Thus, adjacent symbols from any codeword are separated by B symbol periods at the interleaver output. This convolutional interleaver can protect against error burst durations of B symbol periods. For a block or codeword size of n symbols and M*B greater than or equal to n, a burst duration less than M*B symbol periods will result in no more than M errors in the interleaved block. The deinterleaver operates in the reverse order passing the first received symbol through a delay section of M*(B−1) symbols and the next received symbols through sections having M fewer delayed symbols per section. The final received symbol is passed through a section with no delay. The total delay of combined interleaver and deinterleaver is then M*(B−1) symbol periods for all symbols.

0010Conventional interleaving methods have undesirable side effects. Conventional interleavers delay the data prior to transmission and scramble the original order of the source data. The reordered source symbols yield unrecognizable data at remote receivers unless they are deinterleaved. A deinterleaver is required in the receiver to reassemble the data in the correct order for decoding. The deinterleaver adds undesirable additional delay and typically must be synchronized with the remote interleaver. The codeword symbols are spread out in the channel over M*B*(B−1) symbol periods. The final decoding of the full codeword is delayed by M*B*(B−1)+n−1 symbol periods. The conventional interleavers and deinterleavers add complexity to equipment and usually require significant additional memory.

0011There is a need in the industry for better systems and methods for correcting burst errors. The inventor has discovered a new coding methodology that addresses, among other things, the correction of burst errors.

SUMMARY OF INVENTION

0012The present invention provides various embodiments for implementing distributed block coding (DBC). This new DBC can be used for, among other things, distributed forward error correction (DFEC) of source data corrupted by burst errors or distributed parity backup of source data in storage systems where the source data may be corrupted by burst errors.

0013One embodiment, among others, for implementing DBC is a distributed block encoder (DBE). The DBE encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols.

0014More specifically, each sequential data symbol is processed by a different block encoder. For a set of B block encoders, B symbols are processed and transmitted before the next symbol enters the first block encoder. In this way, each symbol of a coded block, or codeword, is separated from other symbols in the codeword by B symbol periods. This protects each codeword from error bursts of B symbol periods in duration. This method beneficially transmits the original source data with no delay and in its original temporal sequence. This also beneficially reduces memory requirements in the DBE which does not store the source data. Prior art interleaved systems must store both source data and parity information in the transmitter to facilitate interleaving.

0015Another embodiment, among others, for implementing DBC is a distributed block decoder (DBD). The DBD receives the source data and interleaved parity codewords from the DBE (or the DRBE described later) and decodes the source data and interleaved parity codewords with a plurality of sequential block decoders to produce sequential decoded error-corrected source data symbols. Source data can be decoded with no delay and/or error corrected with less delay than conventional interleaved systems and with lower complexity.

0016Another embodiment, among others, for implementing DBC is a distributed register block encoder (DRBE), which is essentially a type of DBE. The DRBE can be implemented in a single block encoder by using a distributed register arrangement. The single block encoder utilizes multiple registers that can be selected by indirect addressing with very little additional complexity.

0017Another embodiment, among others, for implementing DBC is a distributed register block decoder (DRBD), which is essentially a type of DBD. The DRBD can be implemented in a single block decoder by using a distributed register arrangement. The DRBD receives the source data and interleaved parity codewords from either the DBE or the DRBE. A plurality of registers residing within or associated with the single block decoder stores the source data and interleaved parity codewords, respectively. Furthermore, the source data symbols are produced by sequentially communicating the source data and interleaved parity codewords from the registers to the single block decoder. Source data can be decoded with no delay and/or error corrected with less delay than conventional interleaved systems and with lower complexity.

0018Another embodiment, among others, is a communication system that includes receivers with differing FEC capabilities and that is made possible by the DBE or DRBE in a transmitter. The system comprises a transmitter having a DBE or DRBE. The transmitter transmits a data stream having original source data and interleaved parity codewords to a medium on the same or separate channels. A first receiver without a DBD or DRBD can receive the data stream from the medium and can identify source data in the data stream. A second receiver with the DBD or the DRBD can receive the data stream from the medium and can identify and/or correct the source data in the data stream with the DBD or DRBD. The corrected source data will correspond more accurately to the original source data as compared to the uncorrected source data, because the corrected source data has been reconstructed from interleaved parity codewords whereas the uncorrected source data is corrupted by the medium.

0019Other embodiments, systems, methods, features, and/or advantages associated with the present invention will become apparent to one of skill in the art upon examination of the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

0020The present invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Like reference numerals designate corresponding parts throughout the several views.

0021<figref idref="DRAWINGS">FIG. 1</figref> is a block diagram of an example implementation of a prior art conventional interleaved coding system.

0022<figref idref="DRAWINGS">FIG. 2</figref> is a block diagram of a prior art convolutional interleaver of <figref idref="DRAWINGS">FIG. 1</figref>.

0023<figref idref="DRAWINGS">FIG. 3</figref> is a table illustrating relative interleaver timing delays associated with the prior art convolutional interleaver of <figref idref="DRAWINGS">FIG. 2</figref> and the distributed block encoder (DBE) of <figref idref="DRAWINGS">FIG. 4</figref>.

0024<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram of an example implementation of a distributed block encoder (DBE) in accordance with the present invention.

0025<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram of an example implementation of a distributed block decoder (DBD) in accordance with the present invention that can decode the interleaved parity codewords produced by the DBE of <figref idref="DRAWINGS">FIG. 4</figref> (or the DRBE of <figref idref="DRAWINGS">FIG. 6</figref>).

0026<figref idref="DRAWINGS">FIG. 6</figref> is a block diagram of an example implementation of a distributed register block encoder (DRBE) in accordance with the present invention that uses registers associated with a single block encoder to implement the DBE of <figref idref="DRAWINGS">FIG. 4</figref>.

0027<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram of an example implementation of (a) a distributed register block decoder (DRBD) in accordance with the present invention that uses registers associated with a single block decoder and that can decode the interleaved parity codewords produced by the DBE of <figref idref="DRAWINGS">FIG. 4</figref> or the DRBE of <figref idref="DRAWINGS">FIG. 6</figref> and (b) a data communication system in accordance with the present invention wherein a first receiver without a DRBD receives the data stream from the medium and identifies the source data and a second receiver with the DRBD receives the data stream from the medium and identifies the source data with the DRBD.

0028<figref idref="DRAWINGS">FIG. 8</figref> is a block diagram of another example implementation of a DRBD, which uses a dual set of registers.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

0029Many forward error correction (FEC) systems implement concatenated codes, such as a RS block code concatenated with a trellis code. In burst error environments, the FEC system may include an interleaved RS block code concatenated with a distributed trellis encoder, as is shown in prior art interleaved coding system of <figref idref="DRAWINGS">FIG. 1</figref>. <figref idref="DRAWINGS">FIG. 1</figref> illustrates one example of a prior art interleaved coding system with functions that are common to most FEC systems and relevant to the new distributed block encoder (DBE). Such a system can be used for the transmission or storage of digital data.

0030Referring to <figref idref="DRAWINGS">FIG. 1</figref>, data source <b>101</b> generates digital source data into optional randomizer <b>102</b>. Data is randomized in most data transmission systems to assure data transitions and avoid bias that may color the transmitted signal spectrum or disrupt automatic equipment such as adaptive equalizers. Source data from the randomizer <b>102</b> is input to the block encoder <b>104</b>.

0031Block encoder <b>104</b> could be any type of FEC encoder, such as a Hamming, BCH, or RS encoder. A common type of block encoder implements the RS code. Block encoder <b>104</b> encodes k source data symbols into a fixed block or codeword of n symbols containing p redundant parity check symbols where p=n−k.

0032The codeword, or block, of n symbols is output from block encoder <b>104</b> into optional convolutional interleaver <b>200</b>. Interleaver <b>200</b> can be any known interleaver. A common type of interleaver is the convolutional interleaver. The operation of optional convolutional interleaver <b>200</b> will be described later.

0033The output of optional interleaver <b>200</b> is coupled to an optional trellis encoder <b>106</b>. Trellis encoding is a coded modulation format used in many data communications systems. Trellis encoding as used in this document may encompass other coded modulation formats, such as turbo coding.

0034Modulator <b>107</b> conditions the signal for transmission into the medium <b>120</b>, which can be a propagation medium, where data is communicated on a signal that is propagated, or a storage medium, where data is stored. The operation of modulator <b>107</b> depends on specific applications.

0035The output of modulator <b>107</b> is coupled by signal path <b>108</b> into the medium <b>120</b>. The medium <b>120</b> can be a propagation medium or a storage medium.

0036The output of medium <b>120</b> is coupled by signal path <b>158</b> into the demodulator <b>157</b>. The demodulator <b>157</b> demodulates the signal from signal path <b>158</b> to recover the coded symbol stream that was transmitted by the remote FEC system <b>100</b>. The demodulated symbol stream may contain single errors or bursts of multiple errors due to imperfections or disturbances in the medium <b>120</b>.

0037The output of demodulator <b>157</b> is a recovered baseband signal that is processed by optional trellis decoder <b>156</b>. Optional trellis decoder <b>156</b> may correct some errors in the recovered baseband signal. Optional trellis decoder <b>156</b> is not required for uncoded modulation formats.

0038The output of optional trellis decoder <b>156</b> is deinterleaved by optional deinterleaver <b>250</b> as will be described later. Burst errors from the imperfect medium will be dispersed across multiple codewords by the deinterleaver <b>250</b>, resulting in fewer random errors in the deinterleaved codewords output from the deinterleaver <b>250</b>. Errors in the deinterleaved codewords can be corrected by the RS decoder <b>154</b>, depending upon the error correction capability of the FEC code. The decoder <b>154</b> can be any type of FEC block decoder, but must match the FEC encoder <b>104</b> in the remote transmitter. Examples of such FEC decoders include Hamming decoders or BCH decoders, such as the popular RS decoders.

0039The error corrected output of decoder <b>154</b> is coupled to optional derandomizer <b>152</b>. Optional derandomizer <b>152</b> is required if the remote FEC system <b>100</b> utilized an optional randomizer <b>102</b>. Derandomizer <b>152</b> restores the original source data that was generated by data source <b>101</b>. The restored error corrected source data is coupled to the final destination data terminal <b>151</b>.

0000Prior Art Convolutional Interleaver

0040Interleavers, such as the prior art convolutional interleaver shown in <figref idref="DRAWINGS">FIG. 2</figref>, are used to disperse burst errors. The convolutional interleaver <b>200</b> passes coded symbols through B sections of increasing delay. Switch <b>202</b> passes the symbols to each section and switch <b>203</b> extracts a delayed symbol from the same section for output. Each section has delay increasing in steps of M symbols. The first section <b>201</b> has a delay of zero and the last section <b>206</b> has a delay of (B−1)*M symbols. Switch <b>202</b> and switch <b>203</b> pass one symbol through each of the B sections then repeat the process for the next B symbols. Thus, adjacent symbols from any codeword are separated by B symbol periods at the interleaver output. This convolutional interleaver can protect against error burst durations of B symbol periods. For a block or codeword size of n symbols and M*B greater than or equal to n, a burst duration less than M*B symbol periods will result in no more than M errors in the interleaved block.

0041The deinterleaver <b>250</b> operates in the reverse order. Switch <b>252</b> passes the received symbols to each section and switch <b>253</b> extracts a delayed symbol from the same section for output. Switch <b>252</b> passes the first received symbol through section <b>256</b> for a delay of (B−1)*M symbols and the next received symbols through sections having M fewer delayed symbols per section. The final received symbol is passed through section <b>251</b> with no delay. Switch <b>252</b> and switch <b>253</b> pass one symbol through each of the B sections, then repeat the process for the next B symbols. The total delay of combined interleaver and deinterleaver is then M*B*(B−1) symbol periods for all symbols.

0000Interleaver Symbol Timing

0042<figref idref="DRAWINGS">FIG. 3</figref> is a timing table illustrating undesirable effects of the convolutional interleaver of <figref idref="DRAWINGS">FIG. 2</figref>, such as the additional delay and the reordering of the source data. The codeword symbols are spread out in the channel over M*B*(B−1)+n−1 symbol periods. The final decoding of the full codeword is delayed by M*B*(B−1)+n−1 symbol periods. The example in <figref idref="DRAWINGS">FIG. 3</figref> uses codewords of n=6 coded symbols, B=3 interleaver sections, M=2 delay steps and p=3 parity symbols. Column <b>1</b> illustrates the input of packets of data symbols. Columns <b>2</b> and <b>3</b> illustrate the time sequence of data symbols coming in and coded symbols going out. Note that there are twice as many coded output symbols as raw input source symbols due to the added redundancy of 3 parity symbols. The output data rate is increased by a factor of 2 as computed by the ratio n/(n−p).

0043Columns <b>4</b> and <b>5</b> illustrate the sequence of codewords generated by the prior art coding system. Each codeword contains 3 data symbols and 3 parity symbols. Column <b>5</b> identifies the codewords sequentially as C<b>0</b>, C<b>1</b> . . . etc. Columns <b>6</b> and <b>7</b> illustrate the output of the prior art convolutional interleaver in the transmitter. The negative indices in columns <b>6</b> and <b>7</b> identify symbols that entered the convolutional interleaver prior to the relative reference time zero used in the table. The convolutional interleaver delay elements contain memory that retains symbols of previous codewords until the final symbol of the codeword exits the interleaver as identified in column <b>8</b>. Notice that symbols from codeword C<b>0</b> are separated by 3 or 4 output symbol periods. Thus, any burst error of 3 symbols in duration cannot impact more than 1 symbol of the codeword. However, the sequence of source data is dispersed significantly with source symbols D<b>0</b> and D<b>1</b> in column <b>6</b> separated by 7 symbol periods. The reordered source symbols yield unrecognizable data at remote receivers unless they are deinterleaved.

0044Column <b>8</b> identifies when the decoded symbols arrive at the output of the deinterleaver. Symbols cannot be decoded until all 6 symbols of each codeword are output from the deinterleaver. The 6^thsymbol of codeword C<b>0</b> arrives at the deinterleaver output after a delay of 17 symbol periods. The RS decoder can then recover and correct the first data symbols D<b>0</b>, D<b>1</b> and D<b>2</b>. The codeword is delayed by M*B*(B−1)+n−1 symbol periods.

0045Columns <b>9</b> and <b>10</b> illustrate the beneficial improvements to be realized by the new DBE. All data symbols in column <b>9</b> are output immediately in their original order: D<b>0</b>, D<b>1</b>, D<b>2</b> . . . etc. There is no memory of previous codewords in the DBE. All symbols from each codeword are separated by 3 symbol periods yielding protection for all burst errors of duration <b>3</b> symbol periods or less. Beneficially the output of the first codeword C<b>0</b> arrives after a delay of 15 symbol periods when the DBD can recover and correct the data symbols D<b>0</b>, D<b>3</b> and D<b>6</b> of the first codeword. Data symbol D<b>0</b> can be output immediately but the remaining data symbols are buffered until all three codewords have been received. The output of the third codeword C<b>2</b> arrives after a delay of 17 symbol periods. After 17 symbol periods all data symbols D<b>0</b> through D<b>8</b> can be recovered, corrected and output. This decoding of a complete block of distributed codewords is beneficial in packet communications and storage systems where packets of data are transmitted and may traverse the internet independently. In the prior art interleaver of column <b>8</b> the final data symbols D<b>6</b>, D<b>7</b> and D<b>8</b> of codeword C<b>2</b> arrive after a longer delay of 29 symbol periods.

0000Distributed Block Encoder (DBE)

0046<figref idref="DRAWINGS">FIG. 4</figref> is a block diagram of an example implementation of DBE <b>400</b> in accordance with the present invention. Such a system can be used in connection with the transmission or storage of digital data.

0047Data source <b>101</b> generates digital source data into optional randomizer <b>102</b>. Data is randomized in most data transmission systems to assure data transitions and avoid bias that may color the transmitted signal spectrum or disrupt automatic equipment such as adaptive equalizers. The randomizer <b>102</b> may be an encryption device to protect the privacy of the source data. The randomizer <b>102</b> may not be required in other applications, such as data storage systems. Source data from the randomizer <b>102</b> is input to the DBE <b>430</b> for distributed FEC (DFEC) encoding as will be described later.

0048The output of DBE <b>430</b> is coupled to an optional trellis encoder <b>106</b>. Trellis encoding is a coded modulation format used in many data communications systems. Trellis encoding as used in this document may encompass other coded modulation formats such as turbo coding. Trellis encoding may not be required in some digital data storage applications. The optional trellis encoder <b>106</b> may be a distributed trellis encoder as taught in my U.S. Pat. No. 4,677,625 titled “Distributed Trellis Encoder,” which is incorporated herein by reference. The output of optional trellis encoder <b>106</b> is a baseband signal that is coupled to modulator <b>107</b>.

0049Modulator <b>107</b> conditions the signal for transmission into the medium <b>120</b>. The operation of modulator <b>107</b> depends on specific applications. For wireless broadcast applications the modulator may utilize frequency modulation, phase modulation, quadrature amplitude modulation (QAM), vestigial sideband (VSB) modulation, pulse amplitude modulation (PAM), spread spectrum modulation, orthogonal frequency division modulation (OFDM), code division multiple access (CDMA) modulation or any other modulation format. For wired applications the modulator may utilize QAM, VSB modulation, PAM, discrete multitone (DMT) modulation, or any other modulation format. For storage in magnetic media the modulator may use PAM or other common magnetic media formats. The modulator can operate in the appropriate frequency range of the medium including for example acoustic sound pressure waves, radio frequency (RF), ultra high frequency (UHF), microwave, and optical frequencies.

0050The output of modulator <b>107</b> is coupled by signal path <b>108</b> into the medium <b>120</b>. Signal path <b>108</b> may be a wire(s) for wired applications, a radio frequency antenna for wireless applications, a fiber optic cable or lens for optical applications, a mechanical transducer for acoustic applications, a write device such as a magnetic head for magnetic storage applications, etc. The medium <b>120</b> may be free space for wireless applications and may contain additional equipment, such as repeaters, satellite relay, switching centers, internet routers, etc. The distributed FEC (DFEC) system will protect the source data as it propagates through or is stored in the medium <b>120</b>.

0051The DFEC is implemented in the transmitter by DBE <b>430</b>. The DBE <b>430</b> couples the source data on connection <b>431</b> to switch <b>432</b> and switch <b>435</b>. Switch <b>435</b> receives source data on connection <b>431</b> and operates initially to output the source data from DBE <b>430</b> directly to the optional trellis encoder <b>106</b> with no delay. This beneficially transmits the source data in its original order such that a remote receiver without a FEC system can recover the data. There is no requirement for synchronization of the source data in the remote receiver.

0052Source data on connection <b>431</b> is also routed to switch <b>432</b>. Switch <b>432</b> distributes the source data to two or more block encoders <b>440</b>. Each block encoder <b>440</b> implements a block encoding method, for example but not limited to, Hamming or Bose-Chaudhuri-Hocquenghem (BCH) encoding, The block encoders <b>440</b> can be different block encoders that perform different types of block encoding. In the preferred embodiment, the block encoders <b>440</b> are identical and implement Reed-Solomon (RS) encoding (a type of BCH encoding). The number B of block encoders <b>440</b> is dependent on the amount of interleaving that is desired. The block encoders <b>440</b> operate on source data symbols that may be single digital data bits or fields containing multiple data bits. A block encoder symbol is typically one byte or 8 bits of data. A burst error event duration of B symbol periods can be dispersed by using B block encoders. In the preferred embodiments, B is two or more. Switch <b>432</b> operates to pass the first symbol to block encoder <b>1</b> and the second symbol to block encoder <b>2</b>. Switch <b>432</b> distributes one symbol to all B block encoders. After B symbols have been distributed, the switch <b>432</b> repeats the sequence passing the next B symbols to the block encoders <b>440</b>.

0053The block encoders <b>440</b> will each encode k source data symbols into a block of n coded symbols while constructing p=n−k redundant parity symbols. In the preferred embodiments, k is one or more and n is two or more. After k*B source symbols have been encoded by DBE <b>430</b>, each block encoder <b>440</b> will have constructed one interleaved parity codeword register containing p symbols. Beneficially, the DBE <b>430</b> will have already transmitted the k*B source symbols without delay. Switch <b>435</b> will then select connection <b>434</b>, the output of switch <b>433</b> for transmission. Switch <b>433</b> will first transmit an interleaved parity codeword symbol from block encoder <b>1</b>, then from block encoder <b>2</b>. Switch <b>433</b> will transmit one interleaved parity codeword symbol from all block encoders <b>440</b>. After B interleaved parity codeword symbols have been transmitted, the switch <b>433</b> repeats the sequence transmitting the next B interleaved parity codeword symbols from all block encoders <b>440</b>. This process continues until all p interleaved parity codeword symbols have been transmitted from all B block encoders.

0054After p*B interleaved parity codeword symbols have been transmitted, the switch <b>435</b> again selects the source data on connection <b>431</b> for transmission and the block encoders <b>440</b> are reset to begin encoding the next blocks of data. The output data rate is increased by a factor of n/k over the source data rate to accommodate the FEC interleaved parity codeword symbols. While transmitting the interleaved parity codeword symbols, the source data can be gated or buffered.

0055In general, the prior art FEC systems generate interleaved codewords that include source symbols and parity symbols. In the example of <figref idref="DRAWINGS">FIG. 3</figref>, the prior art system generates a first 6 symbol codeword containing symbols D<b>0</b>, D<b>1</b>, D<b>2</b>, P<b>0</b>, P<b>1</b> and P<b>2</b>. These symbols are then interleaved prior to transmission. In contrast, the new DBE <b>430</b> generates a first codeword containing the symbols D<b>0</b>, D<b>3</b>, D<b>6</b>, P<b>0</b>, P<b>1</b> and P<b>2</b>. Thus, the DBE codeword source symbols are interleaved with respect to the code. In effect, as the DBE <b>430</b> alternates its output between source data symbols and interleaved parity codewords, the source symbols are transmitted in their original order and the parity symbols (encoded in the interleaved parity codewords) are interleaved with parity symbols from other codewords as shown in columns <b>9</b> and <b>10</b> of <figref idref="DRAWINGS">FIG. 3</figref>.

0056The DBE <b>430</b> has an optional mode of operation allowing the interleaved parity codewords to be transmitted in another packet or over another channel. The interleaved parity codewords on connection <b>434</b> can be routed to a second modulator for transmission. This allows remote receivers to recover the source data on the first channel without benefit of interleaved parity codewords. More capable receivers can recover the interleaved parity codewords on the second channel for error correction. The performance margin on the interleaved parity codeword channel can be different than that of the primary source data channel. Such a dual mode is a basic capability of modulation formats, such as orthogonal frequency division multiplexing (OFDM) and discrete multi-tone (DMT).

0057Switch <b>435</b> is not required if dual transmission paths are used. It is important to note that most block encoders <b>440</b> incorporate switching that passes the source data directly while encoding a block and subsequently passes the redundant parity symbols at the end of the block. In this configuration, switch <b>435</b> is not required because source data passes directly through each block encoder <b>440</b> to switch <b>433</b>, where it can be output from DBE <b>430</b> directly to optional trellis encoder <b>106</b>.

0058The DBE <b>430</b> offers protection against burst errors by permitting reconstruction of source data with little increase in complexity. The additional complexity includes switching logic for switch <b>432</b> and switch <b>433</b> and the additional memory of (B−1) registers for interleaved parity codewords.

0000Distributed Block Decoder (DBD)

0059<figref idref="DRAWINGS">FIG. 5</figref> is a block diagram of an example implementation of a distributed block decoder (DBD) system <b>500</b>. Such a system can be used for the reception or recovery of source data from the medium <b>120</b>.

0060The output of medium <b>120</b> is coupled by signal path <b>158</b> into the demodulator <b>157</b>. Signal path <b>158</b> may be a wire(s) for wired applications, a radio frequency antenna for wireless applications, a fiber optic cable or lens for optical applications, a mechanical transducer for acoustic applications, a read device, such as a magnetic head for magnetic storage applications, etc. The demodulator <b>157</b> demodulates the signal from signal path <b>158</b> to recover the coded symbol stream that was transmitted by a remote DBE <b>400</b>. The demodulated symbol stream may contain single errors or bursts of multiple errors due to imperfections in the medium <b>120</b>.

0061The output of demodulator <b>157</b> is a recovered baseband signal that is processed by optional trellis decoder <b>156</b>. Optional trellis decoder <b>156</b> may correct some errors in the recovered baseband signal. The optional trellis decoder <b>156</b> may be a distributed trellis decoder as taught in my U.S. Pat. No. 4,677,625 titled “Distributed Trellis Encoder,” which is incorporated herein by reference. Optional trellis decoder <b>156</b> is not required for uncoded modulation formats. The output of optional trellis decoder <b>156</b> is processed by distributed block decoder DBD <b>530</b> to correct errors, as will be described later.

0062The error corrected output of DBD <b>530</b> is coupled to optional derandomizer <b>152</b>. Optional derandomizer <b>152</b> is required if the remote DBE <b>400</b> utilized an optional randomizer <b>102</b>. If the remote DBE <b>400</b> randomizer <b>102</b> was an encryption device then the derandomizer <b>152</b> is a decryption device. Note that synchronization of a decryption device can be beneficially expedited because the source data has not been interleaved and can be used immediately without time consuming deinterleaving and error correction. Derandomizer <b>152</b> restores the original source data that was generated by data source <b>101</b>. The restored error corrected source data is coupled to the final destination data terminal <b>151</b>.

0063The DFEC is implemented in the receiver by DBD <b>530</b>. The DBD <b>530</b> couples the uncorrected data on connection <b>531</b> to switch <b>532</b> and switch <b>535</b>. These switches are operated to distribute the incoming uncorrected symbols. The first k*B uncorrected symbols are the original source data. The next p*B symbols are the interleaved parity codeword symbols that were generated by the remote DBE <b>430</b> to facilitate FEC. Switch <b>535</b> will be positioned to discard the interleaved parity codeword symbols and can output either the incoming uncorrected symbols from connection <b>531</b> or the corrected symbols from connection <b>534</b>.

0064Switch <b>535</b> receives uncorrected data on connection <b>531</b> and operates initially to output the uncorrected source data from DBD <b>530</b> directly to the optional derandomizer <b>152</b> with no delay. This beneficially recovers the uncorrected source data in its original order with no delay. Certain types of data, such as but not limited to, audio, video, and image data, contain redundancy that may be sufficient to convey information even in a high error rate environment. Data fields containing synchronization, address, routing, or similar information may be preferentially accessed immediately without the benefit of error correction to accelerate synchronization and to setup initial routing instructions.

0065Thus, various embodiments are possible. For example, in one embodiment, the source data symbols can be processed (used in some way) and then later updated with the decoded source data symbols (e.g., updating or refreshing an image on a screen). As another example embodiment, a determination can be made in the DBD <b>530</b> as to whether the source data symbols are corrupted and then a selection can be made in the DBD <b>530</b> as to whether to replace the source data symbols that are corrupted with the decoded and error corrected source data symbols.

0066Recovery of error corrected data requires a significant delay in the DBD <b>530</b>. Each block decoder <b>540</b> receives a complete codeword of n symbols before errors can be corrected. The n-symbol codeword contains the original k source symbols and p=n−k interleaved parity codeword symbols, any of which can be in error. After receiving the n-symbol codeword, the block decoders <b>540</b> can correct typically p/2 symbol errors in the n-symbol codeword. The output of the block decoders <b>540</b> is the original k error corrected source symbols. Block decoders <b>540</b> can be any type of FEC decoders, such as RS decoder <b>154</b>, but generally match the block encoders <b>440</b> in the remote DBE <b>430</b>. Although clearly not limited to this implementation, in the preferred embodiments, the block decoders <b>540</b> are all RS block decoders.

0067Uncorrected data on connection <b>531</b> is routed to switch <b>532</b> for error correction. Switch <b>532</b> distributes the uncorrected data to multiple block decoders <b>540</b>. The number B of block decoders <b>540</b> is dependent on the amount of interleaving that is desired and matches the number of block encoders <b>440</b> in the remote DBE <b>430</b>. The block decoders <b>540</b> operate on uncorrected data symbols that may be single digital data bits or fields containing multiple data bits. A block decoder symbol is typically one byte, or 8 bits, of data. A burst error event duration of B symbol periods can be dispersed by using B block decoders. Switch <b>532</b> operates to pass the first symbol to block decoder <b>1</b> and the second symbol to block decoder <b>2</b>. Switch <b>532</b> distributes one symbol to all B block decoders. After B symbols have been distributed the switch <b>532</b> repeats the sequence passing the next B symbols to the block decoders. This process will repeat until n uncorrected symbols have been distributed to every block decoder <b>540</b>. Note that a burst error of duration B symbols will result in only one symbol error into each block decoder <b>540</b>. This significantly improves the error correction performance of the system.

0068The block decoders <b>540</b> will each receive a full block or codeword of n uncorrected symbols including k uncorrected source symbols and p=n−k interleaved parity codeword symbols. The block decoders <b>540</b> will correct up to p/2 errors in the k source symbols using the p interleaved parity codeword symbols which are subsequently discarded. After n*B uncorrected symbols have been decoded by DBD <b>530</b> each block decoder <b>540</b> will have decoded one block of k corrected source symbols from n uncorrected symbols. Switch <b>535</b> will then select connection <b>534</b>, the output of switch <b>533</b> for output. Switch <b>533</b> will first output a corrected source symbol from block decoder <b>1</b>, then from block decoder <b>2</b>. Switch <b>533</b> will output one corrected source symbol from all block decoders <b>540</b>. After B corrected source symbols have been output the switch <b>533</b> repeats the sequence transmitting the next B corrected source symbols from all block decoders <b>540</b>. This process continues until all k corrected source symbols have been transmitted from all B block decoders. A total of k*B corrected source symbols are output and the p*B interleaved parity codeword symbols are discarded.

0069After k*B corrected source symbols have been output, the block decoders <b>540</b> are reset to begin decoding the next blocks of data. The output data rate is decreased by a factor of k/n below the uncorrected data rate as the redundant FEC interleaved parity codeword symbols are discarded. While collecting the next block of n*B uncorrected symbols, the switch <b>535</b> can be positioned to output no symbols or to output uncorrected source symbols from connection <b>531</b>.

0070The DBD <b>530</b> has an optional mode of operation allowing the interleaved parity codeword symbols to be received in another channel from a second demodulator. This allows remote receivers to recover the source data on the first channel without benefit of FEC. More capable receivers can recover the interleaved parity codeword symbols on the second channel for error correction. Such a dual mode is a basic capability of modulation formats, such as OFDM and DMT. Total throughput delay is beneficially reduced by utilizing multiple channels.

0071It is important to note that most block decoders <b>540</b> incorporate switching and buffers that pass the corrected source symbols directly out, while decoding the next block of uncorrected symbols. In this configuration, switch <b>535</b> is not required because data passes directly through each block decoder <b>540</b> to switch <b>533</b>, where it can be output from DBD <b>530</b> directly to optional derandomizer <b>152</b>. Uncorrected symbols are available without delay on connection <b>531</b> for use in applications that do not require error correction.

0072The DBD <b>530</b> offers protection against burst errors with little increase in complexity. The additional complexity includes switching logic for switch <b>532</b> and switch <b>533</b> and the additional memory of (B−1) registers to retain each n symbol uncorrected codeword. This is in contrast to a conventional interleaved block code that requires the additional deinterleaver and its memory.

0000ARQ System with DBD

0073In another embodiment, the DBD <b>530</b> (or DRBD <b>730</b> of <figref idref="DRAWINGS">FIG. 7</figref>) can be used in conjunction with an automatic repeat request (ARQ) system that requests retransmission of blocks that are detected to be in error. The ARQ systems typically disrupt transmission, while sending a request and while receiving a repeated block back from the remote transmitter. The DBD <b>530</b> will allow raw source data to flow rapidly with no delay for FEC. When errors are detected, then the blocks in error can be reprocessed by the block decoders <b>540</b> of the DBD <b>530</b> to correct the errors without requiring retransmission. This keeps the signal channels clear for the flow of data. In the event the block decoders <b>540</b> cannot correct the errors, then the ARQ system can be activated to request a full retransmission of a block.

0000Distributed Register Block Encoder (DRBE)

0074In another embodiment, the DBE <b>430</b> can be implemented in a single FEC block encoder by using a distributed register arrangement, as shown in <figref idref="DRAWINGS">FIG. 6</figref>. Referring to <figref idref="DRAWINGS">FIG. 6</figref>, the distributed register block encoder (DRBE) <b>600</b> utilizes multiple registers (associated with but preferably residing within the single FEC block encoder) that can be selected by indirect addressing with very little additional complexity. Indirect addressing is a common technique used in software-based systems. The DRBE <b>600</b> incorporates parity memory elements that are represented by delay elements <b>601</b>, <b>602</b>, <b>603</b> and <b>604</b> that store respective parity symbols P<b>0</b>, P<b>1</b>, through P(p−2) and P(p−1). There are p delay elements, one for each parity symbol. A conventional FEC block encoder stores one symbol in each delay element. This new DRBE encoder <b>600</b> stores B past symbols in each delay element <b>601</b>, <b>602</b>, <b>603</b> and <b>604</b>. The delay elements can access past symbols independently, but it is only necessary to access the oldest symbols. A symbol generated B symbol periods earlier is recovered, modified in accordance with the coding algorithm, and then stored. As examples, the memory can take the form of a conventional shift register or other low complexity memory.

0075Source data symbols are input on connection <b>631</b>. Initially, switch <b>635</b> selects these source symbols on connection <b>631</b> for immediate output on connection <b>636</b> with no delay or modification. The source symbols on connection <b>631</b> are also provided to the first addition device <b>611</b>, where they are added to the parity symbol output on connection <b>634</b> from delay element <b>601</b>. The output of addition device <b>611</b> is then sent through switch <b>632</b> to multiplier devices <b>621</b>, <b>622</b>, <b>623</b> and <b>624</b>. The multiplier devices effectively select and weigh the addition result by factors w<b>0</b>, w<b>1</b>, through w(p−2) and w(p−1), respectively. The output of multiplier device <b>621</b> is added to the output of delay element <b>602</b> by addition element <b>612</b> and stored in delay element <b>601</b> as an updated parity symbol P<b>0</b>. The output of multiplier device <b>622</b> is added to the output of the next delay element, which may be delay element <b>603</b>, by addition element <b>613</b> and stored in delay element <b>602</b> as an updated parity symbol P<b>1</b>. The output of multiplier device <b>623</b> is added to the output of delay element <b>604</b>, by addition element <b>614</b> and stored in delay element <b>603</b> as an updated parity symbol P(p−2). The output of multiplier device <b>624</b> is stored in delay element <b>604</b> as an updated parity symbol P(p−1). The delay element outputs are not modified until all delay elements have been updated. While the operations have been explained sequentially, they may actually occur simultaneously in some designs.

0076This process is repeated once for each source symbol. After all k source data symbols have been processed, switch <b>635</b> selects the parity symbols on connection <b>634</b> for output from the delay elements. Switch <b>632</b> is opened while the parity symbols are output. The B parity symbols P<b>0</b> from delay element <b>601</b> are output first. Then, the B parity symbols P<b>1</b> from delay element <b>602</b> are output. All parity symbols are output from all delay elements, finishing with P(p−2) and P(p−1) from delay elements <b>603</b> and <b>604</b>. The B stored parity elements can be identified by the codewords they represent as C<b>0</b>, C<b>1</b>, C<b>2</b> . . . C(B−1). Then, the sequence of output parity symbols can be identified as P<b>0</b>C<b>0</b>, P<b>0</b>C<b>1</b>, P<b>0</b>C<b>2</b> . . . P<b>0</b>C(B−1), P<b>1</b>C<b>0</b>, P<b>1</b>C<b>1</b>, P<b>1</b>C<b>2</b> . . . P<b>1</b>C(B−1), P<b>2</b>C<b>0</b>, P<b>2</b>C<b>1</b>, P<b>2</b>C<b>2</b> . . . P<b>2</b>C(B−1) . . . . Thus, the parity symbols from any codeword can be seen to be separated by B symbol periods and are effectively interleaved. These interleaved parity codewords are protected from burst errors having durations of up to B symbol periods.

0077The example presented here used a simple combination of addition and multiplier devices to compute parity symbols. Many other combinations and logic designs are possible in FEC systems. All parity calculation methods can be used with the DRBE <b>600</b>.

0078A conventional FEC encoder, such as a RS encoder, can be enhanced by the use of distributed registers. The set of RS parity symbol registers is replaced by a set of multiple registers.

Example of (6,3) DRBE

0079For purposes of illustration, the DRBE <b>600</b> can implement a (6,3) block code. This is a simple example to illustrate the combinatorial logic of <figref idref="DRAWINGS">FIG. 6</figref> for a single block encoder where B=1.

0080The codeword length is n=6, there are k=3 source data symbols and p=3 parity symbols. Multiplication devices have the values w<b>2</b>=1, w<b>1</b>=1 and w<b>0</b>=0. For this case after the first source data symbol D<b>0</b> is processed then the parity symbols will store P<b>2</b>=D<b>0</b>, P<b>1</b>=D<b>0</b> and P<b>0</b>=0. Then following D<b>1</b> the parity symbols are updated to P<b>2</b>=D<b>1</b>, P<b>1</b>=D<b>1</b>+D<b>0</b> and P<b>0</b>=D<b>0</b>. Then following D<b>2</b> the parity symbols are updated to P<b>2</b>=D<b>2</b>+D<b>0</b>, P<b>1</b>=D<b>2</b>+D<b>1</b>+D<b>0</b> and P<b>0</b>=D<b>1</b>+D<b>0</b>. Thus, each source data symbol D<b>0</b>, D<b>1</b> and D<b>2</b> is represented in at least two of the parity symbols. The parity symbols are then transmitted following the source data symbols yielding a codeword sequence of D<b>0</b>, D<b>1</b>, D<b>2</b>, P<b>0</b>, P<b>1</b> and P<b>2</b>. This codeword provides sufficient redundancy to correct any single error that may occur in the remote received codeword.

0081The decoder can replicate the encoder operating on the received and possibly corrupted source data symbols D<b>0</b>′, D<b>1</b>′ and D<b>2</b>′ to produce decoder parity symbols P<b>0</b>′, P<b>1</b>′ and P<b>2</b>′. If no errors have occurred then the decoder parity symbols will equal the received parity symbols. The code can correct only one error so if any one of the decoder parity symbols does not match the corresponding received parity symbol then that received parity symbol must be in error and all data symbols are assumed to be correct. If two or more parity symbols do not match then the data symbol represented in those mismatching parity symbols must be in error and can be corrected. For example: <ul id="ul0001" list-style="none"><li id="ul0001-0001" num="0000"><ul id="ul0002" list-style="none"><li id="ul0002-0001" num="0082">If P<b>2</b>, P<b>1</b> and P<b>0</b> don't match P<b>2</b>′, P<b>1</b>′ and P<b>0</b>′ then correct D<b>0</b>′</li><li id="ul0002-0002" num="0083">If P<b>1</b> and P<b>0</b> don't match P<b>1</b>′ and P<b>0</b>′ then correct D<b>1</b>′</li><li id="ul0002-0003" num="0084">If P<b>2</b> and P<b>1</b> don't match P<b>2</b>′ and P<b>1</b>′ then correct D<b>2</b>′</li></ul></li></ul>

0085Note that two erasures can be corrected. Subtraction will be used in the example but the actual operations are modulo 2 exclusive-or operations. For example: <ul id="ul0003" list-style="none"><li id="ul0003-0001" num="0000"><ul id="ul0004" list-style="none"><li id="ul0004-0001" num="0086">If D<b>0</b> and D<b>1</b> are missing then D<b>0</b>=P<b>2</b>−D<b>2</b> and D<b>1</b>=P<b>0</b>−D<b>0</b></li><li id="ul0004-0002" num="0087">If D<b>0</b> and D<b>2</b> are missing then D<b>0</b>=P<b>0</b>−D<b>1</b> and D<b>2</b>=P<b>2</b>−D<b>0</b></li><li id="ul0004-0003" num="0088">If D<b>1</b> and D<b>2</b> are missing then D<b>1</b>=P<b>0</b>−D<b>0</b> and D<b>2</b>=P<b>2</b>−D<b>0</b></li></ul></li></ul>

0089Note that three erasures of all data symbols can be corrected. For example: <ul id="ul0005" list-style="none"><li id="ul0005-0001" num="0000"><ul id="ul0006" list-style="none"><li id="ul0006-0001" num="0090">First compute D<b>2</b>=P<b>1</b>−P<b>0</b></li><li id="ul0006-0002" num="0091">Then D<b>0</b>=P<b>2</b>−D<b>2</b> and D<b>1</b>=P<b>0</b>−D<b>0</b></li></ul></li></ul>

0092For the case where B=2 we have a codeword sequence of D<b>0</b>C<b>0</b>, D<b>1</b>C<b>1</b>, D<b>2</b>C<b>0</b>, D<b>3</b>C<b>1</b>, D<b>4</b>C<b>0</b>, D<b>5</b>C<b>1</b>, P<b>0</b>C<b>0</b>, P<b>0</b>C<b>1</b>, P<b>1</b>C<b>0</b>, P<b>1</b>C<b>1</b>, P<b>2</b>C<b>0</b> and P<b>2</b>C<b>1</b>. Where C<b>0</b> and C<b>1</b> identify the respective block codewords, the source symbols are D<b>0</b>C<b>0</b>, D<b>1</b>C<b>1</b>, D<b>2</b>C<b>0</b>, D<b>3</b>C<b>1</b>, D<b>4</b>C<b>0</b>, D<b>5</b>C<b>1</b> and the interleaved parity codewords are P<b>0</b>C<b>0</b>, P<b>0</b>C<b>1</b>, P<b>1</b>C<b>0</b>, P<b>1</b>C<b>1</b>, P<b>2</b>C<b>0</b>, P<b>2</b>C<b>1</b>. For this case: <ul id="ul0007" list-style="none"><li id="ul0007-0001" num="0000"><ul id="ul0008" list-style="none"><li id="ul0008-0001" num="0093">P<b>2</b>C<b>0</b>=D<b>4</b>C<b>0</b>+D<b>0</b>C<b>0</b>, P<b>1</b>C<b>0</b>=D<b>4</b>C<b>0</b>+D<b>2</b>C<b>0</b>+D<b>0</b>C<b>0</b> and P<b>0</b>C<b>0</b>=D<b>2</b>C<b>0</b>+D<b>0</b>C<b>0</b></li><li id="ul0008-0002" num="0094">P<b>2</b>C<b>1</b>=D<b>5</b>C<b>1</b>+D<b>1</b>C<b>1</b>, P<b>1</b>C<b>1</b>=D<b>5</b>C<b>1</b>+D<b>3</b>C<b>1</b>+D<b>1</b>C<b>1</b> and P<b>0</b>C<b>1</b>=D<b>3</b>C<b>1</b>+D<b>1</b>C<b>1</b></li></ul></li></ul>

0095It can be seen that a burst error impacting any two adjacent sequential symbols will result in only one error in any block codeword and both errors can be corrected. For example if D<b>3</b>C<b>1</b>′ and D<b>4</b>C<b>0</b>′ are in error then: <ul id="ul0009" list-style="none"><li id="ul0009-0001" num="0000"><ul id="ul0010" list-style="none"><li id="ul0010-0001" num="0096">P<b>1</b>C<b>1</b>′ and P<b>0</b>C<b>1</b>′ will not match and D<b>3</b>C<b>1</b>=P<b>0</b>C<b>1</b>−D<b>1</b>C<b>1</b>′ is corrected</li><li id="ul0010-0002" num="0097">P<b>2</b>C<b>0</b>′ and P<b>1</b>C<b>0</b>′ will not match and D<b>4</b>C<b>0</b>=P<b>2</b>C<b>0</b>−D<b>0</b>C<b>0</b>′ is corrected</li></ul></li></ul>

0098For the binary case corrections simply require inversion of the erroneous bits. For erasures the missing source symbols are computed from the known source symbols and parity symbols.

0099These examples have been given for illustrative purposes only. The well known block codes, such as the Hamming, BCH, and RS codes, are recommended. The structure of their encoders and decoders is well known in the art. As an example, computer code that implements Reed-Solomon error correction encoding and decoding functions is presented in U.S. Pat. No. 5,602,382 titled “Mail Piece Bar Code Having A Data Content Identifier,” which is incorporated herein by reference.

0000Distributed Register Block Decoder (DRBD)

0100<figref idref="DRAWINGS">FIG. 7</figref> is a block diagram illustrating an example implementation of a distributed register block decoder (DRBD) <b>730</b> and further illustrating the concept of utilizing a plurality of receivers <b>700</b> with differing FEC capabilities. The receivers <b>700</b> receive broadcast data from a DBE <b>400</b> (<figref idref="DRAWINGS">FIG. 4</figref>) or a DRBE <b>600</b> (<figref idref="DRAWINGS">FIG. 6</figref>) via signal path <b>158</b> from medium <b>120</b>. One receiver has a distributed register block decoder (DRBD) <b>730</b>. Beneficially, a receiver <b>700</b> that does not include a DRBD <b>730</b> can receive the source symbols directly.

First Example Implementation

0101In a first example implementation, the remote DBE <b>400</b> or DRBE <b>600</b> is designed to transmit original source symbols alternating with interleaved parity codewords.

0102In the receiver without a DRBD <b>730</b>, a signal from medium <b>120</b> is routed via signal path <b>158</b>B to demodulator <b>157</b>B, then optional trellis decoder <b>156</b>B. The output of optional trellis decoder <b>156</b>B on connection <b>731</b>B contains the original source symbols alternating with interleaved parity codewords with possible errors due to imperfections in the medium <b>120</b>.

0103Optional switch <b>153</b>B can be opened to discard the interleaved parity codewords. The output of optional switch <b>153</b>B contains only the original source symbols in their original sequential order. If the remote DBE <b>400</b> utilized an optional randomizer <b>102</b>, then optional derandomizer <b>152</b>B is used to derandomize the source symbols. The optional derandomizer <b>152</b>B delivers recovered source symbols to data terminal <b>151</b>B with the possible inclusion of symbol errors due to imperfect medium <b>120</b>.

0104In the receiver <b>700</b> with a DRBD <b>730</b>, the receiver <b>700</b> receives the signal from medium <b>120</b> on signal path <b>158</b>. The signal from medium <b>120</b> is routed via signal path <b>158</b> to demodulator <b>157</b> then to optional trellis decoder <b>156</b>. The output of optional trellis decoder <b>156</b> on connection <b>731</b> contains the original source symbols with possible errors due to imperfections in the medium. In this first example, the signal on connection <b>731</b> contains groups of original source symbols alternating with groups of interleaved parity codewords. Optional buffer <b>739</b> is not required. The symbols on connection <b>731</b> are routed via switch <b>737</b>A directly to distributed register switch <b>732</b>. A plurality of codeword registers <b>745</b> are associated with the single block decoder <b>740</b>, but preferably reside within the single block decoder <b>740</b>, as shown in <figref idref="DRAWINGS">FIG. 7</figref>. Switch <b>732</b> will distribute symbols to each of the codeword registers <b>745</b> in sequential order. Switch <b>732</b> routes the first source symbol to codeword register <b>1</b> and the next to codeword register <b>2</b>. This process repeats until B source symbols have been distributed to all codeword registers <b>745</b>, then continues again with a source symbol to codeword register <b>1</b>. After k*B source symbols in a block have been received, the interleaved parity codewords are received on connection <b>731</b> as input to distributed register switch <b>732</b>. The distributed register switch <b>732</b> continues to distribute all of the parity symbols in the interleaved parity codewords to the codeword registers <b>745</b>. After p*B parity symbols in a block have been received, the B distributed codeword registers <b>745</b> contain complete n-symbol codewords.

0105Distributed register switch <b>733</b> selects the codewords from each codeword register <b>745</b> for decoding by block decoder <b>740</b>. The codeword symbols from codeword register <b>1</b> are routed by distributed register switch <b>733</b> to switch <b>735</b> and from switch <b>735</b> to connection <b>746</b> for input to block decoder <b>740</b>. Block decoder <b>740</b> corrects any errors in a block up to the capacity of the FEC code then outputs the k corrected source symbols on connection <b>748</b>. While decoding, switch <b>737</b>A is positioned to route the corrected source symbols on connection <b>748</b> through distributed register switch <b>732</b> back into the codeword registers <b>745</b>. After correcting the source symbols in codeword register <b>1</b> the distributed register switches <b>732</b> and <b>733</b> select codeword register <b>2</b> and block decoder <b>740</b> corrects the source symbols in codeword register <b>2</b>. This process continues until the source symbols in all B codeword registers have been corrected. Then switch <b>735</b> is connected to connection <b>747</b> to output the corrected source symbols through optional derandomizer <b>152</b> to data terminal <b>151</b>. Distributed register switch <b>733</b> outputs the first corrected source symbol from codeword register <b>1</b>, the next corrected source symbol from codeword register <b>2</b> and continues outputting one corrected symbol from all B codeword registers. This process continues taking one corrected source symbol from each codeword register in sequence until all k*B corrected source symbols have been output. Then switch <b>737</b>A is positioned to receive the next uncorrected symbols from connection <b>731</b> for input to distributed register switch <b>732</b> and distribution to the codeword registers <b>745</b>.

0106This cycle repeats with switch <b>732</b> delivering the next received symbols to the codeword registers <b>745</b>. In one variation it is possible for new received symbols to be loading into the codeword registers <b>745</b> through distributed register switch <b>732</b> at the same time as corrected source symbols are being output through distributed register switch <b>733</b>. In some implementations, it may be beneficial to have double buffers on the codeword registers <b>745</b> so that they may continue to receive new received source symbols, while distributed register switch <b>733</b> delivers previously received complete codewords to block decoder <b>740</b>. In such an arrangement the switches <b>737</b>A and <b>735</b> may operate in “double throw” fashion. One set of codeword registers <b>745</b> accepts uncorrected symbols from connection <b>731</b> for input and outputs corrected source symbols on connection <b>747</b> while a second set of codeword registers <b>745</b>A (not shown) delivers complete received codewords on connection <b>746</b> to block decoder <b>740</b> and accepts corrected source symbols on connection <b>748</b>. The functions of each register set <b>745</b> and <b>745</b>A alternate while one functions for input and output, the other functions for error correction. Such buffering mechanisms are very common in software systems and are easily implemented by indirect addressing.

Second Example Implementation

0107In a second example implementation, the remote DBE <b>400</b> or DRBE <b>600</b> is designed to transmit the interleaved parity codewords on a second channel, while the source symbols are transmitted on a first channel.

0108In this case, in connection with the receiver <b>700</b> without a DRBD <b>730</b>, the optional switch <b>153</b>B is not required. The signal on connection <b>731</b>B contains only source symbols. The source symbols are processed by optional derandomizer <b>152</b>B and delivered to data terminal <b>151</b>B.

0109In this second example, the receiver <b>700</b> with the DRBD <b>730</b> can receive the interleaved parity codewords on the second channel via signal connection <b>158</b>A. Demodulator <b>157</b>A and optional trellis decoder <b>156</b>A recover the interleaved parity codewords and deliver them to optional buffer <b>759</b>A. Optional buffer <b>759</b>A allows for simultaneous reception of interleaved parity codewords from one block on the second channel, while receiving source symbols from the next block on the first channel. The interleaved parity codewords from optional buffer <b>759</b>A are delivered on connection <b>731</b>A to the DRBD <b>730</b>.

0110DRBD <b>730</b> incorporates B codeword registers <b>745</b>, where B is two or more. Each codeword register <b>745</b> collects and stores a complete received codeword containing n symbols, where n is one or more. Optional buffer <b>739</b> receives source symbols on connection <b>731</b> for input to switch <b>737</b>A. The demodulator <b>157</b> and optional trellis decoder <b>156</b> provide the source symbols to the connection <b>731</b>. Switch <b>737</b>A first selects source data symbols from optional buffer <b>739</b>. Source symbols pass from optional buffer <b>739</b> through switch <b>737</b>A to distributed register switch <b>732</b>. Switch <b>732</b> will distribute symbols to each of the codeword registers <b>745</b> in sequential order. Switch <b>732</b> routes the first source symbol to codeword register <b>1</b> and the next to codeword register <b>2</b>. This process repeats until B source symbols have been distributed to all codeword registers <b>745</b>, then continuing again with a source symbol to codeword register <b>1</b>. After k*B source symbols in a block have been received from optional buffer <b>739</b>, then each codeword register will contain the k source symbols of their respective codeword. Then switch <b>737</b>A selects interleaved parity codewords from connection <b>731</b>A as input to distributed register switch <b>732</b>. After all p*B parity symbols in a block have been received from the interleaved parity codewords, the B codeword registers <b>745</b> contain complete codewords.

0111Distributed register switch <b>733</b> selects the codewords from each codeword register <b>745</b> for decoding by block decoder <b>740</b> as described above. This cycle repeats with switch <b>737</b>A, alternately delivering source symbols and interleaved parity codewords for each block.

0000Dual Register Set DRBD

0112An alternative dual register set DRBD <b>830</b> uses a set of codeword registers <b>845</b> and a set of corrected registers <b>855</b> as shown in <figref idref="DRAWINGS">FIG. 8</figref>. In this example, the signal on connection <b>831</b> contains groups of original source symbols alternating with groups of interleaved parity codewords. The symbols on connection <b>831</b> are routed directly to distributed register switch <b>832</b>. A plurality of codeword registers <b>845</b> are associated with the single block decoder <b>840</b>, but preferably reside within the single block decoder <b>840</b>, as shown in <figref idref="DRAWINGS">FIG. 8</figref>. Switch <b>832</b> will distribute symbols to each of the codeword registers <b>845</b> in sequential order. Switch <b>832</b> routes the first source symbol to codeword register <b>1</b> and the next to codeword register <b>2</b>. This process repeats until B source symbols have been distributed to all codeword registers <b>845</b>, and then continues again with a source symbol to codeword register <b>1</b>.

0113After k*B source symbols in a block have been received, the interleaved parity codewords are received on connection <b>831</b> as input to distributed register switch <b>832</b>. The distributed register switch <b>832</b> continues to distribute all of the interleaved parity codewords to the codeword registers <b>845</b>. After p*B parity symbols in a block have been received from the interleaved parity codewords, the B distributed codeword registers <b>845</b> each contain complete n-symbol codewords.

0114Distributed register switch <b>833</b> selects the codewords from each codeword register <b>845</b> for decoding by block decoder <b>840</b>. The codeword symbols from codeword register <b>1</b> are routed by distributed register switch <b>833</b> on connection <b>835</b> to block decoder <b>840</b>. Block decoder <b>840</b> corrects any errors in a block up to the capacity of the FEC code, then outputs the k corrected source symbols to distributed register switch <b>852</b>. Distributed register switch <b>852</b> distributes the corrected source symbols to corrected registers <b>855</b>. All k corrected source symbols from codeword register <b>1</b> are routed to corrected register <b>1</b>. After correcting the source symbols in codeword register <b>1</b> the distributed register switches <b>833</b> and <b>852</b> select codeword register <b>2</b>, and block decoder <b>840</b> corrects the source symbols in codeword register <b>2</b> and stores the corrected source symbols in corrected register <b>2</b>. This process continues until the source symbols in all B codeword registers <b>845</b> have been corrected and stored in all B corrected registers <b>855</b>. Then, distributed register switch <b>853</b> outputs the first corrected source symbol from corrected register <b>1</b>, the next corrected source symbol from corrected register <b>2</b> and continues outputting one corrected symbol from all B corrected registers. This process continues taking one corrected source symbol from each codeword register in sequence until all k*B corrected source symbols have been output over connection <b>847</b>. While outputting corrected source symbols, new uncorrected symbols can be collected from connection <b>831</b> and distributed by distributed switch <b>832</b> to the codeword registers <b>845</b> repeating the cycle.

0000Distributed Parity Backup

0115The DBC can be used to construct backup packets of parity symbols or interleaved parity codewords. The backup parity packets can be processed independently. The DBC can monitor source data flow and construct redundant parity files or parity packets. The DBC operates to protect parity packets and their source data from burst errors, while conveniently isolating the source data from the parity packets. These parity packets can be stored for backup restoration or transmitted on independent channels as a service for applications that require low error rates. This allows source data to be stored or communicated without redundancy to increase the efficiency of storage systems or communications channels. Very powerful codes can be used to construct the backup parity packets. Common FEC systems use codes that may compromise correction capability by using a minimum of redundant parity information to increase efficiency.

0116The backup packets can be offered as a higher cost option in storage or communications systems. The generation of DBE parity packets requires relatively low complexity in the encoder. The decoder may require a significant increase in complexity that may be justified in some applications, but not others. Users that require low error rates can implement the complex decoders and access the backup parity packets.

0117In communications systems, the backup packets can be communicated over an independent channel. The channel can be isolated through normal means of frequency band, time slot, or code. Common channelization methods include frequency division multiplexing (FDM), time division multiplexing (TDM), code division multiple access (CDMA) and others.

0118A variation in the ARQ system would allow a backup parity packet or block to be sent as a reply instead of the normal retransmission of entire blocks. If the parity packet is sufficient to correct a block error, then communication resumes with minimal disruption. If the parity packet is not sufficient to correct an erroneous block then the entire block can be retransmitted.

0119Independent parity packets will enable adaptive FEC. In low error environments, the parity packets are not required. As the error rate environment increases, then the parity packets can be used.

0120In data storage systems, source data files can be stored as normal media data files. Then backup parity packets or files can be generated and stored as independent files. Systems accessing the storage medium can simply access the raw source data files whenever needed. The backup parity files can be ignored, unless an error is detected. If a file is retrieved and found to be in error, then the backup parity file can be used to recover the original source data from the corrupted source data file. One advantage of RS type codes is that p parity symbols can correct p/2 errors or p erasures. Files that are detected to be in error can be flagged as erasures thereby doubling the recovery capability of the code. Errors can be detected in files or packets by simple cyclic redundancy check (CRC) codes.

0121For archive systems, the source files can be periodically scanned to detect any degradation. If errors are found, then the corrupted files can be restored using the parity files. In a system that may slowly degrade, the DFEC codes will be sufficient to correct all errors if detected early before the number of errors exceeds the capacity of the code. The burst error protection of DBC is beneficial where areas of media may degrade contiguous segments of both source data and parity information. The use of complex error correction algorithms can be justified when applied to only files or packets that are known to be corrupted. Complex algorithms can seldom be justified if it is necessary to apply them to all data when only a small amount of data may be in error.

0122One example applies to computer disks, such as magnetic disks, compact disks (CDs), and DVD disks. In many applications, media elements contain a specific set of data, such as files from a particular project or entertainment programs. Frequently the media is not full. It would be beneficial to store backup parity packets or files in the media to make use of any spare capacity.

0123The DFEC system is particularly well suited to systems that transmit or store groups of packets or files. The transmission can be terminated without the addition of excess overhead to purge interleavers or fill unreasonably large codewords. Consider a largest packet containing L symbols. It is recommended that the DFEC system use B greater than or equal to L to enable restoration of a packet that may be completely obliterated. It may be sufficient to use B greater than or equal to L*2/p if the code can correct p/2 symbol errors. A complete DFEC block normally contains n*B symbols consisting of k*B source data symbols and p*B parity symbols. An abbreviated transmission can be terminated after sending k<b>2</b>*B+k<b>1</b> source data symbols where k<b>2</b>*B+k<b>1</b> is less than the designed DFEC block size of k*B source data symbols. After the last source symbol is sent the DBE can be filled with predetermined fill symbols such as zeros that are not transmitted. The DFEC then transmits all p*B parity symbols to complete the DFEC block.

0124There are two preferred methods of sending the final parity symbols, while maintaining the B symbol burst protection. The parity symbols can be transmitted out of order starting with P(k<b>1</b>), P(k<b>1</b>+1) . . . through P(p−1) then P<b>0</b>, P<b>1</b>, P<b>2</b> . . . through P(k<b>1</b>−1). A second preferred method is to fill out the last codewords by transmitting p−k<b>1</b> fill symbols then the parity symbols commencing with P<b>0</b>, P<b>1</b>, P<b>2</b> . . . P(p−1). It is not recommended to transmit the first parity symbol P<b>0</b> immediately following an abbreviated frame of k<b>2</b>*B+k<b>1</b> source symbols because this would leave only k<b>1</b> symbols between the last source symbol of codeword 0 and its first parity symbol P<b>0</b> thereby reducing the burst error protection to only k<b>1</b> symbols. The parity symbols can be stored or transmitted in an independent packet but it is best to maintain the B symbol separation between codeword symbols spread across two or more packets.

0000Software and Hardware Implementations

0125The transmitter and receiver elements, including but not limited to, the DBE <b>430</b>, the DBD <b>530</b>, the DRBE <b>600</b>, and the DRBD <b>730</b>, can be implemented in hardware, software, or a combination thereof. In the preferred embodiment(s), these elements are implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system, such as a digital signal processor (DSP) or general purpose microprocessor. Moreover, connections and switches in the figures represent logical connectivity.

0126If implemented in hardware, as in an alternative embodiment, these elements can be implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), a quantum computer having quantum gates for implementing manipulations on qubits, etc.

0127When the foregoing elements are implemented in software, they can be stored on any suitable computer readable medium. In the context of this document, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, processor, apparatus, or device. The computer readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a nonexhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM) (electronic), a read-only memory (ROM) (electronic), an erasable programmable read-only memory (EPROM or Flash memory) (electronic), an optical fiber (optical), and a portable compact disc read-only memory (CDROM) (optical).

0000Variations and Modifications

0128In concluding the detailed description, it should be noted that the terminology “preferred embodiment” herein means the one embodiment currently believed by the inventor(s) to be the best embodiment of a plurality of possible embodiments. Moreover, it will be obvious to those skilled in the art that many variations and modifications may be made to the preferred embodiment(s) without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the teachings of the present invention in this document.