US7994573B2

Structure and method for forming power devices with carbon-containing region

Summary by NHIP

Carbon-embedded FET structure

The invention forms a field effect transistor with a carbon-containing region situated below body regions within the semiconductor substrate. This region contacts the substrate directly while remaining spaced from the body regions and extending beneath trench gate electrodes.

Claim Score by NHIP

Read claim 1, the broadest

Abstract

A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.

US7994573B2, drawing sheet 1 — Sheet 1 of 9

Term

2.2 yearsleft in the term

Expires 12 December 2028.

13 claims: 1 independent, 12 dependent

1
Broadest claimClaim Score 61, broad(NHIP)A field effect transistor (FET), comprising:body regions of a first conductivity type over a semiconductor region of a second conductivity type, the body regions forming p-n junctions with the semiconductor region;source regions of the second conductivity type over the body regions, the source regions forming p-n junctions with the body regions;gate electrodes extending adjacent to but being insulated from the body regions by a gate dielectric;a carbon-containing region of the second conductivity type extending in the semiconductor region below the body regions, wherein the semiconductor region comprises a substrate of the second conductivity type over which the carbon-containing region extends and a drift region of the second conductivity type extending between the carbon-containing region and the body regions.

53 paragraphs in 5 sections, as filed

0001This application claims the benefit of U.S. Provisional Application No. 61/013,953, filed Dec. 14, 2007, which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

0002The present invention relates in general to semiconductor technology and more particularly to semiconductor power devices with carbon-doped region and method of forming the same.

0003Generally, an n-channel trench-gate power MOSFET includes an n-type substrate on which an n-type epitaxial layer is formed. The substrate embodies the drain of the MOSFET. A p-type body region extends into the epitaxial layer. Trenches extend through the body region and into the portion of the epitaxial layer bounded by the body region and the substrate (commonly referred to as the drift region). A gate dielectric layer is formed on the sidewalls and bottom of each trench. Source regions flank the trenches. Heavy body regions are formed within the body region between adjacent source regions. Gate electrodes (e.g., from polysilicon) fill the trenches and embody the gate of the MOSFET. A dielectric cap covers the trenches and also partially extends over the source regions. A top-side metal layer electrically contacts the source regions and the heavy body regions. A bottom-side metal layer contacts the substrate

0004In such conventional power devices, obtaining a higher breakdown voltage often comes at the expense of higher on-resistance (Rdson). Thus, there is a need for techniques that improve breakdown voltage of power devices without adversely impacting other device characteristics.

BRIEF SUMMARY OF THE INVENTION

0005In accordance with an embodiment of the invention, a field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.

0006In one embodiment, the semiconductor region further includes a substrate over which the carbon-containing region extends, and a drift region of the second conductivity type that extends between the carbon-containing region and the body regions. The substrate has a doping concentration greater than that of the drift region.

0007In another embodiment, the carbon-containing region is in direct contact with the substrate and is spaced from the body regions.

0008In another embodiment, each gate electrode is disposed in a trench extending adjacent the body regions and terminating within the semiconductor region.

0009In another embodiment, each trench further includes a shield electrode disposed below the gate electrode. The gate and shield electrodes are insulated from one another by an inter-electrode dielectric layer.

0010In another embodiment, each trench includes a thick bottom dielectric extending along the bottom of the trench below the gate electrode.

0011In another embodiment, the gate electrodes extend laterally over the semiconductor and body regions and overlap the source regions.

0012In another embodiment, the entirety of carbon-containing region extends below the trenches.

0013In another embodiment, the carbon-containing region abuts sidewalls of the trenches.

0014In another embodiment, the carbon-containing region is of the second conductivity type.

0015In accordance with an embodiment of the invention, a method of forming a field effect transistor (FET) includes forming a carbon-containing region over a substrate. An epitaxial layer is formed over the carbon-containing region. The epitaxial layer has a lower doping concentration than the substrate. A body region of a first conductivity type is formed in the epitaxial layer. The epitaxial layer is of a second conductivity type and forms a p-n junction with the body region. Gate electrodes are formed adjacent to but insulated from the body regions. Source regions of the second conductivity type are formed in the body regions. The source regions form p-n junctions with the body regions.

0016In one embodiment, the carbon-containing region is formed epitaxially.

0017In another embodiment, the carbon-containing region is in direct contact with the substrate.

0018In another embodiment, the carbon-containing region is of the second conductivity type.

0019In another embodiment, trenches extending into semiconductor regions are formed. The trenches house the gate electrodes.

0020In another embodiment, the entirety of carbon-containing region extends below the trenches.

0021In another embodiment, the trenches extend into the carbon-containing region.

BRIEF DESCRIPTION OF THE DRAWINGS

0022<figref idref="DRAWINGS">FIGS. 1A-1C</figref> are simplified cross-sectional views showing an exemplary method for forming a shielded gate trench power MOSFET in accordance with an embodiment of the present invention;

0023<figref idref="DRAWINGS">FIG. 1D</figref> is a schematic figure showing an exemplary carbon concentration profile within a carbon-containing layer in accordance with an embodiment of the present invention;

0024<figref idref="DRAWINGS">FIG. 2</figref> is a simplified cross-sectional view showing an exemplary shielded gate trench power MOSFET in accordance with another embodiment of the present invention;

0025<figref idref="DRAWINGS">FIG. 3</figref> is a simplified cross-sectional view showing an exemplary trench gate power MOSFET in accordance with an embodiment of the present invention;

0026<figref idref="DRAWINGS">FIG. 4</figref> is a simplified cross-sectional view of an exemplary planar gate MOSFET in accordance with an embodiment of the present invention; and

0027<figref idref="DRAWINGS">FIGS. 5A-5D</figref> are simplified cross-sectional views showing an exemplary method for forming a shielded gate trench power MOSFET in accordance with yet another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

0028According to the embodiments of the present invention, techniques directed to integrated circuits and their processing are disclosed. More particularly, the invention provides methods and devices for power field effect transistors (FETs) which include a carbon-containing layer. The carbon-containing layer is configured to provide a higher breakdown voltage and other advantageous features described more fully below. Merely by way of example, the invention has been described in the context of trench power MOSFETs, but it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to planar power MOSFETs as well as to trench gate and planar gate IGBTs.

0029Depending on the embodiments, the carbon-containing layer may be formed in the drift region a trench gate FET. Alternatively, the carbon containing layer may abut sidewalls of trenches extending into the drift region. In some embodiments, the carbon-containing layer has a graded profile to allow for smooth transition from adjacent silicon regions. The above features may be in one or more of the embodiments described herein and their obvious variants. One of ordinary skill in the art would recognize many variations, modifications, and alternatives in view of this disclosure.

0030<figref idref="DRAWINGS">FIGS. 1A-1C</figref> are simplified cross-sectional views showing an exemplary method for forming a shielded gate trench power MOSFET in accordance with an embodiment of the present invention. In <figref idref="DRAWINGS">FIG. 1A</figref>, a carbon-containing layer 104 is formed over a substrate 100. Substrate 100 can be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. The embodiment shown is an n-channel MOSFET, and substrate 100 may include n-type dopants such as phosphorus, arsenic and/or other group V elements.

0031In some embodiments, carbon-containing layer 104 may be a carbon-containing silicon epitaxial layer, a containing-carbon silicon-germanium epitaxial layer, or various combinations thereof. In some embodiments, carbon-containing layer 104 may be formed by an epitaxial process. The epitaxial process may use a silicon-containing precursor such as silane (SiH4) and a carbon-containing precursor such as alkane (e.g., propane) to form carbon-containing layer 104. In some embodiments, the carbon-containing precursor may have a flow rate between about 1 standard cubic centimeter per minute (sccm) and about 1,000 sccm. In some embodiments, carbon containing layer 104 may have a carbon concentration between about 1×1018 and about 1×1021. For the n-channel MOSFET embodiment shown, carbon-containing layer 104 may include n-type dopants such as phosphorus, arsenic and/or other group V dopants. In some embodiments, carbon-containing layer 104 may have a thickness between about 500 Å and about 5 μm. In other embodiments, carbon-containing layer 104 may have a thickness of about 1 μm.

0032In <figref idref="DRAWINGS">FIG. 1B</figref>, n-type epitaxial layer 105 is formed over carbon-containing layer 104. In some embodiments, epitaxial layer 105 may be a silicon epitaxial layer, a silicon-germanium epitaxial layer, or a combination thereof. Epitaxial layer 105 may have n-type dopants such as phosphorus, arsenic and/or other group V dopant.

0033In some embodiments, carbon-containing layer 104 and epitaxial layer 105 are formed by different processes. In other embodiments, carbon-containing layer 104 and epitaxial layer 105 are formed in a single process. For example, during the formation of carbon-containing layer 104, the carbon-containing precursor, e.g., propane, is added within the processing chamber for interacting with the silicon precursor. After the formation of carbon-containing layer 104, the flow of the carbon-containing precursor is reduced and/or turned off, such that epitaxial layer 105 with little or no carbon therein is formed over carbon-containing layer 104.

0034In <figref idref="DRAWINGS">FIG. 1C</figref>, p-type body region 106 may be formed in or over epitaxial layer 105. In some embodiments, body region 106 may be formed by implanting dopants in epitaxial layer 105. In other embodiments, body region 106 may be formed by an epitaxial process over epitaxial layer 105. Trenches 102 extending through body region 106 and terminating within a region of epitaxial layer 105 bounded by body region 106 and substrate 100 is formed using conventional techniques. The region of epitaxial layer 105 bounded by body region 106 and substrate 100 is commonly referred to as the drift region. Shield dielectric layer 101 lining the bottom and the lower sidewalls of trenches 102 is formed using known processes.

0035Shield electrode 110 (e.g., comprising doped or undoped polysilicon) is formed in a bottom portion of each trenches 102 using conventional techniques. Inter-electrode dielectric 103 (e.g., comprising oxide) extending over shield electrode 110 is formed in each trench using conventional techniques. Gate dielectric layer 107 lining upper trench sidewalls is formed using know techniques. In some embodiments, gate dielectric layer 107 is thinner than shield dielectric layer 101. Gate electrode 115 is formed in an upper portion of each trench 102 using conventional methods. N-type source regions 120 are formed in body regions 106 adjacent the trenches, using known techniques.

0036Gate dielectric 107 may comprise, for example, oxide, nitride, oxynitride, dielectric material, high-k dielectric material or various combinations thereof. In some embodiments, the high-k dielectric can be one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO4), yttrium oxide (Y2O3), lanthanum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), or combinations thereof. Gate dielectric 107 may be formed by, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process or other known processes. Gate electrodes 115 may comprise, for example, polysilicon; amorphous silicon; metal-containing material such as Ru, Ti, Ta, W, Hf, metal nitride stacked gates; metal oxide gates such as RuO2 or IrO2; metal nitride gates such as MoN, WN, TiN, TaN, TaAlN; poly SiGe; gate silicide such as CoSi2 or NiSi; or various combinations thereof Gate electrodes 115 may be formed by, for example, a CVD process, a PVD process, an electrochemical plating process, an electroless plating process or other known techniques.

0037In <figref idref="DRAWINGS">FIG. 1C</figref>, a dielectric layer 125 overlies gate electrodes 115. Dielectric layer 125 may comprise, for example, oxide, nitride, oxynitride, other dielectric material or various combinations thereof. In some embodiments, dielectric layer 125 may be a boron-phosphorus-silicate-glass (BPSG) layer which can be formed by, for example, a CVD process. While dielectric layer 125 is shown as having a flat top surface, in some embodiments, dielectric layer 125 has a dome shape and extends out of trench 102 and overlaps source regions 120.

0038Contact openings 130 are formed in a center portion of body region 106 between adjacent trenches. In some embodiments, contact openings 130 are formed using a patterned mask layer having a pattern corresponding to openings 130. The patterned mask may be, for example, a patterned photoresist layer or a patterned dielectric layer. P+ heavy body region 165 is formed in body region 106 along the bottom of each contact opening 130. Heavy body region 165 may be formed using conventional techniques such as implanting dopants in body region 106 through contact openings 130.

0039A top-side source interconnect layer 140 (not completely shown) is formed over the structure, substantially filling contact opening 130. The Source interconnect layer 140 makes direct contact with heavy body region 165 along the bottom of contact opening 130, and with source regions 120 at least along sidewalls of contact opening 130. The source interconnect layer 140 may comprise, for example, copper, tungsten, aluminum, aluminum copper, titanium, tantalum, cobalt, nickel, platinum, polysilicon, or various combinations thereof. The source interconnect layer 140 may be formed by a CVD process, a PVD process, an electrochemical planting process and/or an electroless plating process. A backside drain interconnect layer (not shown) may be formed on the backside of substrate 100. The drain interconnect layer may comprise similar material as the top-side source interconnect layer 140, and can be formed in a similar manner to the top-side source interconnect layer 140.

0040While the <figref idref="DRAWINGS">FIGS. 1A-1C</figref> show only one trench 102 and the structure appears asymmetric, it is to be understood that the design to which the cross section views shown and described herein correspond is a cell-based design where one cell is repeated many times to form the complete device.

0041In <figref idref="DRAWINGS">FIG. 1C</figref>, carbon-containing layer 104 may be directly under or within epitaxial layer 105. In some embodiments, a bottom surface 109 of carbon-containing layer 104 may be spaced from substrate 100. In other embodiments, bottom surface 109 may directly contact substrate 100. As shown in <figref idref="DRAWINGS">FIG. 1C</figref>, top surface 108 of carbon-containing layer 104 extends under trench 102.

0042<figref idref="DRAWINGS">FIG. 1D</figref> is a graph showing an exemplary carbon concentration profile within carbon-containing layer 104 in accordance with an embodiment of the present invention. In some embodiments, the carbon distribution within carbon-containing layer 104 may have a Gaussian distribution profile. In some embodiments, the carbon concentration near top surface 108 of carbon-containing layer 104 is about 1×1018. In other embodiments, the carbon concentration near bottom surface 109 of carbon-containing layer 104 is also about 1×1018. In still other embodiments, the carbon concentration at the peak of the Gaussian distribution profile of carbon-containing layer 104 is about 1×1021. In yet other embodiments, carbon-containing layer 104 has a graded carbon distribution profile to allow for smooth transition from adjacent silicon regions. For example, the carbon concentration of carbon-containing layer 104 is gradually increased from bottom surface 109 and top surface 108 of carbon-containing layer 104 to reach a peak concentration in a center region of layer 104.

0043Carbon-containing layer 104 advantageously has increased energy band gap such that the avalanche breakdown voltage is desirably increased. Also, carbon-containing layer 104 desirably increases the thermal conductivity of the power MOSFET. Accordingly, heat generated during operation of the power MOSFET may be dissipated through carbon-containing layer 104 more rapidly.

0044While carbon-containing layer 104 is shown extending below trench 102, it can be formed to extend higher up and abut sidewalls of trench 102. <figref idref="DRAWINGS">FIG. 2</figref> shows such structure. The structure in <figref idref="DRAWINGS">FIG. 2</figref> is substantially similar to that in <figref idref="DRAWINGS">FIG. 1C</figref> except that carbon-containing layer 104a is formed to extend up along the sidewalls of trench 102. As shown, top surface 111 of carbon-containing layer 104a is adjacent to but is separated from body region 106 by n-type drift region 105a. Materials and methods for forming carbon-containing layer 104a are similar to those of carbon-containing layer 104 described above in reference to <figref idref="DRAWINGS">FIG. 1C</figref>, except that carbon-containing layer 104a is thicker than carbon-containing layer 104.

0045<figref idref="DRAWINGS">FIG. 3</figref> is a simplified cross-sectional view of an exemplary trench gate MOSFET according to another embodiment of the present invention. This embodiment is substantially similar to the embodiment in <figref idref="DRAWINGS">FIG. 1C</figref> except that no shield electrode is formed under gate electrode 145. Instead a dielectric layer which in some embodiments is thicker than gate dielectric 107 (i.e., what is commonly knows as thick bottom dielectric TBO) extends under gate electrode 145 along the trench bottoms.

0046<figref idref="DRAWINGS">FIG. 4</figref> is a simplified cross-sectional view of an exemplary planar MOSFET in accordance with yet another embodiment of the invention. The structure in <figref idref="DRAWINGS">FIG. 4</figref> is the planar gate variation of the trench gate MOSFET shown in <figref idref="DRAWINGS">FIG. 3</figref>, and thus many of the same process and structural variations described above in connection with the carbon-containing layer of the various embodiments also apply to the structure in <figref idref="DRAWINGS">FIG. 4</figref>.

0047In <figref idref="DRAWINGS">FIG. 4</figref>, carbon-containing layer 205 extends over substrate 200. In some embodiments, the materials and methods for forming carbon-containing layer 205 and substrate 200 are similar to carbon-containing layer 104 and substrate 100 in <figref idref="DRAWINGS">FIG. 1C</figref>. N-type epitaxial layer 210 is formed over carbon-containing layer 205. In some embodiments, carbon-containing layer 205 is formed within epitaxial layer 210. Materials and methods for forming epitaxial layer 210 may be similar to epitaxial layer 105 in <figref idref="DRAWINGS">FIG. 1C</figref>.

0048The stacks of gate dielectric layer 215 and gate electrode 220 are formed over epitaxial layer 210 using known techniques. Body regions 225 are formed in epitaxial layer 210 using conventional techniques. Source regions 230 are formed in body regions 225 using conventional techniques. Heavy body contact openings are forming in body region 225 and later filled with contact material 240. Contact material 240 may form part of a top-side source interconnect layer (not shown) that extends over the structure but is insulated from gate electrodes 220.

0049<figref idref="DRAWINGS">FIGS. 5A-5D</figref> are simplified cross-sectional views showing an exemplary method for forming a shielded gate trench power MOSFET in accordance with another embodiment of the present invention. In <figref idref="DRAWINGS">FIG. 5A</figref>, epitaxial layer 304 may be formed over substrate 300. Materials and methods for forming substrate 300 may be similar to substrate 100 in <figref idref="DRAWINGS">FIG. 1A</figref>. Epitaxial layer 304 may be a doped or an undoped silicon epitaxial layer or silicon-germanium epitaxial layer. In some embodiments for forming an n-type MOSFET, epitaxial layer 304 may have dopants of phosphorus, arsenic or other group V dopant.

0050In <figref idref="DRAWINGS">FIG. 5B</figref>, a carbon implantation process 307 may be carried out to implant carbon into epitaxial layer 304 to form carbon-containing layer 304a. Carbon implantation process 307 can be designed to form carbon-containing layer 304a having a dopant profile similar to that of carbon-containing layer 104 in <figref idref="DRAWINGS">FIGS. 1A-1D</figref>.

0051In <figref idref="DRAWINGS">FIG. 5C</figref>, epitaxial layer 305 is formed over carbon-containing layer 304a. In some embodiments, materials and methods for forming the epitaxial layer 305 may be similar to epitaxial layer 105 in <figref idref="DRAWINGS">FIG. 1B</figref>. In <figref idref="DRAWINGS">FIG. 5D</figref>, the trench structure and the materials therein as well as body region 306, source regions 320, heavy body region 365 and contact opening 330 are all substantially similar to those in <figref idref="DRAWINGS">FIG. 1C</figref> and similar techniques to those described above may be used to form these regions and structures.

0052While in the various embodiments shown and described herein only one carbon-containing region is used, multiple such regions may be employed in the structures. Also, the techniques in accordance with the invention describe herein are not limited to any particular types of transistors and may be implemented in a variety of devices where incorporating a carbon-containing layer in the device is desired. For example, the process sequence depicted in <figref idref="DRAWINGS">FIGS. 1A-1C</figref> can be modified by those skilled in the art to form: p-channel shielded gate trench gate MOSFETs (i.e., a transistor similar in structure to that in <figref idref="DRAWINGS">FIG. 1C</figref> except that the conductivity type of all silicon regions is reversed); n-channel shielded gate trench IGBT (i.e., a transistor similar in structure to that in <figref idref="DRAWINGS">FIG. 1C</figref> except that a p-type substrate is used instead of the n-type substrate); p-channel shielded gate IGBT (i.e., a transistor similar in structure to that in <figref idref="DRAWINGS">FIG. 1C</figref> but with silicon regions of opposite conductivity except the substrate is kept n-type); p-channel variation of the trench gate MOSFET in <figref idref="DRAWINGS">FIG. 3</figref>; p-channel and n-channel IGBT variations of the trench gate MOSFET in <figref idref="DRAWINGS">FIG. 4</figref>; p-channel and n-channel IGBT variations of the planar gate MOSFET in <figref idref="DRAWINGS">FIG. 4</figref>; planar gate and trench gate synchronous FETs (i.e., integrated trench gate or shielded gate or planar gate MOSFET and Schottky rectifier); trench gate and planar gate variety of laterally conducting MOSFETs (i.e., a transistor where the drain contact is made no the top-side) and suprejunction variations of all the above devices (i.e., devices with columns of alternating conductivity type silicon).

0053Thus, while the above is a complete description of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. The scope of this invention should thus not be limited to the embodiments described herein, but is instead defined by the following claims.

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WO2009079458A1	World Intellectual Property Organization (WIPO)	A1	2009-06-25
TW200937639A	Taiwan Province of China	A	2009-09-01
US2009302381A1	United States of America	A1	2009-12-10
CN101971331A	China	A	2011-02-09
US7994573B2This record	United States of America	B2	2011-08-09
US2011263086A1	United States of America	A1	2011-10-27
CN101971331B	China	B	2012-09-05

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2011-04-05	Mail Notice of AllowanceAllowedMN/=.	MN/=.
2011-03-31	Notice of Allowance Data Verification CompletedAllowedN/=.	N/=.
2011-03-31	Case Docketed to Examiner in GAUDOCK	DOCK
2011-03-15	Date Forwarded to ExaminerFWDX	FWDX
2011-03-15	Disposal for a RCE / CPA / R129AbandonedABN9	ABN9
2011-03-10	Request for Continued Examination (RCE)RCEX	RCEX
2011-03-10	Request for Extension of Time - GrantedXT/G	XT/G
2011-03-10	Workflow - Request for RCE - BeginBRCE	BRCE
2011-03-01	Email NotificationEML_NTR	EML_NTR
2011-03-01	Mail Advisory Action (PTOL - 303)MCTAV	MCTAV
2011-02-24	Advisory Action (PTOL-303)CTAV	CTAV
2011-02-15	Date Forwarded to ExaminerFWDX	FWDX
2011-02-14	Response after Final ActionA.NE	A.NE
2011-02-14	Request for Extension of Time - GrantedXT/G	XT/G
2010-10-14	Mail Final Rejection (PTOL - 326)Final rejectionMCTFR	MCTFR
2010-10-12	Final RejectionFinal rejectionCTFR	CTFR
2010-09-17	Date Forwarded to ExaminerFWDX	FWDX
2010-09-14	Response after Non-Final ActionA...	A...
2010-09-14	Request for Extension of Time - GrantedXT/G	XT/G
2010-04-30	Change in Power of Attorney (May Include Associate POA)PA..	PA..
2010-04-14	Mail Non-Final RejectionNon-final rejectionMCTNF	MCTNF
2010-04-12	Non-Final RejectionNon-final rejectionCTNF	CTNF
2010-03-21	Case Docketed to Examiner in GAUDOCK	DOCK
2010-03-16	Case Docketed to Examiner in GAUDOCK	DOCK
2009-12-10	PG-Pub Issue NotificationPG-ISSUE	PG-ISSUE
2009-09-18	Application Dispatched from OIPEOIPE	OIPE
2009-09-03	Sent to Classification ContractorPGPC	PGPC
2009-09-03	Filing Receipt - UpdatedFLRCPT.U	FLRCPT.U
2009-06-19	Information Disclosure Statement consideredIDSC	IDSC
2009-06-19	Information Disclosure Statement (IDS) FiledM844	M844
2009-06-19	Reference capture on IDSRCAP	RCAP
2009-06-19	Information Disclosure Statement (IDS) FiledWIDS	WIDS
2009-04-14	Payment of additional filing fee/PreexamFLFEE	FLFEE
2009-04-14	A statement by one or more inventors satisfying the requirement under 35 USC 115, Oath of the ApplicOATHDECL	OATHDECL
2008-12-29	Notice Mailed--Application Incomplete--Filing Date AssignedINCD	INCD
2008-12-29	Filing ReceiptFLRCPT.O	FLRCPT.O
2008-12-15	Cleared by OIPE CSRL194	L194
2008-12-12	IFW Scan & PACR Auto Security ReviewSCAN	SCAN
2008-12-12	Initial Exam Team nnIEXX	IEXX

16 legal events, as the office reported them to INPADOC

Over the term

Point at a mark for the event

Events

Legal events, newest first
	Event	Code
2023-06-23	AssignmentAS	AS
2023-06-23	AssignmentAS	AS
2023-06-22	AssignmentAS	AS
2023-06-22	AssignmentAS	AS
2023-01-20	Maintenance fee paymentMAFP	MAFP
2021-11-12	AssignmentAS	AS
2021-10-28	AssignmentAS	AS
2021-10-28	AssignmentAS	AS
2021-08-03	AssignmentAS	AS
2021-08-03	AssignmentAS	AS
2019-01-28	Maintenance fee paymentMAFP	MAFP
2016-09-19	AssignmentAS	AS
2016-09-19	AssignmentAS	AS
2015-01-28	Fee paymentFPAY	FPAY
2011-07-20	Information on status: patent grantGrantedPATENTED CASESTCF	STCF
2010-01-26	AssignmentAS	AS

Structure and method for forming power devices with carbon-containing region

Summary by NHIP

Claim Score by NHIP

Abstract